drivers/media/platform/exynos4-is/fimc-is.c

   1 /*
   2  * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *
   6  * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
   7  *          Younghwan Joo <yhwan.joo@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  14
  15 #include <linux/device.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/delay.h>
  18 #include <linux/dma-contiguous.h>
  19 #include <linux/errno.h>
  20 #include <linux/firmware.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_graph.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/slab.h>
  32 #include <linux/types.h>
  33 #include <linux/videodev2.h>
  34 #include <media/videobuf2-dma-contig.h>
  35
  36 #include "media-dev.h"
  37 #include "fimc-is.h"
  38 #include "fimc-is-command.h"
  39 #include "fimc-is-errno.h"
  40 #include "fimc-is-i2c.h"
  41 #include "fimc-is-param.h"
  42 #include "fimc-is-regs.h"
  43
  44
  45 static char *fimc_is_clocks[ISS_CLKS_MAX] = {
  46         [ISS_CLK_PPMUISPX]              = "ppmuispx",
  47         [ISS_CLK_PPMUISPMX]             = "ppmuispmx",
  48         [ISS_CLK_LITE0]                 = "lite0",
  49         [ISS_CLK_LITE1]                 = "lite1",
  50         [ISS_CLK_MPLL]                  = "mpll",
  51         [ISS_CLK_ISP]                   = "isp",
  52         [ISS_CLK_DRC]                   = "drc",
  53         [ISS_CLK_FD]                    = "fd",
  54         [ISS_CLK_MCUISP]                = "mcuisp",
  55         [ISS_CLK_GICISP]                = "gicisp",
  56         [ISS_CLK_PWM_ISP]               = "pwm_isp",
  57         [ISS_CLK_MCUCTL_ISP]            = "mcuctl_isp",
  58         [ISS_CLK_UART]                  = "uart",
  59         [ISS_CLK_ISP_DIV0]              = "ispdiv0",
  60         [ISS_CLK_ISP_DIV1]              = "ispdiv1",
  61         [ISS_CLK_MCUISP_DIV0]           = "mcuispdiv0",
  62         [ISS_CLK_MCUISP_DIV1]           = "mcuispdiv1",
  63         [ISS_CLK_ACLK200]               = "aclk200",
  64         [ISS_CLK_ACLK200_DIV]           = "div_aclk200",
  65         [ISS_CLK_ACLK400MCUISP]         = "aclk400mcuisp",
  66         [ISS_CLK_ACLK400MCUISP_DIV]     = "div_aclk400mcuisp",
  67 };
  68
  69 static void fimc_is_put_clocks(struct fimc_is *is)
  70 {
  71         int i;
  72
  73         for (i = 0; i < ISS_CLKS_MAX; i++) {
  74                 if (IS_ERR(is->clocks[i]))
  75                         continue;
  76                 clk_put(is->clocks[i]);
  77                 is->clocks[i] = ERR_PTR(-EINVAL);
  78         }
  79 }
  80
  81 static int fimc_is_get_clocks(struct fimc_is *is)
  82 {
  83         int i, ret;
  84
  85         for (i = 0; i < ISS_CLKS_MAX; i++)
  86                 is->clocks[i] = ERR_PTR(-EINVAL);
  87
  88         for (i = 0; i < ISS_CLKS_MAX; i++) {
  89                 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]);
  90                 if (IS_ERR(is->clocks[i])) {
  91                         ret = PTR_ERR(is->clocks[i]);
  92                         goto err;
  93                 }
  94         }
  95
  96         return 0;
  97 err:
  98         fimc_is_put_clocks(is);
  99         dev_err(&is->pdev->dev, "failed to get clock: %s\n",
 100                 fimc_is_clocks[i]);
 101         return ret;
 102 }
 103
 104 static int fimc_is_setup_clocks(struct fimc_is *is)
 105 {
 106         int ret;
 107
 108         ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200],
 109                                         is->clocks[ISS_CLK_ACLK200_DIV]);
 110         if (ret < 0)
 111                 return ret;
 112
 113         ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP],
 114                                         is->clocks[ISS_CLK_ACLK400MCUISP_DIV]);
 115         if (ret < 0)
 116                 return ret;
 117
 118         ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY);
 119         if (ret < 0)
 120                 return ret;
 121
 122         ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY);
 123         if (ret < 0)
 124                 return ret;
 125
 126         ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0],
 127                                         ATCLK_MCUISP_FREQUENCY);
 128         if (ret < 0)
 129                 return ret;
 130
 131         return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1],
 132                                         ATCLK_MCUISP_FREQUENCY);
 133 }
 134
 135 static int fimc_is_enable_clocks(struct fimc_is *is)
 136 {
 137         int i, ret;
 138
 139         for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
 140                 if (IS_ERR(is->clocks[i]))
 141                         continue;
 142                 ret = clk_prepare_enable(is->clocks[i]);
 143                 if (ret < 0) {
 144                         dev_err(&is->pdev->dev, "clock %s enable failed\n",
 145                                 fimc_is_clocks[i]);
 146                         for (--i; i >= 0; i--)
 147                                 clk_disable_unprepare(is->clocks[i]);
 148                         return ret;
 149                 }
 150                 pr_debug("enabled clock: %s\n", fimc_is_clocks[i]);
 151         }
 152         return 0;
 153 }
 154
 155 static void fimc_is_disable_clocks(struct fimc_is *is)
 156 {
 157         int i;
 158
 159         for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
 160                 if (!IS_ERR(is->clocks[i])) {
 161                         clk_disable_unprepare(is->clocks[i]);
 162                         pr_debug("disabled clock: %s\n", fimc_is_clocks[i]);
 163                 }
 164         }
 165 }
 166
 167 static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
 168                                                 struct device_node *node)
 169 {
 170         struct fimc_is_sensor *sensor = &is->sensor[index];
 171         struct device_node *ep, *port;
 172         u32 tmp = 0;
 173         int ret;
 174
 175         sensor->drvdata = fimc_is_sensor_get_drvdata(node);
 176         if (!sensor->drvdata) {
 177                 dev_err(&is->pdev->dev, "no driver data found for: %pOF\n",
 178                                                          node);
 179                 return -EINVAL;
 180         }
 181
 182         ep = of_graph_get_next_endpoint(node, NULL);
 183         if (!ep)
 184                 return -ENXIO;
 185
 186         port = of_graph_get_remote_port(ep);
 187         of_node_put(ep);
 188         if (!port)
 189                 return -ENXIO;
 190
 191         /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
 192         ret = of_property_read_u32(port, "reg", &tmp);
 193         if (ret < 0) {
 194                 dev_err(&is->pdev->dev, "reg property not found at: %pOF\n",
 195                                                          port);
 196                 of_node_put(port);
 197                 return ret;
 198         }
 199
 200         of_node_put(port);
 201         sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
 202         return 0;
 203 }
 204
 205 static int fimc_is_register_subdevs(struct fimc_is *is)
 206 {
 207         struct device_node *i2c_bus, *child;
 208         int ret, index = 0;
 209
 210         ret = fimc_isp_subdev_create(&is->isp);
 211         if (ret < 0)
 212                 return ret;
 213
 214         for_each_compatible_node(i2c_bus, NULL, FIMC_IS_I2C_COMPATIBLE) {
 215                 for_each_available_child_of_node(i2c_bus, child) {
 216                         ret = fimc_is_parse_sensor_config(is, index, child);
 217
 218                         if (ret < 0 || index >= FIMC_IS_SENSORS_NUM) {
 219                                 of_node_put(child);
 220                                 of_node_put(i2c_bus);
 221                                 return ret;
 222                         }
 223                         index++;
 224                 }
 225         }
 226         return 0;
 227 }
 228
 229 static int fimc_is_unregister_subdevs(struct fimc_is *is)
 230 {
 231         fimc_isp_subdev_destroy(&is->isp);
 232         return 0;
 233 }
 234
 235 static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
 236 {
 237         const struct firmware *fw;
 238         void *buf;
 239         int ret;
 240
 241         ret = reject_firmware(&fw, file_name, &is->pdev->dev);
 242         if (ret < 0) {
 243                 dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
 244                 return ret;
 245         }
 246         buf = is->memory.vaddr + is->setfile.base;
 247         memcpy(buf, fw->data, fw->size);
 248         fimc_is_mem_barrier();
 249         is->setfile.size = fw->size;
 250
 251         pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
 252
 253         memcpy(is->fw.setfile_info,
 254                 fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN,
 255                 FIMC_IS_SETFILE_INFO_LEN - 1);
 256
 257         is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
 258         is->setfile.state = 1;
 259
 260         pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n",
 261                  is->setfile.base, fw->size);
 262
 263         release_firmware(fw);
 264         return ret;
 265 }
 266
 267 int fimc_is_cpu_set_power(struct fimc_is *is, int on)
 268 {
 269         unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT;
 270
 271         if (on) {
 272                 /* Disable watchdog */
 273                 mcuctl_write(0, is, REG_WDT_ISP);
 274
 275                 /* Cortex-A5 start address setting */
 276                 mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR);
 277
 278                 /* Enable and start Cortex-A5 */
 279                 pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
 280                 pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION);
 281         } else {
 282                 /* A5 power off */
 283                 pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION);
 284                 pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION);
 285
 286                 while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) {
 287                         if (timeout == 0)
 288                                 return -ETIME;
 289                         timeout--;
 290                         udelay(1);
 291                 }
 292         }
 293
 294         return 0;
 295 }
 296
 297 /* Wait until @bit of @is->state is set to @state in the interrupt handler. */
 298 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
 299                        unsigned int state, unsigned int timeout)
 300 {
 301
 302         int ret = wait_event_timeout(is->irq_queue,
 303                                      !state ^ test_bit(bit, &is->state),
 304                                      timeout);
 305         if (ret == 0) {
 306                 dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__);
 307                 return -ETIME;
 308         }
 309         return 0;
 310 }
 311
 312 int fimc_is_start_firmware(struct fimc_is *is)
 313 {
 314         struct device *dev = &is->pdev->dev;
 315         int ret;
 316
 317         if (is->fw.f_w == NULL) {
 318                 dev_err(dev, "firmware is not loaded\n");
 319                 return -EINVAL;
 320         }
 321
 322         memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size);
 323         wmb();
 324
 325         ret = fimc_is_cpu_set_power(is, 1);
 326         if (ret < 0)
 327                 return ret;
 328
 329         ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1,
 330                                  msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT));
 331         if (ret < 0)
 332                 dev_err(dev, "FIMC-IS CPU power on failed\n");
 333
 334         return ret;
 335 }
 336
 337 /* Allocate working memory for the FIMC-IS CPU. */
 338 static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
 339 {
 340         struct device *dev = &is->pdev->dev;
 341
 342         is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
 343                                               &is->memory.paddr, GFP_KERNEL);
 344         if (is->memory.vaddr == NULL)
 345                 return -ENOMEM;
 346
 347         is->memory.size = FIMC_IS_CPU_MEM_SIZE;
 348         memset(is->memory.vaddr, 0, is->memory.size);
 349
 350         dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr);
 351
 352         if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) {
 353                 dev_err(dev, "invalid firmware memory alignment: %#x\n",
 354                         (u32)is->memory.paddr);
 355                 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
 356                                   is->memory.paddr);
 357                 return -EIO;
 358         }
 359
 360         is->is_p_region = (struct is_region *)(is->memory.vaddr +
 361                                 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
 362
 363         is->is_dma_p_region = is->memory.paddr +
 364                                 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
 365
 366         is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
 367                                 FIMC_IS_SHARED_REGION_OFFSET);
 368         return 0;
 369 }
 370
 371 static void fimc_is_free_cpu_memory(struct fimc_is *is)
 372 {
 373         struct device *dev = &is->pdev->dev;
 374
 375         if (is->memory.vaddr == NULL)
 376                 return;
 377
 378         dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
 379                           is->memory.paddr);
 380 }
 381
 382 static void fimc_is_load_firmware(const struct firmware *fw, void *context)
 383 {
 384         struct fimc_is *is = context;
 385         struct device *dev = &is->pdev->dev;
 386         void *buf;
 387         int ret;
 388
 389         if (fw == NULL) {
 390                 dev_err(dev, "firmware request failed\n");
 391                 return;
 392         }
 393         mutex_lock(&is->lock);
 394
 395         if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) {
 396                 dev_err(dev, "wrong firmware size: %zu\n", fw->size);
 397                 goto done;
 398         }
 399
 400         is->fw.size = fw->size;
 401
 402         ret = fimc_is_alloc_cpu_memory(is);
 403         if (ret < 0) {
 404                 dev_err(dev, "failed to allocate FIMC-IS CPU memory\n");
 405                 goto done;
 406         }
 407
 408         memcpy(is->memory.vaddr, fw->data, fw->size);
 409         wmb();
 410
 411         /* Read firmware description. */
 412         buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
 413         memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
 414         is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
 415
 416         buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
 417         memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
 418         is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
 419
 420         is->fw.state = 1;
 421
 422         dev_info(dev, "loaded firmware: %s, rev. %s\n",
 423                  is->fw.info, is->fw.version);
 424         dev_dbg(dev, "FW size: %zu, paddr: %pad\n", fw->size, &is->memory.paddr);
 425
 426         is->is_shared_region->chip_id = 0xe4412;
 427         is->is_shared_region->chip_rev_no = 1;
 428
 429         fimc_is_mem_barrier();
 430
 431         /*
 432          * FIXME: The firmware is not being released for now, as it is
 433          * needed around for copying to the IS working memory every
 434          * time before the Cortex-A5 is restarted.
 435          */
 436         release_firmware(is->fw.f_w);
 437         is->fw.f_w = fw;
 438 done:
 439         mutex_unlock(&is->lock);
 440 }
 441
 442 static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name)
 443 {
 444         return reject_firmware_nowait(THIS_MODULE,
 445                                 FW_ACTION_HOTPLUG, fw_name, &is->pdev->dev,
 446                                 GFP_KERNEL, is, fimc_is_load_firmware);
 447 }
 448
 449 /* General IS interrupt handler */
 450 static void fimc_is_general_irq_handler(struct fimc_is *is)
 451 {
 452         is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
 453
 454         switch (is->i2h_cmd.cmd) {
 455         case IHC_GET_SENSOR_NUM:
 456                 fimc_is_hw_get_params(is, 1);
 457                 fimc_is_hw_wait_intmsr0_intmsd0(is);
 458                 fimc_is_hw_set_sensor_num(is);
 459                 pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
 460                 break;
 461         case IHC_SET_FACE_MARK:
 462         case IHC_FRAME_DONE:
 463                 fimc_is_hw_get_params(is, 2);
 464                 break;
 465         case IHC_SET_SHOT_MARK:
 466         case IHC_AA_DONE:
 467         case IH_REPLY_DONE:
 468                 fimc_is_hw_get_params(is, 3);
 469                 break;
 470         case IH_REPLY_NOT_DONE:
 471                 fimc_is_hw_get_params(is, 4);
 472                 break;
 473         case IHC_NOT_READY:
 474                 break;
 475         default:
 476                 pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
 477         }
 478
 479         fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
 480
 481         switch (is->i2h_cmd.cmd) {
 482         case IHC_GET_SENSOR_NUM:
 483                 fimc_is_hw_set_intgr0_gd0(is);
 484                 set_bit(IS_ST_A5_PWR_ON, &is->state);
 485                 break;
 486
 487         case IHC_SET_SHOT_MARK:
 488                 break;
 489
 490         case IHC_SET_FACE_MARK:
 491                 is->fd_header.count = is->i2h_cmd.args[0];
 492                 is->fd_header.index = is->i2h_cmd.args[1];
 493                 is->fd_header.offset = 0;
 494                 break;
 495
 496         case IHC_FRAME_DONE:
 497                 break;
 498
 499         case IHC_AA_DONE:
 500                 pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
 501                          is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
 502                 break;
 503
 504         case IH_REPLY_DONE:
 505                 pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
 506
 507                 switch (is->i2h_cmd.args[0]) {
 508                 case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
 509                         /* Get CAC margin */
 510                         set_bit(IS_ST_CHANGE_MODE, &is->state);
 511                         is->isp.cac_margin_x = is->i2h_cmd.args[1];
 512                         is->isp.cac_margin_y = is->i2h_cmd.args[2];
 513                         pr_debug("CAC margin (x,y): (%d,%d)\n",
 514                                  is->isp.cac_margin_x, is->isp.cac_margin_y);
 515                         break;
 516
 517                 case HIC_STREAM_ON:
 518                         clear_bit(IS_ST_STREAM_OFF, &is->state);
 519                         set_bit(IS_ST_STREAM_ON, &is->state);
 520                         break;
 521
 522                 case HIC_STREAM_OFF:
 523                         clear_bit(IS_ST_STREAM_ON, &is->state);
 524                         set_bit(IS_ST_STREAM_OFF, &is->state);
 525                         break;
 526
 527                 case HIC_SET_PARAMETER:
 528                         is->config[is->config_index].p_region_index[0] = 0;
 529                         is->config[is->config_index].p_region_index[1] = 0;
 530                         set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
 531                         pr_debug("HIC_SET_PARAMETER\n");
 532                         break;
 533
 534                 case HIC_GET_PARAMETER:
 535                         break;
 536
 537                 case HIC_SET_TUNE:
 538                         break;
 539
 540                 case HIC_GET_STATUS:
 541                         break;
 542
 543                 case HIC_OPEN_SENSOR:
 544                         set_bit(IS_ST_OPEN_SENSOR, &is->state);
 545                         pr_debug("data lanes: %d, settle line: %d\n",
 546                                  is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
 547                         break;
 548
 549                 case HIC_CLOSE_SENSOR:
 550                         clear_bit(IS_ST_OPEN_SENSOR, &is->state);
 551                         is->sensor_index = 0;
 552                         break;
 553
 554                 case HIC_MSG_TEST:
 555                         pr_debug("config MSG level completed\n");
 556                         break;
 557
 558                 case HIC_POWER_DOWN:
 559                         clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
 560                         break;
 561
 562                 case HIC_GET_SET_FILE_ADDR:
 563                         is->setfile.base = is->i2h_cmd.args[1];
 564                         set_bit(IS_ST_SETFILE_LOADED, &is->state);
 565                         break;
 566
 567                 case HIC_LOAD_SET_FILE:
 568                         set_bit(IS_ST_SETFILE_LOADED, &is->state);
 569                         break;
 570                 }
 571                 break;
 572
 573         case IH_REPLY_NOT_DONE:
 574                 pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
 575                        is->i2h_cmd.args[1],
 576                        fimc_is_strerr(is->i2h_cmd.args[1]));
 577
 578                 if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
 579                         pr_err("IS_ERROR_TIME_OUT\n");
 580
 581                 switch (is->i2h_cmd.args[1]) {
 582                 case IS_ERROR_SET_PARAMETER:
 583                         fimc_is_mem_barrier();
 584                 }
 585
 586                 switch (is->i2h_cmd.args[0]) {
 587                 case HIC_SET_PARAMETER:
 588                         is->config[is->config_index].p_region_index[0] = 0;
 589                         is->config[is->config_index].p_region_index[1] = 0;
 590                         set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
 591                         break;
 592                 }
 593                 break;
 594
 595         case IHC_NOT_READY:
 596                 pr_err("IS control sequence error: Not Ready\n");
 597                 break;
 598         }
 599
 600         wake_up(&is->irq_queue);
 601 }
 602
 603 static irqreturn_t fimc_is_irq_handler(int irq, void *priv)
 604 {
 605         struct fimc_is *is = priv;
 606         unsigned long flags;
 607         u32 status;
 608
 609         spin_lock_irqsave(&is->slock, flags);
 610         status = mcuctl_read(is, MCUCTL_REG_INTSR1);
 611
 612         if (status & (1UL << FIMC_IS_INT_GENERAL))
 613                 fimc_is_general_irq_handler(is);
 614
 615         if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP))
 616                 fimc_isp_irq_handler(is);
 617
 618         spin_unlock_irqrestore(&is->slock, flags);
 619         return IRQ_HANDLED;
 620 }
 621
 622 static int fimc_is_hw_open_sensor(struct fimc_is *is,
 623                                   struct fimc_is_sensor *sensor)
 624 {
 625         struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
 626
 627         fimc_is_hw_wait_intmsr0_intmsd0(is);
 628
 629         soe->self_calibration_mode = 1;
 630         soe->actuator_type = 0;
 631         soe->mipi_lane_num = 0;
 632         soe->mclk = 0;
 633         soe->mipi_speed = 0;
 634         soe->fast_open_sensor = 0;
 635         soe->i2c_sclk = 88000000;
 636
 637         fimc_is_mem_barrier();
 638
 639         /*
 640          * Some user space use cases hang up here without this
 641          * empirically chosen delay.
 642          */
 643         udelay(100);
 644
 645         mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
 646         mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
 647         mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
 648         mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
 649         mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
 650
 651         fimc_is_hw_set_intgr0_gd0(is);
 652
 653         return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
 654                                   sensor->drvdata->open_timeout);
 655 }
 656
 657
 658 int fimc_is_hw_initialize(struct fimc_is *is)
 659 {
 660         const int config_ids[] = {
 661                 IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO,
 662                 IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO
 663         };
 664         struct device *dev = &is->pdev->dev;
 665         u32 prev_id;
 666         int i, ret;
 667
 668         /* Sensor initialization. Only one sensor is currently supported. */
 669         ret = fimc_is_hw_open_sensor(is, &is->sensor[0]);
 670         if (ret < 0)
 671                 return ret;
 672
 673         /* Get the setfile address. */
 674         fimc_is_hw_get_setfile_addr(is);
 675
 676         ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
 677                                  FIMC_IS_CONFIG_TIMEOUT);
 678         if (ret < 0) {
 679                 dev_err(dev, "get setfile address timed out\n");
 680                 return ret;
 681         }
 682         pr_debug("setfile.base: %#x\n", is->setfile.base);
 683
 684         /* Load the setfile. */
 685         fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3);
 686         clear_bit(IS_ST_SETFILE_LOADED, &is->state);
 687         fimc_is_hw_load_setfile(is);
 688         ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
 689                                  FIMC_IS_CONFIG_TIMEOUT);
 690         if (ret < 0) {
 691                 dev_err(dev, "loading setfile timed out\n");
 692                 return ret;
 693         }
 694
 695         pr_debug("setfile: base: %#x, size: %d\n",
 696                  is->setfile.base, is->setfile.size);
 697         pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info);
 698
 699         /* Check magic number. */
 700         if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] !=
 701             FIMC_IS_MAGIC_NUMBER) {
 702                 dev_err(dev, "magic number error!\n");
 703                 return -EIO;
 704         }
 705
 706         pr_debug("shared region: %pad, parameter region: %pad\n",
 707                  &is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET,
 708                  &is->is_dma_p_region);
 709
 710         is->setfile.sub_index = 0;
 711
 712         /* Stream off. */
 713         fimc_is_hw_stream_off(is);
 714         ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
 715                                  FIMC_IS_CONFIG_TIMEOUT);
 716         if (ret < 0) {
 717                 dev_err(dev, "stream off timeout\n");
 718                 return ret;
 719         }
 720
 721         /* Preserve previous mode. */
 722         prev_id = is->config_index;
 723
 724         /* Set initial parameter values. */
 725         for (i = 0; i < ARRAY_SIZE(config_ids); i++) {
 726                 is->config_index = config_ids[i];
 727                 fimc_is_set_initial_params(is);
 728                 ret = fimc_is_itf_s_param(is, true);
 729                 if (ret < 0) {
 730                         is->config_index = prev_id;
 731                         return ret;
 732                 }
 733         }
 734         is->config_index = prev_id;
 735
 736         set_bit(IS_ST_INIT_DONE, &is->state);
 737         dev_info(dev, "initialization sequence completed (%d)\n",
 738                                                 is->config_index);
 739         return 0;
 740 }
 741
 742 static int fimc_is_log_show(struct seq_file *s, void *data)
 743 {
 744         struct fimc_is *is = s->private;
 745         const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
 746
 747         if (is->memory.vaddr == NULL) {
 748                 dev_err(&is->pdev->dev, "firmware memory is not initialized\n");
 749                 return -EIO;
 750         }
 751
 752         seq_printf(s, "%s\n", buf);
 753         return 0;
 754 }
 755
 756 static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
 757 {
 758         return single_open(file, fimc_is_log_show, inode->i_private);
 759 }
 760
 761 static const struct file_operations fimc_is_debugfs_fops = {
 762         .open           = fimc_is_debugfs_open,
 763         .read           = seq_read,
 764         .llseek         = seq_lseek,
 765         .release        = single_release,
 766 };
 767
 768 static void fimc_is_debugfs_remove(struct fimc_is *is)
 769 {
 770         debugfs_remove_recursive(is->debugfs_entry);
 771         is->debugfs_entry = NULL;
 772 }
 773
 774 static int fimc_is_debugfs_create(struct fimc_is *is)
 775 {
 776         struct dentry *dentry;
 777
 778         is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
 779
 780         dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry,
 781                                      is, &fimc_is_debugfs_fops);
 782         if (!dentry)
 783                 fimc_is_debugfs_remove(is);
 784
 785         return is->debugfs_entry == NULL ? -EIO : 0;
 786 }
 787
 788 static int fimc_is_runtime_resume(struct device *dev);
 789 static int fimc_is_runtime_suspend(struct device *dev);
 790
 791 static int fimc_is_probe(struct platform_device *pdev)
 792 {
 793         struct device *dev = &pdev->dev;
 794         struct fimc_is *is;
 795         struct resource res;
 796         struct device_node *node;
 797         int ret;
 798
 799         is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
 800         if (!is)
 801                 return -ENOMEM;
 802
 803         is->pdev = pdev;
 804         is->isp.pdev = pdev;
 805
 806         init_waitqueue_head(&is->irq_queue);
 807         spin_lock_init(&is->slock);
 808         mutex_init(&is->lock);
 809
 810         ret = of_address_to_resource(dev->of_node, 0, &res);
 811         if (ret < 0)
 812                 return ret;
 813
 814         is->regs = devm_ioremap_resource(dev, &res);
 815         if (IS_ERR(is->regs))
 816                 return PTR_ERR(is->regs);
 817
 818         node = of_get_child_by_name(dev->of_node, "pmu");
 819         if (!node)
 820                 return -ENODEV;
 821
 822         is->pmu_regs = of_iomap(node, 0);
 823         of_node_put(node);
 824         if (!is->pmu_regs)
 825                 return -ENOMEM;
 826
 827         is->irq = irq_of_parse_and_map(dev->of_node, 0);
 828         if (!is->irq) {
 829                 dev_err(dev, "no irq found\n");
 830                 ret = -EINVAL;
 831                 goto err_iounmap;
 832         }
 833
 834         ret = fimc_is_get_clocks(is);
 835         if (ret < 0)
 836                 goto err_iounmap;
 837
 838         platform_set_drvdata(pdev, is);
 839
 840         ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is);
 841         if (ret < 0) {
 842                 dev_err(dev, "irq request failed\n");
 843                 goto err_clk;
 844         }
 845         pm_runtime_enable(dev);
 846
 847         if (!pm_runtime_enabled(dev)) {
 848                 ret = fimc_is_runtime_resume(dev);
 849                 if (ret < 0)
 850                         goto err_irq;
 851         }
 852
 853         ret = pm_runtime_get_sync(dev);
 854         if (ret < 0)
 855                 goto err_pm;
 856
 857         vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
 858
 859         ret = devm_of_platform_populate(dev);
 860         if (ret < 0)
 861                 goto err_pm;
 862
 863         /*
 864          * Register FIMC-IS V4L2 subdevs to this driver. The video nodes
 865          * will be created within the subdev's registered() callback.
 866          */
 867         ret = fimc_is_register_subdevs(is);
 868         if (ret < 0)
 869                 goto err_pm;
 870
 871         ret = fimc_is_debugfs_create(is);
 872         if (ret < 0)
 873                 goto err_sd;
 874
 875         ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME);
 876         if (ret < 0)
 877                 goto err_dfs;
 878
 879         pm_runtime_put_sync(dev);
 880
 881         dev_dbg(dev, "FIMC-IS registered successfully\n");
 882         return 0;
 883
 884 err_dfs:
 885         fimc_is_debugfs_remove(is);
 886 err_sd:
 887         fimc_is_unregister_subdevs(is);
 888 err_pm:
 889         if (!pm_runtime_enabled(dev))
 890                 fimc_is_runtime_suspend(dev);
 891 err_irq:
 892         free_irq(is->irq, is);
 893 err_clk:
 894         fimc_is_put_clocks(is);
 895 err_iounmap:
 896         iounmap(is->pmu_regs);
 897         return ret;
 898 }
 899
 900 static int fimc_is_runtime_resume(struct device *dev)
 901 {
 902         struct fimc_is *is = dev_get_drvdata(dev);
 903         int ret;
 904
 905         ret = fimc_is_setup_clocks(is);
 906         if (ret)
 907                 return ret;
 908
 909         return fimc_is_enable_clocks(is);
 910 }
 911
 912 static int fimc_is_runtime_suspend(struct device *dev)
 913 {
 914         struct fimc_is *is = dev_get_drvdata(dev);
 915
 916         fimc_is_disable_clocks(is);
 917         return 0;
 918 }
 919
 920 #ifdef CONFIG_PM_SLEEP
 921 static int fimc_is_resume(struct device *dev)
 922 {
 923         /* TODO: */
 924         return 0;
 925 }
 926
 927 static int fimc_is_suspend(struct device *dev)
 928 {
 929         struct fimc_is *is = dev_get_drvdata(dev);
 930
 931         /* TODO: */
 932         if (test_bit(IS_ST_A5_PWR_ON, &is->state))
 933                 return -EBUSY;
 934
 935         return 0;
 936 }
 937 #endif /* CONFIG_PM_SLEEP */
 938
 939 static int fimc_is_remove(struct platform_device *pdev)
 940 {
 941         struct device *dev = &pdev->dev;
 942         struct fimc_is *is = dev_get_drvdata(dev);
 943
 944         pm_runtime_disable(dev);
 945         pm_runtime_set_suspended(dev);
 946         if (!pm_runtime_status_suspended(dev))
 947                 fimc_is_runtime_suspend(dev);
 948         free_irq(is->irq, is);
 949         fimc_is_unregister_subdevs(is);
 950         vb2_dma_contig_clear_max_seg_size(dev);
 951         fimc_is_put_clocks(is);
 952         iounmap(is->pmu_regs);
 953         fimc_is_debugfs_remove(is);
 954         release_firmware(is->fw.f_w);
 955         fimc_is_free_cpu_memory(is);
 956
 957         return 0;
 958 }
 959
 960 static const struct of_device_id fimc_is_of_match[] = {
 961         { .compatible = "samsung,exynos4212-fimc-is" },
 962         { /* sentinel */ },
 963 };
 964 MODULE_DEVICE_TABLE(of, fimc_is_of_match);
 965
 966 static const struct dev_pm_ops fimc_is_pm_ops = {
 967         SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
 968         SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
 969                            NULL)
 970 };
 971
 972 static struct platform_driver fimc_is_driver = {
 973         .probe          = fimc_is_probe,
 974         .remove         = fimc_is_remove,
 975         .driver = {
 976                 .of_match_table = fimc_is_of_match,
 977                 .name           = FIMC_IS_DRV_NAME,
 978                 .pm             = &fimc_is_pm_ops,
 979         }
 980 };
 981
 982 static int fimc_is_module_init(void)
 983 {
 984         int ret;
 985
 986         ret = fimc_is_register_i2c_driver();
 987         if (ret < 0)
 988                 return ret;
 989
 990         ret = platform_driver_register(&fimc_is_driver);
 991
 992         if (ret < 0)
 993                 fimc_is_unregister_i2c_driver();
 994
 995         return ret;
 996 }
 997
 998 static void fimc_is_module_exit(void)
 999 {
1000         fimc_is_unregister_i2c_driver();
1001         platform_driver_unregister(&fimc_is_driver);
1002 }
1003
1004 module_init(fimc_is_module_init);
1005 module_exit(fimc_is_module_exit);
1006
1007 MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME);
1008 MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>");
1009 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1010 MODULE_LICENSE("GPL v2");