2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 * Younghwan Joo <yhwan.joo@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
15 #include <linux/device.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/dma-contiguous.h>
19 #include <linux/errno.h>
20 #include <linux/firmware.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_address.h>
27 #include <linux/of_graph.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/slab.h>
32 #include <linux/types.h>
33 #include <linux/videodev2.h>
34 #include <media/videobuf2-dma-contig.h>
36 #include "media-dev.h"
38 #include "fimc-is-command.h"
39 #include "fimc-is-errno.h"
40 #include "fimc-is-i2c.h"
41 #include "fimc-is-param.h"
42 #include "fimc-is-regs.h"
45 static char *fimc_is_clocks[ISS_CLKS_MAX] = {
46 [ISS_CLK_PPMUISPX] = "ppmuispx",
47 [ISS_CLK_PPMUISPMX] = "ppmuispmx",
48 [ISS_CLK_LITE0] = "lite0",
49 [ISS_CLK_LITE1] = "lite1",
50 [ISS_CLK_MPLL] = "mpll",
51 [ISS_CLK_ISP] = "isp",
52 [ISS_CLK_DRC] = "drc",
54 [ISS_CLK_MCUISP] = "mcuisp",
55 [ISS_CLK_GICISP] = "gicisp",
56 [ISS_CLK_PWM_ISP] = "pwm_isp",
57 [ISS_CLK_MCUCTL_ISP] = "mcuctl_isp",
58 [ISS_CLK_UART] = "uart",
59 [ISS_CLK_ISP_DIV0] = "ispdiv0",
60 [ISS_CLK_ISP_DIV1] = "ispdiv1",
61 [ISS_CLK_MCUISP_DIV0] = "mcuispdiv0",
62 [ISS_CLK_MCUISP_DIV1] = "mcuispdiv1",
63 [ISS_CLK_ACLK200] = "aclk200",
64 [ISS_CLK_ACLK200_DIV] = "div_aclk200",
65 [ISS_CLK_ACLK400MCUISP] = "aclk400mcuisp",
66 [ISS_CLK_ACLK400MCUISP_DIV] = "div_aclk400mcuisp",
69 static void fimc_is_put_clocks(struct fimc_is *is)
73 for (i = 0; i < ISS_CLKS_MAX; i++) {
74 if (IS_ERR(is->clocks[i]))
76 clk_put(is->clocks[i]);
77 is->clocks[i] = ERR_PTR(-EINVAL);
81 static int fimc_is_get_clocks(struct fimc_is *is)
85 for (i = 0; i < ISS_CLKS_MAX; i++)
86 is->clocks[i] = ERR_PTR(-EINVAL);
88 for (i = 0; i < ISS_CLKS_MAX; i++) {
89 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]);
90 if (IS_ERR(is->clocks[i])) {
91 ret = PTR_ERR(is->clocks[i]);
98 fimc_is_put_clocks(is);
99 dev_err(&is->pdev->dev, "failed to get clock: %s\n",
104 static int fimc_is_setup_clocks(struct fimc_is *is)
108 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200],
109 is->clocks[ISS_CLK_ACLK200_DIV]);
113 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP],
114 is->clocks[ISS_CLK_ACLK400MCUISP_DIV]);
118 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY);
122 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY);
126 ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0],
127 ATCLK_MCUISP_FREQUENCY);
131 return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1],
132 ATCLK_MCUISP_FREQUENCY);
135 static int fimc_is_enable_clocks(struct fimc_is *is)
139 for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
140 if (IS_ERR(is->clocks[i]))
142 ret = clk_prepare_enable(is->clocks[i]);
144 dev_err(&is->pdev->dev, "clock %s enable failed\n",
146 for (--i; i >= 0; i--)
147 clk_disable_unprepare(is->clocks[i]);
150 pr_debug("enabled clock: %s\n", fimc_is_clocks[i]);
155 static void fimc_is_disable_clocks(struct fimc_is *is)
159 for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
160 if (!IS_ERR(is->clocks[i])) {
161 clk_disable_unprepare(is->clocks[i]);
162 pr_debug("disabled clock: %s\n", fimc_is_clocks[i]);
167 static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
168 struct device_node *node)
170 struct fimc_is_sensor *sensor = &is->sensor[index];
171 struct device_node *ep, *port;
175 sensor->drvdata = fimc_is_sensor_get_drvdata(node);
176 if (!sensor->drvdata) {
177 dev_err(&is->pdev->dev, "no driver data found for: %pOF\n",
182 ep = of_graph_get_next_endpoint(node, NULL);
186 port = of_graph_get_remote_port(ep);
191 /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
192 ret = of_property_read_u32(port, "reg", &tmp);
194 dev_err(&is->pdev->dev, "reg property not found at: %pOF\n",
201 sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
205 static int fimc_is_register_subdevs(struct fimc_is *is)
207 struct device_node *i2c_bus, *child;
210 ret = fimc_isp_subdev_create(&is->isp);
214 for_each_compatible_node(i2c_bus, NULL, FIMC_IS_I2C_COMPATIBLE) {
215 for_each_available_child_of_node(i2c_bus, child) {
216 ret = fimc_is_parse_sensor_config(is, index, child);
218 if (ret < 0 || index >= FIMC_IS_SENSORS_NUM) {
220 of_node_put(i2c_bus);
229 static int fimc_is_unregister_subdevs(struct fimc_is *is)
231 fimc_isp_subdev_destroy(&is->isp);
235 static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
237 const struct firmware *fw;
241 ret = reject_firmware(&fw, file_name, &is->pdev->dev);
243 dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
246 buf = is->memory.vaddr + is->setfile.base;
247 memcpy(buf, fw->data, fw->size);
248 fimc_is_mem_barrier();
249 is->setfile.size = fw->size;
251 pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
253 memcpy(is->fw.setfile_info,
254 fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN,
255 FIMC_IS_SETFILE_INFO_LEN - 1);
257 is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
258 is->setfile.state = 1;
260 pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n",
261 is->setfile.base, fw->size);
263 release_firmware(fw);
267 int fimc_is_cpu_set_power(struct fimc_is *is, int on)
269 unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT;
272 /* Disable watchdog */
273 mcuctl_write(0, is, REG_WDT_ISP);
275 /* Cortex-A5 start address setting */
276 mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR);
278 /* Enable and start Cortex-A5 */
279 pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
280 pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION);
283 pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION);
284 pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION);
286 while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) {
297 /* Wait until @bit of @is->state is set to @state in the interrupt handler. */
298 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
299 unsigned int state, unsigned int timeout)
302 int ret = wait_event_timeout(is->irq_queue,
303 !state ^ test_bit(bit, &is->state),
306 dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__);
312 int fimc_is_start_firmware(struct fimc_is *is)
314 struct device *dev = &is->pdev->dev;
317 if (is->fw.f_w == NULL) {
318 dev_err(dev, "firmware is not loaded\n");
322 memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size);
325 ret = fimc_is_cpu_set_power(is, 1);
329 ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1,
330 msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT));
332 dev_err(dev, "FIMC-IS CPU power on failed\n");
337 /* Allocate working memory for the FIMC-IS CPU. */
338 static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
340 struct device *dev = &is->pdev->dev;
342 is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
343 &is->memory.paddr, GFP_KERNEL);
344 if (is->memory.vaddr == NULL)
347 is->memory.size = FIMC_IS_CPU_MEM_SIZE;
348 memset(is->memory.vaddr, 0, is->memory.size);
350 dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr);
352 if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) {
353 dev_err(dev, "invalid firmware memory alignment: %#x\n",
354 (u32)is->memory.paddr);
355 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
360 is->is_p_region = (struct is_region *)(is->memory.vaddr +
361 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
363 is->is_dma_p_region = is->memory.paddr +
364 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
366 is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
367 FIMC_IS_SHARED_REGION_OFFSET);
371 static void fimc_is_free_cpu_memory(struct fimc_is *is)
373 struct device *dev = &is->pdev->dev;
375 if (is->memory.vaddr == NULL)
378 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
382 static void fimc_is_load_firmware(const struct firmware *fw, void *context)
384 struct fimc_is *is = context;
385 struct device *dev = &is->pdev->dev;
390 dev_err(dev, "firmware request failed\n");
393 mutex_lock(&is->lock);
395 if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) {
396 dev_err(dev, "wrong firmware size: %zu\n", fw->size);
400 is->fw.size = fw->size;
402 ret = fimc_is_alloc_cpu_memory(is);
404 dev_err(dev, "failed to allocate FIMC-IS CPU memory\n");
408 memcpy(is->memory.vaddr, fw->data, fw->size);
411 /* Read firmware description. */
412 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
413 memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
414 is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
416 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
417 memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
418 is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
422 dev_info(dev, "loaded firmware: %s, rev. %s\n",
423 is->fw.info, is->fw.version);
424 dev_dbg(dev, "FW size: %zu, paddr: %pad\n", fw->size, &is->memory.paddr);
426 is->is_shared_region->chip_id = 0xe4412;
427 is->is_shared_region->chip_rev_no = 1;
429 fimc_is_mem_barrier();
432 * FIXME: The firmware is not being released for now, as it is
433 * needed around for copying to the IS working memory every
434 * time before the Cortex-A5 is restarted.
436 release_firmware(is->fw.f_w);
439 mutex_unlock(&is->lock);
442 static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name)
444 return reject_firmware_nowait(THIS_MODULE,
445 FW_ACTION_HOTPLUG, fw_name, &is->pdev->dev,
446 GFP_KERNEL, is, fimc_is_load_firmware);
449 /* General IS interrupt handler */
450 static void fimc_is_general_irq_handler(struct fimc_is *is)
452 is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
454 switch (is->i2h_cmd.cmd) {
455 case IHC_GET_SENSOR_NUM:
456 fimc_is_hw_get_params(is, 1);
457 fimc_is_hw_wait_intmsr0_intmsd0(is);
458 fimc_is_hw_set_sensor_num(is);
459 pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
461 case IHC_SET_FACE_MARK:
463 fimc_is_hw_get_params(is, 2);
465 case IHC_SET_SHOT_MARK:
468 fimc_is_hw_get_params(is, 3);
470 case IH_REPLY_NOT_DONE:
471 fimc_is_hw_get_params(is, 4);
476 pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
479 fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
481 switch (is->i2h_cmd.cmd) {
482 case IHC_GET_SENSOR_NUM:
483 fimc_is_hw_set_intgr0_gd0(is);
484 set_bit(IS_ST_A5_PWR_ON, &is->state);
487 case IHC_SET_SHOT_MARK:
490 case IHC_SET_FACE_MARK:
491 is->fd_header.count = is->i2h_cmd.args[0];
492 is->fd_header.index = is->i2h_cmd.args[1];
493 is->fd_header.offset = 0;
500 pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
501 is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
505 pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
507 switch (is->i2h_cmd.args[0]) {
508 case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
510 set_bit(IS_ST_CHANGE_MODE, &is->state);
511 is->isp.cac_margin_x = is->i2h_cmd.args[1];
512 is->isp.cac_margin_y = is->i2h_cmd.args[2];
513 pr_debug("CAC margin (x,y): (%d,%d)\n",
514 is->isp.cac_margin_x, is->isp.cac_margin_y);
518 clear_bit(IS_ST_STREAM_OFF, &is->state);
519 set_bit(IS_ST_STREAM_ON, &is->state);
523 clear_bit(IS_ST_STREAM_ON, &is->state);
524 set_bit(IS_ST_STREAM_OFF, &is->state);
527 case HIC_SET_PARAMETER:
528 is->config[is->config_index].p_region_index[0] = 0;
529 is->config[is->config_index].p_region_index[1] = 0;
530 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
531 pr_debug("HIC_SET_PARAMETER\n");
534 case HIC_GET_PARAMETER:
543 case HIC_OPEN_SENSOR:
544 set_bit(IS_ST_OPEN_SENSOR, &is->state);
545 pr_debug("data lanes: %d, settle line: %d\n",
546 is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
549 case HIC_CLOSE_SENSOR:
550 clear_bit(IS_ST_OPEN_SENSOR, &is->state);
551 is->sensor_index = 0;
555 pr_debug("config MSG level completed\n");
559 clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
562 case HIC_GET_SET_FILE_ADDR:
563 is->setfile.base = is->i2h_cmd.args[1];
564 set_bit(IS_ST_SETFILE_LOADED, &is->state);
567 case HIC_LOAD_SET_FILE:
568 set_bit(IS_ST_SETFILE_LOADED, &is->state);
573 case IH_REPLY_NOT_DONE:
574 pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
576 fimc_is_strerr(is->i2h_cmd.args[1]));
578 if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
579 pr_err("IS_ERROR_TIME_OUT\n");
581 switch (is->i2h_cmd.args[1]) {
582 case IS_ERROR_SET_PARAMETER:
583 fimc_is_mem_barrier();
586 switch (is->i2h_cmd.args[0]) {
587 case HIC_SET_PARAMETER:
588 is->config[is->config_index].p_region_index[0] = 0;
589 is->config[is->config_index].p_region_index[1] = 0;
590 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
596 pr_err("IS control sequence error: Not Ready\n");
600 wake_up(&is->irq_queue);
603 static irqreturn_t fimc_is_irq_handler(int irq, void *priv)
605 struct fimc_is *is = priv;
609 spin_lock_irqsave(&is->slock, flags);
610 status = mcuctl_read(is, MCUCTL_REG_INTSR1);
612 if (status & (1UL << FIMC_IS_INT_GENERAL))
613 fimc_is_general_irq_handler(is);
615 if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP))
616 fimc_isp_irq_handler(is);
618 spin_unlock_irqrestore(&is->slock, flags);
622 static int fimc_is_hw_open_sensor(struct fimc_is *is,
623 struct fimc_is_sensor *sensor)
625 struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
627 fimc_is_hw_wait_intmsr0_intmsd0(is);
629 soe->self_calibration_mode = 1;
630 soe->actuator_type = 0;
631 soe->mipi_lane_num = 0;
634 soe->fast_open_sensor = 0;
635 soe->i2c_sclk = 88000000;
637 fimc_is_mem_barrier();
640 * Some user space use cases hang up here without this
641 * empirically chosen delay.
645 mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
646 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
647 mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
648 mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
649 mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
651 fimc_is_hw_set_intgr0_gd0(is);
653 return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
654 sensor->drvdata->open_timeout);
658 int fimc_is_hw_initialize(struct fimc_is *is)
660 const int config_ids[] = {
661 IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO,
662 IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO
664 struct device *dev = &is->pdev->dev;
668 /* Sensor initialization. Only one sensor is currently supported. */
669 ret = fimc_is_hw_open_sensor(is, &is->sensor[0]);
673 /* Get the setfile address. */
674 fimc_is_hw_get_setfile_addr(is);
676 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
677 FIMC_IS_CONFIG_TIMEOUT);
679 dev_err(dev, "get setfile address timed out\n");
682 pr_debug("setfile.base: %#x\n", is->setfile.base);
684 /* Load the setfile. */
685 fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3);
686 clear_bit(IS_ST_SETFILE_LOADED, &is->state);
687 fimc_is_hw_load_setfile(is);
688 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
689 FIMC_IS_CONFIG_TIMEOUT);
691 dev_err(dev, "loading setfile timed out\n");
695 pr_debug("setfile: base: %#x, size: %d\n",
696 is->setfile.base, is->setfile.size);
697 pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info);
699 /* Check magic number. */
700 if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] !=
701 FIMC_IS_MAGIC_NUMBER) {
702 dev_err(dev, "magic number error!\n");
706 pr_debug("shared region: %pad, parameter region: %pad\n",
707 &is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET,
708 &is->is_dma_p_region);
710 is->setfile.sub_index = 0;
713 fimc_is_hw_stream_off(is);
714 ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
715 FIMC_IS_CONFIG_TIMEOUT);
717 dev_err(dev, "stream off timeout\n");
721 /* Preserve previous mode. */
722 prev_id = is->config_index;
724 /* Set initial parameter values. */
725 for (i = 0; i < ARRAY_SIZE(config_ids); i++) {
726 is->config_index = config_ids[i];
727 fimc_is_set_initial_params(is);
728 ret = fimc_is_itf_s_param(is, true);
730 is->config_index = prev_id;
734 is->config_index = prev_id;
736 set_bit(IS_ST_INIT_DONE, &is->state);
737 dev_info(dev, "initialization sequence completed (%d)\n",
742 static int fimc_is_log_show(struct seq_file *s, void *data)
744 struct fimc_is *is = s->private;
745 const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
747 if (is->memory.vaddr == NULL) {
748 dev_err(&is->pdev->dev, "firmware memory is not initialized\n");
752 seq_printf(s, "%s\n", buf);
756 static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
758 return single_open(file, fimc_is_log_show, inode->i_private);
761 static const struct file_operations fimc_is_debugfs_fops = {
762 .open = fimc_is_debugfs_open,
765 .release = single_release,
768 static void fimc_is_debugfs_remove(struct fimc_is *is)
770 debugfs_remove_recursive(is->debugfs_entry);
771 is->debugfs_entry = NULL;
774 static int fimc_is_debugfs_create(struct fimc_is *is)
776 struct dentry *dentry;
778 is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
780 dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry,
781 is, &fimc_is_debugfs_fops);
783 fimc_is_debugfs_remove(is);
785 return is->debugfs_entry == NULL ? -EIO : 0;
788 static int fimc_is_runtime_resume(struct device *dev);
789 static int fimc_is_runtime_suspend(struct device *dev);
791 static int fimc_is_probe(struct platform_device *pdev)
793 struct device *dev = &pdev->dev;
796 struct device_node *node;
799 is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
806 init_waitqueue_head(&is->irq_queue);
807 spin_lock_init(&is->slock);
808 mutex_init(&is->lock);
810 ret = of_address_to_resource(dev->of_node, 0, &res);
814 is->regs = devm_ioremap_resource(dev, &res);
815 if (IS_ERR(is->regs))
816 return PTR_ERR(is->regs);
818 node = of_get_child_by_name(dev->of_node, "pmu");
822 is->pmu_regs = of_iomap(node, 0);
827 is->irq = irq_of_parse_and_map(dev->of_node, 0);
829 dev_err(dev, "no irq found\n");
834 ret = fimc_is_get_clocks(is);
838 platform_set_drvdata(pdev, is);
840 ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is);
842 dev_err(dev, "irq request failed\n");
845 pm_runtime_enable(dev);
847 if (!pm_runtime_enabled(dev)) {
848 ret = fimc_is_runtime_resume(dev);
853 ret = pm_runtime_get_sync(dev);
857 vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
859 ret = devm_of_platform_populate(dev);
864 * Register FIMC-IS V4L2 subdevs to this driver. The video nodes
865 * will be created within the subdev's registered() callback.
867 ret = fimc_is_register_subdevs(is);
871 ret = fimc_is_debugfs_create(is);
875 ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME);
879 pm_runtime_put_sync(dev);
881 dev_dbg(dev, "FIMC-IS registered successfully\n");
885 fimc_is_debugfs_remove(is);
887 fimc_is_unregister_subdevs(is);
889 if (!pm_runtime_enabled(dev))
890 fimc_is_runtime_suspend(dev);
892 free_irq(is->irq, is);
894 fimc_is_put_clocks(is);
896 iounmap(is->pmu_regs);
900 static int fimc_is_runtime_resume(struct device *dev)
902 struct fimc_is *is = dev_get_drvdata(dev);
905 ret = fimc_is_setup_clocks(is);
909 return fimc_is_enable_clocks(is);
912 static int fimc_is_runtime_suspend(struct device *dev)
914 struct fimc_is *is = dev_get_drvdata(dev);
916 fimc_is_disable_clocks(is);
920 #ifdef CONFIG_PM_SLEEP
921 static int fimc_is_resume(struct device *dev)
927 static int fimc_is_suspend(struct device *dev)
929 struct fimc_is *is = dev_get_drvdata(dev);
932 if (test_bit(IS_ST_A5_PWR_ON, &is->state))
937 #endif /* CONFIG_PM_SLEEP */
939 static int fimc_is_remove(struct platform_device *pdev)
941 struct device *dev = &pdev->dev;
942 struct fimc_is *is = dev_get_drvdata(dev);
944 pm_runtime_disable(dev);
945 pm_runtime_set_suspended(dev);
946 if (!pm_runtime_status_suspended(dev))
947 fimc_is_runtime_suspend(dev);
948 free_irq(is->irq, is);
949 fimc_is_unregister_subdevs(is);
950 vb2_dma_contig_clear_max_seg_size(dev);
951 fimc_is_put_clocks(is);
952 iounmap(is->pmu_regs);
953 fimc_is_debugfs_remove(is);
954 release_firmware(is->fw.f_w);
955 fimc_is_free_cpu_memory(is);
960 static const struct of_device_id fimc_is_of_match[] = {
961 { .compatible = "samsung,exynos4212-fimc-is" },
964 MODULE_DEVICE_TABLE(of, fimc_is_of_match);
966 static const struct dev_pm_ops fimc_is_pm_ops = {
967 SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
968 SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
972 static struct platform_driver fimc_is_driver = {
973 .probe = fimc_is_probe,
974 .remove = fimc_is_remove,
976 .of_match_table = fimc_is_of_match,
977 .name = FIMC_IS_DRV_NAME,
978 .pm = &fimc_is_pm_ops,
982 static int fimc_is_module_init(void)
986 ret = fimc_is_register_i2c_driver();
990 ret = platform_driver_register(&fimc_is_driver);
993 fimc_is_unregister_i2c_driver();
998 static void fimc_is_module_exit(void)
1000 fimc_is_unregister_i2c_driver();
1001 platform_driver_unregister(&fimc_is_driver);
1004 module_init(fimc_is_module_init);
1005 module_exit(fimc_is_module_exit);
1007 MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME);
1008 MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>");
1009 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1010 MODULE_LICENSE("GPL v2");