1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Samsung EXYNOS5 SoC series G-Scaler driver
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/types.h>
12 #include <linux/errno.h>
13 #include <linux/bug.h>
14 #include <linux/interrupt.h>
15 #include <linux/workqueue.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18 #include <linux/list.h>
20 #include <linux/slab.h>
21 #include <linux/clk.h>
23 #include <linux/of_device.h>
24 #include <media/v4l2-ioctl.h>
28 static const struct gsc_fmt gsc_formats[] = {
30 .pixelformat = V4L2_PIX_FMT_RGB565X,
36 .pixelformat = V4L2_PIX_FMT_BGR32,
42 .pixelformat = V4L2_PIX_FMT_YUYV,
49 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
51 .pixelformat = V4L2_PIX_FMT_UYVY,
58 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
60 .pixelformat = V4L2_PIX_FMT_VYUY,
67 .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
69 .pixelformat = V4L2_PIX_FMT_YVYU,
76 .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
78 .pixelformat = V4L2_PIX_FMT_YUV32,
86 .pixelformat = V4L2_PIX_FMT_YUV422P,
94 .pixelformat = V4L2_PIX_FMT_NV16,
102 .pixelformat = V4L2_PIX_FMT_NV16M,
110 .pixelformat = V4L2_PIX_FMT_NV61,
118 .pixelformat = V4L2_PIX_FMT_NV61M,
126 .pixelformat = V4L2_PIX_FMT_YUV420,
134 .pixelformat = V4L2_PIX_FMT_YVU420,
143 .pixelformat = V4L2_PIX_FMT_NV12,
151 .pixelformat = V4L2_PIX_FMT_NV21,
159 .pixelformat = V4L2_PIX_FMT_NV21M,
167 .pixelformat = V4L2_PIX_FMT_NV12M,
175 .pixelformat = V4L2_PIX_FMT_YUV420M,
176 .depth = { 8, 2, 2 },
183 .pixelformat = V4L2_PIX_FMT_YVU420M,
184 .depth = { 8, 2, 2 },
191 .pixelformat = V4L2_PIX_FMT_NV12MT_16X16,
201 const struct gsc_fmt *get_format(int index)
203 if (index >= ARRAY_SIZE(gsc_formats))
206 return (struct gsc_fmt *)&gsc_formats[index];
209 const struct gsc_fmt *find_fmt(u32 *pixelformat, u32 *mbus_code, u32 index)
211 const struct gsc_fmt *fmt, *def_fmt = NULL;
214 if (index >= ARRAY_SIZE(gsc_formats))
217 for (i = 0; i < ARRAY_SIZE(gsc_formats); ++i) {
219 if (pixelformat && fmt->pixelformat == *pixelformat)
221 if (mbus_code && fmt->mbus_code == *mbus_code)
230 void gsc_set_frame_size(struct gsc_frame *frame, int width, int height)
232 frame->f_width = width;
233 frame->f_height = height;
234 frame->crop.width = width;
235 frame->crop.height = height;
236 frame->crop.left = 0;
240 int gsc_cal_prescaler_ratio(struct gsc_variant *var, u32 src, u32 dst,
243 if ((dst > src) || (dst >= src / var->poly_sc_down_max)) {
248 if ((src / var->poly_sc_down_max / var->pre_sc_down_max) > dst) {
249 pr_err("Exceeded maximum downscaling ratio (1/16))");
253 *ratio = (dst > (src / 8)) ? 2 : 4;
258 void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *sh)
260 if (hratio == 4 && vratio == 4)
262 else if ((hratio == 4 && vratio == 2) ||
263 (hratio == 2 && vratio == 4))
265 else if ((hratio == 4 && vratio == 1) ||
266 (hratio == 1 && vratio == 4) ||
267 (hratio == 2 && vratio == 2))
269 else if (hratio == 1 && vratio == 1)
275 void gsc_check_src_scale_info(struct gsc_variant *var,
276 struct gsc_frame *s_frame, u32 *wratio,
277 u32 tx, u32 ty, u32 *hratio)
279 int remainder = 0, walign, halign;
281 if (is_yuv420(s_frame->fmt->color)) {
282 walign = GSC_SC_ALIGN_4;
283 halign = GSC_SC_ALIGN_4;
284 } else if (is_yuv422(s_frame->fmt->color)) {
285 walign = GSC_SC_ALIGN_4;
286 halign = GSC_SC_ALIGN_2;
288 walign = GSC_SC_ALIGN_2;
289 halign = GSC_SC_ALIGN_2;
292 remainder = s_frame->crop.width % (*wratio * walign);
294 s_frame->crop.width -= remainder;
295 gsc_cal_prescaler_ratio(var, s_frame->crop.width, tx, wratio);
296 pr_info("cropped src width size is recalculated from %d to %d",
297 s_frame->crop.width + remainder, s_frame->crop.width);
300 remainder = s_frame->crop.height % (*hratio * halign);
302 s_frame->crop.height -= remainder;
303 gsc_cal_prescaler_ratio(var, s_frame->crop.height, ty, hratio);
304 pr_info("cropped src height size is recalculated from %d to %d",
305 s_frame->crop.height + remainder, s_frame->crop.height);
309 int gsc_enum_fmt(struct v4l2_fmtdesc *f)
311 const struct gsc_fmt *fmt;
313 fmt = find_fmt(NULL, NULL, f->index);
317 f->pixelformat = fmt->pixelformat;
322 static int get_plane_info(struct gsc_frame *frm, u32 addr, u32 *index, u32 *ret_addr)
324 if (frm->addr.y == addr) {
326 *ret_addr = frm->addr.y;
327 } else if (frm->addr.cb == addr) {
329 *ret_addr = frm->addr.cb;
330 } else if (frm->addr.cr == addr) {
332 *ret_addr = frm->addr.cr;
334 pr_err("Plane address is wrong");
340 void gsc_set_prefbuf(struct gsc_dev *gsc, struct gsc_frame *frm)
342 u32 f_chk_addr, f_chk_len, s_chk_addr, s_chk_len;
343 f_chk_addr = f_chk_len = s_chk_addr = s_chk_len = 0;
345 f_chk_addr = frm->addr.y;
346 f_chk_len = frm->payload[0];
347 if (frm->fmt->num_planes == 2) {
348 s_chk_addr = frm->addr.cb;
349 s_chk_len = frm->payload[1];
350 } else if (frm->fmt->num_planes == 3) {
351 u32 low_addr, low_plane, mid_addr, mid_plane;
352 u32 high_addr, high_plane;
355 t_min = min3(frm->addr.y, frm->addr.cb, frm->addr.cr);
356 if (get_plane_info(frm, t_min, &low_plane, &low_addr))
358 t_max = max3(frm->addr.y, frm->addr.cb, frm->addr.cr);
359 if (get_plane_info(frm, t_max, &high_plane, &high_addr))
362 mid_plane = 3 - (low_plane + high_plane);
364 mid_addr = frm->addr.y;
365 else if (mid_plane == 1)
366 mid_addr = frm->addr.cb;
367 else if (mid_plane == 2)
368 mid_addr = frm->addr.cr;
372 f_chk_addr = low_addr;
373 if (mid_addr + frm->payload[mid_plane] - low_addr >
374 high_addr + frm->payload[high_plane] - mid_addr) {
375 f_chk_len = frm->payload[low_plane];
376 s_chk_addr = mid_addr;
377 s_chk_len = high_addr +
378 frm->payload[high_plane] - mid_addr;
380 f_chk_len = mid_addr +
381 frm->payload[mid_plane] - low_addr;
382 s_chk_addr = high_addr;
383 s_chk_len = frm->payload[high_plane];
386 pr_debug("f_addr = 0x%08x, f_len = %d, s_addr = 0x%08x, s_len = %d\n",
387 f_chk_addr, f_chk_len, s_chk_addr, s_chk_len);
390 int gsc_try_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f)
392 struct gsc_dev *gsc = ctx->gsc_dev;
393 struct gsc_variant *variant = gsc->variant;
394 struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
395 const struct gsc_fmt *fmt;
396 u32 max_w, max_h, mod_x, mod_y;
397 u32 min_w, min_h, tmp_w, tmp_h;
400 pr_debug("user put w: %d, h: %d", pix_mp->width, pix_mp->height);
402 fmt = find_fmt(&pix_mp->pixelformat, NULL, 0);
404 pr_err("pixelformat format (0x%X) invalid\n",
405 pix_mp->pixelformat);
409 if (pix_mp->field == V4L2_FIELD_ANY)
410 pix_mp->field = V4L2_FIELD_NONE;
411 else if (pix_mp->field != V4L2_FIELD_NONE) {
412 pr_debug("Not supported field order(%d)\n", pix_mp->field);
416 max_w = variant->pix_max->target_rot_dis_w;
417 max_h = variant->pix_max->target_rot_dis_h;
419 mod_x = ffs(variant->pix_align->org_w) - 1;
420 if (is_yuv420(fmt->color))
421 mod_y = ffs(variant->pix_align->org_h) - 1;
423 mod_y = ffs(variant->pix_align->org_h) - 2;
425 if (V4L2_TYPE_IS_OUTPUT(f->type)) {
426 min_w = variant->pix_min->org_w;
427 min_h = variant->pix_min->org_h;
429 min_w = variant->pix_min->target_rot_dis_w;
430 min_h = variant->pix_min->target_rot_dis_h;
431 pix_mp->colorspace = ctx->out_colorspace;
434 pr_debug("mod_x: %d, mod_y: %d, max_w: %d, max_h = %d",
435 mod_x, mod_y, max_w, max_h);
437 /* To check if image size is modified to adjust parameter against
438 hardware abilities */
439 tmp_w = pix_mp->width;
440 tmp_h = pix_mp->height;
442 v4l_bound_align_image(&pix_mp->width, min_w, max_w, mod_x,
443 &pix_mp->height, min_h, max_h, mod_y, 0);
444 if (tmp_w != pix_mp->width || tmp_h != pix_mp->height)
445 pr_debug("Image size has been modified from %dx%d to %dx%d\n",
446 tmp_w, tmp_h, pix_mp->width, pix_mp->height);
448 pix_mp->num_planes = fmt->num_planes;
450 if (V4L2_TYPE_IS_OUTPUT(f->type))
451 ctx->out_colorspace = pix_mp->colorspace;
453 for (i = 0; i < pix_mp->num_planes; ++i) {
454 struct v4l2_plane_pix_format *plane_fmt = &pix_mp->plane_fmt[i];
455 u32 bpl = plane_fmt->bytesperline;
457 if (fmt->num_comp == 1 && /* Packed */
458 (bpl == 0 || (bpl * 8 / fmt->depth[i]) < pix_mp->width))
459 bpl = pix_mp->width * fmt->depth[i] / 8;
461 if (fmt->num_comp > 1 && /* Planar */
462 (bpl == 0 || bpl < pix_mp->width))
465 if (i != 0 && fmt->num_comp == 3)
468 plane_fmt->bytesperline = bpl;
469 plane_fmt->sizeimage = max(pix_mp->width * pix_mp->height *
471 plane_fmt->sizeimage);
472 pr_debug("[%d]: bpl: %d, sizeimage: %d",
473 i, bpl, pix_mp->plane_fmt[i].sizeimage);
479 int gsc_g_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f)
481 struct gsc_frame *frame;
482 struct v4l2_pix_format_mplane *pix_mp;
485 frame = ctx_get_frame(ctx, f->type);
487 return PTR_ERR(frame);
489 pix_mp = &f->fmt.pix_mp;
491 pix_mp->width = frame->f_width;
492 pix_mp->height = frame->f_height;
493 pix_mp->field = V4L2_FIELD_NONE;
494 pix_mp->pixelformat = frame->fmt->pixelformat;
495 pix_mp->num_planes = frame->fmt->num_planes;
496 pix_mp->colorspace = ctx->out_colorspace;
498 for (i = 0; i < pix_mp->num_planes; ++i) {
499 pix_mp->plane_fmt[i].bytesperline = (frame->f_width *
500 frame->fmt->depth[i]) / 8;
501 pix_mp->plane_fmt[i].sizeimage =
502 pix_mp->plane_fmt[i].bytesperline * frame->f_height;
508 void gsc_check_crop_change(u32 tmp_w, u32 tmp_h, u32 *w, u32 *h)
510 if (tmp_w != *w || tmp_h != *h) {
511 pr_info("Cropped size has been modified from %dx%d to %dx%d",
512 *w, *h, tmp_w, tmp_h);
518 int gsc_try_selection(struct gsc_ctx *ctx, struct v4l2_selection *s)
521 struct gsc_dev *gsc = ctx->gsc_dev;
522 struct gsc_variant *variant = gsc->variant;
523 u32 mod_x = 0, mod_y = 0, tmp_w, tmp_h;
524 u32 min_w, min_h, max_w, max_h;
526 if (s->r.top < 0 || s->r.left < 0) {
527 pr_err("doesn't support negative values for top & left\n");
530 pr_debug("user put w: %d, h: %d", s->r.width, s->r.height);
532 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
534 else if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
544 if (V4L2_TYPE_IS_OUTPUT(s->type)) {
545 if ((is_yuv422(f->fmt->color) && f->fmt->num_comp == 1) ||
546 is_rgb(f->fmt->color))
550 if ((is_yuv422(f->fmt->color) && f->fmt->num_comp == 3) ||
551 is_yuv420(f->fmt->color))
556 if (is_yuv420(f->fmt->color) || is_yuv422(f->fmt->color))
557 mod_x = ffs(variant->pix_align->target_w) - 1;
558 if (is_yuv420(f->fmt->color))
559 mod_y = ffs(variant->pix_align->target_h) - 1;
560 if (ctx->gsc_ctrls.rotate->val == 90 ||
561 ctx->gsc_ctrls.rotate->val == 270) {
564 min_w = variant->pix_min->target_rot_en_w;
565 min_h = variant->pix_min->target_rot_en_h;
569 min_w = variant->pix_min->target_rot_dis_w;
570 min_h = variant->pix_min->target_rot_dis_h;
573 pr_debug("mod_x: %d, mod_y: %d, min_w: %d, min_h = %d",
574 mod_x, mod_y, min_w, min_h);
575 pr_debug("tmp_w : %d, tmp_h : %d", tmp_w, tmp_h);
577 v4l_bound_align_image(&tmp_w, min_w, max_w, mod_x,
578 &tmp_h, min_h, max_h, mod_y, 0);
580 if (V4L2_TYPE_IS_CAPTURE(s->type) &&
581 (ctx->gsc_ctrls.rotate->val == 90 ||
582 ctx->gsc_ctrls.rotate->val == 270))
583 gsc_check_crop_change(tmp_h, tmp_w,
584 &s->r.width, &s->r.height);
586 gsc_check_crop_change(tmp_w, tmp_h,
587 &s->r.width, &s->r.height);
590 /* adjust left/top if cropping rectangle is out of bounds */
591 /* Need to add code to algin left value with 2's multiple */
592 if (s->r.left + tmp_w > max_w)
593 s->r.left = max_w - tmp_w;
594 if (s->r.top + tmp_h > max_h)
595 s->r.top = max_h - tmp_h;
597 if ((is_yuv420(f->fmt->color) || is_yuv422(f->fmt->color)) &&
601 pr_debug("Aligned l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
602 s->r.left, s->r.top, s->r.width, s->r.height, max_w, max_h);
607 int gsc_check_scaler_ratio(struct gsc_variant *var, int sw, int sh, int dw,
608 int dh, int rot, int out_path)
610 int tmp_w, tmp_h, sc_down_max;
612 if (out_path == GSC_DMA)
613 sc_down_max = var->sc_down_max;
615 sc_down_max = var->local_sc_down;
617 if (rot == 90 || rot == 270) {
625 if ((sw / tmp_w) > sc_down_max ||
626 (sh / tmp_h) > sc_down_max ||
627 (tmp_w / sw) > var->sc_up_max ||
628 (tmp_h / sh) > var->sc_up_max)
634 int gsc_set_scaler_info(struct gsc_ctx *ctx)
636 struct gsc_scaler *sc = &ctx->scaler;
637 struct gsc_frame *s_frame = &ctx->s_frame;
638 struct gsc_frame *d_frame = &ctx->d_frame;
639 struct gsc_variant *variant = ctx->gsc_dev->variant;
640 struct device *dev = &ctx->gsc_dev->pdev->dev;
644 ret = gsc_check_scaler_ratio(variant, s_frame->crop.width,
645 s_frame->crop.height, d_frame->crop.width, d_frame->crop.height,
646 ctx->gsc_ctrls.rotate->val, ctx->out_path);
648 pr_err("out of scaler range");
652 if (ctx->gsc_ctrls.rotate->val == 90 ||
653 ctx->gsc_ctrls.rotate->val == 270) {
654 ty = d_frame->crop.width;
655 tx = d_frame->crop.height;
657 tx = d_frame->crop.width;
658 ty = d_frame->crop.height;
661 if (tx <= 0 || ty <= 0) {
662 dev_err(dev, "Invalid target size: %dx%d", tx, ty);
666 ret = gsc_cal_prescaler_ratio(variant, s_frame->crop.width,
667 tx, &sc->pre_hratio);
669 pr_err("Horizontal scale ratio is out of range");
673 ret = gsc_cal_prescaler_ratio(variant, s_frame->crop.height,
674 ty, &sc->pre_vratio);
676 pr_err("Vertical scale ratio is out of range");
680 gsc_check_src_scale_info(variant, s_frame, &sc->pre_hratio,
681 tx, ty, &sc->pre_vratio);
683 gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
686 sc->main_hratio = (s_frame->crop.width << 16) / tx;
687 sc->main_vratio = (s_frame->crop.height << 16) / ty;
689 pr_debug("scaler input/output size : sx = %d, sy = %d, tx = %d, ty = %d",
690 s_frame->crop.width, s_frame->crop.height, tx, ty);
691 pr_debug("scaler ratio info : pre_shfactor : %d, pre_h : %d",
692 sc->pre_shfactor, sc->pre_hratio);
693 pr_debug("pre_v :%d, main_h : %d, main_v : %d",
694 sc->pre_vratio, sc->main_hratio, sc->main_vratio);
699 static int __gsc_s_ctrl(struct gsc_ctx *ctx, struct v4l2_ctrl *ctrl)
701 struct gsc_dev *gsc = ctx->gsc_dev;
702 struct gsc_variant *variant = gsc->variant;
703 unsigned int flags = GSC_DST_FMT | GSC_SRC_FMT;
706 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
711 ctx->hflip = ctrl->val;
715 ctx->vflip = ctrl->val;
718 case V4L2_CID_ROTATE:
719 if ((ctx->state & flags) == flags) {
720 ret = gsc_check_scaler_ratio(variant,
721 ctx->s_frame.crop.width,
722 ctx->s_frame.crop.height,
723 ctx->d_frame.crop.width,
724 ctx->d_frame.crop.height,
725 ctx->gsc_ctrls.rotate->val,
732 ctx->rotation = ctrl->val;
735 case V4L2_CID_ALPHA_COMPONENT:
736 ctx->d_frame.alpha = ctrl->val;
740 ctx->state |= GSC_PARAMS;
744 static int gsc_s_ctrl(struct v4l2_ctrl *ctrl)
746 struct gsc_ctx *ctx = ctrl_to_ctx(ctrl);
750 spin_lock_irqsave(&ctx->gsc_dev->slock, flags);
751 ret = __gsc_s_ctrl(ctx, ctrl);
752 spin_unlock_irqrestore(&ctx->gsc_dev->slock, flags);
757 static const struct v4l2_ctrl_ops gsc_ctrl_ops = {
758 .s_ctrl = gsc_s_ctrl,
761 int gsc_ctrls_create(struct gsc_ctx *ctx)
763 if (ctx->ctrls_rdy) {
764 pr_err("Control handler of this context was created already");
768 v4l2_ctrl_handler_init(&ctx->ctrl_handler, GSC_MAX_CTRL_NUM);
770 ctx->gsc_ctrls.rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler,
771 &gsc_ctrl_ops, V4L2_CID_ROTATE, 0, 270, 90, 0);
772 ctx->gsc_ctrls.hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler,
773 &gsc_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
774 ctx->gsc_ctrls.vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler,
775 &gsc_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
776 ctx->gsc_ctrls.global_alpha = v4l2_ctrl_new_std(&ctx->ctrl_handler,
777 &gsc_ctrl_ops, V4L2_CID_ALPHA_COMPONENT, 0, 255, 1, 0);
779 ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
781 if (ctx->ctrl_handler.error) {
782 int err = ctx->ctrl_handler.error;
783 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
784 pr_err("Failed to create G-Scaler control handlers");
791 void gsc_ctrls_delete(struct gsc_ctx *ctx)
793 if (ctx->ctrls_rdy) {
794 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
795 ctx->ctrls_rdy = false;
799 /* The color format (num_comp, num_planes) must be already configured. */
800 int gsc_prepare_addr(struct gsc_ctx *ctx, struct vb2_buffer *vb,
801 struct gsc_frame *frame, struct gsc_addr *addr)
806 if ((vb == NULL) || (frame == NULL))
809 pix_size = frame->f_width * frame->f_height;
811 pr_debug("num_planes= %d, num_comp= %d, pix_size= %d",
812 frame->fmt->num_planes, frame->fmt->num_comp, pix_size);
814 addr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
816 if (frame->fmt->num_planes == 1) {
817 switch (frame->fmt->num_comp) {
823 /* decompose Y into Y/Cb */
824 addr->cb = (dma_addr_t)(addr->y + pix_size);
828 /* decompose Y into Y/Cb/Cr */
829 addr->cb = (dma_addr_t)(addr->y + pix_size);
830 if (GSC_YUV420 == frame->fmt->color)
831 addr->cr = (dma_addr_t)(addr->cb
834 addr->cr = (dma_addr_t)(addr->cb
838 pr_err("Invalid the number of color planes");
842 if (frame->fmt->num_planes >= 2)
843 addr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
845 if (frame->fmt->num_planes == 3)
846 addr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
849 if ((frame->fmt->pixelformat == V4L2_PIX_FMT_VYUY) ||
850 (frame->fmt->pixelformat == V4L2_PIX_FMT_YVYU) ||
851 (frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420) ||
852 (frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420M))
853 swap(addr->cb, addr->cr);
855 pr_debug("ADDR: y= %pad cb= %pad cr= %pad ret= %d",
856 &addr->y, &addr->cb, &addr->cr, ret);
861 static irqreturn_t gsc_irq_handler(int irq, void *priv)
863 struct gsc_dev *gsc = priv;
867 gsc_irq = gsc_hw_get_irq_status(gsc);
868 gsc_hw_clear_irq(gsc, gsc_irq);
870 if (gsc_irq == GSC_IRQ_OVERRUN) {
871 pr_err("Local path input over-run interrupt has occurred!\n");
875 spin_lock(&gsc->slock);
877 if (test_and_clear_bit(ST_M2M_PEND, &gsc->state)) {
879 gsc_hw_enable_control(gsc, false);
881 if (test_and_clear_bit(ST_M2M_SUSPENDING, &gsc->state)) {
882 set_bit(ST_M2M_SUSPENDED, &gsc->state);
883 wake_up(&gsc->irq_queue);
886 ctx = v4l2_m2m_get_curr_priv(gsc->m2m.m2m_dev);
888 if (!ctx || !ctx->m2m_ctx)
891 spin_unlock(&gsc->slock);
892 gsc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
894 /* wake_up job_abort, stop_streaming */
895 if (ctx->state & GSC_CTX_STOP_REQ) {
896 ctx->state &= ~GSC_CTX_STOP_REQ;
897 wake_up(&gsc->irq_queue);
903 spin_unlock(&gsc->slock);
907 static struct gsc_pix_max gsc_v_100_max = {
908 .org_scaler_bypass_w = 8192,
909 .org_scaler_bypass_h = 8192,
910 .org_scaler_input_w = 4800,
911 .org_scaler_input_h = 3344,
912 .real_rot_dis_w = 4800,
913 .real_rot_dis_h = 3344,
914 .real_rot_en_w = 2047,
915 .real_rot_en_h = 2047,
916 .target_rot_dis_w = 4800,
917 .target_rot_dis_h = 3344,
918 .target_rot_en_w = 2016,
919 .target_rot_en_h = 2016,
922 static struct gsc_pix_max gsc_v_5250_max = {
923 .org_scaler_bypass_w = 8192,
924 .org_scaler_bypass_h = 8192,
925 .org_scaler_input_w = 4800,
926 .org_scaler_input_h = 3344,
927 .real_rot_dis_w = 4800,
928 .real_rot_dis_h = 3344,
929 .real_rot_en_w = 2016,
930 .real_rot_en_h = 2016,
931 .target_rot_dis_w = 4800,
932 .target_rot_dis_h = 3344,
933 .target_rot_en_w = 2016,
934 .target_rot_en_h = 2016,
937 static struct gsc_pix_max gsc_v_5420_max = {
938 .org_scaler_bypass_w = 8192,
939 .org_scaler_bypass_h = 8192,
940 .org_scaler_input_w = 4800,
941 .org_scaler_input_h = 3344,
942 .real_rot_dis_w = 4800,
943 .real_rot_dis_h = 3344,
944 .real_rot_en_w = 2048,
945 .real_rot_en_h = 2048,
946 .target_rot_dis_w = 4800,
947 .target_rot_dis_h = 3344,
948 .target_rot_en_w = 2016,
949 .target_rot_en_h = 2016,
952 static struct gsc_pix_max gsc_v_5433_max = {
953 .org_scaler_bypass_w = 8192,
954 .org_scaler_bypass_h = 8192,
955 .org_scaler_input_w = 4800,
956 .org_scaler_input_h = 3344,
957 .real_rot_dis_w = 4800,
958 .real_rot_dis_h = 3344,
959 .real_rot_en_w = 2047,
960 .real_rot_en_h = 2047,
961 .target_rot_dis_w = 4800,
962 .target_rot_dis_h = 3344,
963 .target_rot_en_w = 2016,
964 .target_rot_en_h = 2016,
967 static struct gsc_pix_min gsc_v_100_min = {
972 .target_rot_dis_w = 64,
973 .target_rot_dis_h = 32,
974 .target_rot_en_w = 32,
975 .target_rot_en_h = 16,
978 static struct gsc_pix_align gsc_v_100_align = {
980 .org_w = 16, /* yuv420 : 16, others : 8 */
981 .offset_h = 2, /* yuv420/422 : 2, others : 1 */
982 .real_w = 16, /* yuv420/422 : 4~16, others : 2~8 */
983 .real_h = 16, /* yuv420 : 4~16, others : 1 */
984 .target_w = 2, /* yuv420/422 : 2, others : 1 */
985 .target_h = 2, /* yuv420 : 2, others : 1 */
988 static struct gsc_variant gsc_v_100_variant = {
989 .pix_max = &gsc_v_100_max,
990 .pix_min = &gsc_v_100_min,
991 .pix_align = &gsc_v_100_align,
996 .poly_sc_down_max = 4,
997 .pre_sc_down_max = 4,
1001 static struct gsc_variant gsc_v_5250_variant = {
1002 .pix_max = &gsc_v_5250_max,
1003 .pix_min = &gsc_v_100_min,
1004 .pix_align = &gsc_v_100_align,
1009 .poly_sc_down_max = 4,
1010 .pre_sc_down_max = 4,
1014 static struct gsc_variant gsc_v_5420_variant = {
1015 .pix_max = &gsc_v_5420_max,
1016 .pix_min = &gsc_v_100_min,
1017 .pix_align = &gsc_v_100_align,
1022 .poly_sc_down_max = 4,
1023 .pre_sc_down_max = 4,
1027 static struct gsc_variant gsc_v_5433_variant = {
1028 .pix_max = &gsc_v_5433_max,
1029 .pix_min = &gsc_v_100_min,
1030 .pix_align = &gsc_v_100_align,
1035 .poly_sc_down_max = 4,
1036 .pre_sc_down_max = 4,
1040 static struct gsc_driverdata gsc_v_100_drvdata = {
1042 [0] = &gsc_v_100_variant,
1043 [1] = &gsc_v_100_variant,
1044 [2] = &gsc_v_100_variant,
1045 [3] = &gsc_v_100_variant,
1048 .clk_names = { "gscl" },
1052 static struct gsc_driverdata gsc_v_5250_drvdata = {
1054 [0] = &gsc_v_5250_variant,
1055 [1] = &gsc_v_5250_variant,
1056 [2] = &gsc_v_5250_variant,
1057 [3] = &gsc_v_5250_variant,
1060 .clk_names = { "gscl" },
1064 static struct gsc_driverdata gsc_v_5420_drvdata = {
1066 [0] = &gsc_v_5420_variant,
1067 [1] = &gsc_v_5420_variant,
1070 .clk_names = { "gscl" },
1074 static struct gsc_driverdata gsc_5433_drvdata = {
1076 [0] = &gsc_v_5433_variant,
1077 [1] = &gsc_v_5433_variant,
1078 [2] = &gsc_v_5433_variant,
1081 .clk_names = { "pclk", "aclk", "aclk_xiu", "aclk_gsclbend" },
1085 static const struct of_device_id exynos_gsc_match[] = {
1087 .compatible = "samsung,exynos5250-gsc",
1088 .data = &gsc_v_5250_drvdata,
1091 .compatible = "samsung,exynos5420-gsc",
1092 .data = &gsc_v_5420_drvdata,
1095 .compatible = "samsung,exynos5433-gsc",
1096 .data = &gsc_5433_drvdata,
1099 .compatible = "samsung,exynos5-gsc",
1100 .data = &gsc_v_100_drvdata,
1104 MODULE_DEVICE_TABLE(of, exynos_gsc_match);
1106 static int gsc_probe(struct platform_device *pdev)
1108 struct gsc_dev *gsc;
1109 struct resource *res;
1110 struct device *dev = &pdev->dev;
1111 const struct gsc_driverdata *drv_data = of_device_get_match_data(dev);
1115 gsc = devm_kzalloc(dev, sizeof(struct gsc_dev), GFP_KERNEL);
1119 ret = of_alias_get_id(pdev->dev.of_node, "gsc");
1123 if (drv_data == &gsc_v_100_drvdata)
1124 dev_info(dev, "compatible 'exynos5-gsc' is deprecated\n");
1127 if (gsc->id >= drv_data->num_entities) {
1128 dev_err(dev, "Invalid platform device id: %d\n", gsc->id);
1132 gsc->num_clocks = drv_data->num_clocks;
1133 gsc->variant = drv_data->variant[gsc->id];
1136 init_waitqueue_head(&gsc->irq_queue);
1137 spin_lock_init(&gsc->slock);
1138 mutex_init(&gsc->lock);
1140 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1141 gsc->regs = devm_ioremap_resource(dev, res);
1142 if (IS_ERR(gsc->regs))
1143 return PTR_ERR(gsc->regs);
1145 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1147 dev_err(dev, "failed to get IRQ resource\n");
1151 for (i = 0; i < gsc->num_clocks; i++) {
1152 gsc->clock[i] = devm_clk_get(dev, drv_data->clk_names[i]);
1153 if (IS_ERR(gsc->clock[i])) {
1154 dev_err(dev, "failed to get clock: %s\n",
1155 drv_data->clk_names[i]);
1156 return PTR_ERR(gsc->clock[i]);
1160 for (i = 0; i < gsc->num_clocks; i++) {
1161 ret = clk_prepare_enable(gsc->clock[i]);
1163 dev_err(dev, "clock prepare failed for clock: %s\n",
1164 drv_data->clk_names[i]);
1166 clk_disable_unprepare(gsc->clock[i]);
1171 ret = devm_request_irq(dev, res->start, gsc_irq_handler,
1172 0, pdev->name, gsc);
1174 dev_err(dev, "failed to install irq (%d)\n", ret);
1178 ret = v4l2_device_register(dev, &gsc->v4l2_dev);
1182 ret = gsc_register_m2m_device(gsc);
1186 platform_set_drvdata(pdev, gsc);
1188 gsc_hw_set_sw_reset(gsc);
1189 gsc_wait_reset(gsc);
1191 vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
1193 dev_dbg(dev, "gsc-%d registered successfully\n", gsc->id);
1195 pm_runtime_set_active(dev);
1196 pm_runtime_enable(dev);
1201 v4l2_device_unregister(&gsc->v4l2_dev);
1203 for (i = gsc->num_clocks - 1; i >= 0; i--)
1204 clk_disable_unprepare(gsc->clock[i]);
1208 static int gsc_remove(struct platform_device *pdev)
1210 struct gsc_dev *gsc = platform_get_drvdata(pdev);
1213 pm_runtime_get_sync(&pdev->dev);
1215 gsc_unregister_m2m_device(gsc);
1216 v4l2_device_unregister(&gsc->v4l2_dev);
1218 vb2_dma_contig_clear_max_seg_size(&pdev->dev);
1219 for (i = 0; i < gsc->num_clocks; i++)
1220 clk_disable_unprepare(gsc->clock[i]);
1222 pm_runtime_put_noidle(&pdev->dev);
1223 pm_runtime_disable(&pdev->dev);
1225 dev_dbg(&pdev->dev, "%s driver unloaded\n", pdev->name);
1230 static int gsc_m2m_suspend(struct gsc_dev *gsc)
1232 unsigned long flags;
1235 spin_lock_irqsave(&gsc->slock, flags);
1236 if (!gsc_m2m_pending(gsc)) {
1237 spin_unlock_irqrestore(&gsc->slock, flags);
1240 clear_bit(ST_M2M_SUSPENDED, &gsc->state);
1241 set_bit(ST_M2M_SUSPENDING, &gsc->state);
1242 spin_unlock_irqrestore(&gsc->slock, flags);
1244 timeout = wait_event_timeout(gsc->irq_queue,
1245 test_bit(ST_M2M_SUSPENDED, &gsc->state),
1246 GSC_SHUTDOWN_TIMEOUT);
1248 clear_bit(ST_M2M_SUSPENDING, &gsc->state);
1249 return timeout == 0 ? -EAGAIN : 0;
1252 static void gsc_m2m_resume(struct gsc_dev *gsc)
1254 struct gsc_ctx *ctx;
1255 unsigned long flags;
1257 spin_lock_irqsave(&gsc->slock, flags);
1258 /* Clear for full H/W setup in first run after resume */
1260 gsc->m2m.ctx = NULL;
1261 spin_unlock_irqrestore(&gsc->slock, flags);
1263 if (test_and_clear_bit(ST_M2M_SUSPENDED, &gsc->state))
1264 gsc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
1267 static int gsc_runtime_resume(struct device *dev)
1269 struct gsc_dev *gsc = dev_get_drvdata(dev);
1273 pr_debug("gsc%d: state: 0x%lx\n", gsc->id, gsc->state);
1275 for (i = 0; i < gsc->num_clocks; i++) {
1276 ret = clk_prepare_enable(gsc->clock[i]);
1279 clk_disable_unprepare(gsc->clock[i]);
1284 gsc_hw_set_sw_reset(gsc);
1285 gsc_wait_reset(gsc);
1286 gsc_m2m_resume(gsc);
1291 static int gsc_runtime_suspend(struct device *dev)
1293 struct gsc_dev *gsc = dev_get_drvdata(dev);
1297 ret = gsc_m2m_suspend(gsc);
1301 for (i = gsc->num_clocks - 1; i >= 0; i--)
1302 clk_disable_unprepare(gsc->clock[i]);
1304 pr_debug("gsc%d: state: 0x%lx\n", gsc->id, gsc->state);
1309 static const struct dev_pm_ops gsc_pm_ops = {
1310 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1311 pm_runtime_force_resume)
1312 SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
1315 static struct platform_driver gsc_driver = {
1317 .remove = gsc_remove,
1319 .name = GSC_MODULE_NAME,
1321 .of_match_table = exynos_gsc_match,
1325 module_platform_driver(gsc_driver);
1327 MODULE_AUTHOR("Hyunwong Kim <khw0178.kim@samsung.com>");
1328 MODULE_DESCRIPTION("Samsung EXYNOS5 Soc series G-Scaler driver");
1329 MODULE_LICENSE("GPL");