drivers/media/platform/davinci/vpif.c

   1 /*
   2  * vpif - Video Port Interface driver
   3  * VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
   4  * that receiveing video byte stream and two channels(2, 3) for video output.
   5  * The hardware supports SDTV, HDTV formats, raw data capture.
   6  * Currently, the driver supports NTSC and PAL standards.
   7  *
   8  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation version 2.
  13  *
  14  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  15  * kind, whether express or implied; without even the implied warranty
  16  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <linux/err.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/v4l2-dv-timings.h>
  29 #include <linux/of_graph.h>
  30
  31 #include "vpif.h"
  32
  33 MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");
  34 MODULE_LICENSE("GPL");
  35
  36 #define VPIF_DRIVER_NAME        "vpif"
  37 MODULE_ALIAS("platform:" VPIF_DRIVER_NAME);
  38
  39 #define VPIF_CH0_MAX_MODES      22
  40 #define VPIF_CH1_MAX_MODES      2
  41 #define VPIF_CH2_MAX_MODES      15
  42 #define VPIF_CH3_MAX_MODES      2
  43
  44 spinlock_t vpif_lock;
  45 EXPORT_SYMBOL_GPL(vpif_lock);
  46
  47 void __iomem *vpif_base;
  48 EXPORT_SYMBOL_GPL(vpif_base);
  49
  50 /**
  51  * vpif_ch_params: video standard configuration parameters for vpif
  52  * The table must include all presets from supported subdevices.
  53  */
  54 const struct vpif_channel_config_params vpif_ch_params[] = {
  55         /* HDTV formats */
  56         {
  57                 .name = "480p59_94",
  58                 .width = 720,
  59                 .height = 480,
  60                 .frm_fmt = 1,
  61                 .ycmux_mode = 0,
  62                 .eav2sav = 138-8,
  63                 .sav2eav = 720,
  64                 .l1 = 1,
  65                 .l3 = 43,
  66                 .l5 = 523,
  67                 .vsize = 525,
  68                 .capture_format = 0,
  69                 .vbi_supported = 0,
  70                 .hd_sd = 1,
  71                 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
  72         },
  73         {
  74                 .name = "576p50",
  75                 .width = 720,
  76                 .height = 576,
  77                 .frm_fmt = 1,
  78                 .ycmux_mode = 0,
  79                 .eav2sav = 144-8,
  80                 .sav2eav = 720,
  81                 .l1 = 1,
  82                 .l3 = 45,
  83                 .l5 = 621,
  84                 .vsize = 625,
  85                 .capture_format = 0,
  86                 .vbi_supported = 0,
  87                 .hd_sd = 1,
  88                 .dv_timings = V4L2_DV_BT_CEA_720X576P50,
  89         },
  90         {
  91                 .name = "720p50",
  92                 .width = 1280,
  93                 .height = 720,
  94                 .frm_fmt = 1,
  95                 .ycmux_mode = 0,
  96                 .eav2sav = 700-8,
  97                 .sav2eav = 1280,
  98                 .l1 = 1,
  99                 .l3 = 26,
 100                 .l5 = 746,
 101                 .vsize = 750,
 102                 .capture_format = 0,
 103                 .vbi_supported = 0,
 104                 .hd_sd = 1,
 105                 .dv_timings = V4L2_DV_BT_CEA_1280X720P50,
 106         },
 107         {
 108                 .name = "720p60",
 109                 .width = 1280,
 110                 .height = 720,
 111                 .frm_fmt = 1,
 112                 .ycmux_mode = 0,
 113                 .eav2sav = 370 - 8,
 114                 .sav2eav = 1280,
 115                 .l1 = 1,
 116                 .l3 = 26,
 117                 .l5 = 746,
 118                 .vsize = 750,
 119                 .capture_format = 0,
 120                 .vbi_supported = 0,
 121                 .hd_sd = 1,
 122                 .dv_timings = V4L2_DV_BT_CEA_1280X720P60,
 123         },
 124         {
 125                 .name = "1080I50",
 126                 .width = 1920,
 127                 .height = 1080,
 128                 .frm_fmt = 0,
 129                 .ycmux_mode = 0,
 130                 .eav2sav = 720 - 8,
 131                 .sav2eav = 1920,
 132                 .l1 = 1,
 133                 .l3 = 21,
 134                 .l5 = 561,
 135                 .l7 = 563,
 136                 .l9 = 584,
 137                 .l11 = 1124,
 138                 .vsize = 1125,
 139                 .capture_format = 0,
 140                 .vbi_supported = 0,
 141                 .hd_sd = 1,
 142                 .dv_timings = V4L2_DV_BT_CEA_1920X1080I50,
 143         },
 144         {
 145                 .name = "1080I60",
 146                 .width = 1920,
 147                 .height = 1080,
 148                 .frm_fmt = 0,
 149                 .ycmux_mode = 0,
 150                 .eav2sav = 280 - 8,
 151                 .sav2eav = 1920,
 152                 .l1 = 1,
 153                 .l3 = 21,
 154                 .l5 = 561,
 155                 .l7 = 563,
 156                 .l9 = 584,
 157                 .l11 = 1124,
 158                 .vsize = 1125,
 159                 .capture_format = 0,
 160                 .vbi_supported = 0,
 161                 .hd_sd = 1,
 162                 .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
 163         },
 164         {
 165                 .name = "1080p60",
 166                 .width = 1920,
 167                 .height = 1080,
 168                 .frm_fmt = 1,
 169                 .ycmux_mode = 0,
 170                 .eav2sav = 280 - 8,
 171                 .sav2eav = 1920,
 172                 .l1 = 1,
 173                 .l3 = 42,
 174                 .l5 = 1122,
 175                 .vsize = 1125,
 176                 .capture_format = 0,
 177                 .vbi_supported = 0,
 178                 .hd_sd = 1,
 179                 .dv_timings = V4L2_DV_BT_CEA_1920X1080P60,
 180         },
 181
 182         /* SDTV formats */
 183         {
 184                 .name = "NTSC_M",
 185                 .width = 720,
 186                 .height = 480,
 187                 .frm_fmt = 0,
 188                 .ycmux_mode = 1,
 189                 .eav2sav = 268,
 190                 .sav2eav = 1440,
 191                 .l1 = 1,
 192                 .l3 = 23,
 193                 .l5 = 263,
 194                 .l7 = 266,
 195                 .l9 = 286,
 196                 .l11 = 525,
 197                 .vsize = 525,
 198                 .capture_format = 0,
 199                 .vbi_supported = 1,
 200                 .hd_sd = 0,
 201                 .stdid = V4L2_STD_525_60,
 202         },
 203         {
 204                 .name = "PAL_BDGHIK",
 205                 .width = 720,
 206                 .height = 576,
 207                 .frm_fmt = 0,
 208                 .ycmux_mode = 1,
 209                 .eav2sav = 280,
 210                 .sav2eav = 1440,
 211                 .l1 = 1,
 212                 .l3 = 23,
 213                 .l5 = 311,
 214                 .l7 = 313,
 215                 .l9 = 336,
 216                 .l11 = 624,
 217                 .vsize = 625,
 218                 .capture_format = 0,
 219                 .vbi_supported = 1,
 220                 .hd_sd = 0,
 221                 .stdid = V4L2_STD_625_50,
 222         },
 223 };
 224 EXPORT_SYMBOL_GPL(vpif_ch_params);
 225
 226 const unsigned int vpif_ch_params_count = ARRAY_SIZE(vpif_ch_params);
 227 EXPORT_SYMBOL_GPL(vpif_ch_params_count);
 228
 229 static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val)
 230 {
 231         if (val)
 232                 vpif_set_bit(reg, bit);
 233         else
 234                 vpif_clr_bit(reg, bit);
 235 }
 236
 237 /* This structure is used to keep track of VPIF size register's offsets */
 238 struct vpif_registers {
 239         u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl;
 240         u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt;
 241         u32 vanc1_size, width_mask, len_mask;
 242         u8 max_modes;
 243 };
 244
 245 static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = {
 246         /* Channel0 */
 247         {
 248                 VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01,
 249                 VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL,
 250                 VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
 251                 VPIF_CH0_MAX_MODES,
 252         },
 253         /* Channel1 */
 254         {
 255                 VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01,
 256                 VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL,
 257                 VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
 258                 VPIF_CH1_MAX_MODES,
 259         },
 260         /* Channel2 */
 261         {
 262                 VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01,
 263                 VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL,
 264                 VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE,
 265                 VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF,
 266                 VPIF_CH2_MAX_MODES
 267         },
 268         /* Channel3 */
 269         {
 270                 VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01,
 271                 VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL,
 272                 VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE,
 273                 VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF,
 274                 VPIF_CH3_MAX_MODES
 275         },
 276 };
 277
 278 /* vpif_set_mode_info:
 279  * This function is used to set horizontal and vertical config parameters
 280  * As per the standard in the channel, configure the values of L1, L3,
 281  * L5, L7  L9, L11 in VPIF Register , also write width and height
 282  */
 283 static void vpif_set_mode_info(const struct vpif_channel_config_params *config,
 284                                 u8 channel_id, u8 config_channel_id)
 285 {
 286         u32 value;
 287
 288         value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
 289         value <<= VPIF_CH_LEN_SHIFT;
 290         value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);
 291         regw(value, vpifregs[channel_id].h_cfg);
 292
 293         value = (config->l1 & vpifregs[config_channel_id].len_mask);
 294         value <<= VPIF_CH_LEN_SHIFT;
 295         value |= (config->l3 & vpifregs[config_channel_id].len_mask);
 296         regw(value, vpifregs[channel_id].v_cfg_00);
 297
 298         value = (config->l5 & vpifregs[config_channel_id].len_mask);
 299         value <<= VPIF_CH_LEN_SHIFT;
 300         value |= (config->l7 & vpifregs[config_channel_id].len_mask);
 301         regw(value, vpifregs[channel_id].v_cfg_01);
 302
 303         value = (config->l9 & vpifregs[config_channel_id].len_mask);
 304         value <<= VPIF_CH_LEN_SHIFT;
 305         value |= (config->l11 & vpifregs[config_channel_id].len_mask);
 306         regw(value, vpifregs[channel_id].v_cfg_02);
 307
 308         value = (config->vsize & vpifregs[config_channel_id].len_mask);
 309         regw(value, vpifregs[channel_id].v_cfg);
 310 }
 311
 312 /* config_vpif_params
 313  * Function to set the parameters of a channel
 314  * Mainly modifies the channel ciontrol register
 315  * It sets frame format, yc mux mode
 316  */
 317 static void config_vpif_params(struct vpif_params *vpifparams,
 318                                 u8 channel_id, u8 found)
 319 {
 320         const struct vpif_channel_config_params *config = &vpifparams->std_info;
 321         u32 value, ch_nip, reg;
 322         u8 start, end;
 323         int i;
 324
 325         start = channel_id;
 326         end = channel_id + found;
 327
 328         for (i = start; i < end; i++) {
 329                 reg = vpifregs[i].ch_ctrl;
 330                 if (channel_id < 2)
 331                         ch_nip = VPIF_CAPTURE_CH_NIP;
 332                 else
 333                         ch_nip = VPIF_DISPLAY_CH_NIP;
 334
 335                 vpif_wr_bit(reg, ch_nip, config->frm_fmt);
 336                 vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);
 337                 vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,
 338                                         vpifparams->video_params.storage_mode);
 339
 340                 /* Set raster scanning SDR Format */
 341                 vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);
 342                 vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);
 343
 344                 if (channel_id > 1)     /* Set the Pixel enable bit */
 345                         vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);
 346                 else if (config->capture_format) {
 347                         /* Set the polarity of various pins */
 348                         vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,
 349                                         vpifparams->iface.fid_pol);
 350                         vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,
 351                                         vpifparams->iface.vd_pol);
 352                         vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,
 353                                         vpifparams->iface.hd_pol);
 354
 355                         value = regr(reg);
 356                         /* Set data width */
 357                         value &= ~(0x3u <<
 358                                         VPIF_CH_DATA_WIDTH_BIT);
 359                         value |= ((vpifparams->params.data_sz) <<
 360                                                      VPIF_CH_DATA_WIDTH_BIT);
 361                         regw(value, reg);
 362                 }
 363
 364                 /* Write the pitch in the driver */
 365                 regw((vpifparams->video_params.hpitch),
 366                                                 vpifregs[i].line_offset);
 367         }
 368 }
 369
 370 /* vpif_set_video_params
 371  * This function is used to set video parameters in VPIF register
 372  */
 373 int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)
 374 {
 375         const struct vpif_channel_config_params *config = &vpifparams->std_info;
 376         int found = 1;
 377
 378         vpif_set_mode_info(config, channel_id, channel_id);
 379         if (!config->ycmux_mode) {
 380                 /* YC are on separate channels (HDTV formats) */
 381                 vpif_set_mode_info(config, channel_id + 1, channel_id);
 382                 found = 2;
 383         }
 384
 385         config_vpif_params(vpifparams, channel_id, found);
 386
 387         regw(0x80, VPIF_REQ_SIZE);
 388         regw(0x01, VPIF_EMULATION_CTRL);
 389
 390         return found;
 391 }
 392 EXPORT_SYMBOL(vpif_set_video_params);
 393
 394 void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
 395                                 u8 channel_id)
 396 {
 397         u32 value;
 398
 399         value = 0x3F8 & (vbiparams->hstart0);
 400         value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
 401         regw(value, vpifregs[channel_id].vanc0_strt);
 402
 403         value = 0x3F8 & (vbiparams->hstart1);
 404         value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
 405         regw(value, vpifregs[channel_id].vanc1_strt);
 406
 407         value = 0x3F8 & (vbiparams->hsize0);
 408         value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
 409         regw(value, vpifregs[channel_id].vanc0_size);
 410
 411         value = 0x3F8 & (vbiparams->hsize1);
 412         value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
 413         regw(value, vpifregs[channel_id].vanc1_size);
 414
 415 }
 416 EXPORT_SYMBOL(vpif_set_vbi_display_params);
 417
 418 int vpif_channel_getfid(u8 channel_id)
 419 {
 420         return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)
 421                                         >> VPIF_CH_FID_SHIFT;
 422 }
 423 EXPORT_SYMBOL(vpif_channel_getfid);
 424
 425 static int vpif_probe(struct platform_device *pdev)
 426 {
 427         static struct resource  *res, *res_irq;
 428         struct platform_device *pdev_capture, *pdev_display;
 429         struct device_node *endpoint = NULL;
 430
 431         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 432         vpif_base = devm_ioremap_resource(&pdev->dev, res);
 433         if (IS_ERR(vpif_base))
 434                 return PTR_ERR(vpif_base);
 435
 436         pm_runtime_enable(&pdev->dev);
 437         pm_runtime_get(&pdev->dev);
 438
 439         spin_lock_init(&vpif_lock);
 440         dev_info(&pdev->dev, "vpif probe success\n");
 441
 442         /*
 443          * If VPIF Node has endpoints, assume "new" DT support,
 444          * where capture and display drivers don't have DT nodes
 445          * so their devices need to be registered manually here
 446          * for their legacy platform_drivers to work.
 447          */
 448         endpoint = of_graph_get_next_endpoint(pdev->dev.of_node,
 449                                               endpoint);
 450         if (!endpoint)
 451                 return 0;
 452
 453         /*
 454          * For DT platforms, manually create platform_devices for
 455          * capture/display drivers.
 456          */
 457         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 458         if (!res_irq) {
 459                 dev_warn(&pdev->dev, "Missing IRQ resource.\n");
 460                 return -EINVAL;
 461         }
 462
 463         pdev_capture = devm_kzalloc(&pdev->dev, sizeof(*pdev_capture),
 464                                     GFP_KERNEL);
 465         if (pdev_capture) {
 466                 pdev_capture->name = "vpif_capture";
 467                 pdev_capture->id = -1;
 468                 pdev_capture->resource = res_irq;
 469                 pdev_capture->num_resources = 1;
 470                 pdev_capture->dev.dma_mask = pdev->dev.dma_mask;
 471                 pdev_capture->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask;
 472                 pdev_capture->dev.parent = &pdev->dev;
 473                 platform_device_register(pdev_capture);
 474         } else {
 475                 dev_warn(&pdev->dev, "Unable to allocate memory for pdev_capture.\n");
 476         }
 477
 478         pdev_display = devm_kzalloc(&pdev->dev, sizeof(*pdev_display),
 479                                     GFP_KERNEL);
 480         if (pdev_display) {
 481                 pdev_display->name = "vpif_display";
 482                 pdev_display->id = -1;
 483                 pdev_display->resource = res_irq;
 484                 pdev_display->num_resources = 1;
 485                 pdev_display->dev.dma_mask = pdev->dev.dma_mask;
 486                 pdev_display->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask;
 487                 pdev_display->dev.parent = &pdev->dev;
 488                 platform_device_register(pdev_display);
 489         } else {
 490                 dev_warn(&pdev->dev, "Unable to allocate memory for pdev_display.\n");
 491         }
 492
 493         return 0;
 494 }
 495
 496 static int vpif_remove(struct platform_device *pdev)
 497 {
 498         pm_runtime_put(&pdev->dev);
 499         pm_runtime_disable(&pdev->dev);
 500         return 0;
 501 }
 502
 503 #ifdef CONFIG_PM
 504 static int vpif_suspend(struct device *dev)
 505 {
 506         pm_runtime_put(dev);
 507         return 0;
 508 }
 509
 510 static int vpif_resume(struct device *dev)
 511 {
 512         pm_runtime_get(dev);
 513         return 0;
 514 }
 515
 516 static const struct dev_pm_ops vpif_pm = {
 517         .suspend        = vpif_suspend,
 518         .resume         = vpif_resume,
 519 };
 520
 521 #define vpif_pm_ops (&vpif_pm)
 522 #else
 523 #define vpif_pm_ops NULL
 524 #endif
 525
 526 #if IS_ENABLED(CONFIG_OF)
 527 static const struct of_device_id vpif_of_match[] = {
 528         { .compatible = "ti,da850-vpif", },
 529         { /* sentinel */ },
 530 };
 531 MODULE_DEVICE_TABLE(of, vpif_of_match);
 532 #endif
 533
 534 static struct platform_driver vpif_driver = {
 535         .driver = {
 536                 .of_match_table = of_match_ptr(vpif_of_match),
 537                 .name   = VPIF_DRIVER_NAME,
 538                 .pm     = vpif_pm_ops,
 539         },
 540         .remove = vpif_remove,
 541         .probe = vpif_probe,
 542 };
 543
 544 static void vpif_exit(void)
 545 {
 546         platform_driver_unregister(&vpif_driver);
 547 }
 548
 549 static int __init vpif_init(void)
 550 {
 551         return platform_driver_register(&vpif_driver);
 552 }
 553 subsys_initcall(vpif_init);
 554 module_exit(vpif_exit);
 555