drivers/media/platform/amphion/vpu_malone.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2020-2021 NXP
   4  */
   5
   6 #include <linux/init.h>
   7 #include <linux/interconnect.h>
   8 #include <linux/ioctl.h>
   9 #include <linux/list.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/of_address.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/delay.h>
  16 #include <linux/rational.h>
  17 #include <linux/time64.h>
  18 #include <media/videobuf2-v4l2.h>
  19 #include <media/videobuf2-dma-contig.h>
  20 #include <linux/videodev2.h>
  21 #include "vpu.h"
  22 #include "vpu_rpc.h"
  23 #include "vpu_defs.h"
  24 #include "vpu_helpers.h"
  25 #include "vpu_v4l2.h"
  26 #include "vpu_cmds.h"
  27 #include "vpu_imx8q.h"
  28 #include "vpu_malone.h"
  29
  30 #define CMD_SIZE                        25600
  31 #define MSG_SIZE                        25600
  32 #define CODEC_SIZE                      0x1000
  33 #define JPEG_SIZE                       0x1000
  34 #define SEQ_SIZE                        0x1000
  35 #define GOP_SIZE                        0x1000
  36 #define PIC_SIZE                        0x1000
  37 #define QMETER_SIZE                     0x1000
  38 #define DBGLOG_SIZE                     0x10000
  39 #define DEBUG_SIZE                      0x80000
  40 #define ENG_SIZE                        0x1000
  41 #define MALONE_SKIPPED_FRAME_ID         0x555
  42
  43 #define MALONE_ALIGN_MBI                0x800
  44 #define MALONE_DCP_CHUNK_BIT            16
  45 #define MALONE_DCP_SIZE_MAX             0x3000000
  46 #define MALONE_DCP_SIZE_MIN             0x100000
  47 #define MALONE_DCP_FIXED_MB_ALLOC       250
  48
  49 #define CONFIG_SET(val, cfg, pos, mask)         \
  50                 (*(cfg) |= (((val) << (pos)) & (mask)))
  51 //x means source data , y means destination data
  52 #define STREAM_CONFIG_FORMAT_SET(x, y)          CONFIG_SET(x, y, 0, 0x0000000F)
  53 #define STREAM_CONFIG_STRBUFIDX_SET(x, y)       CONFIG_SET(x, y, 8, 0x00000300)
  54 #define STREAM_CONFIG_NOSEQ_SET(x, y)           CONFIG_SET(x, y, 10, 0x00000400)
  55 #define STREAM_CONFIG_DEBLOCK_SET(x, y)         CONFIG_SET(x, y, 11, 0x00000800)
  56 #define STREAM_CONFIG_DERING_SET(x, y)          CONFIG_SET(x, y, 12, 0x00001000)
  57 #define STREAM_CONFIG_IBWAIT_SET(x, y)          CONFIG_SET(x, y, 13, 0x00002000)
  58 #define STREAM_CONFIG_FBC_SET(x, y)             CONFIG_SET(x, y, 14, 0x00004000)
  59 #define STREAM_CONFIG_PLAY_MODE_SET(x, y)       CONFIG_SET(x, y, 16, 0x00030000)
  60 #define STREAM_CONFIG_ENABLE_DCP_SET(x, y)      CONFIG_SET(x, y, 20, 0x00100000)
  61 #define STREAM_CONFIG_NUM_STR_BUF_SET(x, y)     CONFIG_SET(x, y, 21, 0x00600000)
  62 #define STREAM_CONFIG_MALONE_USAGE_SET(x, y)    CONFIG_SET(x, y, 23, 0x01800000)
  63 #define STREAM_CONFIG_MULTI_VID_SET(x, y)       CONFIG_SET(x, y, 25, 0x02000000)
  64 #define STREAM_CONFIG_OBFUSC_EN_SET(x, y)       CONFIG_SET(x, y, 26, 0x04000000)
  65 #define STREAM_CONFIG_RC4_EN_SET(x, y)          CONFIG_SET(x, y, 27, 0x08000000)
  66 #define STREAM_CONFIG_MCX_SET(x, y)             CONFIG_SET(x, y, 28, 0x10000000)
  67 #define STREAM_CONFIG_PES_SET(x, y)             CONFIG_SET(x, y, 29, 0x20000000)
  68 #define STREAM_CONFIG_NUM_DBE_SET(x, y)         CONFIG_SET(x, y, 30, 0x40000000)
  69 #define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y)    CONFIG_SET(x, y, 31, 0x80000000)
  70
  71 enum vpu_malone_stream_input_mode {
  72         INVALID_MODE = 0,
  73         FRAME_LVL,
  74         NON_FRAME_LVL
  75 };
  76
  77 enum vpu_malone_format {
  78         MALONE_FMT_NULL = 0x0,
  79         MALONE_FMT_AVC  = 0x1,
  80         MALONE_FMT_MP2  = 0x2,
  81         MALONE_FMT_VC1  = 0x3,
  82         MALONE_FMT_AVS  = 0x4,
  83         MALONE_FMT_ASP  = 0x5,
  84         MALONE_FMT_JPG  = 0x6,
  85         MALONE_FMT_RV   = 0x7,
  86         MALONE_FMT_VP6  = 0x8,
  87         MALONE_FMT_SPK  = 0x9,
  88         MALONE_FMT_VP8  = 0xA,
  89         MALONE_FMT_HEVC = 0xB,
  90         MALONE_FMT_LAST = MALONE_FMT_HEVC
  91 };
  92
  93 enum {
  94         VID_API_CMD_NULL              = 0x00,
  95         VID_API_CMD_PARSE_NEXT_SEQ    = 0x01,
  96         VID_API_CMD_PARSE_NEXT_I      = 0x02,
  97         VID_API_CMD_PARSE_NEXT_IP     = 0x03,
  98         VID_API_CMD_PARSE_NEXT_ANY    = 0x04,
  99         VID_API_CMD_DEC_PIC           = 0x05,
 100         VID_API_CMD_UPDATE_ES_WR_PTR  = 0x06,
 101         VID_API_CMD_UPDATE_ES_RD_PTR  = 0x07,
 102         VID_API_CMD_UPDATE_UDATA      = 0x08,
 103         VID_API_CMD_GET_FSINFO        = 0x09,
 104         VID_API_CMD_SKIP_PIC          = 0x0a,
 105         VID_API_CMD_DEC_CHUNK         = 0x0b,
 106         VID_API_CMD_START             = 0x10,
 107         VID_API_CMD_STOP              = 0x11,
 108         VID_API_CMD_ABORT             = 0x12,
 109         VID_API_CMD_RST_BUF           = 0x13,
 110         VID_API_CMD_FS_RELEASE        = 0x15,
 111         VID_API_CMD_MEM_REGION_ATTACH = 0x16,
 112         VID_API_CMD_MEM_REGION_DETACH = 0x17,
 113         VID_API_CMD_MVC_VIEW_SELECT   = 0x18,
 114         VID_API_CMD_FS_ALLOC          = 0x19,
 115         VID_API_CMD_DBG_GET_STATUS    = 0x1C,
 116         VID_API_CMD_DBG_START_LOG     = 0x1D,
 117         VID_API_CMD_DBG_STOP_LOG      = 0x1E,
 118         VID_API_CMD_DBG_DUMP_LOG      = 0x1F,
 119         VID_API_CMD_YUV_READY         = 0x20,
 120         VID_API_CMD_TS                = 0x21,
 121
 122         VID_API_CMD_FIRM_RESET        = 0x40,
 123
 124         VID_API_CMD_SNAPSHOT          = 0xAA,
 125         VID_API_CMD_ROLL_SNAPSHOT     = 0xAB,
 126         VID_API_CMD_LOCK_SCHEDULER    = 0xAC,
 127         VID_API_CMD_UNLOCK_SCHEDULER  = 0xAD,
 128         VID_API_CMD_CQ_FIFO_DUMP      = 0xAE,
 129         VID_API_CMD_DBG_FIFO_DUMP     = 0xAF,
 130         VID_API_CMD_SVC_ILP           = 0xBB,
 131         VID_API_CMD_FW_STATUS         = 0xF0,
 132         VID_API_CMD_INVALID           = 0xFF
 133 };
 134
 135 enum {
 136         VID_API_EVENT_NULL                      = 0x00,
 137         VID_API_EVENT_RESET_DONE                = 0x01,
 138         VID_API_EVENT_SEQ_HDR_FOUND             = 0x02,
 139         VID_API_EVENT_PIC_HDR_FOUND             = 0x03,
 140         VID_API_EVENT_PIC_DECODED               = 0x04,
 141         VID_API_EVENT_FIFO_LOW                  = 0x05,
 142         VID_API_EVENT_FIFO_HIGH                 = 0x06,
 143         VID_API_EVENT_FIFO_EMPTY                = 0x07,
 144         VID_API_EVENT_FIFO_FULL                 = 0x08,
 145         VID_API_EVENT_BS_ERROR                  = 0x09,
 146         VID_API_EVENT_UDATA_FIFO_UPTD           = 0x0A,
 147         VID_API_EVENT_RES_CHANGE                = 0x0B,
 148         VID_API_EVENT_FIFO_OVF                  = 0x0C,
 149         VID_API_EVENT_CHUNK_DECODED             = 0x0D,
 150         VID_API_EVENT_REQ_FRAME_BUFF            = 0x10,
 151         VID_API_EVENT_FRAME_BUFF_RDY            = 0x11,
 152         VID_API_EVENT_REL_FRAME_BUFF            = 0x12,
 153         VID_API_EVENT_STR_BUF_RST               = 0x13,
 154         VID_API_EVENT_RET_PING                  = 0x14,
 155         VID_API_EVENT_QMETER                    = 0x15,
 156         VID_API_EVENT_STR_FMT_CHANGE            = 0x16,
 157         VID_API_EVENT_FIRMWARE_XCPT             = 0x17,
 158         VID_API_EVENT_START_DONE                = 0x18,
 159         VID_API_EVENT_STOPPED                   = 0x19,
 160         VID_API_EVENT_ABORT_DONE                = 0x1A,
 161         VID_API_EVENT_FINISHED                  = 0x1B,
 162         VID_API_EVENT_DBG_STAT_UPDATE           = 0x1C,
 163         VID_API_EVENT_DBG_LOG_STARTED           = 0x1D,
 164         VID_API_EVENT_DBG_LOG_STOPPED           = 0x1E,
 165         VID_API_EVENT_DBG_LOG_UPDATED           = 0x1F,
 166         VID_API_EVENT_DBG_MSG_DEC               = 0x20,
 167         VID_API_EVENT_DEC_SC_ERR                = 0x21,
 168         VID_API_EVENT_CQ_FIFO_DUMP              = 0x22,
 169         VID_API_EVENT_DBG_FIFO_DUMP             = 0x23,
 170         VID_API_EVENT_DEC_CHECK_RES             = 0x24,
 171         VID_API_EVENT_DEC_CFG_INFO              = 0x25,
 172         VID_API_EVENT_UNSUPPORTED_STREAM        = 0x26,
 173         VID_API_EVENT_PIC_SKIPPED               = 0x27,
 174         VID_API_EVENT_STR_SUSPENDED             = 0x30,
 175         VID_API_EVENT_SNAPSHOT_DONE             = 0x40,
 176         VID_API_EVENT_FW_STATUS                 = 0xF0,
 177         VID_API_EVENT_INVALID                   = 0xFF
 178 };
 179
 180 struct vpu_malone_buffer_desc {
 181         struct vpu_rpc_buffer_desc buffer;
 182         u32 low;
 183         u32 high;
 184 };
 185
 186 struct vpu_malone_str_buffer {
 187         u32 wptr;
 188         u32 rptr;
 189         u32 start;
 190         u32 end;
 191         u32 lwm;
 192 };
 193
 194 struct vpu_malone_picth_info {
 195         u32 frame_pitch;
 196 };
 197
 198 struct vpu_malone_table_desc {
 199         u32 array_base;
 200         u32 size;
 201 };
 202
 203 struct vpu_malone_dbglog_desc {
 204         u32 addr;
 205         u32 size;
 206         u32 level;
 207         u32 reserved;
 208 };
 209
 210 struct vpu_malone_frame_buffer {
 211         u32 addr;
 212         u32 size;
 213 };
 214
 215 struct vpu_malone_udata {
 216         u32 base;
 217         u32 total_size;
 218         u32 slot_size;
 219 };
 220
 221 struct vpu_malone_buffer_info {
 222         u32 stream_input_mode;
 223         u32 stream_pic_input_count;
 224         u32 stream_pic_parsed_count;
 225         u32 stream_buffer_threshold;
 226         u32 stream_pic_end_flag;
 227 };
 228
 229 struct vpu_malone_encrypt_info {
 230         u32 rec4key[8];
 231         u32 obfusc;
 232 };
 233
 234 struct malone_iface {
 235         u32 exec_base_addr;
 236         u32 exec_area_size;
 237         struct vpu_malone_buffer_desc cmd_buffer_desc;
 238         struct vpu_malone_buffer_desc msg_buffer_desc;
 239         u32 cmd_int_enable[VID_API_NUM_STREAMS];
 240         struct vpu_malone_picth_info stream_pitch_info[VID_API_NUM_STREAMS];
 241         u32 stream_config[VID_API_NUM_STREAMS];
 242         struct vpu_malone_table_desc codec_param_tab_desc;
 243         struct vpu_malone_table_desc jpeg_param_tab_desc;
 244         u32 stream_buffer_desc[VID_API_NUM_STREAMS][VID_API_MAX_BUF_PER_STR];
 245         struct vpu_malone_table_desc seq_info_tab_desc;
 246         struct vpu_malone_table_desc pic_info_tab_desc;
 247         struct vpu_malone_table_desc gop_info_tab_desc;
 248         struct vpu_malone_table_desc qmeter_info_tab_desc;
 249         u32 stream_error[VID_API_NUM_STREAMS];
 250         u32 fw_version;
 251         u32 fw_offset;
 252         u32 max_streams;
 253         struct vpu_malone_dbglog_desc dbglog_desc;
 254         struct vpu_rpc_buffer_desc api_cmd_buffer_desc[VID_API_NUM_STREAMS];
 255         struct vpu_malone_udata udata_buffer[VID_API_NUM_STREAMS];
 256         struct vpu_malone_buffer_desc debug_buffer_desc;
 257         struct vpu_malone_buffer_desc eng_access_buff_desc[VID_API_NUM_STREAMS];
 258         u32 encrypt_info[VID_API_NUM_STREAMS];
 259         struct vpu_rpc_system_config system_cfg;
 260         u32 api_version;
 261         struct vpu_malone_buffer_info stream_buff_info[VID_API_NUM_STREAMS];
 262 };
 263
 264 struct malone_jpg_params {
 265         u32 rotation_angle;
 266         u32 horiz_scale_factor;
 267         u32 vert_scale_factor;
 268         u32 rotation_mode;
 269         u32 rgb_mode;
 270         u32 chunk_mode; /* 0 ~ 1 */
 271         u32 last_chunk; /* 0 ~ 1 */
 272         u32 chunk_rows; /* 0 ~ 255 */
 273         u32 num_bytes;
 274         u32 jpg_crop_x;
 275         u32 jpg_crop_y;
 276         u32 jpg_crop_width;
 277         u32 jpg_crop_height;
 278         u32 jpg_mjpeg_mode;
 279         u32 jpg_mjpeg_interlaced;
 280 };
 281
 282 struct malone_codec_params {
 283         u32 disp_imm;
 284         u32 fourcc;
 285         u32 codec_version;
 286         u32 frame_rate;
 287         u32 dbglog_enable;
 288         u32 bsdma_lwm;
 289         u32 bbd_coring;
 290         u32 bbd_s_thr_row;
 291         u32 bbd_p_thr_row;
 292         u32 bbd_s_thr_logo_row;
 293         u32 bbd_p_thr_logo_row;
 294         u32 bbd_s_thr_col;
 295         u32 bbd_p_thr_col;
 296         u32 bbd_chr_thr_row;
 297         u32 bbd_chr_thr_col;
 298         u32 bbd_uv_mid_level;
 299         u32 bbd_excl_win_mb_left;
 300         u32 bbd_excl_win_mb_right;
 301 };
 302
 303 struct malone_padding_scode {
 304         u32 scode_type;
 305         u32 pixelformat;
 306         u32 data[2];
 307 };
 308
 309 struct malone_fmt_mapping {
 310         u32 pixelformat;
 311         enum vpu_malone_format malone_format;
 312 };
 313
 314 struct malone_scode_t {
 315         struct vpu_inst *inst;
 316         struct vb2_buffer *vb;
 317         u32 wptr;
 318         u32 need_data;
 319 };
 320
 321 struct malone_scode_handler {
 322         u32 pixelformat;
 323         int (*insert_scode_seq)(struct malone_scode_t *scode);
 324         int (*insert_scode_pic)(struct malone_scode_t *scode);
 325 };
 326
 327 struct vpu_dec_ctrl {
 328         struct malone_codec_params *codec_param;
 329         struct malone_jpg_params *jpg;
 330         void *seq_mem;
 331         void *pic_mem;
 332         void *gop_mem;
 333         void *qmeter_mem;
 334         void *dbglog_mem;
 335         struct vpu_malone_str_buffer __iomem *str_buf[VID_API_NUM_STREAMS];
 336         u32 buf_addr[VID_API_NUM_STREAMS];
 337 };
 338
 339 u32 vpu_malone_get_data_size(void)
 340 {
 341         return sizeof(struct vpu_dec_ctrl);
 342 }
 343
 344 void vpu_malone_init_rpc(struct vpu_shared_addr *shared,
 345                          struct vpu_buffer *rpc, dma_addr_t boot_addr)
 346 {
 347         struct malone_iface *iface;
 348         struct vpu_dec_ctrl *hc;
 349         unsigned long base_phy_addr;
 350         unsigned long phy_addr;
 351         unsigned long offset;
 352         unsigned int i;
 353
 354         if (rpc->phys < boot_addr)
 355                 return;
 356
 357         iface = rpc->virt;
 358         base_phy_addr = rpc->phys - boot_addr;
 359         hc = shared->priv;
 360
 361         shared->iface = iface;
 362         shared->boot_addr = boot_addr;
 363
 364         iface->exec_base_addr = base_phy_addr;
 365         iface->exec_area_size = rpc->length;
 366
 367         offset = sizeof(struct malone_iface);
 368         phy_addr = base_phy_addr + offset;
 369
 370         shared->cmd_desc = &iface->cmd_buffer_desc.buffer;
 371         shared->cmd_mem_vir = rpc->virt + offset;
 372         iface->cmd_buffer_desc.buffer.start =
 373         iface->cmd_buffer_desc.buffer.rptr =
 374         iface->cmd_buffer_desc.buffer.wptr = phy_addr;
 375         iface->cmd_buffer_desc.buffer.end = iface->cmd_buffer_desc.buffer.start + CMD_SIZE;
 376         offset += CMD_SIZE;
 377         phy_addr = base_phy_addr + offset;
 378
 379         shared->msg_desc = &iface->msg_buffer_desc.buffer;
 380         shared->msg_mem_vir = rpc->virt + offset;
 381         iface->msg_buffer_desc.buffer.start =
 382         iface->msg_buffer_desc.buffer.wptr =
 383         iface->msg_buffer_desc.buffer.rptr = phy_addr;
 384         iface->msg_buffer_desc.buffer.end = iface->msg_buffer_desc.buffer.start + MSG_SIZE;
 385         offset += MSG_SIZE;
 386         phy_addr = base_phy_addr + offset;
 387
 388         iface->codec_param_tab_desc.array_base = phy_addr;
 389         hc->codec_param = rpc->virt + offset;
 390         offset += CODEC_SIZE;
 391         phy_addr = base_phy_addr + offset;
 392
 393         iface->jpeg_param_tab_desc.array_base = phy_addr;
 394         hc->jpg = rpc->virt + offset;
 395         offset += JPEG_SIZE;
 396         phy_addr = base_phy_addr + offset;
 397
 398         iface->seq_info_tab_desc.array_base = phy_addr;
 399         hc->seq_mem = rpc->virt + offset;
 400         offset += SEQ_SIZE;
 401         phy_addr = base_phy_addr + offset;
 402
 403         iface->pic_info_tab_desc.array_base = phy_addr;
 404         hc->pic_mem = rpc->virt + offset;
 405         offset += PIC_SIZE;
 406         phy_addr = base_phy_addr + offset;
 407
 408         iface->gop_info_tab_desc.array_base = phy_addr;
 409         hc->gop_mem = rpc->virt + offset;
 410         offset += GOP_SIZE;
 411         phy_addr = base_phy_addr + offset;
 412
 413         iface->qmeter_info_tab_desc.array_base = phy_addr;
 414         hc->qmeter_mem = rpc->virt + offset;
 415         offset += QMETER_SIZE;
 416         phy_addr = base_phy_addr + offset;
 417
 418         iface->dbglog_desc.addr = phy_addr;
 419         iface->dbglog_desc.size = DBGLOG_SIZE;
 420         hc->dbglog_mem = rpc->virt + offset;
 421         offset += DBGLOG_SIZE;
 422         phy_addr = base_phy_addr + offset;
 423
 424         for (i = 0; i < VID_API_NUM_STREAMS; i++) {
 425                 iface->eng_access_buff_desc[i].buffer.start =
 426                 iface->eng_access_buff_desc[i].buffer.wptr =
 427                 iface->eng_access_buff_desc[i].buffer.rptr = phy_addr;
 428                 iface->eng_access_buff_desc[i].buffer.end =
 429                         iface->eng_access_buff_desc[i].buffer.start + ENG_SIZE;
 430                 offset += ENG_SIZE;
 431                 phy_addr = base_phy_addr + offset;
 432         }
 433
 434         for (i = 0; i < VID_API_NUM_STREAMS; i++) {
 435                 iface->encrypt_info[i] = phy_addr;
 436                 offset += sizeof(struct vpu_malone_encrypt_info);
 437                 phy_addr = base_phy_addr + offset;
 438         }
 439
 440         rpc->bytesused = offset;
 441 }
 442
 443 void vpu_malone_set_log_buf(struct vpu_shared_addr *shared,
 444                             struct vpu_buffer *log)
 445 {
 446         struct malone_iface *iface = shared->iface;
 447
 448         iface->debug_buffer_desc.buffer.start =
 449         iface->debug_buffer_desc.buffer.wptr =
 450         iface->debug_buffer_desc.buffer.rptr = log->phys - shared->boot_addr;
 451         iface->debug_buffer_desc.buffer.end = iface->debug_buffer_desc.buffer.start + log->length;
 452 }
 453
 454 static u32 get_str_buffer_offset(u32 instance)
 455 {
 456         return DEC_MFD_XREG_SLV_BASE + MFD_MCX + MFD_MCX_OFF * instance;
 457 }
 458
 459 void vpu_malone_set_system_cfg(struct vpu_shared_addr *shared,
 460                                u32 regs_base, void __iomem *regs, u32 core_id)
 461 {
 462         struct malone_iface *iface = shared->iface;
 463         struct vpu_rpc_system_config *config = &iface->system_cfg;
 464         struct vpu_dec_ctrl *hc = shared->priv;
 465         int i;
 466
 467         vpu_imx8q_set_system_cfg_common(config, regs_base, core_id);
 468         for (i = 0; i < VID_API_NUM_STREAMS; i++) {
 469                 u32 offset = get_str_buffer_offset(i);
 470
 471                 hc->buf_addr[i] = regs_base + offset;
 472                 hc->str_buf[i] = regs + offset;
 473         }
 474 }
 475
 476 u32 vpu_malone_get_version(struct vpu_shared_addr *shared)
 477 {
 478         struct malone_iface *iface = shared->iface;
 479
 480         return iface->fw_version;
 481 }
 482
 483 int vpu_malone_get_stream_buffer_size(struct vpu_shared_addr *shared)
 484 {
 485         return 0xc00000;
 486 }
 487
 488 int vpu_malone_config_stream_buffer(struct vpu_shared_addr *shared,
 489                                     u32 instance,
 490                                     struct vpu_buffer *buf)
 491 {
 492         struct malone_iface *iface = shared->iface;
 493         struct vpu_dec_ctrl *hc = shared->priv;
 494         struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
 495
 496         writel(buf->phys, &str_buf->start);
 497         writel(buf->phys, &str_buf->rptr);
 498         writel(buf->phys, &str_buf->wptr);
 499         writel(buf->phys + buf->length, &str_buf->end);
 500         writel(0x1, &str_buf->lwm);
 501
 502         iface->stream_buffer_desc[instance][0] = hc->buf_addr[instance];
 503
 504         return 0;
 505 }
 506
 507 int vpu_malone_get_stream_buffer_desc(struct vpu_shared_addr *shared,
 508                                       u32 instance,
 509                                       struct vpu_rpc_buffer_desc *desc)
 510 {
 511         struct vpu_dec_ctrl *hc = shared->priv;
 512         struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
 513
 514         if (desc) {
 515                 desc->wptr = readl(&str_buf->wptr);
 516                 desc->rptr = readl(&str_buf->rptr);
 517                 desc->start = readl(&str_buf->start);
 518                 desc->end = readl(&str_buf->end);
 519         }
 520
 521         return 0;
 522 }
 523
 524 static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr)
 525 {
 526         /*update wptr after data is written*/
 527         mb();
 528         writel(wptr, &str_buf->wptr);
 529 }
 530
 531 static void vpu_malone_update_rptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 rptr)
 532 {
 533         /*update rptr after data is read*/
 534         mb();
 535         writel(rptr, &str_buf->rptr);
 536 }
 537
 538 int vpu_malone_update_stream_buffer(struct vpu_shared_addr *shared,
 539                                     u32 instance, u32 ptr, bool write)
 540 {
 541         struct vpu_dec_ctrl *hc = shared->priv;
 542         struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
 543
 544         if (write)
 545                 vpu_malone_update_wptr(str_buf, ptr);
 546         else
 547                 vpu_malone_update_rptr(str_buf, ptr);
 548
 549         return 0;
 550 }
 551
 552 static struct malone_fmt_mapping fmt_mappings[] = {
 553         {V4L2_PIX_FMT_H264,        MALONE_FMT_AVC},
 554         {V4L2_PIX_FMT_H264_MVC,    MALONE_FMT_AVC},
 555         {V4L2_PIX_FMT_HEVC,        MALONE_FMT_HEVC},
 556         {V4L2_PIX_FMT_VC1_ANNEX_G, MALONE_FMT_VC1},
 557         {V4L2_PIX_FMT_VC1_ANNEX_L, MALONE_FMT_VC1},
 558         {V4L2_PIX_FMT_MPEG2,       MALONE_FMT_MP2},
 559         {V4L2_PIX_FMT_MPEG4,       MALONE_FMT_ASP},
 560         {V4L2_PIX_FMT_XVID,        MALONE_FMT_ASP},
 561         {V4L2_PIX_FMT_H263,        MALONE_FMT_ASP},
 562         {V4L2_PIX_FMT_JPEG,        MALONE_FMT_JPG},
 563         {V4L2_PIX_FMT_VP8,         MALONE_FMT_VP8},
 564 };
 565
 566 static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat)
 567 {
 568         u32 i;
 569
 570         for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) {
 571                 if (pixelformat == fmt_mappings[i].pixelformat)
 572                         return fmt_mappings[i].malone_format;
 573         }
 574
 575         return MALONE_FMT_NULL;
 576 }
 577
 578 static void vpu_malone_set_stream_cfg(struct vpu_shared_addr *shared,
 579                                       u32 instance,
 580                                       enum vpu_malone_format malone_format)
 581 {
 582         struct malone_iface *iface = shared->iface;
 583         u32 *curr_str_cfg = &iface->stream_config[instance];
 584
 585         *curr_str_cfg = 0;
 586         STREAM_CONFIG_FORMAT_SET(malone_format, curr_str_cfg);
 587         STREAM_CONFIG_STRBUFIDX_SET(0, curr_str_cfg);
 588         STREAM_CONFIG_NOSEQ_SET(0, curr_str_cfg);
 589         STREAM_CONFIG_DEBLOCK_SET(0, curr_str_cfg);
 590         STREAM_CONFIG_DERING_SET(0, curr_str_cfg);
 591         STREAM_CONFIG_PLAY_MODE_SET(0x3, curr_str_cfg);
 592         STREAM_CONFIG_FS_CTRL_MODE_SET(0x1, curr_str_cfg);
 593         STREAM_CONFIG_ENABLE_DCP_SET(1, curr_str_cfg);
 594         STREAM_CONFIG_NUM_STR_BUF_SET(1, curr_str_cfg);
 595         STREAM_CONFIG_MALONE_USAGE_SET(1, curr_str_cfg);
 596         STREAM_CONFIG_MULTI_VID_SET(0, curr_str_cfg);
 597         STREAM_CONFIG_OBFUSC_EN_SET(0, curr_str_cfg);
 598         STREAM_CONFIG_RC4_EN_SET(0, curr_str_cfg);
 599         STREAM_CONFIG_MCX_SET(1, curr_str_cfg);
 600         STREAM_CONFIG_PES_SET(0, curr_str_cfg);
 601         STREAM_CONFIG_NUM_DBE_SET(1, curr_str_cfg);
 602 }
 603
 604 static int vpu_malone_set_params(struct vpu_shared_addr *shared,
 605                                  u32 instance,
 606                                  struct vpu_decode_params *params)
 607 {
 608         struct malone_iface *iface = shared->iface;
 609         struct vpu_dec_ctrl *hc = shared->priv;
 610         enum vpu_malone_format malone_format;
 611
 612         malone_format = vpu_malone_format_remap(params->codec_format);
 613         iface->udata_buffer[instance].base = params->udata.base;
 614         iface->udata_buffer[instance].slot_size = params->udata.size;
 615
 616         vpu_malone_set_stream_cfg(shared, instance, malone_format);
 617
 618         if (malone_format == MALONE_FMT_JPG) {
 619                 //1:JPGD_MJPEG_MODE_A; 2:JPGD_MJPEG_MODE_B
 620                 hc->jpg[instance].jpg_mjpeg_mode = 1;
 621                 //0: JPGD_MJPEG_PROGRESSIVE
 622                 hc->jpg[instance].jpg_mjpeg_interlaced = 0;
 623         }
 624
 625         hc->codec_param[instance].disp_imm = params->b_dis_reorder ? 1 : 0;
 626         hc->codec_param[instance].dbglog_enable = 0;
 627         iface->dbglog_desc.level = 0;
 628
 629         if (params->b_non_frame)
 630                 iface->stream_buff_info[instance].stream_input_mode = NON_FRAME_LVL;
 631         else
 632                 iface->stream_buff_info[instance].stream_input_mode = FRAME_LVL;
 633         iface->stream_buff_info[instance].stream_buffer_threshold = 0;
 634         iface->stream_buff_info[instance].stream_pic_input_count = 0;
 635
 636         return 0;
 637 }
 638
 639 static bool vpu_malone_is_non_frame_mode(struct vpu_shared_addr *shared, u32 instance)
 640 {
 641         struct malone_iface *iface = shared->iface;
 642
 643         if (iface->stream_buff_info[instance].stream_input_mode == NON_FRAME_LVL)
 644                 return true;
 645
 646         return false;
 647 }
 648
 649 static int vpu_malone_update_params(struct vpu_shared_addr *shared,
 650                                     u32 instance,
 651                                     struct vpu_decode_params *params)
 652 {
 653         struct malone_iface *iface = shared->iface;
 654
 655         if (params->end_flag)
 656                 iface->stream_buff_info[instance].stream_pic_end_flag = params->end_flag;
 657         params->end_flag = 0;
 658
 659         return 0;
 660 }
 661
 662 int vpu_malone_set_decode_params(struct vpu_shared_addr *shared,
 663                                  u32 instance,
 664                                  struct vpu_decode_params *params,
 665                                  u32 update)
 666 {
 667         if (!params)
 668                 return -EINVAL;
 669
 670         if (!update)
 671                 return vpu_malone_set_params(shared, instance, params);
 672         else
 673                 return vpu_malone_update_params(shared, instance, params);
 674 }
 675
 676 static struct vpu_pair malone_cmds[] = {
 677         {VPU_CMD_ID_START, VID_API_CMD_START},
 678         {VPU_CMD_ID_STOP, VID_API_CMD_STOP},
 679         {VPU_CMD_ID_ABORT, VID_API_CMD_ABORT},
 680         {VPU_CMD_ID_RST_BUF, VID_API_CMD_RST_BUF},
 681         {VPU_CMD_ID_SNAPSHOT, VID_API_CMD_SNAPSHOT},
 682         {VPU_CMD_ID_FIRM_RESET, VID_API_CMD_FIRM_RESET},
 683         {VPU_CMD_ID_FS_ALLOC, VID_API_CMD_FS_ALLOC},
 684         {VPU_CMD_ID_FS_RELEASE, VID_API_CMD_FS_RELEASE},
 685         {VPU_CMD_ID_TIMESTAMP, VID_API_CMD_TS},
 686         {VPU_CMD_ID_DEBUG, VID_API_CMD_FW_STATUS},
 687 };
 688
 689 static struct vpu_pair malone_msgs[] = {
 690         {VPU_MSG_ID_RESET_DONE, VID_API_EVENT_RESET_DONE},
 691         {VPU_MSG_ID_START_DONE, VID_API_EVENT_START_DONE},
 692         {VPU_MSG_ID_STOP_DONE, VID_API_EVENT_STOPPED},
 693         {VPU_MSG_ID_ABORT_DONE, VID_API_EVENT_ABORT_DONE},
 694         {VPU_MSG_ID_BUF_RST, VID_API_EVENT_STR_BUF_RST},
 695         {VPU_MSG_ID_PIC_EOS, VID_API_EVENT_FINISHED},
 696         {VPU_MSG_ID_SEQ_HDR_FOUND, VID_API_EVENT_SEQ_HDR_FOUND},
 697         {VPU_MSG_ID_RES_CHANGE, VID_API_EVENT_RES_CHANGE},
 698         {VPU_MSG_ID_PIC_HDR_FOUND, VID_API_EVENT_PIC_HDR_FOUND},
 699         {VPU_MSG_ID_PIC_DECODED, VID_API_EVENT_PIC_DECODED},
 700         {VPU_MSG_ID_DEC_DONE, VID_API_EVENT_FRAME_BUFF_RDY},
 701         {VPU_MSG_ID_FRAME_REQ, VID_API_EVENT_REQ_FRAME_BUFF},
 702         {VPU_MSG_ID_FRAME_RELEASE, VID_API_EVENT_REL_FRAME_BUFF},
 703         {VPU_MSG_ID_FIFO_LOW, VID_API_EVENT_FIFO_LOW},
 704         {VPU_MSG_ID_BS_ERROR, VID_API_EVENT_BS_ERROR},
 705         {VPU_MSG_ID_UNSUPPORTED, VID_API_EVENT_UNSUPPORTED_STREAM},
 706         {VPU_MSG_ID_FIRMWARE_XCPT, VID_API_EVENT_FIRMWARE_XCPT},
 707         {VPU_MSG_ID_PIC_SKIPPED, VID_API_EVENT_PIC_SKIPPED},
 708 };
 709
 710 static void vpu_malone_pack_fs_alloc(struct vpu_rpc_event *pkt,
 711                                      struct vpu_fs_info *fs)
 712 {
 713         const u32 fs_type[] = {
 714                 [MEM_RES_FRAME] = 0,
 715                 [MEM_RES_MBI] = 1,
 716                 [MEM_RES_DCP] = 2,
 717         };
 718
 719         pkt->hdr.num = 7;
 720         pkt->data[0] = fs->id | (fs->tag << 24);
 721         pkt->data[1] = fs->luma_addr;
 722         if (fs->type == MEM_RES_FRAME) {
 723                 /*
 724                  * if luma_addr equal to chroma_addr,
 725                  * means luma(plane[0]) and chromau(plane[1]) used the
 726                  * same fd -- usage of NXP codec2. Need to manually
 727                  * offset chroma addr.
 728                  */
 729                 if (fs->luma_addr == fs->chroma_addr)
 730                         fs->chroma_addr = fs->luma_addr + fs->luma_size;
 731                 pkt->data[2] = fs->luma_addr + fs->luma_size / 2;
 732                 pkt->data[3] = fs->chroma_addr;
 733                 pkt->data[4] = fs->chroma_addr + fs->chromau_size / 2;
 734                 pkt->data[5] = fs->bytesperline;
 735         } else {
 736                 pkt->data[2] = fs->luma_size;
 737                 pkt->data[3] = 0;
 738                 pkt->data[4] = 0;
 739                 pkt->data[5] = 0;
 740         }
 741         pkt->data[6] = fs_type[fs->type];
 742 }
 743
 744 static void vpu_malone_pack_fs_release(struct vpu_rpc_event *pkt,
 745                                        struct vpu_fs_info *fs)
 746 {
 747         pkt->hdr.num = 1;
 748         pkt->data[0] = fs->id | (fs->tag << 24);
 749 }
 750
 751 static void vpu_malone_pack_timestamp(struct vpu_rpc_event *pkt,
 752                                       struct vpu_ts_info *info)
 753 {
 754         struct timespec64 ts = ns_to_timespec64(info->timestamp);
 755
 756         pkt->hdr.num = 3;
 757
 758         pkt->data[0] = ts.tv_sec;
 759         pkt->data[1] = ts.tv_nsec;
 760         pkt->data[2] = info->size;
 761 }
 762
 763 int vpu_malone_pack_cmd(struct vpu_rpc_event *pkt, u32 index, u32 id, void *data)
 764 {
 765         int ret;
 766
 767         ret = vpu_find_dst_by_src(malone_cmds, ARRAY_SIZE(malone_cmds), id);
 768         if (ret < 0)
 769                 return ret;
 770
 771         pkt->hdr.id = ret;
 772         pkt->hdr.num = 0;
 773         pkt->hdr.index = index;
 774
 775         switch (id) {
 776         case VPU_CMD_ID_FS_ALLOC:
 777                 vpu_malone_pack_fs_alloc(pkt, data);
 778                 break;
 779         case VPU_CMD_ID_FS_RELEASE:
 780                 vpu_malone_pack_fs_release(pkt, data);
 781                 break;
 782         case VPU_CMD_ID_TIMESTAMP:
 783                 vpu_malone_pack_timestamp(pkt, data);
 784                 break;
 785         }
 786
 787         pkt->hdr.index = index;
 788         return 0;
 789 }
 790
 791 int vpu_malone_convert_msg_id(u32 id)
 792 {
 793         return vpu_find_src_by_dst(malone_msgs, ARRAY_SIZE(malone_msgs), id);
 794 }
 795
 796 static void vpu_malone_fill_planes(struct vpu_dec_codec_info *info)
 797 {
 798         u32 interlaced = info->progressive ? 0 : 1;
 799
 800         info->bytesperline[0] = 0;
 801         info->sizeimage[0] = vpu_helper_get_plane_size(info->pixfmt,
 802                                                        info->decoded_width,
 803                                                        info->decoded_height,
 804                                                        0,
 805                                                        info->stride,
 806                                                        interlaced,
 807                                                        &info->bytesperline[0]);
 808         info->bytesperline[1] = 0;
 809         info->sizeimage[1] = vpu_helper_get_plane_size(info->pixfmt,
 810                                                        info->decoded_width,
 811                                                        info->decoded_height,
 812                                                        1,
 813                                                        info->stride,
 814                                                        interlaced,
 815                                                        &info->bytesperline[1]);
 816 }
 817
 818 static void vpu_malone_init_seq_hdr(struct vpu_dec_codec_info *info)
 819 {
 820         u32 chunks = info->num_dfe_area >> MALONE_DCP_CHUNK_BIT;
 821
 822         vpu_malone_fill_planes(info);
 823
 824         info->mbi_size = (info->sizeimage[0] + info->sizeimage[1]) >> 2;
 825         info->mbi_size = ALIGN(info->mbi_size, MALONE_ALIGN_MBI);
 826
 827         info->dcp_size = MALONE_DCP_SIZE_MAX;
 828         if (chunks) {
 829                 u32 mb_num;
 830                 u32 mb_w;
 831                 u32 mb_h;
 832
 833                 mb_w = DIV_ROUND_UP(info->decoded_width, 16);
 834                 mb_h = DIV_ROUND_UP(info->decoded_height, 16);
 835                 mb_num = mb_w * mb_h;
 836                 info->dcp_size = mb_num * MALONE_DCP_FIXED_MB_ALLOC * chunks;
 837                 info->dcp_size = clamp_t(u32, info->dcp_size,
 838                                          MALONE_DCP_SIZE_MIN, MALONE_DCP_SIZE_MAX);
 839         }
 840 }
 841
 842 static void vpu_malone_unpack_seq_hdr(struct vpu_rpc_event *pkt,
 843                                       struct vpu_dec_codec_info *info)
 844 {
 845         info->num_ref_frms = pkt->data[0];
 846         info->num_dpb_frms = pkt->data[1];
 847         info->num_dfe_area = pkt->data[2];
 848         info->progressive = pkt->data[3];
 849         info->width = pkt->data[5];
 850         info->height = pkt->data[4];
 851         info->decoded_width = pkt->data[12];
 852         info->decoded_height = pkt->data[11];
 853         info->frame_rate.numerator = 1000;
 854         info->frame_rate.denominator = pkt->data[8];
 855         info->dsp_asp_ratio = pkt->data[9];
 856         info->level_idc = pkt->data[10];
 857         info->bit_depth_luma = pkt->data[13];
 858         info->bit_depth_chroma = pkt->data[14];
 859         info->chroma_fmt = pkt->data[15];
 860         info->color_primaries = vpu_color_cvrt_primaries_i2v(pkt->data[16]);
 861         info->transfer_chars = vpu_color_cvrt_transfers_i2v(pkt->data[17]);
 862         info->matrix_coeffs = vpu_color_cvrt_matrix_i2v(pkt->data[18]);
 863         info->full_range = vpu_color_cvrt_full_range_i2v(pkt->data[19]);
 864         info->vui_present = pkt->data[20];
 865         info->mvc_num_views = pkt->data[21];
 866         info->offset_x = pkt->data[23];
 867         info->offset_y = pkt->data[25];
 868         info->tag = pkt->data[27];
 869         if (info->bit_depth_luma > 8)
 870                 info->pixfmt = V4L2_PIX_FMT_NV12M_10BE_8L128;
 871         else
 872                 info->pixfmt = V4L2_PIX_FMT_NV12M_8L128;
 873         if (info->frame_rate.numerator && info->frame_rate.denominator) {
 874                 unsigned long n, d;
 875
 876                 rational_best_approximation(info->frame_rate.numerator,
 877                                             info->frame_rate.denominator,
 878                                             info->frame_rate.numerator,
 879                                             info->frame_rate.denominator,
 880                                             &n, &d);
 881                 info->frame_rate.numerator = n;
 882                 info->frame_rate.denominator = d;
 883         }
 884         vpu_malone_init_seq_hdr(info);
 885 }
 886
 887 static void vpu_malone_unpack_pic_info(struct vpu_rpc_event *pkt,
 888                                        struct vpu_dec_pic_info *info)
 889 {
 890         info->id = pkt->data[7];
 891         info->luma = pkt->data[0];
 892         info->start = pkt->data[10];
 893         info->end = pkt->data[12];
 894         info->pic_size = pkt->data[11];
 895         info->stride = pkt->data[5];
 896         info->consumed_count = pkt->data[13];
 897         if (info->id == MALONE_SKIPPED_FRAME_ID)
 898                 info->skipped = 1;
 899         else
 900                 info->skipped = 0;
 901 }
 902
 903 static void vpu_malone_unpack_req_frame(struct vpu_rpc_event *pkt,
 904                                         struct vpu_fs_info *info)
 905 {
 906         info->type = pkt->data[1];
 907 }
 908
 909 static void vpu_malone_unpack_rel_frame(struct vpu_rpc_event *pkt,
 910                                         struct vpu_fs_info *info)
 911 {
 912         info->id = pkt->data[0];
 913         info->type = pkt->data[1];
 914         info->not_displayed = pkt->data[2];
 915 }
 916
 917 static void vpu_malone_unpack_buff_rdy(struct vpu_rpc_event *pkt,
 918                                        struct vpu_dec_pic_info *info)
 919 {
 920         struct timespec64 ts = { pkt->data[9], pkt->data[10] };
 921
 922         info->id = pkt->data[0];
 923         info->luma = pkt->data[1];
 924         info->stride = pkt->data[3];
 925         if (info->id == MALONE_SKIPPED_FRAME_ID)
 926                 info->skipped = 1;
 927         else
 928                 info->skipped = 0;
 929
 930         info->timestamp = timespec64_to_ns(&ts);
 931 }
 932
 933 int vpu_malone_unpack_msg_data(struct vpu_rpc_event *pkt, void *data)
 934 {
 935         if (!pkt || !data)
 936                 return -EINVAL;
 937
 938         switch (pkt->hdr.id) {
 939         case VID_API_EVENT_SEQ_HDR_FOUND:
 940                 vpu_malone_unpack_seq_hdr(pkt, data);
 941                 break;
 942         case VID_API_EVENT_PIC_DECODED:
 943                 vpu_malone_unpack_pic_info(pkt, data);
 944                 break;
 945         case VID_API_EVENT_REQ_FRAME_BUFF:
 946                 vpu_malone_unpack_req_frame(pkt, data);
 947                 break;
 948         case VID_API_EVENT_REL_FRAME_BUFF:
 949                 vpu_malone_unpack_rel_frame(pkt, data);
 950                 break;
 951         case VID_API_EVENT_FRAME_BUFF_RDY:
 952                 vpu_malone_unpack_buff_rdy(pkt, data);
 953                 break;
 954         }
 955
 956         return 0;
 957 }
 958
 959 static const struct malone_padding_scode padding_scodes[] = {
 960         {SCODE_PADDING_EOS,      V4L2_PIX_FMT_H264,        {0x0B010000, 0}},
 961         {SCODE_PADDING_EOS,      V4L2_PIX_FMT_H264_MVC,    {0x0B010000, 0}},
 962         {SCODE_PADDING_EOS,      V4L2_PIX_FMT_HEVC,        {0x4A010000, 0x20}},
 963         {SCODE_PADDING_EOS,      V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
 964         {SCODE_PADDING_EOS,      V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
 965         {SCODE_PADDING_EOS,      V4L2_PIX_FMT_MPEG2,       {0xCC010000, 0x0}},
 966         {SCODE_PADDING_EOS,      V4L2_PIX_FMT_MPEG4,       {0xb1010000, 0x0}},
 967         {SCODE_PADDING_EOS,      V4L2_PIX_FMT_XVID,        {0xb1010000, 0x0}},
 968         {SCODE_PADDING_EOS,      V4L2_PIX_FMT_H263,        {0xb1010000, 0x0}},
 969         {SCODE_PADDING_EOS,      V4L2_PIX_FMT_VP8,         {0x34010000, 0x0}},
 970         {SCODE_PADDING_EOS,      V4L2_PIX_FMT_JPEG,        {0xefff0000, 0x0}},
 971         {SCODE_PADDING_ABORT,    V4L2_PIX_FMT_H264,        {0x0B010000, 0}},
 972         {SCODE_PADDING_ABORT,    V4L2_PIX_FMT_H264_MVC,    {0x0B010000, 0}},
 973         {SCODE_PADDING_ABORT,    V4L2_PIX_FMT_HEVC,        {0x4A010000, 0x20}},
 974         {SCODE_PADDING_ABORT,    V4L2_PIX_FMT_VC1_ANNEX_G, {0x0a010000, 0x0}},
 975         {SCODE_PADDING_ABORT,    V4L2_PIX_FMT_VC1_ANNEX_L, {0x0a010000, 0x0}},
 976         {SCODE_PADDING_ABORT,    V4L2_PIX_FMT_MPEG2,       {0xb7010000, 0x0}},
 977         {SCODE_PADDING_ABORT,    V4L2_PIX_FMT_MPEG4,       {0xb1010000, 0x0}},
 978         {SCODE_PADDING_ABORT,    V4L2_PIX_FMT_XVID,        {0xb1010000, 0x0}},
 979         {SCODE_PADDING_ABORT,    V4L2_PIX_FMT_H263,        {0xb1010000, 0x0}},
 980         {SCODE_PADDING_ABORT,    V4L2_PIX_FMT_VP8,         {0x34010000, 0x0}},
 981         {SCODE_PADDING_EOS,      V4L2_PIX_FMT_JPEG,        {0x0, 0x0}},
 982         {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264,        {0x15010000, 0x0}},
 983         {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC,    {0x15010000, 0x0}},
 984 };
 985
 986 static const struct malone_padding_scode padding_scode_dft = {0x0, 0x0};
 987
 988 static const struct malone_padding_scode *get_padding_scode(u32 type, u32 fmt)
 989 {
 990         const struct malone_padding_scode *s;
 991         int i;
 992
 993         for (i = 0; i < ARRAY_SIZE(padding_scodes); i++) {
 994                 s = &padding_scodes[i];
 995
 996                 if (s->scode_type == type && s->pixelformat == fmt)
 997                         return s;
 998         }
 999
1000         if (type != SCODE_PADDING_BUFFLUSH)
1001                 return &padding_scode_dft;
1002
1003         return NULL;
1004 }
1005
1006 static int vpu_malone_add_padding_scode(struct vpu_buffer *stream_buffer,
1007                                         struct vpu_malone_str_buffer __iomem *str_buf,
1008                                         u32 pixelformat, u32 scode_type)
1009 {
1010         u32 wptr;
1011         int size;
1012         int total_size = 0;
1013         const struct malone_padding_scode *ps;
1014         const u32 padding_size = 4096;
1015         int ret;
1016
1017         ps = get_padding_scode(scode_type, pixelformat);
1018         if (!ps)
1019                 return -EINVAL;
1020
1021         wptr = readl(&str_buf->wptr);
1022         if (wptr < stream_buffer->phys || wptr > stream_buffer->phys + stream_buffer->length)
1023                 return -EINVAL;
1024         if (wptr == stream_buffer->phys + stream_buffer->length)
1025                 wptr = stream_buffer->phys;
1026         size = ALIGN(wptr, 4) - wptr;
1027         if (size)
1028                 vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size);
1029         total_size += size;
1030
1031         size = sizeof(ps->data);
1032         ret = vpu_helper_copy_to_stream_buffer(stream_buffer, &wptr, size, (void *)ps->data);
1033         if (ret < 0)
1034                 return -EINVAL;
1035         total_size += size;
1036
1037         size = padding_size - sizeof(ps->data);
1038         vpu_helper_memset_stream_buffer(stream_buffer, &wptr, 0, size);
1039         total_size += size;
1040
1041         vpu_malone_update_wptr(str_buf, wptr);
1042         return total_size;
1043 }
1044
1045 int vpu_malone_add_scode(struct vpu_shared_addr *shared,
1046                          u32 instance,
1047                          struct vpu_buffer *stream_buffer,
1048                          u32 pixelformat,
1049                          u32 scode_type)
1050 {
1051         struct vpu_dec_ctrl *hc = shared->priv;
1052         struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[instance];
1053         int ret = -EINVAL;
1054
1055         switch (scode_type) {
1056         case SCODE_PADDING_EOS:
1057         case SCODE_PADDING_ABORT:
1058         case SCODE_PADDING_BUFFLUSH:
1059                 ret = vpu_malone_add_padding_scode(stream_buffer, str_buf, pixelformat, scode_type);
1060                 break;
1061         default:
1062                 break;
1063         }
1064
1065         return ret;
1066 }
1067
1068 #define MALONE_PAYLOAD_HEADER_SIZE              16
1069 #define MALONE_CODEC_VERSION_ID                 0x1
1070 #define MALONE_CODEC_ID_VC1_SIMPLE              0x10
1071 #define MALONE_CODEC_ID_VC1_MAIN                0x11
1072 #define MALONE_CODEC_ID_ARV8                    0x28
1073 #define MALONE_CODEC_ID_ARV9                    0x29
1074 #define MALONE_CODEC_ID_VP6                     0x36
1075 #define MALONE_CODEC_ID_VP8                     0x36
1076 #define MALONE_CODEC_ID_DIVX3                   0x38
1077 #define MALONE_CODEC_ID_SPK                     0x39
1078
1079 #define MALONE_VP8_IVF_SEQ_HEADER_LEN           32
1080 #define MALONE_VP8_IVF_FRAME_HEADER_LEN         8
1081
1082 #define MALONE_VC1_RCV_CODEC_V1_VERSION         0x85
1083 #define MALONE_VC1_RCV_CODEC_V2_VERSION         0xC5
1084 #define MALONE_VC1_RCV_NUM_FRAMES               0xFF
1085 #define MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE        4
1086 #define MALONE_VC1_RCV_SEQ_HEADER_LEN           20
1087 #define MALONE_VC1_RCV_PIC_HEADER_LEN           4
1088 #define MALONE_VC1_NAL_HEADER_LEN               4
1089 #define MALONE_VC1_CONTAIN_NAL(data)            (((data) & 0x00FFFFFF) == 0x00010000)
1090
1091 static void set_payload_hdr(u8 *dst, u32 scd_type, u32 codec_id,
1092                             u32 buffer_size, u32 width, u32 height)
1093 {
1094         unsigned int payload_size;
1095         /* payload_size = buffer_size + itself_size(16) - start_code(4) */
1096         payload_size = buffer_size + 12;
1097
1098         dst[0] = 0x00;
1099         dst[1] = 0x00;
1100         dst[2] = 0x01;
1101         dst[3] = scd_type;
1102
1103         /* length */
1104         dst[4] = ((payload_size >> 16) & 0xff);
1105         dst[5] = ((payload_size >> 8) & 0xff);
1106         dst[6] = 0x4e;
1107         dst[7] = ((payload_size >> 0) & 0xff);
1108
1109         /* Codec ID and Version */
1110         dst[8] = codec_id;
1111         dst[9] = MALONE_CODEC_VERSION_ID;
1112
1113         /* width */
1114         dst[10] = ((width >> 8) & 0xff);
1115         dst[11] = ((width >> 0) & 0xff);
1116         dst[12] = 0x58;
1117
1118         /* height */
1119         dst[13] = ((height >> 8) & 0xff);
1120         dst[14] = ((height >> 0) & 0xff);
1121         dst[15] = 0x50;
1122 }
1123
1124 static void set_vp8_ivf_seqhdr(u8 *dst, u32 width, u32 height)
1125 {
1126         /* 0-3byte signature "DKIF" */
1127         dst[0] = 0x44;
1128         dst[1] = 0x4b;
1129         dst[2] = 0x49;
1130         dst[3] = 0x46;
1131         /* 4-5byte version: should be 0*/
1132         dst[4] = 0x00;
1133         dst[5] = 0x00;
1134         /* 6-7 length of Header */
1135         dst[6] = MALONE_VP8_IVF_SEQ_HEADER_LEN;
1136         dst[7] = MALONE_VP8_IVF_SEQ_HEADER_LEN >> 8;
1137         /* 8-11 VP8 fourcc */
1138         dst[8] = 0x56;
1139         dst[9] = 0x50;
1140         dst[10] = 0x38;
1141         dst[11] = 0x30;
1142         /* 12-13 width in pixels */
1143         dst[12] = width;
1144         dst[13] = width >> 8;
1145         /* 14-15 height in pixels */
1146         dst[14] = height;
1147         dst[15] = height >> 8;
1148         /* 16-19 frame rate */
1149         dst[16] = 0xe8;
1150         dst[17] = 0x03;
1151         dst[18] = 0x00;
1152         dst[19] = 0x00;
1153         /* 20-23 time scale */
1154         dst[20] = 0x01;
1155         dst[21] = 0x00;
1156         dst[22] = 0x00;
1157         dst[23] = 0x00;
1158         /* 24-27 number frames */
1159         dst[24] = 0xdf;
1160         dst[25] = 0xf9;
1161         dst[26] = 0x09;
1162         dst[27] = 0x00;
1163         /* 28-31 reserved */
1164 }
1165
1166 static void set_vp8_ivf_pichdr(u8 *dst, u32 frame_size)
1167 {
1168         /*
1169          * firmware just parse 64-bit timestamp(8 bytes).
1170          * As not transfer timestamp to firmware, use default value(ZERO).
1171          * No need to do anything here
1172          */
1173 }
1174
1175 static void set_vc1_rcv_seqhdr(u8 *dst, u8 *src, u32 width, u32 height)
1176 {
1177         u32 frames = MALONE_VC1_RCV_NUM_FRAMES;
1178         u32 ext_data_size = MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE;
1179
1180         /* 0-2 Number of frames, used default value 0xFF */
1181         dst[0] = frames;
1182         dst[1] = frames >> 8;
1183         dst[2] = frames >> 16;
1184
1185         /* 3 RCV version, used V1 */
1186         dst[3] = MALONE_VC1_RCV_CODEC_V1_VERSION;
1187
1188         /* 4-7 extension data size */
1189         dst[4] = ext_data_size;
1190         dst[5] = ext_data_size >> 8;
1191         dst[6] = ext_data_size >> 16;
1192         dst[7] = ext_data_size >> 24;
1193         /* 8-11 extension data */
1194         dst[8] = src[0];
1195         dst[9] = src[1];
1196         dst[10] = src[2];
1197         dst[11] = src[3];
1198
1199         /* height */
1200         dst[12] = height;
1201         dst[13] = (height >> 8) & 0xff;
1202         dst[14] = (height >> 16) & 0xff;
1203         dst[15] = (height >> 24) & 0xff;
1204         /* width */
1205         dst[16] = width;
1206         dst[17] = (width >> 8) & 0xff;
1207         dst[18] = (width >> 16) & 0xff;
1208         dst[19] = (width >> 24) & 0xff;
1209 }
1210
1211 static void set_vc1_rcv_pichdr(u8 *dst, u32 buffer_size)
1212 {
1213         dst[0] = buffer_size;
1214         dst[1] = buffer_size >> 8;
1215         dst[2] = buffer_size >> 16;
1216         dst[3] = buffer_size >> 24;
1217 }
1218
1219 static void create_vc1_nal_pichdr(u8 *dst)
1220 {
1221         /* need insert nal header: special ID */
1222         dst[0] = 0x0;
1223         dst[1] = 0x0;
1224         dst[2] = 0x01;
1225         dst[3] = 0x0D;
1226 }
1227
1228 static int vpu_malone_insert_scode_seq(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
1229 {
1230         u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
1231         int ret;
1232
1233         set_payload_hdr(hdr,
1234                         SCODE_SEQUENCE,
1235                         codec_id,
1236                         ext_size,
1237                         scode->inst->out_format.width,
1238                         scode->inst->out_format.height);
1239         ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1240                                                &scode->wptr,
1241                                                sizeof(hdr),
1242                                                hdr);
1243         if (ret < 0)
1244                 return ret;
1245         return sizeof(hdr);
1246 }
1247
1248 static int vpu_malone_insert_scode_pic(struct malone_scode_t *scode, u32 codec_id, u32 ext_size)
1249 {
1250         u8 hdr[MALONE_PAYLOAD_HEADER_SIZE];
1251         int ret;
1252
1253         set_payload_hdr(hdr,
1254                         SCODE_PICTURE,
1255                         codec_id,
1256                         ext_size + vb2_get_plane_payload(scode->vb, 0),
1257                         scode->inst->out_format.width,
1258                         scode->inst->out_format.height);
1259         ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1260                                                &scode->wptr,
1261                                                sizeof(hdr),
1262                                                hdr);
1263         if (ret < 0)
1264                 return ret;
1265         return sizeof(hdr);
1266 }
1267
1268 static int vpu_malone_insert_scode_vc1_g_pic(struct malone_scode_t *scode)
1269 {
1270         struct vb2_v4l2_buffer *vbuf;
1271         u8 nal_hdr[MALONE_VC1_NAL_HEADER_LEN];
1272         u32 *data = NULL;
1273         int ret;
1274
1275         vbuf = to_vb2_v4l2_buffer(scode->vb);
1276         data = vb2_plane_vaddr(scode->vb, 0);
1277
1278         if (vbuf->sequence == 0 || vpu_vb_is_codecconfig(vbuf))
1279                 return 0;
1280         if (MALONE_VC1_CONTAIN_NAL(*data))
1281                 return 0;
1282
1283         create_vc1_nal_pichdr(nal_hdr);
1284         ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1285                                                &scode->wptr,
1286                                                sizeof(nal_hdr),
1287                                                nal_hdr);
1288         if (ret < 0)
1289                 return ret;
1290         return sizeof(nal_hdr);
1291 }
1292
1293 static int vpu_malone_insert_scode_vc1_l_seq(struct malone_scode_t *scode)
1294 {
1295         int ret;
1296         int size = 0;
1297         u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN];
1298
1299         scode->need_data = 0;
1300
1301         ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VC1_SIMPLE, sizeof(rcv_seqhdr));
1302         if (ret < 0)
1303                 return ret;
1304         size = ret;
1305
1306         set_vc1_rcv_seqhdr(rcv_seqhdr,
1307                            vb2_plane_vaddr(scode->vb, 0),
1308                            scode->inst->out_format.width,
1309                            scode->inst->out_format.height);
1310         ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1311                                                &scode->wptr,
1312                                                sizeof(rcv_seqhdr),
1313                                                rcv_seqhdr);
1314
1315         if (ret < 0)
1316                 return ret;
1317         size += sizeof(rcv_seqhdr);
1318         return size;
1319 }
1320
1321 static int vpu_malone_insert_scode_vc1_l_pic(struct malone_scode_t *scode)
1322 {
1323         int ret;
1324         int size = 0;
1325         u8 rcv_pichdr[MALONE_VC1_RCV_PIC_HEADER_LEN];
1326
1327         ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VC1_SIMPLE,
1328                                           sizeof(rcv_pichdr));
1329         if (ret < 0)
1330                 return ret;
1331         size = ret;
1332
1333         set_vc1_rcv_pichdr(rcv_pichdr, vb2_get_plane_payload(scode->vb, 0));
1334         ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1335                                                &scode->wptr,
1336                                                sizeof(rcv_pichdr),
1337                                                rcv_pichdr);
1338         if (ret < 0)
1339                 return ret;
1340         size += sizeof(rcv_pichdr);
1341         return size;
1342 }
1343
1344 static int vpu_malone_insert_scode_vp8_seq(struct malone_scode_t *scode)
1345 {
1346         int ret;
1347         int size = 0;
1348         u8 ivf_hdr[MALONE_VP8_IVF_SEQ_HEADER_LEN];
1349
1350         ret = vpu_malone_insert_scode_seq(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr));
1351         if (ret < 0)
1352                 return ret;
1353         size = ret;
1354
1355         set_vp8_ivf_seqhdr(ivf_hdr,
1356                            scode->inst->out_format.width,
1357                            scode->inst->out_format.height);
1358         ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1359                                                &scode->wptr,
1360                                                sizeof(ivf_hdr),
1361                                                ivf_hdr);
1362         if (ret < 0)
1363                 return ret;
1364         size += sizeof(ivf_hdr);
1365
1366         return size;
1367 }
1368
1369 static int vpu_malone_insert_scode_vp8_pic(struct malone_scode_t *scode)
1370 {
1371         int ret;
1372         int size = 0;
1373         u8 ivf_hdr[MALONE_VP8_IVF_FRAME_HEADER_LEN] = {0};
1374
1375         ret = vpu_malone_insert_scode_pic(scode, MALONE_CODEC_ID_VP8, sizeof(ivf_hdr));
1376         if (ret < 0)
1377                 return ret;
1378         size = ret;
1379
1380         set_vp8_ivf_pichdr(ivf_hdr, vb2_get_plane_payload(scode->vb, 0));
1381         ret = vpu_helper_copy_to_stream_buffer(&scode->inst->stream_buffer,
1382                                                &scode->wptr,
1383                                                sizeof(ivf_hdr),
1384                                                ivf_hdr);
1385         if (ret < 0)
1386                 return ret;
1387         size += sizeof(ivf_hdr);
1388
1389         return size;
1390 }
1391
1392 static const struct malone_scode_handler scode_handlers[] = {
1393         {
1394                 /* fix me, need to swap return operation after gstreamer swap */
1395                 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_L,
1396                 .insert_scode_seq = vpu_malone_insert_scode_vc1_l_seq,
1397                 .insert_scode_pic = vpu_malone_insert_scode_vc1_l_pic,
1398         },
1399         {
1400                 .pixelformat = V4L2_PIX_FMT_VC1_ANNEX_G,
1401                 .insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic,
1402         },
1403         {
1404                 .pixelformat = V4L2_PIX_FMT_VP8,
1405                 .insert_scode_seq = vpu_malone_insert_scode_vp8_seq,
1406                 .insert_scode_pic = vpu_malone_insert_scode_vp8_pic,
1407         },
1408 };
1409
1410 static const struct malone_scode_handler *get_scode_handler(u32 pixelformat)
1411 {
1412         int i;
1413
1414         for (i = 0; i < ARRAY_SIZE(scode_handlers); i++) {
1415                 if (scode_handlers[i].pixelformat == pixelformat)
1416                         return &scode_handlers[i];
1417         }
1418
1419         return NULL;
1420 }
1421
1422 static int vpu_malone_insert_scode(struct malone_scode_t *scode, u32 type)
1423 {
1424         const struct malone_scode_handler *handler;
1425         int ret = 0;
1426
1427         if (!scode || !scode->inst || !scode->vb)
1428                 return 0;
1429
1430         scode->need_data = 1;
1431         handler = get_scode_handler(scode->inst->out_format.pixfmt);
1432         if (!handler)
1433                 return 0;
1434
1435         switch (type) {
1436         case SCODE_SEQUENCE:
1437                 if (handler->insert_scode_seq)
1438                         ret = handler->insert_scode_seq(scode);
1439                 break;
1440         case SCODE_PICTURE:
1441                 if (handler->insert_scode_pic)
1442                         ret = handler->insert_scode_pic(scode);
1443                 break;
1444         default:
1445                 break;
1446         }
1447
1448         return ret;
1449 }
1450
1451 static int vpu_malone_input_frame_data(struct vpu_malone_str_buffer __iomem *str_buf,
1452                                        struct vpu_inst *inst, struct vb2_buffer *vb,
1453                                        u32 disp_imm)
1454 {
1455         struct malone_scode_t scode;
1456         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1457         u32 wptr = readl(&str_buf->wptr);
1458         int size = 0;
1459         int ret = 0;
1460
1461         /*add scode: SCODE_SEQUENCE, SCODE_PICTURE, SCODE_SLICE*/
1462         scode.inst = inst;
1463         scode.vb = vb;
1464         scode.wptr = wptr;
1465         scode.need_data = 1;
1466         if (vbuf->sequence == 0 || vpu_vb_is_codecconfig(vbuf))
1467                 ret = vpu_malone_insert_scode(&scode, SCODE_SEQUENCE);
1468
1469         if (ret < 0)
1470                 return -ENOMEM;
1471         size += ret;
1472         wptr = scode.wptr;
1473         if (!scode.need_data) {
1474                 vpu_malone_update_wptr(str_buf, wptr);
1475                 return size;
1476         }
1477
1478         ret = vpu_malone_insert_scode(&scode, SCODE_PICTURE);
1479         if (ret < 0)
1480                 return -ENOMEM;
1481         size += ret;
1482         wptr = scode.wptr;
1483
1484         ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
1485                                                &wptr,
1486                                                vb2_get_plane_payload(vb, 0),
1487                                                vb2_plane_vaddr(vb, 0));
1488         if (ret < 0)
1489                 return -ENOMEM;
1490         size += vb2_get_plane_payload(vb, 0);
1491
1492         vpu_malone_update_wptr(str_buf, wptr);
1493
1494         if (disp_imm && !vpu_vb_is_codecconfig(vbuf)) {
1495                 ret = vpu_malone_add_scode(inst->core->iface,
1496                                            inst->id,
1497                                            &inst->stream_buffer,
1498                                            inst->out_format.pixfmt,
1499                                            SCODE_PADDING_BUFFLUSH);
1500                 if (ret < 0)
1501                         return ret;
1502                 size += ret;
1503         }
1504
1505         return size;
1506 }
1507
1508 static int vpu_malone_input_stream_data(struct vpu_malone_str_buffer __iomem *str_buf,
1509                                         struct vpu_inst *inst, struct vb2_buffer *vb)
1510 {
1511         u32 wptr = readl(&str_buf->wptr);
1512         int ret = 0;
1513
1514         ret = vpu_helper_copy_to_stream_buffer(&inst->stream_buffer,
1515                                                &wptr,
1516                                                vb2_get_plane_payload(vb, 0),
1517                                                vb2_plane_vaddr(vb, 0));
1518         if (ret < 0)
1519                 return -ENOMEM;
1520
1521         vpu_malone_update_wptr(str_buf, wptr);
1522
1523         return ret;
1524 }
1525
1526 static int vpu_malone_input_ts(struct vpu_inst *inst, s64  timestamp, u32 size)
1527 {
1528         struct vpu_ts_info info;
1529
1530         memset(&info, 0, sizeof(info));
1531         info.timestamp = timestamp;
1532         info.size = size;
1533
1534         return vpu_session_fill_timestamp(inst, &info);
1535 }
1536
1537 int vpu_malone_input_frame(struct vpu_shared_addr *shared,
1538                            struct vpu_inst *inst, struct vb2_buffer *vb)
1539 {
1540         struct vpu_dec_ctrl *hc = shared->priv;
1541         struct vb2_v4l2_buffer *vbuf;
1542         struct vpu_malone_str_buffer __iomem *str_buf = hc->str_buf[inst->id];
1543         u32 disp_imm = hc->codec_param[inst->id].disp_imm;
1544         u32 size;
1545         int ret;
1546
1547         if (vpu_malone_is_non_frame_mode(shared, inst->id))
1548                 ret = vpu_malone_input_stream_data(str_buf, inst, vb);
1549         else
1550                 ret = vpu_malone_input_frame_data(str_buf, inst, vb, disp_imm);
1551         if (ret < 0)
1552                 return ret;
1553         size = ret;
1554
1555         /*
1556          * if buffer only contain codec data, and the timestamp is invalid,
1557          * don't put the invalid timestamp to resync
1558          * merge the data to next frame
1559          */
1560         vbuf = to_vb2_v4l2_buffer(vb);
1561         if (vpu_vb_is_codecconfig(vbuf)) {
1562                 inst->extra_size += size;
1563                 return 0;
1564         }
1565         if (inst->extra_size) {
1566                 size += inst->extra_size;
1567                 inst->extra_size = 0;
1568         }
1569
1570         ret = vpu_malone_input_ts(inst, vb->timestamp, size);
1571         if (ret)
1572                 return ret;
1573
1574         return 0;
1575 }
1576
1577 static bool vpu_malone_check_ready(struct vpu_shared_addr *shared, u32 instance)
1578 {
1579         struct malone_iface *iface = shared->iface;
1580         struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1581         u32 size = desc->end - desc->start;
1582         u32 rptr = desc->rptr;
1583         u32 wptr = desc->wptr;
1584         u32 used;
1585
1586         if (!size)
1587                 return true;
1588
1589         used = (wptr + size - rptr) % size;
1590         if (used < (size / 2))
1591                 return true;
1592
1593         return false;
1594 }
1595
1596 bool vpu_malone_is_ready(struct vpu_shared_addr *shared, u32 instance)
1597 {
1598         u32 cnt = 0;
1599
1600         while (!vpu_malone_check_ready(shared, instance)) {
1601                 if (cnt > 30)
1602                         return false;
1603                 mdelay(1);
1604                 cnt++;
1605         }
1606         return true;
1607 }
1608
1609 int vpu_malone_pre_cmd(struct vpu_shared_addr *shared, u32 instance)
1610 {
1611         if (!vpu_malone_is_ready(shared, instance))
1612                 return -EINVAL;
1613
1614         return 0;
1615 }
1616
1617 int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance)
1618 {
1619         struct malone_iface *iface = shared->iface;
1620         struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1621
1622         desc->wptr++;
1623         if (desc->wptr == desc->end)
1624                 desc->wptr = desc->start;
1625
1626         return 0;
1627 }
1628
1629 int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance)
1630 {
1631         struct malone_iface *iface = shared->iface;
1632         struct vpu_rpc_buffer_desc *desc = &iface->api_cmd_buffer_desc[instance];
1633
1634         desc->wptr = desc->rptr;
1635         if (desc->wptr == desc->end)
1636                 desc->wptr = desc->start;
1637
1638         return 0;
1639 }
1640
1641 u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared)
1642 {
1643         struct malone_iface *iface = shared->iface;
1644
1645         return iface->max_streams;
1646 }