drivers/media/platform/am437x/am437x-vpfe_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * TI AM437x Image Sensor Interface Registers
   4  *
   5  * Copyright (C) 2013 - 2014 Texas Instruments, Inc.
   6  *
   7  * Benoit Parrot <bparrot@ti.com>
   8  * Lad, Prabhakar <prabhakar.csengg@gmail.com>
   9  */
  10
  11 #ifndef AM437X_VPFE_REGS_H
  12 #define AM437X_VPFE_REGS_H
  13
  14 /* VPFE module register offset */
  15 #define VPFE_REVISION                           0x0
  16 #define VPFE_PCR                                0x4
  17 #define VPFE_SYNMODE                            0x8
  18 #define VPFE_HD_VD_WID                          0xc
  19 #define VPFE_PIX_LINES                          0x10
  20 #define VPFE_HORZ_INFO                          0x14
  21 #define VPFE_VERT_START                         0x18
  22 #define VPFE_VERT_LINES                         0x1c
  23 #define VPFE_CULLING                            0x20
  24 #define VPFE_HSIZE_OFF                          0x24
  25 #define VPFE_SDOFST                             0x28
  26 #define VPFE_SDR_ADDR                           0x2c
  27 #define VPFE_CLAMP                              0x30
  28 #define VPFE_DCSUB                              0x34
  29 #define VPFE_COLPTN                             0x38
  30 #define VPFE_BLKCMP                             0x3c
  31 #define VPFE_VDINT                              0x48
  32 #define VPFE_ALAW                               0x4c
  33 #define VPFE_REC656IF                           0x50
  34 #define VPFE_CCDCFG                             0x54
  35 #define VPFE_DMA_CNTL                           0x98
  36 #define VPFE_SYSCONFIG                          0x104
  37 #define VPFE_CONFIG                             0x108
  38 #define VPFE_IRQ_EOI                            0x110
  39 #define VPFE_IRQ_STS_RAW                        0x114
  40 #define VPFE_IRQ_STS                            0x118
  41 #define VPFE_IRQ_EN_SET                         0x11c
  42 #define VPFE_IRQ_EN_CLR                         0x120
  43 #define VPFE_REG_END                            0x124
  44
  45 /* Define bit fields within selected registers */
  46 #define VPFE_FID_POL_MASK                       1
  47 #define VPFE_FID_POL_SHIFT                      4
  48 #define VPFE_HD_POL_MASK                        1
  49 #define VPFE_HD_POL_SHIFT                       3
  50 #define VPFE_VD_POL_MASK                        1
  51 #define VPFE_VD_POL_SHIFT                       2
  52 #define VPFE_HSIZE_OFF_MASK                     0xffffffe0
  53 #define VPFE_32BYTE_ALIGN_VAL                   31
  54 #define VPFE_FRM_FMT_MASK                       0x1
  55 #define VPFE_FRM_FMT_SHIFT                      7
  56 #define VPFE_DATA_SZ_MASK                       7
  57 #define VPFE_DATA_SZ_SHIFT                      8
  58 #define VPFE_PIX_FMT_MASK                       3
  59 #define VPFE_PIX_FMT_SHIFT                      12
  60 #define VPFE_VP2SDR_DISABLE                     0xfffbffff
  61 #define VPFE_WEN_ENABLE                         BIT(17)
  62 #define VPFE_SDR2RSZ_DISABLE                    0xfff7ffff
  63 #define VPFE_VDHDEN_ENABLE                      BIT(16)
  64 #define VPFE_LPF_ENABLE                         BIT(14)
  65 #define VPFE_ALAW_ENABLE                        BIT(3)
  66 #define VPFE_ALAW_GAMMA_WD_MASK                 7
  67 #define VPFE_BLK_CLAMP_ENABLE                   BIT(31)
  68 #define VPFE_BLK_SGAIN_MASK                     0x1f
  69 #define VPFE_BLK_ST_PXL_MASK                    0x7fff
  70 #define VPFE_BLK_ST_PXL_SHIFT                   10
  71 #define VPFE_BLK_SAMPLE_LN_MASK                 7
  72 #define VPFE_BLK_SAMPLE_LN_SHIFT                28
  73 #define VPFE_BLK_SAMPLE_LINE_MASK               7
  74 #define VPFE_BLK_SAMPLE_LINE_SHIFT              25
  75 #define VPFE_BLK_DC_SUB_MASK                    0x03fff
  76 #define VPFE_BLK_COMP_MASK                      0xff
  77 #define VPFE_BLK_COMP_GB_COMP_SHIFT             8
  78 #define VPFE_BLK_COMP_GR_COMP_SHIFT             16
  79 #define VPFE_BLK_COMP_R_COMP_SHIFT              24
  80 #define VPFE_LATCH_ON_VSYNC_DISABLE             BIT(15)
  81 #define VPFE_DATA_PACK_ENABLE                   BIT(11)
  82 #define VPFE_HORZ_INFO_SPH_SHIFT                16
  83 #define VPFE_VERT_START_SLV0_SHIFT              16
  84 #define VPFE_VDINT_VDINT0_SHIFT                 16
  85 #define VPFE_VDINT_VDINT1_MASK                  0xffff
  86 #define VPFE_PPC_RAW                            1
  87 #define VPFE_DCSUB_DEFAULT_VAL                  0
  88 #define VPFE_CLAMP_DEFAULT_VAL                  0
  89 #define VPFE_COLPTN_VAL                         0xbb11bb11
  90 #define VPFE_TWO_BYTES_PER_PIXEL                2
  91 #define VPFE_INTERLACED_IMAGE_INVERT            0x4b6d
  92 #define VPFE_INTERLACED_NO_IMAGE_INVERT         0x0249
  93 #define VPFE_PROGRESSIVE_IMAGE_INVERT           0x4000
  94 #define VPFE_PROGRESSIVE_NO_IMAGE_INVERT        0
  95 #define VPFE_INTERLACED_HEIGHT_SHIFT            1
  96 #define VPFE_SYN_MODE_INPMOD_SHIFT              12
  97 #define VPFE_SYN_MODE_INPMOD_MASK               3
  98 #define VPFE_SYN_MODE_8BITS                     (7 << 8)
  99 #define VPFE_SYN_MODE_10BITS                    (6 << 8)
 100 #define VPFE_SYN_MODE_11BITS                    (5 << 8)
 101 #define VPFE_SYN_MODE_12BITS                    (4 << 8)
 102 #define VPFE_SYN_MODE_13BITS                    (3 << 8)
 103 #define VPFE_SYN_MODE_14BITS                    (2 << 8)
 104 #define VPFE_SYN_MODE_15BITS                    (1 << 8)
 105 #define VPFE_SYN_MODE_16BITS                    (0 << 8)
 106 #define VPFE_SYN_FLDMODE_MASK                   1
 107 #define VPFE_SYN_FLDMODE_SHIFT                  7
 108 #define VPFE_REC656IF_BT656_EN                  3
 109 #define VPFE_SYN_MODE_VD_POL_NEGATIVE           BIT(2)
 110 #define VPFE_CCDCFG_Y8POS_SHIFT                 11
 111 #define VPFE_CCDCFG_BW656_10BIT                 BIT(5)
 112 #define VPFE_SDOFST_FIELD_INTERLEAVED           0x249
 113 #define VPFE_NO_CULLING                         0xffff00ff
 114 #define VPFE_VDINT0                             BIT(0)
 115 #define VPFE_VDINT1                             BIT(1)
 116 #define VPFE_VDINT2                             BIT(2)
 117 #define VPFE_DMA_CNTL_OVERFLOW                  BIT(31)
 118
 119 #define VPFE_CONFIG_PCLK_INV_SHIFT              0
 120 #define VPFE_CONFIG_PCLK_INV_MASK               1
 121 #define VPFE_CONFIG_PCLK_INV_NOT_INV            0
 122 #define VPFE_CONFIG_PCLK_INV_INV                1
 123 #define VPFE_CONFIG_EN_SHIFT                    1
 124 #define VPFE_CONFIG_EN_MASK                     2
 125 #define VPFE_CONFIG_EN_DISABLE                  0
 126 #define VPFE_CONFIG_EN_ENABLE                   1
 127 #define VPFE_CONFIG_ST_SHIFT                    2
 128 #define VPFE_CONFIG_ST_MASK                     4
 129 #define VPFE_CONFIG_ST_OCP_ACTIVE               0
 130 #define VPFE_CONFIG_ST_OCP_STANDBY              1
 131
 132 #endif          /* AM437X_VPFE_REGS_H */