drivers/media/platform/allegro-dvt/allegro-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Pengutronix, Michael Tretter <kernel@pengutronix.de>
   4  *
   5  * Allegro DVT video encoder driver
   6  */
   7
   8 #include <linux/bits.h>
   9 #include <linux/clk.h>
  10 #include <linux/firmware.h>
  11 #include <linux/gcd.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/log2.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/mfd/syscon/xlnx-vcu.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regmap.h>
  23 #include <linux/sizes.h>
  24 #include <linux/slab.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-ctrls.h>
  27 #include <media/v4l2-device.h>
  28 #include <media/v4l2-event.h>
  29 #include <media/v4l2-ioctl.h>
  30 #include <media/v4l2-mem2mem.h>
  31 #include <media/videobuf2-dma-contig.h>
  32 #include <media/videobuf2-v4l2.h>
  33
  34 #include "allegro-mail.h"
  35 #include "nal-h264.h"
  36 #include "nal-hevc.h"
  37
  38 /*
  39  * Support up to 4k video streams. The hardware actually supports higher
  40  * resolutions, which are specified in PG252 June 6, 2018 (H.264/H.265 Video
  41  * Codec Unit v1.1) Chapter 3.
  42  */
  43 #define ALLEGRO_WIDTH_MIN 128
  44 #define ALLEGRO_WIDTH_DEFAULT 1920
  45 #define ALLEGRO_WIDTH_MAX 3840
  46 #define ALLEGRO_HEIGHT_MIN 64
  47 #define ALLEGRO_HEIGHT_DEFAULT 1080
  48 #define ALLEGRO_HEIGHT_MAX 2160
  49
  50 #define ALLEGRO_FRAMERATE_DEFAULT ((struct v4l2_fract) { 30, 1 })
  51
  52 #define ALLEGRO_GOP_SIZE_DEFAULT 25
  53 #define ALLEGRO_GOP_SIZE_MAX 1000
  54
  55 /*
  56  * MCU Control Registers
  57  *
  58  * The Zynq UltraScale+ Devices Register Reference documents the registers
  59  * with an offset of 0x9000, which equals the size of the SRAM and one page
  60  * gap. The driver handles SRAM and registers separately and, therefore, is
  61  * oblivious of the offset.
  62  */
  63 #define AL5_MCU_RESET                   0x0000
  64 #define AL5_MCU_RESET_SOFT              BIT(0)
  65 #define AL5_MCU_RESET_REGS              BIT(1)
  66 #define AL5_MCU_RESET_MODE              0x0004
  67 #define AL5_MCU_RESET_MODE_SLEEP        BIT(0)
  68 #define AL5_MCU_RESET_MODE_HALT         BIT(1)
  69 #define AL5_MCU_STA                     0x0008
  70 #define AL5_MCU_STA_SLEEP               BIT(0)
  71 #define AL5_MCU_WAKEUP                  0x000c
  72
  73 #define AL5_ICACHE_ADDR_OFFSET_MSB      0x0010
  74 #define AL5_ICACHE_ADDR_OFFSET_LSB      0x0014
  75 #define AL5_DCACHE_ADDR_OFFSET_MSB      0x0018
  76 #define AL5_DCACHE_ADDR_OFFSET_LSB      0x001c
  77
  78 #define AL5_MCU_INTERRUPT               0x0100
  79 #define AL5_ITC_CPU_IRQ_MSK             0x0104
  80 #define AL5_ITC_CPU_IRQ_CLR             0x0108
  81 #define AL5_ITC_CPU_IRQ_STA             0x010C
  82 #define AL5_ITC_CPU_IRQ_STA_TRIGGERED   BIT(0)
  83
  84 #define AXI_ADDR_OFFSET_IP              0x0208
  85
  86 /*
  87  * The MCU accesses the system memory with a 2G offset compared to CPU
  88  * physical addresses.
  89  */
  90 #define MCU_CACHE_OFFSET SZ_2G
  91
  92 /*
  93  * The driver needs to reserve some space at the beginning of capture buffers,
  94  * because it needs to write SPS/PPS NAL units. The encoder writes the actual
  95  * frame data after the offset.
  96  */
  97 #define ENCODER_STREAM_OFFSET SZ_128
  98
  99 #define SIZE_MACROBLOCK 16
 100
 101 /* Encoding options */
 102 #define LOG2_MAX_FRAME_NUM              4
 103 #define LOG2_MAX_PIC_ORDER_CNT          10
 104 #define BETA_OFFSET_DIV_2               -1
 105 #define TC_OFFSET_DIV_2                 -1
 106
 107 /*
 108  * This control allows applications to explicitly disable the encoder buffer.
 109  * This value is Allegro specific.
 110  */
 111 #define V4L2_CID_USER_ALLEGRO_ENCODER_BUFFER (V4L2_CID_USER_ALLEGRO_BASE + 0)
 112
 113 static int debug;
 114 module_param(debug, int, 0644);
 115 MODULE_PARM_DESC(debug, "Debug level (0-2)");
 116
 117 struct allegro_buffer {
 118         void *vaddr;
 119         dma_addr_t paddr;
 120         size_t size;
 121         struct list_head head;
 122 };
 123
 124 struct allegro_dev;
 125 struct allegro_channel;
 126
 127 struct allegro_mbox {
 128         struct allegro_dev *dev;
 129         unsigned int head;
 130         unsigned int tail;
 131         unsigned int data;
 132         size_t size;
 133         /* protect mailbox from simultaneous accesses */
 134         struct mutex lock;
 135 };
 136
 137 struct allegro_encoder_buffer {
 138         unsigned int size;
 139         unsigned int color_depth;
 140         unsigned int num_cores;
 141         unsigned int clk_rate;
 142 };
 143
 144 struct allegro_dev {
 145         struct v4l2_device v4l2_dev;
 146         struct video_device video_dev;
 147         struct v4l2_m2m_dev *m2m_dev;
 148         struct platform_device *plat_dev;
 149
 150         /* mutex protecting vb2_queue structure */
 151         struct mutex lock;
 152
 153         struct regmap *regmap;
 154         struct regmap *sram;
 155         struct regmap *settings;
 156
 157         struct clk *clk_core;
 158         struct clk *clk_mcu;
 159
 160         const struct fw_info *fw_info;
 161         struct allegro_buffer firmware;
 162         struct allegro_buffer suballocator;
 163         bool has_encoder_buffer;
 164         struct allegro_encoder_buffer encoder_buffer;
 165
 166         struct completion init_complete;
 167         bool initialized;
 168
 169         /* The mailbox interface */
 170         struct allegro_mbox *mbox_command;
 171         struct allegro_mbox *mbox_status;
 172
 173         /*
 174          * The downstream driver limits the users to 64 users, thus I can use
 175          * a bitfield for the user_ids that are in use. See also user_id in
 176          * struct allegro_channel.
 177          */
 178         unsigned long channel_user_ids;
 179         struct list_head channels;
 180 };
 181
 182 static struct regmap_config allegro_regmap_config = {
 183         .name = "regmap",
 184         .reg_bits = 32,
 185         .val_bits = 32,
 186         .reg_stride = 4,
 187         .max_register = 0xfff,
 188         .cache_type = REGCACHE_NONE,
 189 };
 190
 191 static struct regmap_config allegro_sram_config = {
 192         .name = "sram",
 193         .reg_bits = 32,
 194         .val_bits = 32,
 195         .reg_stride = 4,
 196         .max_register = 0x7fff,
 197         .cache_type = REGCACHE_NONE,
 198 };
 199
 200 #define fh_to_channel(__fh) container_of(__fh, struct allegro_channel, fh)
 201
 202 struct allegro_channel {
 203         struct allegro_dev *dev;
 204         struct v4l2_fh fh;
 205         struct v4l2_ctrl_handler ctrl_handler;
 206
 207         unsigned int width;
 208         unsigned int height;
 209         unsigned int stride;
 210         struct v4l2_fract framerate;
 211
 212         enum v4l2_colorspace colorspace;
 213         enum v4l2_ycbcr_encoding ycbcr_enc;
 214         enum v4l2_quantization quantization;
 215         enum v4l2_xfer_func xfer_func;
 216
 217         u32 pixelformat;
 218         unsigned int sizeimage_raw;
 219         unsigned int osequence;
 220
 221         u32 codec;
 222         unsigned int sizeimage_encoded;
 223         unsigned int csequence;
 224
 225         bool frame_rc_enable;
 226         unsigned int bitrate;
 227         unsigned int bitrate_peak;
 228
 229         struct allegro_buffer config_blob;
 230
 231         unsigned int log2_max_frame_num;
 232         bool temporal_mvp_enable;
 233
 234         bool enable_loop_filter_across_tiles;
 235         bool enable_loop_filter_across_slices;
 236         bool enable_deblocking_filter_override;
 237         bool enable_reordering;
 238         bool dbf_ovr_en;
 239
 240         unsigned int num_ref_idx_l0;
 241         unsigned int num_ref_idx_l1;
 242
 243         /* Maximum range for motion estimation */
 244         int b_hrz_me_range;
 245         int b_vrt_me_range;
 246         int p_hrz_me_range;
 247         int p_vrt_me_range;
 248         /* Size limits of coding unit */
 249         int min_cu_size;
 250         int max_cu_size;
 251         /* Size limits of transform unit */
 252         int min_tu_size;
 253         int max_tu_size;
 254         int max_transfo_depth_intra;
 255         int max_transfo_depth_inter;
 256
 257         struct v4l2_ctrl *mpeg_video_h264_profile;
 258         struct v4l2_ctrl *mpeg_video_h264_level;
 259         struct v4l2_ctrl *mpeg_video_h264_i_frame_qp;
 260         struct v4l2_ctrl *mpeg_video_h264_max_qp;
 261         struct v4l2_ctrl *mpeg_video_h264_min_qp;
 262         struct v4l2_ctrl *mpeg_video_h264_p_frame_qp;
 263         struct v4l2_ctrl *mpeg_video_h264_b_frame_qp;
 264
 265         struct v4l2_ctrl *mpeg_video_hevc_profile;
 266         struct v4l2_ctrl *mpeg_video_hevc_level;
 267         struct v4l2_ctrl *mpeg_video_hevc_tier;
 268         struct v4l2_ctrl *mpeg_video_hevc_i_frame_qp;
 269         struct v4l2_ctrl *mpeg_video_hevc_max_qp;
 270         struct v4l2_ctrl *mpeg_video_hevc_min_qp;
 271         struct v4l2_ctrl *mpeg_video_hevc_p_frame_qp;
 272         struct v4l2_ctrl *mpeg_video_hevc_b_frame_qp;
 273
 274         struct v4l2_ctrl *mpeg_video_frame_rc_enable;
 275         struct { /* video bitrate mode control cluster */
 276                 struct v4l2_ctrl *mpeg_video_bitrate_mode;
 277                 struct v4l2_ctrl *mpeg_video_bitrate;
 278                 struct v4l2_ctrl *mpeg_video_bitrate_peak;
 279         };
 280         struct v4l2_ctrl *mpeg_video_cpb_size;
 281         struct v4l2_ctrl *mpeg_video_gop_size;
 282
 283         struct v4l2_ctrl *encoder_buffer;
 284
 285         /* user_id is used to identify the channel during CREATE_CHANNEL */
 286         /* not sure, what to set here and if this is actually required */
 287         int user_id;
 288         /* channel_id is set by the mcu and used by all later commands */
 289         int mcu_channel_id;
 290
 291         struct list_head buffers_reference;
 292         struct list_head buffers_intermediate;
 293
 294         struct list_head source_shadow_list;
 295         struct list_head stream_shadow_list;
 296         /* protect shadow lists of buffers passed to firmware */
 297         struct mutex shadow_list_lock;
 298
 299         struct list_head list;
 300         struct completion completion;
 301
 302         unsigned int error;
 303 };
 304
 305 static inline int
 306 allegro_channel_get_i_frame_qp(struct allegro_channel *channel)
 307 {
 308         if (channel->codec == V4L2_PIX_FMT_HEVC)
 309                 return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_i_frame_qp);
 310         else
 311                 return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_i_frame_qp);
 312 }
 313
 314 static inline int
 315 allegro_channel_get_p_frame_qp(struct allegro_channel *channel)
 316 {
 317         if (channel->codec == V4L2_PIX_FMT_HEVC)
 318                 return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_p_frame_qp);
 319         else
 320                 return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_p_frame_qp);
 321 }
 322
 323 static inline int
 324 allegro_channel_get_b_frame_qp(struct allegro_channel *channel)
 325 {
 326         if (channel->codec == V4L2_PIX_FMT_HEVC)
 327                 return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_b_frame_qp);
 328         else
 329                 return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_b_frame_qp);
 330 }
 331
 332 static inline int
 333 allegro_channel_get_min_qp(struct allegro_channel *channel)
 334 {
 335         if (channel->codec == V4L2_PIX_FMT_HEVC)
 336                 return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_min_qp);
 337         else
 338                 return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_min_qp);
 339 }
 340
 341 static inline int
 342 allegro_channel_get_max_qp(struct allegro_channel *channel)
 343 {
 344         if (channel->codec == V4L2_PIX_FMT_HEVC)
 345                 return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_max_qp);
 346         else
 347                 return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_max_qp);
 348 }
 349
 350 struct allegro_m2m_buffer {
 351         struct v4l2_m2m_buffer buf;
 352         struct list_head head;
 353 };
 354
 355 #define to_allegro_m2m_buffer(__buf) \
 356         container_of(__buf, struct allegro_m2m_buffer, buf)
 357
 358 struct fw_info {
 359         unsigned int id;
 360         unsigned int id_codec;
 361         char *version;
 362         unsigned int mailbox_cmd;
 363         unsigned int mailbox_status;
 364         size_t mailbox_size;
 365         enum mcu_msg_version mailbox_version;
 366         size_t suballocator_size;
 367 };
 368
 369 static const struct fw_info supported_firmware[] = {
 370         {
 371                 .id = 18296,
 372                 .id_codec = 96272,
 373                 .version = "v2018.2",
 374                 .mailbox_cmd = 0x7800,
 375                 .mailbox_status = 0x7c00,
 376                 .mailbox_size = 0x400 - 0x8,
 377                 .mailbox_version = MCU_MSG_VERSION_2018_2,
 378                 .suballocator_size = SZ_16M,
 379         }, {
 380                 .id = 14680,
 381                 .id_codec = 126572,
 382                 .version = "v2019.2",
 383                 .mailbox_cmd = 0x7000,
 384                 .mailbox_status = 0x7800,
 385                 .mailbox_size = 0x800 - 0x8,
 386                 .mailbox_version = MCU_MSG_VERSION_2019_2,
 387                 .suballocator_size = SZ_32M,
 388         },
 389 };
 390
 391 static inline u32 to_mcu_addr(struct allegro_dev *dev, dma_addr_t phys)
 392 {
 393         if (upper_32_bits(phys) || (lower_32_bits(phys) & MCU_CACHE_OFFSET))
 394                 v4l2_warn(&dev->v4l2_dev,
 395                           "address %pad is outside mcu window\n", &phys);
 396
 397         return lower_32_bits(phys) | MCU_CACHE_OFFSET;
 398 }
 399
 400 static inline u32 to_mcu_size(struct allegro_dev *dev, size_t size)
 401 {
 402         return lower_32_bits(size);
 403 }
 404
 405 static inline u32 to_codec_addr(struct allegro_dev *dev, dma_addr_t phys)
 406 {
 407         if (upper_32_bits(phys))
 408                 v4l2_warn(&dev->v4l2_dev,
 409                           "address %pad cannot be used by codec\n", &phys);
 410
 411         return lower_32_bits(phys);
 412 }
 413
 414 static inline u64 ptr_to_u64(const void *ptr)
 415 {
 416         return (uintptr_t)ptr;
 417 }
 418
 419 /* Helper functions for channel and user operations */
 420
 421 static unsigned long allegro_next_user_id(struct allegro_dev *dev)
 422 {
 423         if (dev->channel_user_ids == ~0UL)
 424                 return -EBUSY;
 425
 426         return ffz(dev->channel_user_ids);
 427 }
 428
 429 static struct allegro_channel *
 430 allegro_find_channel_by_user_id(struct allegro_dev *dev,
 431                                 unsigned int user_id)
 432 {
 433         struct allegro_channel *channel;
 434
 435         list_for_each_entry(channel, &dev->channels, list) {
 436                 if (channel->user_id == user_id)
 437                         return channel;
 438         }
 439
 440         return ERR_PTR(-EINVAL);
 441 }
 442
 443 static struct allegro_channel *
 444 allegro_find_channel_by_channel_id(struct allegro_dev *dev,
 445                                    unsigned int channel_id)
 446 {
 447         struct allegro_channel *channel;
 448
 449         list_for_each_entry(channel, &dev->channels, list) {
 450                 if (channel->mcu_channel_id == channel_id)
 451                         return channel;
 452         }
 453
 454         return ERR_PTR(-EINVAL);
 455 }
 456
 457 static inline bool channel_exists(struct allegro_channel *channel)
 458 {
 459         return channel->mcu_channel_id != -1;
 460 }
 461
 462 #define AL_ERROR                        0x80
 463 #define AL_ERR_INIT_FAILED              0x81
 464 #define AL_ERR_NO_FRAME_DECODED         0x82
 465 #define AL_ERR_RESOLUTION_CHANGE        0x85
 466 #define AL_ERR_NO_MEMORY                0x87
 467 #define AL_ERR_STREAM_OVERFLOW          0x88
 468 #define AL_ERR_TOO_MANY_SLICES          0x89
 469 #define AL_ERR_BUF_NOT_READY            0x8c
 470 #define AL_ERR_NO_CHANNEL_AVAILABLE     0x8d
 471 #define AL_ERR_RESOURCE_UNAVAILABLE     0x8e
 472 #define AL_ERR_NOT_ENOUGH_CORES         0x8f
 473 #define AL_ERR_REQUEST_MALFORMED        0x90
 474 #define AL_ERR_CMD_NOT_ALLOWED          0x91
 475 #define AL_ERR_INVALID_CMD_VALUE        0x92
 476
 477 static inline const char *allegro_err_to_string(unsigned int err)
 478 {
 479         switch (err) {
 480         case AL_ERR_INIT_FAILED:
 481                 return "initialization failed";
 482         case AL_ERR_NO_FRAME_DECODED:
 483                 return "no frame decoded";
 484         case AL_ERR_RESOLUTION_CHANGE:
 485                 return "resolution change";
 486         case AL_ERR_NO_MEMORY:
 487                 return "out of memory";
 488         case AL_ERR_STREAM_OVERFLOW:
 489                 return "stream buffer overflow";
 490         case AL_ERR_TOO_MANY_SLICES:
 491                 return "too many slices";
 492         case AL_ERR_BUF_NOT_READY:
 493                 return "buffer not ready";
 494         case AL_ERR_NO_CHANNEL_AVAILABLE:
 495                 return "no channel available";
 496         case AL_ERR_RESOURCE_UNAVAILABLE:
 497                 return "resource unavailable";
 498         case AL_ERR_NOT_ENOUGH_CORES:
 499                 return "not enough cores";
 500         case AL_ERR_REQUEST_MALFORMED:
 501                 return "request malformed";
 502         case AL_ERR_CMD_NOT_ALLOWED:
 503                 return "command not allowed";
 504         case AL_ERR_INVALID_CMD_VALUE:
 505                 return "invalid command value";
 506         case AL_ERROR:
 507         default:
 508                 return "unknown error";
 509         }
 510 }
 511
 512 static unsigned int estimate_stream_size(unsigned int width,
 513                                          unsigned int height)
 514 {
 515         unsigned int offset = ENCODER_STREAM_OFFSET;
 516         unsigned int num_blocks = DIV_ROUND_UP(width, SIZE_MACROBLOCK) *
 517                                         DIV_ROUND_UP(height, SIZE_MACROBLOCK);
 518         unsigned int pcm_size = SZ_256;
 519         unsigned int partition_table = SZ_256;
 520
 521         return round_up(offset + num_blocks * pcm_size + partition_table, 32);
 522 }
 523
 524 static enum v4l2_mpeg_video_h264_level
 525 select_minimum_h264_level(unsigned int width, unsigned int height)
 526 {
 527         unsigned int pic_width_in_mb = DIV_ROUND_UP(width, SIZE_MACROBLOCK);
 528         unsigned int frame_height_in_mb = DIV_ROUND_UP(height, SIZE_MACROBLOCK);
 529         unsigned int frame_size_in_mb = pic_width_in_mb * frame_height_in_mb;
 530         enum v4l2_mpeg_video_h264_level level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
 531
 532         /*
 533          * The level limits are specified in Rec. ITU-T H.264 Annex A.3.1 and
 534          * also specify limits regarding bit rate and CBP size. Only approximate
 535          * the levels using the frame size.
 536          *
 537          * Level 5.1 allows up to 4k video resolution.
 538          */
 539         if (frame_size_in_mb <= 99)
 540                 level = V4L2_MPEG_VIDEO_H264_LEVEL_1_0;
 541         else if (frame_size_in_mb <= 396)
 542                 level = V4L2_MPEG_VIDEO_H264_LEVEL_1_1;
 543         else if (frame_size_in_mb <= 792)
 544                 level = V4L2_MPEG_VIDEO_H264_LEVEL_2_1;
 545         else if (frame_size_in_mb <= 1620)
 546                 level = V4L2_MPEG_VIDEO_H264_LEVEL_2_2;
 547         else if (frame_size_in_mb <= 3600)
 548                 level = V4L2_MPEG_VIDEO_H264_LEVEL_3_1;
 549         else if (frame_size_in_mb <= 5120)
 550                 level = V4L2_MPEG_VIDEO_H264_LEVEL_3_2;
 551         else if (frame_size_in_mb <= 8192)
 552                 level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0;
 553         else if (frame_size_in_mb <= 8704)
 554                 level = V4L2_MPEG_VIDEO_H264_LEVEL_4_2;
 555         else if (frame_size_in_mb <= 22080)
 556                 level = V4L2_MPEG_VIDEO_H264_LEVEL_5_0;
 557         else
 558                 level = V4L2_MPEG_VIDEO_H264_LEVEL_5_1;
 559
 560         return level;
 561 }
 562
 563 static unsigned int h264_maximum_bitrate(enum v4l2_mpeg_video_h264_level level)
 564 {
 565         switch (level) {
 566         case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
 567                 return 64000;
 568         case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
 569                 return 128000;
 570         case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
 571                 return 192000;
 572         case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
 573                 return 384000;
 574         case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
 575                 return 768000;
 576         case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
 577                 return 2000000;
 578         case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
 579                 return 4000000;
 580         case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
 581                 return 4000000;
 582         case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
 583                 return 10000000;
 584         case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
 585                 return 14000000;
 586         case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
 587                 return 20000000;
 588         case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
 589                 return 20000000;
 590         case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
 591                 return 50000000;
 592         case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
 593                 return 50000000;
 594         case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
 595                 return 135000000;
 596         case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
 597         default:
 598                 return 240000000;
 599         }
 600 }
 601
 602 static unsigned int h264_maximum_cpb_size(enum v4l2_mpeg_video_h264_level level)
 603 {
 604         switch (level) {
 605         case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
 606                 return 175;
 607         case V4L2_MPEG_VIDEO_H264_LEVEL_1B:
 608                 return 350;
 609         case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
 610                 return 500;
 611         case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
 612                 return 1000;
 613         case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
 614                 return 2000;
 615         case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
 616                 return 2000;
 617         case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
 618                 return 4000;
 619         case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
 620                 return 4000;
 621         case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
 622                 return 10000;
 623         case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
 624                 return 14000;
 625         case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
 626                 return 20000;
 627         case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
 628                 return 25000;
 629         case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
 630                 return 62500;
 631         case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
 632                 return 62500;
 633         case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
 634                 return 135000;
 635         case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
 636         default:
 637                 return 240000;
 638         }
 639 }
 640
 641 static enum v4l2_mpeg_video_hevc_level
 642 select_minimum_hevc_level(unsigned int width, unsigned int height)
 643 {
 644         unsigned int luma_picture_size = width * height;
 645         enum v4l2_mpeg_video_hevc_level level;
 646
 647         if (luma_picture_size <= 36864)
 648                 level = V4L2_MPEG_VIDEO_HEVC_LEVEL_1;
 649         else if (luma_picture_size <= 122880)
 650                 level = V4L2_MPEG_VIDEO_HEVC_LEVEL_2;
 651         else if (luma_picture_size <= 245760)
 652                 level = V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1;
 653         else if (luma_picture_size <= 552960)
 654                 level = V4L2_MPEG_VIDEO_HEVC_LEVEL_3;
 655         else if (luma_picture_size <= 983040)
 656                 level = V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1;
 657         else if (luma_picture_size <= 2228224)
 658                 level = V4L2_MPEG_VIDEO_HEVC_LEVEL_4;
 659         else if (luma_picture_size <= 8912896)
 660                 level = V4L2_MPEG_VIDEO_HEVC_LEVEL_5;
 661         else
 662                 level = V4L2_MPEG_VIDEO_HEVC_LEVEL_6;
 663
 664         return level;
 665 }
 666
 667 static unsigned int hevc_maximum_bitrate(enum v4l2_mpeg_video_hevc_level level)
 668 {
 669         /*
 670          * See Rec. ITU-T H.265 v5 (02/2018), A.4.2 Profile-specific level
 671          * limits for the video profiles.
 672          */
 673         switch (level) {
 674         case V4L2_MPEG_VIDEO_HEVC_LEVEL_1:
 675                 return 128;
 676         case V4L2_MPEG_VIDEO_HEVC_LEVEL_2:
 677                 return 1500;
 678         case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1:
 679                 return 3000;
 680         case V4L2_MPEG_VIDEO_HEVC_LEVEL_3:
 681                 return 6000;
 682         case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1:
 683                 return 10000;
 684         case V4L2_MPEG_VIDEO_HEVC_LEVEL_4:
 685                 return 12000;
 686         case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1:
 687                 return 20000;
 688         case V4L2_MPEG_VIDEO_HEVC_LEVEL_5:
 689                 return 25000;
 690         default:
 691         case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1:
 692                 return 40000;
 693         }
 694 }
 695
 696 static unsigned int hevc_maximum_cpb_size(enum v4l2_mpeg_video_hevc_level level)
 697 {
 698         switch (level) {
 699         case V4L2_MPEG_VIDEO_HEVC_LEVEL_1:
 700                 return 350;
 701         case V4L2_MPEG_VIDEO_HEVC_LEVEL_2:
 702                 return 1500;
 703         case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1:
 704                 return 3000;
 705         case V4L2_MPEG_VIDEO_HEVC_LEVEL_3:
 706                 return 6000;
 707         case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1:
 708                 return 10000;
 709         case V4L2_MPEG_VIDEO_HEVC_LEVEL_4:
 710                 return 12000;
 711         case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1:
 712                 return 20000;
 713         case V4L2_MPEG_VIDEO_HEVC_LEVEL_5:
 714                 return 25000;
 715         default:
 716         case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1:
 717                 return 40000;
 718         }
 719 }
 720
 721 static const struct fw_info *
 722 allegro_get_firmware_info(struct allegro_dev *dev,
 723                           const struct firmware *fw,
 724                           const struct firmware *fw_codec)
 725 {
 726         int i;
 727         unsigned int id = fw->size;
 728         unsigned int id_codec = fw_codec->size;
 729
 730         for (i = 0; i < ARRAY_SIZE(supported_firmware); i++)
 731                 if (supported_firmware[i].id == id &&
 732                     supported_firmware[i].id_codec == id_codec)
 733                         return &supported_firmware[i];
 734
 735         return NULL;
 736 }
 737
 738 /*
 739  * Buffers that are used internally by the MCU.
 740  */
 741
 742 static int allegro_alloc_buffer(struct allegro_dev *dev,
 743                                 struct allegro_buffer *buffer, size_t size)
 744 {
 745         buffer->vaddr = dma_alloc_coherent(&dev->plat_dev->dev, size,
 746                                            &buffer->paddr, GFP_KERNEL);
 747         if (!buffer->vaddr)
 748                 return -ENOMEM;
 749         buffer->size = size;
 750
 751         return 0;
 752 }
 753
 754 static void allegro_free_buffer(struct allegro_dev *dev,
 755                                 struct allegro_buffer *buffer)
 756 {
 757         if (buffer->vaddr) {
 758                 dma_free_coherent(&dev->plat_dev->dev, buffer->size,
 759                                   buffer->vaddr, buffer->paddr);
 760                 buffer->vaddr = NULL;
 761                 buffer->size = 0;
 762         }
 763 }
 764
 765 /*
 766  * Mailbox interface to send messages to the MCU.
 767  */
 768
 769 static void allegro_mcu_interrupt(struct allegro_dev *dev);
 770 static void allegro_handle_message(struct allegro_dev *dev,
 771                                    union mcu_msg_response *msg);
 772
 773 static struct allegro_mbox *allegro_mbox_init(struct allegro_dev *dev,
 774                                               unsigned int base, size_t size)
 775 {
 776         struct allegro_mbox *mbox;
 777
 778         mbox = devm_kmalloc(&dev->plat_dev->dev, sizeof(*mbox), GFP_KERNEL);
 779         if (!mbox)
 780                 return ERR_PTR(-ENOMEM);
 781
 782         mbox->dev = dev;
 783
 784         mbox->head = base;
 785         mbox->tail = base + 0x4;
 786         mbox->data = base + 0x8;
 787         mbox->size = size;
 788         mutex_init(&mbox->lock);
 789
 790         regmap_write(dev->sram, mbox->head, 0);
 791         regmap_write(dev->sram, mbox->tail, 0);
 792
 793         return mbox;
 794 }
 795
 796 static int allegro_mbox_write(struct allegro_mbox *mbox,
 797                               const u32 *src, size_t size)
 798 {
 799         struct regmap *sram = mbox->dev->sram;
 800         unsigned int tail;
 801         size_t size_no_wrap;
 802         int err = 0;
 803         int stride = regmap_get_reg_stride(sram);
 804
 805         if (!src)
 806                 return -EINVAL;
 807
 808         if (size > mbox->size)
 809                 return -EINVAL;
 810
 811         mutex_lock(&mbox->lock);
 812         regmap_read(sram, mbox->tail, &tail);
 813         if (tail > mbox->size) {
 814                 err = -EIO;
 815                 goto out;
 816         }
 817         size_no_wrap = min(size, mbox->size - (size_t)tail);
 818         regmap_bulk_write(sram, mbox->data + tail,
 819                           src, size_no_wrap / stride);
 820         regmap_bulk_write(sram, mbox->data,
 821                           src + (size_no_wrap / sizeof(*src)),
 822                           (size - size_no_wrap) / stride);
 823         regmap_write(sram, mbox->tail, (tail + size) % mbox->size);
 824
 825 out:
 826         mutex_unlock(&mbox->lock);
 827
 828         return err;
 829 }
 830
 831 static ssize_t allegro_mbox_read(struct allegro_mbox *mbox,
 832                                  u32 *dst, size_t nbyte)
 833 {
 834         struct {
 835                 u16 length;
 836                 u16 type;
 837         } __attribute__ ((__packed__)) *header;
 838         struct regmap *sram = mbox->dev->sram;
 839         unsigned int head;
 840         ssize_t size;
 841         size_t body_no_wrap;
 842         int stride = regmap_get_reg_stride(sram);
 843
 844         regmap_read(sram, mbox->head, &head);
 845         if (head > mbox->size)
 846                 return -EIO;
 847
 848         /* Assume that the header does not wrap. */
 849         regmap_bulk_read(sram, mbox->data + head,
 850                          dst, sizeof(*header) / stride);
 851         header = (void *)dst;
 852         size = header->length + sizeof(*header);
 853         if (size > mbox->size || size & 0x3)
 854                 return -EIO;
 855         if (size > nbyte)
 856                 return -EINVAL;
 857
 858         /*
 859          * The message might wrap within the mailbox. If the message does not
 860          * wrap, the first read will read the entire message, otherwise the
 861          * first read will read message until the end of the mailbox and the
 862          * second read will read the remaining bytes from the beginning of the
 863          * mailbox.
 864          *
 865          * Skip the header, as was already read to get the size of the body.
 866          */
 867         body_no_wrap = min((size_t)header->length,
 868                            (size_t)(mbox->size - (head + sizeof(*header))));
 869         regmap_bulk_read(sram, mbox->data + head + sizeof(*header),
 870                          dst + (sizeof(*header) / sizeof(*dst)),
 871                          body_no_wrap / stride);
 872         regmap_bulk_read(sram, mbox->data,
 873                          dst + (sizeof(*header) + body_no_wrap) / sizeof(*dst),
 874                          (header->length - body_no_wrap) / stride);
 875
 876         regmap_write(sram, mbox->head, (head + size) % mbox->size);
 877
 878         return size;
 879 }
 880
 881 /**
 882  * allegro_mbox_send() - Send a message via the mailbox
 883  * @mbox: the mailbox which is used to send the message
 884  * @msg: the message to send
 885  */
 886 static int allegro_mbox_send(struct allegro_mbox *mbox, void *msg)
 887 {
 888         struct allegro_dev *dev = mbox->dev;
 889         ssize_t size;
 890         int err;
 891         u32 *tmp;
 892
 893         tmp = kzalloc(mbox->size, GFP_KERNEL);
 894         if (!tmp) {
 895                 err = -ENOMEM;
 896                 goto out;
 897         }
 898
 899         size = allegro_encode_mail(tmp, msg);
 900
 901         err = allegro_mbox_write(mbox, tmp, size);
 902         kfree(tmp);
 903         if (err)
 904                 goto out;
 905
 906         allegro_mcu_interrupt(dev);
 907
 908 out:
 909         return err;
 910 }
 911
 912 /**
 913  * allegro_mbox_notify() - Notify the mailbox about a new message
 914  * @mbox: The allegro_mbox to notify
 915  */
 916 static void allegro_mbox_notify(struct allegro_mbox *mbox)
 917 {
 918         struct allegro_dev *dev = mbox->dev;
 919         union mcu_msg_response *msg;
 920         ssize_t size;
 921         u32 *tmp;
 922         int err;
 923
 924         msg = kmalloc(sizeof(*msg), GFP_KERNEL);
 925         if (!msg)
 926                 return;
 927
 928         msg->header.version = dev->fw_info->mailbox_version;
 929
 930         tmp = kmalloc(mbox->size, GFP_KERNEL);
 931         if (!tmp)
 932                 goto out;
 933
 934         size = allegro_mbox_read(mbox, tmp, mbox->size);
 935         if (size < 0)
 936                 goto out;
 937
 938         err = allegro_decode_mail(msg, tmp);
 939         if (err)
 940                 goto out;
 941
 942         allegro_handle_message(dev, msg);
 943
 944 out:
 945         kfree(tmp);
 946         kfree(msg);
 947 }
 948
 949 static int allegro_encoder_buffer_init(struct allegro_dev *dev,
 950                                        struct allegro_encoder_buffer *buffer)
 951 {
 952         int err;
 953         struct regmap *settings = dev->settings;
 954         unsigned int supports_10_bit;
 955         unsigned int memory_depth;
 956         unsigned int num_cores;
 957         unsigned int color_depth;
 958         unsigned long clk_rate;
 959
 960         /* We don't support the encoder buffer pre Firmware version 2019.2 */
 961         if (dev->fw_info->mailbox_version < MCU_MSG_VERSION_2019_2)
 962                 return -ENODEV;
 963
 964         if (!settings)
 965                 return -EINVAL;
 966
 967         err = regmap_read(settings, VCU_ENC_COLOR_DEPTH, &supports_10_bit);
 968         if (err < 0)
 969                 return err;
 970         err = regmap_read(settings, VCU_MEMORY_DEPTH, &memory_depth);
 971         if (err < 0)
 972                 return err;
 973         err = regmap_read(settings, VCU_NUM_CORE, &num_cores);
 974         if (err < 0)
 975                 return err;
 976
 977         clk_rate = clk_get_rate(dev->clk_core);
 978         if (clk_rate == 0)
 979                 return -EINVAL;
 980
 981         color_depth = supports_10_bit ? 10 : 8;
 982         /* The firmware expects the encoder buffer size in bits. */
 983         buffer->size = color_depth * 32 * memory_depth;
 984         buffer->color_depth = color_depth;
 985         buffer->num_cores = num_cores;
 986         buffer->clk_rate = clk_rate;
 987
 988         v4l2_dbg(1, debug, &dev->v4l2_dev,
 989                  "using %d bits encoder buffer with %d-bit color depth\n",
 990                  buffer->size, color_depth);
 991
 992         return 0;
 993 }
 994
 995 static void allegro_mcu_send_init(struct allegro_dev *dev,
 996                                   dma_addr_t suballoc_dma, size_t suballoc_size)
 997 {
 998         struct mcu_msg_init_request msg;
 999
1000         memset(&msg, 0, sizeof(msg));
1001
1002         msg.header.type = MCU_MSG_TYPE_INIT;
1003         msg.header.version = dev->fw_info->mailbox_version;
1004
1005         msg.suballoc_dma = to_mcu_addr(dev, suballoc_dma);
1006         msg.suballoc_size = to_mcu_size(dev, suballoc_size);
1007
1008         if (dev->has_encoder_buffer) {
1009                 msg.encoder_buffer_size = dev->encoder_buffer.size;
1010                 msg.encoder_buffer_color_depth = dev->encoder_buffer.color_depth;
1011                 msg.num_cores = dev->encoder_buffer.num_cores;
1012                 msg.clk_rate = dev->encoder_buffer.clk_rate;
1013         } else {
1014                 msg.encoder_buffer_size = -1;
1015                 msg.encoder_buffer_color_depth = -1;
1016                 msg.num_cores = -1;
1017                 msg.clk_rate = -1;
1018         }
1019
1020         allegro_mbox_send(dev->mbox_command, &msg);
1021 }
1022
1023 static u32 v4l2_pixelformat_to_mcu_format(u32 pixelformat)
1024 {
1025         switch (pixelformat) {
1026         case V4L2_PIX_FMT_NV12:
1027                 /* AL_420_8BITS: 0x100 -> NV12, 0x88 -> 8 bit */
1028                 return 0x100 | 0x88;
1029         default:
1030                 return -EINVAL;
1031         }
1032 }
1033
1034 static u32 v4l2_colorspace_to_mcu_colorspace(enum v4l2_colorspace colorspace)
1035 {
1036         switch (colorspace) {
1037         case V4L2_COLORSPACE_REC709:
1038                 return 2;
1039         case V4L2_COLORSPACE_SMPTE170M:
1040                 return 3;
1041         case V4L2_COLORSPACE_SMPTE240M:
1042                 return 4;
1043         case V4L2_COLORSPACE_SRGB:
1044                 return 7;
1045         default:
1046                 /* UNKNOWN */
1047                 return 0;
1048         }
1049 }
1050
1051 static u8 v4l2_profile_to_mcu_profile(enum v4l2_mpeg_video_h264_profile profile)
1052 {
1053         switch (profile) {
1054         case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:
1055         default:
1056                 return 66;
1057         }
1058 }
1059
1060 static u16 v4l2_level_to_mcu_level(enum v4l2_mpeg_video_h264_level level)
1061 {
1062         switch (level) {
1063         case V4L2_MPEG_VIDEO_H264_LEVEL_1_0:
1064                 return 10;
1065         case V4L2_MPEG_VIDEO_H264_LEVEL_1_1:
1066                 return 11;
1067         case V4L2_MPEG_VIDEO_H264_LEVEL_1_2:
1068                 return 12;
1069         case V4L2_MPEG_VIDEO_H264_LEVEL_1_3:
1070                 return 13;
1071         case V4L2_MPEG_VIDEO_H264_LEVEL_2_0:
1072                 return 20;
1073         case V4L2_MPEG_VIDEO_H264_LEVEL_2_1:
1074                 return 21;
1075         case V4L2_MPEG_VIDEO_H264_LEVEL_2_2:
1076                 return 22;
1077         case V4L2_MPEG_VIDEO_H264_LEVEL_3_0:
1078                 return 30;
1079         case V4L2_MPEG_VIDEO_H264_LEVEL_3_1:
1080                 return 31;
1081         case V4L2_MPEG_VIDEO_H264_LEVEL_3_2:
1082                 return 32;
1083         case V4L2_MPEG_VIDEO_H264_LEVEL_4_0:
1084                 return 40;
1085         case V4L2_MPEG_VIDEO_H264_LEVEL_4_1:
1086                 return 41;
1087         case V4L2_MPEG_VIDEO_H264_LEVEL_4_2:
1088                 return 42;
1089         case V4L2_MPEG_VIDEO_H264_LEVEL_5_0:
1090                 return 50;
1091         case V4L2_MPEG_VIDEO_H264_LEVEL_5_1:
1092         default:
1093                 return 51;
1094         }
1095 }
1096
1097 static u8 hevc_profile_to_mcu_profile(enum v4l2_mpeg_video_hevc_profile profile)
1098 {
1099         switch (profile) {
1100         default:
1101         case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN:
1102                 return 1;
1103         case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10:
1104                 return 2;
1105         case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE:
1106                 return 3;
1107         }
1108 }
1109
1110 static u16 hevc_level_to_mcu_level(enum v4l2_mpeg_video_hevc_level level)
1111 {
1112         switch (level) {
1113         case V4L2_MPEG_VIDEO_HEVC_LEVEL_1:
1114                 return 10;
1115         case V4L2_MPEG_VIDEO_HEVC_LEVEL_2:
1116                 return 20;
1117         case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1:
1118                 return 21;
1119         case V4L2_MPEG_VIDEO_HEVC_LEVEL_3:
1120                 return 30;
1121         case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1:
1122                 return 31;
1123         case V4L2_MPEG_VIDEO_HEVC_LEVEL_4:
1124                 return 40;
1125         case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1:
1126                 return 41;
1127         case V4L2_MPEG_VIDEO_HEVC_LEVEL_5:
1128                 return 50;
1129         default:
1130         case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1:
1131                 return 51;
1132         }
1133 }
1134
1135 static u8 hevc_tier_to_mcu_tier(enum v4l2_mpeg_video_hevc_tier tier)
1136 {
1137         switch (tier) {
1138         default:
1139         case V4L2_MPEG_VIDEO_HEVC_TIER_MAIN:
1140                 return 0;
1141         case V4L2_MPEG_VIDEO_HEVC_TIER_HIGH:
1142                 return 1;
1143         }
1144 }
1145
1146 static u32
1147 v4l2_bitrate_mode_to_mcu_mode(enum v4l2_mpeg_video_bitrate_mode mode)
1148 {
1149         switch (mode) {
1150         case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR:
1151                 return 2;
1152         case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR:
1153         default:
1154                 return 1;
1155         }
1156 }
1157
1158 static u32 v4l2_cpb_size_to_mcu(unsigned int cpb_size, unsigned int bitrate)
1159 {
1160         unsigned int cpb_size_kbit;
1161         unsigned int bitrate_kbps;
1162
1163         /*
1164          * The mcu expects the CPB size in units of a 90 kHz clock, but the
1165          * channel follows the V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE and stores
1166          * the CPB size in kilobytes.
1167          */
1168         cpb_size_kbit = cpb_size * BITS_PER_BYTE;
1169         bitrate_kbps = bitrate / 1000;
1170
1171         return (cpb_size_kbit * 90000) / bitrate_kbps;
1172 }
1173
1174 static s16 get_qp_delta(int minuend, int subtrahend)
1175 {
1176         if (minuend == subtrahend)
1177                 return -1;
1178         else
1179                 return minuend - subtrahend;
1180 }
1181
1182 static u32 allegro_channel_get_entropy_mode(struct allegro_channel *channel)
1183 {
1184 #define ALLEGRO_ENTROPY_MODE_CAVLC 0
1185 #define ALLEGRO_ENTROPY_MODE_CABAC 1
1186
1187         /* HEVC always uses CABAC, but this has to be explicitly set */
1188         if (channel->codec == V4L2_PIX_FMT_HEVC)
1189                 return ALLEGRO_ENTROPY_MODE_CABAC;
1190
1191         return ALLEGRO_ENTROPY_MODE_CAVLC;
1192 }
1193
1194 static int fill_create_channel_param(struct allegro_channel *channel,
1195                                      struct create_channel_param *param)
1196 {
1197         int i_frame_qp = allegro_channel_get_i_frame_qp(channel);
1198         int p_frame_qp = allegro_channel_get_p_frame_qp(channel);
1199         int b_frame_qp = allegro_channel_get_b_frame_qp(channel);
1200         int bitrate_mode = v4l2_ctrl_g_ctrl(channel->mpeg_video_bitrate_mode);
1201         unsigned int cpb_size = v4l2_ctrl_g_ctrl(channel->mpeg_video_cpb_size);
1202
1203         param->width = channel->width;
1204         param->height = channel->height;
1205         param->format = v4l2_pixelformat_to_mcu_format(channel->pixelformat);
1206         param->colorspace =
1207                 v4l2_colorspace_to_mcu_colorspace(channel->colorspace);
1208         param->src_mode = 0x0;
1209
1210         param->codec = channel->codec;
1211         if (channel->codec == V4L2_PIX_FMT_H264) {
1212                 enum v4l2_mpeg_video_h264_profile profile;
1213                 enum v4l2_mpeg_video_h264_level level;
1214
1215                 profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_profile);
1216                 level = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_level);
1217
1218                 param->profile = v4l2_profile_to_mcu_profile(profile);
1219                 param->constraint_set_flags = BIT(1);
1220                 param->level = v4l2_level_to_mcu_level(level);
1221         } else {
1222                 enum v4l2_mpeg_video_hevc_profile profile;
1223                 enum v4l2_mpeg_video_hevc_level level;
1224                 enum v4l2_mpeg_video_hevc_tier tier;
1225
1226                 profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_profile);
1227                 level = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level);
1228                 tier = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_tier);
1229
1230                 param->profile = hevc_profile_to_mcu_profile(profile);
1231                 param->level = hevc_level_to_mcu_level(level);
1232                 param->tier = hevc_tier_to_mcu_tier(tier);
1233         }
1234
1235         param->log2_max_poc = LOG2_MAX_PIC_ORDER_CNT;
1236         param->log2_max_frame_num = channel->log2_max_frame_num;
1237         param->temporal_mvp_enable = channel->temporal_mvp_enable;
1238
1239         param->dbf_ovr_en = channel->dbf_ovr_en;
1240         param->override_lf = channel->enable_deblocking_filter_override;
1241         param->enable_reordering = channel->enable_reordering;
1242         param->entropy_mode = allegro_channel_get_entropy_mode(channel);
1243         param->rdo_cost_mode = 1;
1244         param->custom_lda = 1;
1245         param->lf = 1;
1246         param->lf_x_tile = channel->enable_loop_filter_across_tiles;
1247         param->lf_x_slice = channel->enable_loop_filter_across_slices;
1248
1249         param->src_bit_depth = 8;
1250
1251         param->beta_offset = BETA_OFFSET_DIV_2;
1252         param->tc_offset = TC_OFFSET_DIV_2;
1253         param->num_slices = 1;
1254         param->me_range[0] = channel->b_hrz_me_range;
1255         param->me_range[1] = channel->b_vrt_me_range;
1256         param->me_range[2] = channel->p_hrz_me_range;
1257         param->me_range[3] = channel->p_vrt_me_range;
1258         param->max_cu_size = channel->max_cu_size;
1259         param->min_cu_size = channel->min_cu_size;
1260         param->max_tu_size = channel->max_tu_size;
1261         param->min_tu_size = channel->min_tu_size;
1262         param->max_transfo_depth_intra = channel->max_transfo_depth_intra;
1263         param->max_transfo_depth_inter = channel->max_transfo_depth_inter;
1264
1265         param->encoder_buffer_enabled = v4l2_ctrl_g_ctrl(channel->encoder_buffer);
1266         param->encoder_buffer_offset = 0;
1267
1268         param->rate_control_mode = channel->frame_rc_enable ?
1269                 v4l2_bitrate_mode_to_mcu_mode(bitrate_mode) : 0;
1270
1271         param->cpb_size = v4l2_cpb_size_to_mcu(cpb_size, channel->bitrate_peak);
1272         /* Shall be ]0;cpb_size in 90 kHz units]. Use maximum value. */
1273         param->initial_rem_delay = param->cpb_size;
1274         param->framerate = DIV_ROUND_UP(channel->framerate.numerator,
1275                                         channel->framerate.denominator);
1276         param->clk_ratio = channel->framerate.denominator == 1001 ? 1001 : 1000;
1277         param->target_bitrate = channel->bitrate;
1278         param->max_bitrate = channel->bitrate_peak;
1279         param->initial_qp = i_frame_qp;
1280         param->min_qp = allegro_channel_get_min_qp(channel);
1281         param->max_qp = allegro_channel_get_max_qp(channel);
1282         param->ip_delta = get_qp_delta(i_frame_qp, p_frame_qp);
1283         param->pb_delta = get_qp_delta(p_frame_qp, b_frame_qp);
1284         param->golden_ref = 0;
1285         param->golden_delta = 2;
1286         param->golden_ref_frequency = 10;
1287         param->rate_control_option = 0x00000000;
1288
1289         param->num_pixel = channel->width + channel->height;
1290         param->max_psnr = 4200;
1291         param->max_pixel_value = 255;
1292
1293         param->gop_ctrl_mode = 0x00000002;
1294         param->freq_idr = v4l2_ctrl_g_ctrl(channel->mpeg_video_gop_size);
1295         param->freq_lt = 0;
1296         param->gdr_mode = 0x00000000;
1297         param->gop_length = v4l2_ctrl_g_ctrl(channel->mpeg_video_gop_size);
1298         param->subframe_latency = 0x00000000;
1299
1300         param->lda_factors[0] = 51;
1301         param->lda_factors[1] = 90;
1302         param->lda_factors[2] = 151;
1303         param->lda_factors[3] = 151;
1304         param->lda_factors[4] = 151;
1305         param->lda_factors[5] = 151;
1306
1307         param->max_num_merge_cand = 5;
1308
1309         return 0;
1310 }
1311
1312 static int allegro_mcu_send_create_channel(struct allegro_dev *dev,
1313                                            struct allegro_channel *channel)
1314 {
1315         struct mcu_msg_create_channel msg;
1316         struct allegro_buffer *blob = &channel->config_blob;
1317         struct create_channel_param param;
1318         size_t size;
1319
1320         memset(&param, 0, sizeof(param));
1321         fill_create_channel_param(channel, &param);
1322         allegro_alloc_buffer(dev, blob, sizeof(struct create_channel_param));
1323         param.version = dev->fw_info->mailbox_version;
1324         size = allegro_encode_config_blob(blob->vaddr, &param);
1325
1326         memset(&msg, 0, sizeof(msg));
1327
1328         msg.header.type = MCU_MSG_TYPE_CREATE_CHANNEL;
1329         msg.header.version = dev->fw_info->mailbox_version;
1330
1331         msg.user_id = channel->user_id;
1332
1333         msg.blob = blob->vaddr;
1334         msg.blob_size = size;
1335         msg.blob_mcu_addr = to_mcu_addr(dev, blob->paddr);
1336
1337         allegro_mbox_send(dev->mbox_command, &msg);
1338
1339         return 0;
1340 }
1341
1342 static int allegro_mcu_send_destroy_channel(struct allegro_dev *dev,
1343                                             struct allegro_channel *channel)
1344 {
1345         struct mcu_msg_destroy_channel msg;
1346
1347         memset(&msg, 0, sizeof(msg));
1348
1349         msg.header.type = MCU_MSG_TYPE_DESTROY_CHANNEL;
1350         msg.header.version = dev->fw_info->mailbox_version;
1351
1352         msg.channel_id = channel->mcu_channel_id;
1353
1354         allegro_mbox_send(dev->mbox_command, &msg);
1355
1356         return 0;
1357 }
1358
1359 static int allegro_mcu_send_put_stream_buffer(struct allegro_dev *dev,
1360                                               struct allegro_channel *channel,
1361                                               dma_addr_t paddr,
1362                                               unsigned long size,
1363                                               u64 dst_handle)
1364 {
1365         struct mcu_msg_put_stream_buffer msg;
1366
1367         memset(&msg, 0, sizeof(msg));
1368
1369         msg.header.type = MCU_MSG_TYPE_PUT_STREAM_BUFFER;
1370         msg.header.version = dev->fw_info->mailbox_version;
1371
1372         msg.channel_id = channel->mcu_channel_id;
1373         msg.dma_addr = to_codec_addr(dev, paddr);
1374         msg.mcu_addr = to_mcu_addr(dev, paddr);
1375         msg.size = size;
1376         msg.offset = ENCODER_STREAM_OFFSET;
1377         /* copied to mcu_msg_encode_frame_response */
1378         msg.dst_handle = dst_handle;
1379
1380         allegro_mbox_send(dev->mbox_command, &msg);
1381
1382         return 0;
1383 }
1384
1385 static int allegro_mcu_send_encode_frame(struct allegro_dev *dev,
1386                                          struct allegro_channel *channel,
1387                                          dma_addr_t src_y, dma_addr_t src_uv,
1388                                          u64 src_handle)
1389 {
1390         struct mcu_msg_encode_frame msg;
1391         bool use_encoder_buffer = v4l2_ctrl_g_ctrl(channel->encoder_buffer);
1392
1393         memset(&msg, 0, sizeof(msg));
1394
1395         msg.header.type = MCU_MSG_TYPE_ENCODE_FRAME;
1396         msg.header.version = dev->fw_info->mailbox_version;
1397
1398         msg.channel_id = channel->mcu_channel_id;
1399         msg.encoding_options = AL_OPT_FORCE_LOAD;
1400         if (use_encoder_buffer)
1401                 msg.encoding_options |= AL_OPT_USE_L2;
1402         msg.pps_qp = 26; /* qp are relative to 26 */
1403         msg.user_param = 0; /* copied to mcu_msg_encode_frame_response */
1404         /* src_handle is copied to mcu_msg_encode_frame_response */
1405         msg.src_handle = src_handle;
1406         msg.src_y = to_codec_addr(dev, src_y);
1407         msg.src_uv = to_codec_addr(dev, src_uv);
1408         msg.stride = channel->stride;
1409
1410         allegro_mbox_send(dev->mbox_command, &msg);
1411
1412         return 0;
1413 }
1414
1415 static int allegro_mcu_wait_for_init_timeout(struct allegro_dev *dev,
1416                                              unsigned long timeout_ms)
1417 {
1418         unsigned long tmo;
1419
1420         tmo = wait_for_completion_timeout(&dev->init_complete,
1421                                           msecs_to_jiffies(timeout_ms));
1422         if (tmo == 0)
1423                 return -ETIMEDOUT;
1424
1425         reinit_completion(&dev->init_complete);
1426         return 0;
1427 }
1428
1429 static int allegro_mcu_push_buffer_internal(struct allegro_channel *channel,
1430                                             enum mcu_msg_type type)
1431 {
1432         struct allegro_dev *dev = channel->dev;
1433         struct mcu_msg_push_buffers_internal *msg;
1434         struct mcu_msg_push_buffers_internal_buffer *buffer;
1435         unsigned int num_buffers = 0;
1436         size_t size;
1437         struct allegro_buffer *al_buffer;
1438         struct list_head *list;
1439         int err;
1440
1441         switch (type) {
1442         case MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE:
1443                 list = &channel->buffers_reference;
1444                 break;
1445         case MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE:
1446                 list = &channel->buffers_intermediate;
1447                 break;
1448         default:
1449                 return -EINVAL;
1450         }
1451
1452         list_for_each_entry(al_buffer, list, head)
1453                 num_buffers++;
1454         size = struct_size(msg, buffer, num_buffers);
1455
1456         msg = kmalloc(size, GFP_KERNEL);
1457         if (!msg)
1458                 return -ENOMEM;
1459
1460         msg->header.type = type;
1461         msg->header.version = dev->fw_info->mailbox_version;
1462
1463         msg->channel_id = channel->mcu_channel_id;
1464         msg->num_buffers = num_buffers;
1465
1466         buffer = msg->buffer;
1467         list_for_each_entry(al_buffer, list, head) {
1468                 buffer->dma_addr = to_codec_addr(dev, al_buffer->paddr);
1469                 buffer->mcu_addr = to_mcu_addr(dev, al_buffer->paddr);
1470                 buffer->size = to_mcu_size(dev, al_buffer->size);
1471                 buffer++;
1472         }
1473
1474         err = allegro_mbox_send(dev->mbox_command, msg);
1475
1476         kfree(msg);
1477         return err;
1478 }
1479
1480 static int allegro_mcu_push_buffer_intermediate(struct allegro_channel *channel)
1481 {
1482         enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE;
1483
1484         return allegro_mcu_push_buffer_internal(channel, type);
1485 }
1486
1487 static int allegro_mcu_push_buffer_reference(struct allegro_channel *channel)
1488 {
1489         enum mcu_msg_type type = MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE;
1490
1491         return allegro_mcu_push_buffer_internal(channel, type);
1492 }
1493
1494 static int allocate_buffers_internal(struct allegro_channel *channel,
1495                                      struct list_head *list,
1496                                      size_t n, size_t size)
1497 {
1498         struct allegro_dev *dev = channel->dev;
1499         unsigned int i;
1500         int err;
1501         struct allegro_buffer *buffer, *tmp;
1502
1503         for (i = 0; i < n; i++) {
1504                 buffer = kmalloc(sizeof(*buffer), GFP_KERNEL);
1505                 if (!buffer) {
1506                         err = -ENOMEM;
1507                         goto err;
1508                 }
1509                 INIT_LIST_HEAD(&buffer->head);
1510
1511                 err = allegro_alloc_buffer(dev, buffer, size);
1512                 if (err)
1513                         goto err;
1514                 list_add(&buffer->head, list);
1515         }
1516
1517         return 0;
1518
1519 err:
1520         list_for_each_entry_safe(buffer, tmp, list, head) {
1521                 list_del(&buffer->head);
1522                 allegro_free_buffer(dev, buffer);
1523                 kfree(buffer);
1524         }
1525         return err;
1526 }
1527
1528 static void destroy_buffers_internal(struct allegro_channel *channel,
1529                                      struct list_head *list)
1530 {
1531         struct allegro_dev *dev = channel->dev;
1532         struct allegro_buffer *buffer, *tmp;
1533
1534         list_for_each_entry_safe(buffer, tmp, list, head) {
1535                 list_del(&buffer->head);
1536                 allegro_free_buffer(dev, buffer);
1537                 kfree(buffer);
1538         }
1539 }
1540
1541 static void destroy_reference_buffers(struct allegro_channel *channel)
1542 {
1543         return destroy_buffers_internal(channel, &channel->buffers_reference);
1544 }
1545
1546 static void destroy_intermediate_buffers(struct allegro_channel *channel)
1547 {
1548         return destroy_buffers_internal(channel,
1549                                         &channel->buffers_intermediate);
1550 }
1551
1552 static int allocate_intermediate_buffers(struct allegro_channel *channel,
1553                                          size_t n, size_t size)
1554 {
1555         return allocate_buffers_internal(channel,
1556                                          &channel->buffers_intermediate,
1557                                          n, size);
1558 }
1559
1560 static int allocate_reference_buffers(struct allegro_channel *channel,
1561                                       size_t n, size_t size)
1562 {
1563         return allocate_buffers_internal(channel,
1564                                          &channel->buffers_reference,
1565                                          n, PAGE_ALIGN(size));
1566 }
1567
1568 static ssize_t allegro_h264_write_sps(struct allegro_channel *channel,
1569                                       void *dest, size_t n)
1570 {
1571         struct allegro_dev *dev = channel->dev;
1572         struct nal_h264_sps *sps;
1573         ssize_t size;
1574         unsigned int size_mb = SIZE_MACROBLOCK;
1575         /* Calculation of crop units in Rec. ITU-T H.264 (04/2017) p. 76 */
1576         unsigned int crop_unit_x = 2;
1577         unsigned int crop_unit_y = 2;
1578         enum v4l2_mpeg_video_h264_profile profile;
1579         enum v4l2_mpeg_video_h264_level level;
1580         unsigned int cpb_size;
1581         unsigned int cpb_size_scale;
1582
1583         sps = kzalloc(sizeof(*sps), GFP_KERNEL);
1584         if (!sps)
1585                 return -ENOMEM;
1586
1587         profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_profile);
1588         level = v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_level);
1589
1590         sps->profile_idc = nal_h264_profile(profile);
1591         sps->constraint_set0_flag = 0;
1592         sps->constraint_set1_flag = 1;
1593         sps->constraint_set2_flag = 0;
1594         sps->constraint_set3_flag = 0;
1595         sps->constraint_set4_flag = 0;
1596         sps->constraint_set5_flag = 0;
1597         sps->level_idc = nal_h264_level(level);
1598         sps->seq_parameter_set_id = 0;
1599         sps->log2_max_frame_num_minus4 = LOG2_MAX_FRAME_NUM - 4;
1600         sps->pic_order_cnt_type = 0;
1601         sps->log2_max_pic_order_cnt_lsb_minus4 = LOG2_MAX_PIC_ORDER_CNT - 4;
1602         sps->max_num_ref_frames = 3;
1603         sps->gaps_in_frame_num_value_allowed_flag = 0;
1604         sps->pic_width_in_mbs_minus1 =
1605                 DIV_ROUND_UP(channel->width, size_mb) - 1;
1606         sps->pic_height_in_map_units_minus1 =
1607                 DIV_ROUND_UP(channel->height, size_mb) - 1;
1608         sps->frame_mbs_only_flag = 1;
1609         sps->mb_adaptive_frame_field_flag = 0;
1610         sps->direct_8x8_inference_flag = 1;
1611         sps->frame_cropping_flag =
1612                 (channel->width % size_mb) || (channel->height % size_mb);
1613         if (sps->frame_cropping_flag) {
1614                 sps->crop_left = 0;
1615                 sps->crop_right = (round_up(channel->width, size_mb) - channel->width) / crop_unit_x;
1616                 sps->crop_top = 0;
1617                 sps->crop_bottom = (round_up(channel->height, size_mb) - channel->height) / crop_unit_y;
1618         }
1619         sps->vui_parameters_present_flag = 1;
1620         sps->vui.aspect_ratio_info_present_flag = 0;
1621         sps->vui.overscan_info_present_flag = 0;
1622
1623         sps->vui.video_signal_type_present_flag = 1;
1624         sps->vui.video_format = 5; /* unspecified */
1625         sps->vui.video_full_range_flag = nal_h264_full_range(channel->quantization);
1626         sps->vui.colour_description_present_flag = 1;
1627         sps->vui.colour_primaries = nal_h264_color_primaries(channel->colorspace);
1628         sps->vui.transfer_characteristics =
1629                 nal_h264_transfer_characteristics(channel->colorspace, channel->xfer_func);
1630         sps->vui.matrix_coefficients =
1631                 nal_h264_matrix_coeffs(channel->colorspace, channel->ycbcr_enc);
1632
1633         sps->vui.chroma_loc_info_present_flag = 1;
1634         sps->vui.chroma_sample_loc_type_top_field = 0;
1635         sps->vui.chroma_sample_loc_type_bottom_field = 0;
1636
1637         sps->vui.timing_info_present_flag = 1;
1638         sps->vui.num_units_in_tick = channel->framerate.denominator;
1639         sps->vui.time_scale = 2 * channel->framerate.numerator;
1640
1641         sps->vui.fixed_frame_rate_flag = 1;
1642         sps->vui.nal_hrd_parameters_present_flag = 0;
1643         sps->vui.vcl_hrd_parameters_present_flag = 1;
1644         sps->vui.vcl_hrd_parameters.cpb_cnt_minus1 = 0;
1645         /* See Rec. ITU-T H.264 (04/2017) p. 410 E-53 */
1646         sps->vui.vcl_hrd_parameters.bit_rate_scale =
1647                 ffs(channel->bitrate_peak) - 6;
1648         sps->vui.vcl_hrd_parameters.bit_rate_value_minus1[0] =
1649                 channel->bitrate_peak / (1 << (6 + sps->vui.vcl_hrd_parameters.bit_rate_scale)) - 1;
1650         /* See Rec. ITU-T H.264 (04/2017) p. 410 E-54 */
1651         cpb_size = v4l2_ctrl_g_ctrl(channel->mpeg_video_cpb_size);
1652         cpb_size_scale = ffs(cpb_size) - 4;
1653         sps->vui.vcl_hrd_parameters.cpb_size_scale = cpb_size_scale;
1654         sps->vui.vcl_hrd_parameters.cpb_size_value_minus1[0] =
1655                 (cpb_size * 1000) / (1 << (4 + cpb_size_scale)) - 1;
1656         sps->vui.vcl_hrd_parameters.cbr_flag[0] =
1657                 !v4l2_ctrl_g_ctrl(channel->mpeg_video_frame_rc_enable);
1658         sps->vui.vcl_hrd_parameters.initial_cpb_removal_delay_length_minus1 = 31;
1659         sps->vui.vcl_hrd_parameters.cpb_removal_delay_length_minus1 = 31;
1660         sps->vui.vcl_hrd_parameters.dpb_output_delay_length_minus1 = 31;
1661         sps->vui.vcl_hrd_parameters.time_offset_length = 0;
1662         sps->vui.low_delay_hrd_flag = 0;
1663         sps->vui.pic_struct_present_flag = 1;
1664         sps->vui.bitstream_restriction_flag = 0;
1665
1666         size = nal_h264_write_sps(&dev->plat_dev->dev, dest, n, sps);
1667
1668         kfree(sps);
1669
1670         return size;
1671 }
1672
1673 static ssize_t allegro_h264_write_pps(struct allegro_channel *channel,
1674                                       void *dest, size_t n)
1675 {
1676         struct allegro_dev *dev = channel->dev;
1677         struct nal_h264_pps *pps;
1678         ssize_t size;
1679
1680         pps = kzalloc(sizeof(*pps), GFP_KERNEL);
1681         if (!pps)
1682                 return -ENOMEM;
1683
1684         pps->pic_parameter_set_id = 0;
1685         pps->seq_parameter_set_id = 0;
1686         pps->entropy_coding_mode_flag = 0;
1687         pps->bottom_field_pic_order_in_frame_present_flag = 0;
1688         pps->num_slice_groups_minus1 = 0;
1689         pps->num_ref_idx_l0_default_active_minus1 = channel->num_ref_idx_l0 - 1;
1690         pps->num_ref_idx_l1_default_active_minus1 = channel->num_ref_idx_l1 - 1;
1691         pps->weighted_pred_flag = 0;
1692         pps->weighted_bipred_idc = 0;
1693         pps->pic_init_qp_minus26 = 0;
1694         pps->pic_init_qs_minus26 = 0;
1695         pps->chroma_qp_index_offset = 0;
1696         pps->deblocking_filter_control_present_flag = 1;
1697         pps->constrained_intra_pred_flag = 0;
1698         pps->redundant_pic_cnt_present_flag = 0;
1699         pps->transform_8x8_mode_flag = 0;
1700         pps->pic_scaling_matrix_present_flag = 0;
1701         pps->second_chroma_qp_index_offset = 0;
1702
1703         size = nal_h264_write_pps(&dev->plat_dev->dev, dest, n, pps);
1704
1705         kfree(pps);
1706
1707         return size;
1708 }
1709
1710 static void allegro_channel_eos_event(struct allegro_channel *channel)
1711 {
1712         const struct v4l2_event eos_event = {
1713                 .type = V4L2_EVENT_EOS
1714         };
1715
1716         v4l2_event_queue_fh(&channel->fh, &eos_event);
1717 }
1718
1719 static ssize_t allegro_hevc_write_vps(struct allegro_channel *channel,
1720                                       void *dest, size_t n)
1721 {
1722         struct allegro_dev *dev = channel->dev;
1723         struct nal_hevc_vps *vps;
1724         struct nal_hevc_profile_tier_level *ptl;
1725         ssize_t size;
1726         unsigned int num_ref_frames = channel->num_ref_idx_l0;
1727         s32 profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_profile);
1728         s32 level = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level);
1729         s32 tier = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_tier);
1730
1731         vps = kzalloc(sizeof(*vps), GFP_KERNEL);
1732         if (!vps)
1733                 return -ENOMEM;
1734
1735         vps->base_layer_internal_flag = 1;
1736         vps->base_layer_available_flag = 1;
1737         vps->temporal_id_nesting_flag = 1;
1738
1739         ptl = &vps->profile_tier_level;
1740         ptl->general_profile_idc = nal_hevc_profile(profile);
1741         ptl->general_profile_compatibility_flag[ptl->general_profile_idc] = 1;
1742         ptl->general_tier_flag = nal_hevc_tier(tier);
1743         ptl->general_progressive_source_flag = 1;
1744         ptl->general_frame_only_constraint_flag = 1;
1745         ptl->general_level_idc = nal_hevc_level(level);
1746
1747         vps->sub_layer_ordering_info_present_flag = 0;
1748         vps->max_dec_pic_buffering_minus1[0] = num_ref_frames;
1749         vps->max_num_reorder_pics[0] = num_ref_frames;
1750
1751         size = nal_hevc_write_vps(&dev->plat_dev->dev, dest, n, vps);
1752
1753         kfree(vps);
1754
1755         return size;
1756 }
1757
1758 static ssize_t allegro_hevc_write_sps(struct allegro_channel *channel,
1759                                       void *dest, size_t n)
1760 {
1761         struct allegro_dev *dev = channel->dev;
1762         struct nal_hevc_sps *sps;
1763         struct nal_hevc_profile_tier_level *ptl;
1764         struct nal_hevc_vui_parameters *vui;
1765         struct nal_hevc_hrd_parameters *hrd;
1766         ssize_t size;
1767         unsigned int cpb_size;
1768         unsigned int num_ref_frames = channel->num_ref_idx_l0;
1769         s32 profile = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_profile);
1770         s32 level = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level);
1771         s32 tier = v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_tier);
1772
1773         sps = kzalloc(sizeof(*sps), GFP_KERNEL);
1774         if (!sps)
1775                 return -ENOMEM;
1776
1777         sps->temporal_id_nesting_flag = 1;
1778
1779         ptl = &sps->profile_tier_level;
1780         ptl->general_profile_idc = nal_hevc_profile(profile);
1781         ptl->general_profile_compatibility_flag[ptl->general_profile_idc] = 1;
1782         ptl->general_tier_flag = nal_hevc_tier(tier);
1783         ptl->general_progressive_source_flag = 1;
1784         ptl->general_frame_only_constraint_flag = 1;
1785         ptl->general_level_idc = nal_hevc_level(level);
1786
1787         sps->seq_parameter_set_id = 0;
1788         sps->chroma_format_idc = 1; /* Only 4:2:0 sampling supported */
1789         sps->pic_width_in_luma_samples = round_up(channel->width, 8);
1790         sps->pic_height_in_luma_samples = round_up(channel->height, 8);
1791         sps->conf_win_right_offset =
1792                 sps->pic_width_in_luma_samples - channel->width;
1793         sps->conf_win_bottom_offset =
1794                 sps->pic_height_in_luma_samples - channel->height;
1795         sps->conformance_window_flag =
1796                 sps->conf_win_right_offset || sps->conf_win_bottom_offset;
1797
1798         sps->log2_max_pic_order_cnt_lsb_minus4 = LOG2_MAX_PIC_ORDER_CNT - 4;
1799
1800         sps->sub_layer_ordering_info_present_flag = 1;
1801         sps->max_dec_pic_buffering_minus1[0] = num_ref_frames;
1802         sps->max_num_reorder_pics[0] = num_ref_frames;
1803
1804         sps->log2_min_luma_coding_block_size_minus3 =
1805                 channel->min_cu_size - 3;
1806         sps->log2_diff_max_min_luma_coding_block_size =
1807                 channel->max_cu_size - channel->min_cu_size;
1808         sps->log2_min_luma_transform_block_size_minus2 =
1809                 channel->min_tu_size - 2;
1810         sps->log2_diff_max_min_luma_transform_block_size =
1811                 channel->max_tu_size - channel->min_tu_size;
1812         sps->max_transform_hierarchy_depth_intra =
1813                 channel->max_transfo_depth_intra;
1814         sps->max_transform_hierarchy_depth_inter =
1815                 channel->max_transfo_depth_inter;
1816
1817         sps->sps_temporal_mvp_enabled_flag = channel->temporal_mvp_enable;
1818         sps->strong_intra_smoothing_enabled_flag = channel->max_cu_size > 4;
1819
1820         sps->vui_parameters_present_flag = 1;
1821         vui = &sps->vui;
1822
1823         vui->video_signal_type_present_flag = 1;
1824         vui->video_format = 5; /* unspecified */
1825         vui->video_full_range_flag = nal_hevc_full_range(channel->quantization);
1826         vui->colour_description_present_flag = 1;
1827         vui->colour_primaries = nal_hevc_color_primaries(channel->colorspace);
1828         vui->transfer_characteristics = nal_hevc_transfer_characteristics(channel->colorspace,
1829                                                                           channel->xfer_func);
1830         vui->matrix_coeffs = nal_hevc_matrix_coeffs(channel->colorspace, channel->ycbcr_enc);
1831
1832         vui->chroma_loc_info_present_flag = 1;
1833         vui->chroma_sample_loc_type_top_field = 0;
1834         vui->chroma_sample_loc_type_bottom_field = 0;
1835
1836         vui->vui_timing_info_present_flag = 1;
1837         vui->vui_num_units_in_tick = channel->framerate.denominator;
1838         vui->vui_time_scale = channel->framerate.numerator;
1839
1840         vui->bitstream_restriction_flag = 1;
1841         vui->motion_vectors_over_pic_boundaries_flag = 1;
1842         vui->restricted_ref_pic_lists_flag = 1;
1843         vui->log2_max_mv_length_horizontal = 15;
1844         vui->log2_max_mv_length_vertical = 15;
1845
1846         vui->vui_hrd_parameters_present_flag = 1;
1847         hrd = &vui->nal_hrd_parameters;
1848         hrd->vcl_hrd_parameters_present_flag = 1;
1849
1850         hrd->initial_cpb_removal_delay_length_minus1 = 31;
1851         hrd->au_cpb_removal_delay_length_minus1 = 30;
1852         hrd->dpb_output_delay_length_minus1 = 30;
1853
1854         hrd->bit_rate_scale = ffs(channel->bitrate_peak) - 6;
1855         hrd->vcl_hrd[0].bit_rate_value_minus1[0] =
1856                 (channel->bitrate_peak >> (6 + hrd->bit_rate_scale)) - 1;
1857
1858         cpb_size = v4l2_ctrl_g_ctrl(channel->mpeg_video_cpb_size) * 1000;
1859         hrd->cpb_size_scale = ffs(cpb_size) - 4;
1860         hrd->vcl_hrd[0].cpb_size_value_minus1[0] = (cpb_size >> (4 + hrd->cpb_size_scale)) - 1;
1861
1862         hrd->vcl_hrd[0].cbr_flag[0] = !v4l2_ctrl_g_ctrl(channel->mpeg_video_frame_rc_enable);
1863
1864         size = nal_hevc_write_sps(&dev->plat_dev->dev, dest, n, sps);
1865
1866         kfree(sps);
1867
1868         return size;
1869 }
1870
1871 static ssize_t allegro_hevc_write_pps(struct allegro_channel *channel,
1872                                       struct mcu_msg_encode_frame_response *msg,
1873                                       void *dest, size_t n)
1874 {
1875         struct allegro_dev *dev = channel->dev;
1876         struct nal_hevc_pps *pps;
1877         ssize_t size;
1878         int i;
1879
1880         pps = kzalloc(sizeof(*pps), GFP_KERNEL);
1881         if (!pps)
1882                 return -ENOMEM;
1883
1884         pps->pps_pic_parameter_set_id = 0;
1885         pps->pps_seq_parameter_set_id = 0;
1886
1887         if (msg->num_column > 1 || msg->num_row > 1) {
1888                 pps->tiles_enabled_flag = 1;
1889                 pps->num_tile_columns_minus1 = msg->num_column - 1;
1890                 pps->num_tile_rows_minus1 = msg->num_row - 1;
1891
1892                 for (i = 0; i < msg->num_column; i++)
1893                         pps->column_width_minus1[i] = msg->tile_width[i] - 1;
1894
1895                 for (i = 0; i < msg->num_row; i++)
1896                         pps->row_height_minus1[i] = msg->tile_height[i] - 1;
1897         }
1898
1899         pps->loop_filter_across_tiles_enabled_flag =
1900                 channel->enable_loop_filter_across_tiles;
1901         pps->pps_loop_filter_across_slices_enabled_flag =
1902                 channel->enable_loop_filter_across_slices;
1903         pps->deblocking_filter_control_present_flag = 1;
1904         pps->deblocking_filter_override_enabled_flag =
1905                 channel->enable_deblocking_filter_override;
1906         pps->pps_beta_offset_div2 = BETA_OFFSET_DIV_2;
1907         pps->pps_tc_offset_div2 = TC_OFFSET_DIV_2;
1908
1909         pps->lists_modification_present_flag = channel->enable_reordering;
1910
1911         size = nal_hevc_write_pps(&dev->plat_dev->dev, dest, n, pps);
1912
1913         kfree(pps);
1914
1915         return size;
1916 }
1917
1918 static u64 allegro_put_buffer(struct allegro_channel *channel,
1919                               struct list_head *list,
1920                               struct vb2_v4l2_buffer *buffer)
1921 {
1922         struct v4l2_m2m_buffer *b = container_of(buffer,
1923                                                  struct v4l2_m2m_buffer, vb);
1924         struct allegro_m2m_buffer *shadow = to_allegro_m2m_buffer(b);
1925
1926         mutex_lock(&channel->shadow_list_lock);
1927         list_add_tail(&shadow->head, list);
1928         mutex_unlock(&channel->shadow_list_lock);
1929
1930         return ptr_to_u64(buffer);
1931 }
1932
1933 static struct vb2_v4l2_buffer *
1934 allegro_get_buffer(struct allegro_channel *channel,
1935                    struct list_head *list, u64 handle)
1936 {
1937         struct allegro_m2m_buffer *shadow, *tmp;
1938         struct vb2_v4l2_buffer *buffer = NULL;
1939
1940         mutex_lock(&channel->shadow_list_lock);
1941         list_for_each_entry_safe(shadow, tmp, list, head) {
1942                 if (handle == ptr_to_u64(&shadow->buf.vb)) {
1943                         buffer = &shadow->buf.vb;
1944                         list_del_init(&shadow->head);
1945                         break;
1946                 }
1947         }
1948         mutex_unlock(&channel->shadow_list_lock);
1949
1950         return buffer;
1951 }
1952
1953 static void allegro_channel_finish_frame(struct allegro_channel *channel,
1954                 struct mcu_msg_encode_frame_response *msg)
1955 {
1956         struct allegro_dev *dev = channel->dev;
1957         struct vb2_v4l2_buffer *src_buf;
1958         struct vb2_v4l2_buffer *dst_buf;
1959         struct {
1960                 u32 offset;
1961                 u32 size;
1962         } *partition;
1963         enum vb2_buffer_state state = VB2_BUF_STATE_ERROR;
1964         char *curr;
1965         ssize_t len;
1966         ssize_t free;
1967
1968         src_buf = allegro_get_buffer(channel, &channel->source_shadow_list,
1969                                      msg->src_handle);
1970         if (!src_buf)
1971                 v4l2_warn(&dev->v4l2_dev,
1972                           "channel %d: invalid source buffer\n",
1973                           channel->mcu_channel_id);
1974
1975         dst_buf = allegro_get_buffer(channel, &channel->stream_shadow_list,
1976                                      msg->dst_handle);
1977         if (!dst_buf)
1978                 v4l2_warn(&dev->v4l2_dev,
1979                           "channel %d: invalid stream buffer\n",
1980                           channel->mcu_channel_id);
1981
1982         if (!src_buf || !dst_buf)
1983                 goto err;
1984
1985         if (v4l2_m2m_is_last_draining_src_buf(channel->fh.m2m_ctx, src_buf)) {
1986                 dst_buf->flags |= V4L2_BUF_FLAG_LAST;
1987                 allegro_channel_eos_event(channel);
1988                 v4l2_m2m_mark_stopped(channel->fh.m2m_ctx);
1989         }
1990
1991         dst_buf->sequence = channel->csequence++;
1992
1993         if (msg->error_code & AL_ERROR) {
1994                 v4l2_err(&dev->v4l2_dev,
1995                          "channel %d: failed to encode frame: %s (%x)\n",
1996                          channel->mcu_channel_id,
1997                          allegro_err_to_string(msg->error_code),
1998                          msg->error_code);
1999                 goto err;
2000         }
2001
2002         if (msg->partition_table_size != 1) {
2003                 v4l2_warn(&dev->v4l2_dev,
2004                           "channel %d: only handling first partition table entry (%d entries)\n",
2005                           channel->mcu_channel_id, msg->partition_table_size);
2006         }
2007
2008         if (msg->partition_table_offset +
2009             msg->partition_table_size * sizeof(*partition) >
2010             vb2_plane_size(&dst_buf->vb2_buf, 0)) {
2011                 v4l2_err(&dev->v4l2_dev,
2012                          "channel %d: partition table outside of dst_buf\n",
2013                          channel->mcu_channel_id);
2014                 goto err;
2015         }
2016
2017         partition =
2018             vb2_plane_vaddr(&dst_buf->vb2_buf, 0) + msg->partition_table_offset;
2019         if (partition->offset + partition->size >
2020             vb2_plane_size(&dst_buf->vb2_buf, 0)) {
2021                 v4l2_err(&dev->v4l2_dev,
2022                          "channel %d: encoded frame is outside of dst_buf (offset 0x%x, size 0x%x)\n",
2023                          channel->mcu_channel_id, partition->offset,
2024                          partition->size);
2025                 goto err;
2026         }
2027
2028         v4l2_dbg(2, debug, &dev->v4l2_dev,
2029                  "channel %d: encoded frame of size %d is at offset 0x%x\n",
2030                  channel->mcu_channel_id, partition->size, partition->offset);
2031
2032         /*
2033          * The payload must include the data before the partition offset,
2034          * because we will put the sps and pps data there.
2035          */
2036         vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
2037                               partition->offset + partition->size);
2038
2039         curr = vb2_plane_vaddr(&dst_buf->vb2_buf, 0);
2040         free = partition->offset;
2041
2042         if (channel->codec == V4L2_PIX_FMT_HEVC && msg->is_idr) {
2043                 len = allegro_hevc_write_vps(channel, curr, free);
2044                 if (len < 0) {
2045                         v4l2_err(&dev->v4l2_dev,
2046                                  "not enough space for video parameter set: %zd left\n",
2047                                  free);
2048                         goto err;
2049                 }
2050                 curr += len;
2051                 free -= len;
2052                 v4l2_dbg(1, debug, &dev->v4l2_dev,
2053                          "channel %d: wrote %zd byte VPS nal unit\n",
2054                          channel->mcu_channel_id, len);
2055         }
2056
2057         if (msg->is_idr) {
2058                 if (channel->codec == V4L2_PIX_FMT_H264)
2059                         len = allegro_h264_write_sps(channel, curr, free);
2060                 else
2061                         len = allegro_hevc_write_sps(channel, curr, free);
2062                 if (len < 0) {
2063                         v4l2_err(&dev->v4l2_dev,
2064                                  "not enough space for sequence parameter set: %zd left\n",
2065                                  free);
2066                         goto err;
2067                 }
2068                 curr += len;
2069                 free -= len;
2070                 v4l2_dbg(1, debug, &dev->v4l2_dev,
2071                          "channel %d: wrote %zd byte SPS nal unit\n",
2072                          channel->mcu_channel_id, len);
2073         }
2074
2075         if (msg->slice_type == AL_ENC_SLICE_TYPE_I) {
2076                 if (channel->codec == V4L2_PIX_FMT_H264)
2077                         len = allegro_h264_write_pps(channel, curr, free);
2078                 else
2079                         len = allegro_hevc_write_pps(channel, msg, curr, free);
2080                 if (len < 0) {
2081                         v4l2_err(&dev->v4l2_dev,
2082                                  "not enough space for picture parameter set: %zd left\n",
2083                                  free);
2084                         goto err;
2085                 }
2086                 curr += len;
2087                 free -= len;
2088                 v4l2_dbg(1, debug, &dev->v4l2_dev,
2089                          "channel %d: wrote %zd byte PPS nal unit\n",
2090                          channel->mcu_channel_id, len);
2091         }
2092
2093         if (msg->slice_type != AL_ENC_SLICE_TYPE_I && !msg->is_idr) {
2094                 dst_buf->vb2_buf.planes[0].data_offset = free;
2095                 free = 0;
2096         } else {
2097                 if (channel->codec == V4L2_PIX_FMT_H264)
2098                         len = nal_h264_write_filler(&dev->plat_dev->dev, curr, free);
2099                 else
2100                         len = nal_hevc_write_filler(&dev->plat_dev->dev, curr, free);
2101                 if (len < 0) {
2102                         v4l2_err(&dev->v4l2_dev,
2103                                  "failed to write %zd filler data\n", free);
2104                         goto err;
2105                 }
2106                 curr += len;
2107                 free -= len;
2108                 v4l2_dbg(2, debug, &dev->v4l2_dev,
2109                          "channel %d: wrote %zd bytes filler nal unit\n",
2110                          channel->mcu_channel_id, len);
2111         }
2112
2113         if (free != 0) {
2114                 v4l2_err(&dev->v4l2_dev,
2115                          "non-VCL NAL units do not fill space until VCL NAL unit: %zd bytes left\n",
2116                          free);
2117                 goto err;
2118         }
2119
2120         state = VB2_BUF_STATE_DONE;
2121
2122         v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, false);
2123         if (msg->is_idr)
2124                 dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
2125         else
2126                 dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
2127
2128         v4l2_dbg(1, debug, &dev->v4l2_dev,
2129                  "channel %d: encoded frame #%03d (%s%s, QP %d, %d bytes)\n",
2130                  channel->mcu_channel_id,
2131                  dst_buf->sequence,
2132                  msg->is_idr ? "IDR, " : "",
2133                  msg->slice_type == AL_ENC_SLICE_TYPE_I ? "I slice" :
2134                  msg->slice_type == AL_ENC_SLICE_TYPE_P ? "P slice" : "unknown",
2135                  msg->qp, partition->size);
2136
2137 err:
2138         if (src_buf)
2139                 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
2140
2141         if (dst_buf)
2142                 v4l2_m2m_buf_done(dst_buf, state);
2143 }
2144
2145 static int allegro_handle_init(struct allegro_dev *dev,
2146                                struct mcu_msg_init_response *msg)
2147 {
2148         complete(&dev->init_complete);
2149
2150         return 0;
2151 }
2152
2153 static int
2154 allegro_handle_create_channel(struct allegro_dev *dev,
2155                               struct mcu_msg_create_channel_response *msg)
2156 {
2157         struct allegro_channel *channel;
2158         int err = 0;
2159         struct create_channel_param param;
2160
2161         channel = allegro_find_channel_by_user_id(dev, msg->user_id);
2162         if (IS_ERR(channel)) {
2163                 v4l2_warn(&dev->v4l2_dev,
2164                           "received %s for unknown user %d\n",
2165                           msg_type_name(msg->header.type),
2166                           msg->user_id);
2167                 return -EINVAL;
2168         }
2169
2170         if (msg->error_code) {
2171                 v4l2_err(&dev->v4l2_dev,
2172                          "user %d: mcu failed to create channel: %s (%x)\n",
2173                          channel->user_id,
2174                          allegro_err_to_string(msg->error_code),
2175                          msg->error_code);
2176                 err = -EIO;
2177                 goto out;
2178         }
2179
2180         channel->mcu_channel_id = msg->channel_id;
2181         v4l2_dbg(1, debug, &dev->v4l2_dev,
2182                  "user %d: channel has channel id %d\n",
2183                  channel->user_id, channel->mcu_channel_id);
2184
2185         err = allegro_decode_config_blob(&param, msg, channel->config_blob.vaddr);
2186         allegro_free_buffer(channel->dev, &channel->config_blob);
2187         if (err)
2188                 goto out;
2189
2190         channel->num_ref_idx_l0 = param.num_ref_idx_l0;
2191         channel->num_ref_idx_l1 = param.num_ref_idx_l1;
2192
2193         v4l2_dbg(1, debug, &dev->v4l2_dev,
2194                  "channel %d: intermediate buffers: %d x %d bytes\n",
2195                  channel->mcu_channel_id,
2196                  msg->int_buffers_count, msg->int_buffers_size);
2197         err = allocate_intermediate_buffers(channel, msg->int_buffers_count,
2198                                             msg->int_buffers_size);
2199         if (err) {
2200                 v4l2_err(&dev->v4l2_dev,
2201                          "channel %d: failed to allocate intermediate buffers\n",
2202                          channel->mcu_channel_id);
2203                 goto out;
2204         }
2205         err = allegro_mcu_push_buffer_intermediate(channel);
2206         if (err)
2207                 goto out;
2208
2209         v4l2_dbg(1, debug, &dev->v4l2_dev,
2210                  "channel %d: reference buffers: %d x %d bytes\n",
2211                  channel->mcu_channel_id,
2212                  msg->rec_buffers_count, msg->rec_buffers_size);
2213         err = allocate_reference_buffers(channel, msg->rec_buffers_count,
2214                                          msg->rec_buffers_size);
2215         if (err) {
2216                 v4l2_err(&dev->v4l2_dev,
2217                          "channel %d: failed to allocate reference buffers\n",
2218                          channel->mcu_channel_id);
2219                 goto out;
2220         }
2221         err = allegro_mcu_push_buffer_reference(channel);
2222         if (err)
2223                 goto out;
2224
2225 out:
2226         channel->error = err;
2227         complete(&channel->completion);
2228
2229         /* Handled successfully, error is passed via channel->error */
2230         return 0;
2231 }
2232
2233 static int
2234 allegro_handle_destroy_channel(struct allegro_dev *dev,
2235                                struct mcu_msg_destroy_channel_response *msg)
2236 {
2237         struct allegro_channel *channel;
2238
2239         channel = allegro_find_channel_by_channel_id(dev, msg->channel_id);
2240         if (IS_ERR(channel)) {
2241                 v4l2_err(&dev->v4l2_dev,
2242                          "received %s for unknown channel %d\n",
2243                          msg_type_name(msg->header.type),
2244                          msg->channel_id);
2245                 return -EINVAL;
2246         }
2247
2248         v4l2_dbg(2, debug, &dev->v4l2_dev,
2249                  "user %d: vcu destroyed channel %d\n",
2250                  channel->user_id, channel->mcu_channel_id);
2251         complete(&channel->completion);
2252
2253         return 0;
2254 }
2255
2256 static int
2257 allegro_handle_encode_frame(struct allegro_dev *dev,
2258                             struct mcu_msg_encode_frame_response *msg)
2259 {
2260         struct allegro_channel *channel;
2261
2262         channel = allegro_find_channel_by_channel_id(dev, msg->channel_id);
2263         if (IS_ERR(channel)) {
2264                 v4l2_err(&dev->v4l2_dev,
2265                          "received %s for unknown channel %d\n",
2266                          msg_type_name(msg->header.type),
2267                          msg->channel_id);
2268                 return -EINVAL;
2269         }
2270
2271         allegro_channel_finish_frame(channel, msg);
2272
2273         return 0;
2274 }
2275
2276 static void allegro_handle_message(struct allegro_dev *dev,
2277                                    union mcu_msg_response *msg)
2278 {
2279         switch (msg->header.type) {
2280         case MCU_MSG_TYPE_INIT:
2281                 allegro_handle_init(dev, &msg->init);
2282                 break;
2283         case MCU_MSG_TYPE_CREATE_CHANNEL:
2284                 allegro_handle_create_channel(dev, &msg->create_channel);
2285                 break;
2286         case MCU_MSG_TYPE_DESTROY_CHANNEL:
2287                 allegro_handle_destroy_channel(dev, &msg->destroy_channel);
2288                 break;
2289         case MCU_MSG_TYPE_ENCODE_FRAME:
2290                 allegro_handle_encode_frame(dev, &msg->encode_frame);
2291                 break;
2292         default:
2293                 v4l2_warn(&dev->v4l2_dev,
2294                           "%s: unknown message %s\n",
2295                           __func__, msg_type_name(msg->header.type));
2296                 break;
2297         }
2298 }
2299
2300 static irqreturn_t allegro_hardirq(int irq, void *data)
2301 {
2302         struct allegro_dev *dev = data;
2303         unsigned int status;
2304
2305         regmap_read(dev->regmap, AL5_ITC_CPU_IRQ_STA, &status);
2306         if (!(status & AL5_ITC_CPU_IRQ_STA_TRIGGERED))
2307                 return IRQ_NONE;
2308
2309         regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_CLR, status);
2310
2311         return IRQ_WAKE_THREAD;
2312 }
2313
2314 static irqreturn_t allegro_irq_thread(int irq, void *data)
2315 {
2316         struct allegro_dev *dev = data;
2317
2318         /*
2319          * The firmware is initialized after the mailbox is setup. We further
2320          * check the AL5_ITC_CPU_IRQ_STA register, if the firmware actually
2321          * triggered the interrupt. Although this should not happen, make sure
2322          * that we ignore interrupts, if the mailbox is not initialized.
2323          */
2324         if (!dev->mbox_status)
2325                 return IRQ_NONE;
2326
2327         allegro_mbox_notify(dev->mbox_status);
2328
2329         return IRQ_HANDLED;
2330 }
2331
2332 static void allegro_copy_firmware(struct allegro_dev *dev,
2333                                   const u8 * const buf, size_t size)
2334 {
2335         int err = 0;
2336
2337         v4l2_dbg(1, debug, &dev->v4l2_dev,
2338                  "copy mcu firmware (%zu B) to SRAM\n", size);
2339         err = regmap_bulk_write(dev->sram, 0x0, buf, size / 4);
2340         if (err)
2341                 v4l2_err(&dev->v4l2_dev,
2342                          "failed to copy firmware: %d\n", err);
2343 }
2344
2345 static void allegro_copy_fw_codec(struct allegro_dev *dev,
2346                                   const u8 * const buf, size_t size)
2347 {
2348         int err;
2349         dma_addr_t icache_offset, dcache_offset;
2350
2351         /*
2352          * The downstream allocates 600 KB for the codec firmware to have some
2353          * extra space for "possible extensions." My tests were fine with
2354          * allocating just enough memory for the actual firmware, but I am not
2355          * sure that the firmware really does not use the remaining space.
2356          */
2357         err = allegro_alloc_buffer(dev, &dev->firmware, size);
2358         if (err) {
2359                 v4l2_err(&dev->v4l2_dev,
2360                          "failed to allocate %zu bytes for firmware\n", size);
2361                 return;
2362         }
2363
2364         v4l2_dbg(1, debug, &dev->v4l2_dev,
2365                  "copy codec firmware (%zd B) to phys %pad\n",
2366                  size, &dev->firmware.paddr);
2367         memcpy(dev->firmware.vaddr, buf, size);
2368
2369         regmap_write(dev->regmap, AXI_ADDR_OFFSET_IP,
2370                      upper_32_bits(dev->firmware.paddr));
2371
2372         icache_offset = dev->firmware.paddr - MCU_CACHE_OFFSET;
2373         v4l2_dbg(2, debug, &dev->v4l2_dev,
2374                  "icache_offset: msb = 0x%x, lsb = 0x%x\n",
2375                  upper_32_bits(icache_offset), lower_32_bits(icache_offset));
2376         regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_MSB,
2377                      upper_32_bits(icache_offset));
2378         regmap_write(dev->regmap, AL5_ICACHE_ADDR_OFFSET_LSB,
2379                      lower_32_bits(icache_offset));
2380
2381         dcache_offset =
2382             (dev->firmware.paddr & 0xffffffff00000000ULL) - MCU_CACHE_OFFSET;
2383         v4l2_dbg(2, debug, &dev->v4l2_dev,
2384                  "dcache_offset: msb = 0x%x, lsb = 0x%x\n",
2385                  upper_32_bits(dcache_offset), lower_32_bits(dcache_offset));
2386         regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_MSB,
2387                      upper_32_bits(dcache_offset));
2388         regmap_write(dev->regmap, AL5_DCACHE_ADDR_OFFSET_LSB,
2389                      lower_32_bits(dcache_offset));
2390 }
2391
2392 static void allegro_free_fw_codec(struct allegro_dev *dev)
2393 {
2394         allegro_free_buffer(dev, &dev->firmware);
2395 }
2396
2397 /*
2398  * Control functions for the MCU
2399  */
2400
2401 static int allegro_mcu_enable_interrupts(struct allegro_dev *dev)
2402 {
2403         return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, BIT(0));
2404 }
2405
2406 static int allegro_mcu_disable_interrupts(struct allegro_dev *dev)
2407 {
2408         return regmap_write(dev->regmap, AL5_ITC_CPU_IRQ_MSK, 0);
2409 }
2410
2411 static int allegro_mcu_wait_for_sleep(struct allegro_dev *dev)
2412 {
2413         unsigned long timeout;
2414         unsigned int status;
2415
2416         timeout = jiffies + msecs_to_jiffies(100);
2417         while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
2418                status != AL5_MCU_STA_SLEEP) {
2419                 if (time_after(jiffies, timeout))
2420                         return -ETIMEDOUT;
2421                 cpu_relax();
2422         }
2423
2424         return 0;
2425 }
2426
2427 static int allegro_mcu_start(struct allegro_dev *dev)
2428 {
2429         unsigned long timeout;
2430         unsigned int status;
2431         int err;
2432
2433         err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, BIT(0));
2434         if (err)
2435                 return err;
2436
2437         timeout = jiffies + msecs_to_jiffies(100);
2438         while (regmap_read(dev->regmap, AL5_MCU_STA, &status) == 0 &&
2439                status == AL5_MCU_STA_SLEEP) {
2440                 if (time_after(jiffies, timeout))
2441                         return -ETIMEDOUT;
2442                 cpu_relax();
2443         }
2444
2445         err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, 0);
2446         if (err)
2447                 return err;
2448
2449         return 0;
2450 }
2451
2452 static int allegro_mcu_reset(struct allegro_dev *dev)
2453 {
2454         int err;
2455
2456         /*
2457          * Ensure that the AL5_MCU_WAKEUP bit is set to 0 otherwise the mcu
2458          * does not go to sleep after the reset.
2459          */
2460         err = regmap_write(dev->regmap, AL5_MCU_WAKEUP, 0);
2461         if (err)
2462                 return err;
2463
2464         err = regmap_write(dev->regmap,
2465                            AL5_MCU_RESET_MODE, AL5_MCU_RESET_MODE_SLEEP);
2466         if (err < 0)
2467                 return err;
2468
2469         err = regmap_write(dev->regmap, AL5_MCU_RESET, AL5_MCU_RESET_SOFT);
2470         if (err < 0)
2471                 return err;
2472
2473         return allegro_mcu_wait_for_sleep(dev);
2474 }
2475
2476 static void allegro_mcu_interrupt(struct allegro_dev *dev)
2477 {
2478         regmap_write(dev->regmap, AL5_MCU_INTERRUPT, BIT(0));
2479 }
2480
2481 static void allegro_destroy_channel(struct allegro_channel *channel)
2482 {
2483         struct allegro_dev *dev = channel->dev;
2484         unsigned long timeout;
2485
2486         if (channel_exists(channel)) {
2487                 reinit_completion(&channel->completion);
2488                 allegro_mcu_send_destroy_channel(dev, channel);
2489                 timeout = wait_for_completion_timeout(&channel->completion,
2490                                                       msecs_to_jiffies(5000));
2491                 if (timeout == 0)
2492                         v4l2_warn(&dev->v4l2_dev,
2493                                   "channel %d: timeout while destroying\n",
2494                                   channel->mcu_channel_id);
2495
2496                 channel->mcu_channel_id = -1;
2497         }
2498
2499         destroy_intermediate_buffers(channel);
2500         destroy_reference_buffers(channel);
2501
2502         v4l2_ctrl_grab(channel->mpeg_video_h264_profile, false);
2503         v4l2_ctrl_grab(channel->mpeg_video_h264_level, false);
2504         v4l2_ctrl_grab(channel->mpeg_video_h264_i_frame_qp, false);
2505         v4l2_ctrl_grab(channel->mpeg_video_h264_max_qp, false);
2506         v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, false);
2507         v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, false);
2508         v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, false);
2509
2510         v4l2_ctrl_grab(channel->mpeg_video_hevc_profile, false);
2511         v4l2_ctrl_grab(channel->mpeg_video_hevc_level, false);
2512         v4l2_ctrl_grab(channel->mpeg_video_hevc_tier, false);
2513         v4l2_ctrl_grab(channel->mpeg_video_hevc_i_frame_qp, false);
2514         v4l2_ctrl_grab(channel->mpeg_video_hevc_max_qp, false);
2515         v4l2_ctrl_grab(channel->mpeg_video_hevc_min_qp, false);
2516         v4l2_ctrl_grab(channel->mpeg_video_hevc_p_frame_qp, false);
2517         v4l2_ctrl_grab(channel->mpeg_video_hevc_b_frame_qp, false);
2518
2519         v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, false);
2520         v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, false);
2521         v4l2_ctrl_grab(channel->mpeg_video_bitrate, false);
2522         v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, false);
2523         v4l2_ctrl_grab(channel->mpeg_video_cpb_size, false);
2524         v4l2_ctrl_grab(channel->mpeg_video_gop_size, false);
2525
2526         v4l2_ctrl_grab(channel->encoder_buffer, false);
2527
2528         if (channel->user_id != -1) {
2529                 clear_bit(channel->user_id, &dev->channel_user_ids);
2530                 channel->user_id = -1;
2531         }
2532 }
2533
2534 /*
2535  * Create the MCU channel
2536  *
2537  * After the channel has been created, the picture size, format, colorspace
2538  * and framerate are fixed. Also the codec, profile, bitrate, etc. cannot be
2539  * changed anymore.
2540  *
2541  * The channel can be created only once. The MCU will accept source buffers
2542  * and stream buffers only after a channel has been created.
2543  */
2544 static int allegro_create_channel(struct allegro_channel *channel)
2545 {
2546         struct allegro_dev *dev = channel->dev;
2547         unsigned long timeout;
2548
2549         if (channel_exists(channel)) {
2550                 v4l2_warn(&dev->v4l2_dev,
2551                           "channel already exists\n");
2552                 return 0;
2553         }
2554
2555         channel->user_id = allegro_next_user_id(dev);
2556         if (channel->user_id < 0) {
2557                 v4l2_err(&dev->v4l2_dev,
2558                          "no free channels available\n");
2559                 return -EBUSY;
2560         }
2561         set_bit(channel->user_id, &dev->channel_user_ids);
2562
2563         v4l2_dbg(1, debug, &dev->v4l2_dev,
2564                  "user %d: creating channel (%4.4s, %dx%d@%d)\n",
2565                  channel->user_id,
2566                  (char *)&channel->codec, channel->width, channel->height,
2567                  DIV_ROUND_UP(channel->framerate.numerator,
2568                               channel->framerate.denominator));
2569
2570         v4l2_ctrl_grab(channel->mpeg_video_h264_profile, true);
2571         v4l2_ctrl_grab(channel->mpeg_video_h264_level, true);
2572         v4l2_ctrl_grab(channel->mpeg_video_h264_i_frame_qp, true);
2573         v4l2_ctrl_grab(channel->mpeg_video_h264_max_qp, true);
2574         v4l2_ctrl_grab(channel->mpeg_video_h264_min_qp, true);
2575         v4l2_ctrl_grab(channel->mpeg_video_h264_p_frame_qp, true);
2576         v4l2_ctrl_grab(channel->mpeg_video_h264_b_frame_qp, true);
2577
2578         v4l2_ctrl_grab(channel->mpeg_video_hevc_profile, true);
2579         v4l2_ctrl_grab(channel->mpeg_video_hevc_level, true);
2580         v4l2_ctrl_grab(channel->mpeg_video_hevc_tier, true);
2581         v4l2_ctrl_grab(channel->mpeg_video_hevc_i_frame_qp, true);
2582         v4l2_ctrl_grab(channel->mpeg_video_hevc_max_qp, true);
2583         v4l2_ctrl_grab(channel->mpeg_video_hevc_min_qp, true);
2584         v4l2_ctrl_grab(channel->mpeg_video_hevc_p_frame_qp, true);
2585         v4l2_ctrl_grab(channel->mpeg_video_hevc_b_frame_qp, true);
2586
2587         v4l2_ctrl_grab(channel->mpeg_video_frame_rc_enable, true);
2588         v4l2_ctrl_grab(channel->mpeg_video_bitrate_mode, true);
2589         v4l2_ctrl_grab(channel->mpeg_video_bitrate, true);
2590         v4l2_ctrl_grab(channel->mpeg_video_bitrate_peak, true);
2591         v4l2_ctrl_grab(channel->mpeg_video_cpb_size, true);
2592         v4l2_ctrl_grab(channel->mpeg_video_gop_size, true);
2593
2594         v4l2_ctrl_grab(channel->encoder_buffer, true);
2595
2596         reinit_completion(&channel->completion);
2597         allegro_mcu_send_create_channel(dev, channel);
2598         timeout = wait_for_completion_timeout(&channel->completion,
2599                                               msecs_to_jiffies(5000));
2600         if (timeout == 0)
2601                 channel->error = -ETIMEDOUT;
2602         if (channel->error)
2603                 goto err;
2604
2605         v4l2_dbg(1, debug, &dev->v4l2_dev,
2606                  "channel %d: accepting buffers\n",
2607                  channel->mcu_channel_id);
2608
2609         return 0;
2610
2611 err:
2612         allegro_destroy_channel(channel);
2613
2614         return channel->error;
2615 }
2616
2617 /**
2618  * allegro_channel_adjust() - Adjust channel parameters to current format
2619  * @channel: the channel to adjust
2620  *
2621  * Various parameters of a channel and their limits depend on the currently
2622  * set format. Adjust the parameters after a format change in one go.
2623  */
2624 static void allegro_channel_adjust(struct allegro_channel *channel)
2625 {
2626         struct allegro_dev *dev = channel->dev;
2627         u32 codec = channel->codec;
2628         struct v4l2_ctrl *ctrl;
2629         s64 min;
2630         s64 max;
2631
2632         channel->sizeimage_encoded =
2633                 estimate_stream_size(channel->width, channel->height);
2634
2635         if (codec == V4L2_PIX_FMT_H264) {
2636                 ctrl = channel->mpeg_video_h264_level;
2637                 min = select_minimum_h264_level(channel->width, channel->height);
2638         } else {
2639                 ctrl = channel->mpeg_video_hevc_level;
2640                 min = select_minimum_hevc_level(channel->width, channel->height);
2641         }
2642         if (ctrl->minimum > min)
2643                 v4l2_dbg(1, debug, &dev->v4l2_dev,
2644                          "%s.minimum: %lld -> %lld\n",
2645                          v4l2_ctrl_get_name(ctrl->id), ctrl->minimum, min);
2646         v4l2_ctrl_lock(ctrl);
2647         __v4l2_ctrl_modify_range(ctrl, min, ctrl->maximum,
2648                                  ctrl->step, ctrl->default_value);
2649         v4l2_ctrl_unlock(ctrl);
2650
2651         ctrl = channel->mpeg_video_bitrate;
2652         if (codec == V4L2_PIX_FMT_H264)
2653                 max = h264_maximum_bitrate(v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_level));
2654         else
2655                 max = hevc_maximum_bitrate(v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_level));
2656         if (ctrl->maximum < max)
2657                 v4l2_dbg(1, debug, &dev->v4l2_dev,
2658                          "%s: maximum: %lld -> %lld\n",
2659                          v4l2_ctrl_get_name(ctrl->id), ctrl->maximum, max);
2660         v4l2_ctrl_lock(ctrl);
2661         __v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max,
2662                                  ctrl->step, ctrl->default_value);
2663         v4l2_ctrl_unlock(ctrl);
2664
2665         ctrl = channel->mpeg_video_bitrate_peak;
2666         v4l2_ctrl_lock(ctrl);
2667         __v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max,
2668                                  ctrl->step, ctrl->default_value);
2669         v4l2_ctrl_unlock(ctrl);
2670
2671         v4l2_ctrl_activate(channel->mpeg_video_h264_profile,
2672                            codec == V4L2_PIX_FMT_H264);
2673         v4l2_ctrl_activate(channel->mpeg_video_h264_level,
2674                            codec == V4L2_PIX_FMT_H264);
2675         v4l2_ctrl_activate(channel->mpeg_video_h264_i_frame_qp,
2676                            codec == V4L2_PIX_FMT_H264);
2677         v4l2_ctrl_activate(channel->mpeg_video_h264_max_qp,
2678                            codec == V4L2_PIX_FMT_H264);
2679         v4l2_ctrl_activate(channel->mpeg_video_h264_min_qp,
2680                            codec == V4L2_PIX_FMT_H264);
2681         v4l2_ctrl_activate(channel->mpeg_video_h264_p_frame_qp,
2682                            codec == V4L2_PIX_FMT_H264);
2683         v4l2_ctrl_activate(channel->mpeg_video_h264_b_frame_qp,
2684                            codec == V4L2_PIX_FMT_H264);
2685
2686         v4l2_ctrl_activate(channel->mpeg_video_hevc_profile,
2687                            codec == V4L2_PIX_FMT_HEVC);
2688         v4l2_ctrl_activate(channel->mpeg_video_hevc_level,
2689                            codec == V4L2_PIX_FMT_HEVC);
2690         v4l2_ctrl_activate(channel->mpeg_video_hevc_tier,
2691                            codec == V4L2_PIX_FMT_HEVC);
2692         v4l2_ctrl_activate(channel->mpeg_video_hevc_i_frame_qp,
2693                            codec == V4L2_PIX_FMT_HEVC);
2694         v4l2_ctrl_activate(channel->mpeg_video_hevc_max_qp,
2695                            codec == V4L2_PIX_FMT_HEVC);
2696         v4l2_ctrl_activate(channel->mpeg_video_hevc_min_qp,
2697                            codec == V4L2_PIX_FMT_HEVC);
2698         v4l2_ctrl_activate(channel->mpeg_video_hevc_p_frame_qp,
2699                            codec == V4L2_PIX_FMT_HEVC);
2700         v4l2_ctrl_activate(channel->mpeg_video_hevc_b_frame_qp,
2701                            codec == V4L2_PIX_FMT_HEVC);
2702
2703         if (codec == V4L2_PIX_FMT_H264)
2704                 channel->log2_max_frame_num = LOG2_MAX_FRAME_NUM;
2705         channel->temporal_mvp_enable = true;
2706         channel->dbf_ovr_en = (codec == V4L2_PIX_FMT_H264);
2707         channel->enable_deblocking_filter_override = (codec == V4L2_PIX_FMT_HEVC);
2708         channel->enable_reordering = (codec == V4L2_PIX_FMT_HEVC);
2709         channel->enable_loop_filter_across_tiles = true;
2710         channel->enable_loop_filter_across_slices = true;
2711
2712         if (codec == V4L2_PIX_FMT_H264) {
2713                 channel->b_hrz_me_range = 8;
2714                 channel->b_vrt_me_range = 8;
2715                 channel->p_hrz_me_range = 16;
2716                 channel->p_vrt_me_range = 16;
2717                 channel->max_cu_size = ilog2(16);
2718                 channel->min_cu_size = ilog2(8);
2719                 channel->max_tu_size = ilog2(4);
2720                 channel->min_tu_size = ilog2(4);
2721         } else {
2722                 channel->b_hrz_me_range = 16;
2723                 channel->b_vrt_me_range = 16;
2724                 channel->p_hrz_me_range = 32;
2725                 channel->p_vrt_me_range = 32;
2726                 channel->max_cu_size = ilog2(32);
2727                 channel->min_cu_size = ilog2(8);
2728                 channel->max_tu_size = ilog2(32);
2729                 channel->min_tu_size = ilog2(4);
2730         }
2731         channel->max_transfo_depth_intra = 1;
2732         channel->max_transfo_depth_inter = 1;
2733 }
2734
2735 static void allegro_set_default_params(struct allegro_channel *channel)
2736 {
2737         channel->width = ALLEGRO_WIDTH_DEFAULT;
2738         channel->height = ALLEGRO_HEIGHT_DEFAULT;
2739         channel->stride = round_up(channel->width, 32);
2740         channel->framerate = ALLEGRO_FRAMERATE_DEFAULT;
2741
2742         channel->colorspace = V4L2_COLORSPACE_REC709;
2743         channel->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
2744         channel->quantization = V4L2_QUANTIZATION_DEFAULT;
2745         channel->xfer_func = V4L2_XFER_FUNC_DEFAULT;
2746
2747         channel->pixelformat = V4L2_PIX_FMT_NV12;
2748         channel->sizeimage_raw = channel->stride * channel->height * 3 / 2;
2749
2750         channel->codec = V4L2_PIX_FMT_H264;
2751 }
2752
2753 static int allegro_queue_setup(struct vb2_queue *vq,
2754                                unsigned int *nbuffers, unsigned int *nplanes,
2755                                unsigned int sizes[],
2756                                struct device *alloc_devs[])
2757 {
2758         struct allegro_channel *channel = vb2_get_drv_priv(vq);
2759         struct allegro_dev *dev = channel->dev;
2760
2761         v4l2_dbg(2, debug, &dev->v4l2_dev,
2762                  "%s: queue setup[%s]: nplanes = %d\n",
2763                  V4L2_TYPE_IS_OUTPUT(vq->type) ? "output" : "capture",
2764                  *nplanes == 0 ? "REQBUFS" : "CREATE_BUFS", *nplanes);
2765
2766         if (*nplanes != 0) {
2767                 if (V4L2_TYPE_IS_OUTPUT(vq->type)) {
2768                         if (sizes[0] < channel->sizeimage_raw)
2769                                 return -EINVAL;
2770                 } else {
2771                         if (sizes[0] < channel->sizeimage_encoded)
2772                                 return -EINVAL;
2773                 }
2774         } else {
2775                 *nplanes = 1;
2776                 if (V4L2_TYPE_IS_OUTPUT(vq->type))
2777                         sizes[0] = channel->sizeimage_raw;
2778                 else
2779                         sizes[0] = channel->sizeimage_encoded;
2780         }
2781
2782         return 0;
2783 }
2784
2785 static int allegro_buf_prepare(struct vb2_buffer *vb)
2786 {
2787         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2788         struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2789         struct allegro_dev *dev = channel->dev;
2790
2791         if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
2792                 if (vbuf->field == V4L2_FIELD_ANY)
2793                         vbuf->field = V4L2_FIELD_NONE;
2794                 if (vbuf->field != V4L2_FIELD_NONE) {
2795                         v4l2_err(&dev->v4l2_dev,
2796                                  "channel %d: unsupported field\n",
2797                                  channel->mcu_channel_id);
2798                         return -EINVAL;
2799                 }
2800         }
2801
2802         return 0;
2803 }
2804
2805 static void allegro_buf_queue(struct vb2_buffer *vb)
2806 {
2807         struct allegro_channel *channel = vb2_get_drv_priv(vb->vb2_queue);
2808         struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2809         struct vb2_queue *q = vb->vb2_queue;
2810
2811         if (V4L2_TYPE_IS_CAPTURE(q->type) &&
2812             vb2_is_streaming(q) &&
2813             v4l2_m2m_dst_buf_is_last(channel->fh.m2m_ctx)) {
2814                 unsigned int i;
2815
2816                 for (i = 0; i < vb->num_planes; i++)
2817                         vb2_set_plane_payload(vb, i, 0);
2818
2819                 vbuf->field = V4L2_FIELD_NONE;
2820                 vbuf->sequence = channel->csequence++;
2821
2822                 v4l2_m2m_last_buffer_done(channel->fh.m2m_ctx, vbuf);
2823                 allegro_channel_eos_event(channel);
2824                 return;
2825         }
2826
2827         v4l2_m2m_buf_queue(channel->fh.m2m_ctx, vbuf);
2828 }
2829
2830 static int allegro_start_streaming(struct vb2_queue *q, unsigned int count)
2831 {
2832         struct allegro_channel *channel = vb2_get_drv_priv(q);
2833         struct allegro_dev *dev = channel->dev;
2834
2835         v4l2_dbg(2, debug, &dev->v4l2_dev,
2836                  "%s: start streaming\n",
2837                  V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2838
2839         v4l2_m2m_update_start_streaming_state(channel->fh.m2m_ctx, q);
2840
2841         if (V4L2_TYPE_IS_OUTPUT(q->type))
2842                 channel->osequence = 0;
2843         else
2844                 channel->csequence = 0;
2845
2846         return 0;
2847 }
2848
2849 static void allegro_stop_streaming(struct vb2_queue *q)
2850 {
2851         struct allegro_channel *channel = vb2_get_drv_priv(q);
2852         struct allegro_dev *dev = channel->dev;
2853         struct vb2_v4l2_buffer *buffer;
2854         struct allegro_m2m_buffer *shadow, *tmp;
2855
2856         v4l2_dbg(2, debug, &dev->v4l2_dev,
2857                  "%s: stop streaming\n",
2858                  V4L2_TYPE_IS_OUTPUT(q->type) ? "output" : "capture");
2859
2860         if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2861                 mutex_lock(&channel->shadow_list_lock);
2862                 list_for_each_entry_safe(shadow, tmp,
2863                                          &channel->source_shadow_list, head) {
2864                         list_del(&shadow->head);
2865                         v4l2_m2m_buf_done(&shadow->buf.vb, VB2_BUF_STATE_ERROR);
2866                 }
2867                 mutex_unlock(&channel->shadow_list_lock);
2868
2869                 while ((buffer = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx)))
2870                         v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2871         } else {
2872                 mutex_lock(&channel->shadow_list_lock);
2873                 list_for_each_entry_safe(shadow, tmp,
2874                                          &channel->stream_shadow_list, head) {
2875                         list_del(&shadow->head);
2876                         v4l2_m2m_buf_done(&shadow->buf.vb, VB2_BUF_STATE_ERROR);
2877                 }
2878                 mutex_unlock(&channel->shadow_list_lock);
2879
2880                 allegro_destroy_channel(channel);
2881                 while ((buffer = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx)))
2882                         v4l2_m2m_buf_done(buffer, VB2_BUF_STATE_ERROR);
2883         }
2884
2885         v4l2_m2m_update_stop_streaming_state(channel->fh.m2m_ctx, q);
2886
2887         if (V4L2_TYPE_IS_OUTPUT(q->type) &&
2888             v4l2_m2m_has_stopped(channel->fh.m2m_ctx))
2889                 allegro_channel_eos_event(channel);
2890 }
2891
2892 static const struct vb2_ops allegro_queue_ops = {
2893         .queue_setup = allegro_queue_setup,
2894         .buf_prepare = allegro_buf_prepare,
2895         .buf_queue = allegro_buf_queue,
2896         .start_streaming = allegro_start_streaming,
2897         .stop_streaming = allegro_stop_streaming,
2898         .wait_prepare = vb2_ops_wait_prepare,
2899         .wait_finish = vb2_ops_wait_finish,
2900 };
2901
2902 static int allegro_queue_init(void *priv,
2903                               struct vb2_queue *src_vq,
2904                               struct vb2_queue *dst_vq)
2905 {
2906         int err;
2907         struct allegro_channel *channel = priv;
2908
2909         src_vq->dev = &channel->dev->plat_dev->dev;
2910         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
2911         src_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2912         src_vq->mem_ops = &vb2_dma_contig_memops;
2913         src_vq->drv_priv = channel;
2914         src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2915         src_vq->ops = &allegro_queue_ops;
2916         src_vq->buf_struct_size = sizeof(struct allegro_m2m_buffer);
2917         src_vq->lock = &channel->dev->lock;
2918         err = vb2_queue_init(src_vq);
2919         if (err)
2920                 return err;
2921
2922         dst_vq->dev = &channel->dev->plat_dev->dev;
2923         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2924         dst_vq->io_modes = VB2_DMABUF | VB2_MMAP;
2925         dst_vq->mem_ops = &vb2_dma_contig_memops;
2926         dst_vq->drv_priv = channel;
2927         dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2928         dst_vq->ops = &allegro_queue_ops;
2929         dst_vq->buf_struct_size = sizeof(struct allegro_m2m_buffer);
2930         dst_vq->lock = &channel->dev->lock;
2931         err = vb2_queue_init(dst_vq);
2932         if (err)
2933                 return err;
2934
2935         return 0;
2936 }
2937
2938 static int allegro_clamp_qp(struct allegro_channel *channel,
2939                             struct v4l2_ctrl *ctrl)
2940 {
2941         struct v4l2_ctrl *next_ctrl;
2942
2943         if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP)
2944                 next_ctrl = channel->mpeg_video_h264_p_frame_qp;
2945         else if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP)
2946                 next_ctrl = channel->mpeg_video_h264_b_frame_qp;
2947         else
2948                 return 0;
2949
2950         /* Modify range automatically updates the value */
2951         __v4l2_ctrl_modify_range(next_ctrl, ctrl->val, 51, 1, ctrl->val);
2952
2953         return allegro_clamp_qp(channel, next_ctrl);
2954 }
2955
2956 static int allegro_clamp_bitrate(struct allegro_channel *channel,
2957                                  struct v4l2_ctrl *ctrl)
2958 {
2959         struct v4l2_ctrl *ctrl_bitrate = channel->mpeg_video_bitrate;
2960         struct v4l2_ctrl *ctrl_bitrate_peak = channel->mpeg_video_bitrate_peak;
2961
2962         if (ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR &&
2963             ctrl_bitrate_peak->val < ctrl_bitrate->val)
2964                 ctrl_bitrate_peak->val = ctrl_bitrate->val;
2965
2966         return 0;
2967 }
2968
2969 static int allegro_try_ctrl(struct v4l2_ctrl *ctrl)
2970 {
2971         struct allegro_channel *channel = container_of(ctrl->handler,
2972                                                        struct allegro_channel,
2973                                                        ctrl_handler);
2974
2975         switch (ctrl->id) {
2976         case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
2977                 allegro_clamp_bitrate(channel, ctrl);
2978                 break;
2979         case V4L2_CID_USER_ALLEGRO_ENCODER_BUFFER:
2980                 if (!channel->dev->has_encoder_buffer)
2981                         ctrl->val = 0;
2982                 break;
2983         }
2984
2985         return 0;
2986 }
2987
2988 static int allegro_s_ctrl(struct v4l2_ctrl *ctrl)
2989 {
2990         struct allegro_channel *channel = container_of(ctrl->handler,
2991                                                        struct allegro_channel,
2992                                                        ctrl_handler);
2993         struct allegro_dev *dev = channel->dev;
2994
2995         v4l2_dbg(1, debug, &dev->v4l2_dev,
2996                  "s_ctrl: %s = %d\n", v4l2_ctrl_get_name(ctrl->id), ctrl->val);
2997
2998         switch (ctrl->id) {
2999         case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE:
3000                 channel->frame_rc_enable = ctrl->val;
3001                 break;
3002         case V4L2_CID_MPEG_VIDEO_BITRATE_MODE:
3003                 channel->bitrate = channel->mpeg_video_bitrate->val;
3004                 channel->bitrate_peak = channel->mpeg_video_bitrate_peak->val;
3005                 v4l2_ctrl_activate(channel->mpeg_video_bitrate_peak,
3006                                    ctrl->val == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR);
3007                 break;
3008         case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
3009         case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
3010         case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP:
3011                 allegro_clamp_qp(channel, ctrl);
3012                 break;
3013         }
3014
3015         return 0;
3016 }
3017
3018 static const struct v4l2_ctrl_ops allegro_ctrl_ops = {
3019         .try_ctrl = allegro_try_ctrl,
3020         .s_ctrl = allegro_s_ctrl,
3021 };
3022
3023 static const struct v4l2_ctrl_config allegro_encoder_buffer_ctrl_config = {
3024         .id = V4L2_CID_USER_ALLEGRO_ENCODER_BUFFER,
3025         .name = "Encoder Buffer Enable",
3026         .type = V4L2_CTRL_TYPE_BOOLEAN,
3027         .min = 0,
3028         .max = 1,
3029         .step = 1,
3030         .def = 1,
3031 };
3032
3033 static int allegro_open(struct file *file)
3034 {
3035         struct video_device *vdev = video_devdata(file);
3036         struct allegro_dev *dev = video_get_drvdata(vdev);
3037         struct allegro_channel *channel = NULL;
3038         struct v4l2_ctrl_handler *handler;
3039         u64 mask;
3040         int ret;
3041         unsigned int bitrate_max;
3042         unsigned int bitrate_def;
3043         unsigned int cpb_size_max;
3044         unsigned int cpb_size_def;
3045
3046         channel = kzalloc(sizeof(*channel), GFP_KERNEL);
3047         if (!channel)
3048                 return -ENOMEM;
3049
3050         v4l2_fh_init(&channel->fh, vdev);
3051
3052         init_completion(&channel->completion);
3053         INIT_LIST_HEAD(&channel->source_shadow_list);
3054         INIT_LIST_HEAD(&channel->stream_shadow_list);
3055         mutex_init(&channel->shadow_list_lock);
3056
3057         channel->dev = dev;
3058
3059         allegro_set_default_params(channel);
3060
3061         handler = &channel->ctrl_handler;
3062         v4l2_ctrl_handler_init(handler, 0);
3063         channel->mpeg_video_h264_profile = v4l2_ctrl_new_std_menu(handler,
3064                         &allegro_ctrl_ops,
3065                         V4L2_CID_MPEG_VIDEO_H264_PROFILE,
3066                         V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 0x0,
3067                         V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE);
3068         mask = 1 << V4L2_MPEG_VIDEO_H264_LEVEL_1B;
3069         channel->mpeg_video_h264_level = v4l2_ctrl_new_std_menu(handler,
3070                         &allegro_ctrl_ops,
3071                         V4L2_CID_MPEG_VIDEO_H264_LEVEL,
3072                         V4L2_MPEG_VIDEO_H264_LEVEL_5_1, mask,
3073                         V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3074         channel->mpeg_video_h264_i_frame_qp =
3075                 v4l2_ctrl_new_std(handler,
3076                                   &allegro_ctrl_ops,
3077                                   V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP,
3078                                   0, 51, 1, 30);
3079         channel->mpeg_video_h264_max_qp =
3080                 v4l2_ctrl_new_std(handler,
3081                                   &allegro_ctrl_ops,
3082                                   V4L2_CID_MPEG_VIDEO_H264_MAX_QP,
3083                                   0, 51, 1, 51);
3084         channel->mpeg_video_h264_min_qp =
3085                 v4l2_ctrl_new_std(handler,
3086                                   &allegro_ctrl_ops,
3087                                   V4L2_CID_MPEG_VIDEO_H264_MIN_QP,
3088                                   0, 51, 1, 0);
3089         channel->mpeg_video_h264_p_frame_qp =
3090                 v4l2_ctrl_new_std(handler,
3091                                   &allegro_ctrl_ops,
3092                                   V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP,
3093                                   0, 51, 1, 30);
3094         channel->mpeg_video_h264_b_frame_qp =
3095                 v4l2_ctrl_new_std(handler,
3096                                   &allegro_ctrl_ops,
3097                                   V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP,
3098                                   0, 51, 1, 30);
3099
3100         channel->mpeg_video_hevc_profile =
3101                 v4l2_ctrl_new_std_menu(handler,
3102                                        &allegro_ctrl_ops,
3103                                        V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
3104                                        V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, 0x0,
3105                                        V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN);
3106         channel->mpeg_video_hevc_level =
3107                 v4l2_ctrl_new_std_menu(handler,
3108                                        &allegro_ctrl_ops,
3109                                        V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
3110                                        V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 0x0,
3111                                        V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3112         channel->mpeg_video_hevc_tier =
3113                 v4l2_ctrl_new_std_menu(handler,
3114                                        &allegro_ctrl_ops,
3115                                        V4L2_CID_MPEG_VIDEO_HEVC_TIER,
3116                                        V4L2_MPEG_VIDEO_HEVC_TIER_HIGH, 0x0,
3117                                        V4L2_MPEG_VIDEO_HEVC_TIER_MAIN);
3118         channel->mpeg_video_hevc_i_frame_qp =
3119                 v4l2_ctrl_new_std(handler,
3120                                   &allegro_ctrl_ops,
3121                                   V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP,
3122                                   0, 51, 1, 30);
3123         channel->mpeg_video_hevc_max_qp =
3124                 v4l2_ctrl_new_std(handler,
3125                                   &allegro_ctrl_ops,
3126                                   V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP,
3127                                   0, 51, 1, 51);
3128         channel->mpeg_video_hevc_min_qp =
3129                 v4l2_ctrl_new_std(handler,
3130                                   &allegro_ctrl_ops,
3131                                   V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
3132                                   0, 51, 1, 0);
3133         channel->mpeg_video_hevc_p_frame_qp =
3134                 v4l2_ctrl_new_std(handler,
3135                                   &allegro_ctrl_ops,
3136                                   V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP,
3137                                   0, 51, 1, 30);
3138         channel->mpeg_video_hevc_b_frame_qp =
3139                 v4l2_ctrl_new_std(handler,
3140                                   &allegro_ctrl_ops,
3141                                   V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP,
3142                                   0, 51, 1, 30);
3143
3144         channel->mpeg_video_frame_rc_enable =
3145                 v4l2_ctrl_new_std(handler,
3146                                   &allegro_ctrl_ops,
3147                                   V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE,
3148                                   false, 0x1,
3149                                   true, false);
3150         channel->mpeg_video_bitrate_mode = v4l2_ctrl_new_std_menu(handler,
3151                         &allegro_ctrl_ops,
3152                         V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
3153                         V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0,
3154                         V4L2_MPEG_VIDEO_BITRATE_MODE_CBR);
3155
3156         if (channel->codec == V4L2_PIX_FMT_H264) {
3157                 bitrate_max = h264_maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3158                 bitrate_def = h264_maximum_bitrate(V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3159                 cpb_size_max = h264_maximum_cpb_size(V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3160                 cpb_size_def = h264_maximum_cpb_size(V4L2_MPEG_VIDEO_H264_LEVEL_5_1);
3161         } else {
3162                 bitrate_max = hevc_maximum_bitrate(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3163                 bitrate_def = hevc_maximum_bitrate(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3164                 cpb_size_max = hevc_maximum_cpb_size(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3165                 cpb_size_def = hevc_maximum_cpb_size(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1);
3166         }
3167         channel->mpeg_video_bitrate = v4l2_ctrl_new_std(handler,
3168                         &allegro_ctrl_ops,
3169                         V4L2_CID_MPEG_VIDEO_BITRATE,
3170                         0, bitrate_max, 1, bitrate_def);
3171         channel->mpeg_video_bitrate_peak = v4l2_ctrl_new_std(handler,
3172                         &allegro_ctrl_ops,
3173                         V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
3174                         0, bitrate_max, 1, bitrate_def);
3175         channel->mpeg_video_cpb_size = v4l2_ctrl_new_std(handler,
3176                         &allegro_ctrl_ops,
3177                         V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE,
3178                         0, cpb_size_max, 1, cpb_size_def);
3179         channel->mpeg_video_gop_size = v4l2_ctrl_new_std(handler,
3180                         &allegro_ctrl_ops,
3181                         V4L2_CID_MPEG_VIDEO_GOP_SIZE,
3182                         0, ALLEGRO_GOP_SIZE_MAX,
3183                         1, ALLEGRO_GOP_SIZE_DEFAULT);
3184         channel->encoder_buffer = v4l2_ctrl_new_custom(handler,
3185                         &allegro_encoder_buffer_ctrl_config, NULL);
3186         v4l2_ctrl_new_std(handler,
3187                           &allegro_ctrl_ops,
3188                           V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
3189                           1, 32,
3190                           1, 1);
3191         if (handler->error != 0) {
3192                 ret = handler->error;
3193                 goto error;
3194         }
3195
3196         channel->fh.ctrl_handler = handler;
3197
3198         v4l2_ctrl_cluster(3, &channel->mpeg_video_bitrate_mode);
3199
3200         v4l2_ctrl_handler_setup(handler);
3201
3202         channel->mcu_channel_id = -1;
3203         channel->user_id = -1;
3204
3205         INIT_LIST_HEAD(&channel->buffers_reference);
3206         INIT_LIST_HEAD(&channel->buffers_intermediate);
3207
3208         channel->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, channel,
3209                                                 allegro_queue_init);
3210
3211         if (IS_ERR(channel->fh.m2m_ctx)) {
3212                 ret = PTR_ERR(channel->fh.m2m_ctx);
3213                 goto error;
3214         }
3215
3216         list_add(&channel->list, &dev->channels);
3217         file->private_data = &channel->fh;
3218         v4l2_fh_add(&channel->fh);
3219
3220         allegro_channel_adjust(channel);
3221
3222         return 0;
3223
3224 error:
3225         v4l2_ctrl_handler_free(handler);
3226         kfree(channel);
3227         return ret;
3228 }
3229
3230 static int allegro_release(struct file *file)
3231 {
3232         struct allegro_channel *channel = fh_to_channel(file->private_data);
3233
3234         v4l2_m2m_ctx_release(channel->fh.m2m_ctx);
3235
3236         list_del(&channel->list);
3237
3238         v4l2_ctrl_handler_free(&channel->ctrl_handler);
3239
3240         v4l2_fh_del(&channel->fh);
3241         v4l2_fh_exit(&channel->fh);
3242
3243         kfree(channel);
3244
3245         return 0;
3246 }
3247
3248 static int allegro_querycap(struct file *file, void *fh,
3249                             struct v4l2_capability *cap)
3250 {
3251         strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
3252         strscpy(cap->card, "Allegro DVT Video Encoder", sizeof(cap->card));
3253
3254         return 0;
3255 }
3256
3257 static int allegro_enum_fmt_vid(struct file *file, void *fh,
3258                                 struct v4l2_fmtdesc *f)
3259 {
3260         switch (f->type) {
3261         case V4L2_BUF_TYPE_VIDEO_OUTPUT:
3262                 if (f->index >= 1)
3263                         return -EINVAL;
3264                 f->pixelformat = V4L2_PIX_FMT_NV12;
3265                 break;
3266         case V4L2_BUF_TYPE_VIDEO_CAPTURE:
3267                 if (f->index >= 2)
3268                         return -EINVAL;
3269                 if (f->index == 0)
3270                         f->pixelformat = V4L2_PIX_FMT_H264;
3271                 if (f->index == 1)
3272                         f->pixelformat = V4L2_PIX_FMT_HEVC;
3273                 break;
3274         default:
3275                 return -EINVAL;
3276         }
3277         return 0;
3278 }
3279
3280 static int allegro_g_fmt_vid_cap(struct file *file, void *fh,
3281                                  struct v4l2_format *f)
3282 {
3283         struct allegro_channel *channel = fh_to_channel(fh);
3284
3285         f->fmt.pix.field = V4L2_FIELD_NONE;
3286         f->fmt.pix.width = channel->width;
3287         f->fmt.pix.height = channel->height;
3288
3289         f->fmt.pix.colorspace = channel->colorspace;
3290         f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
3291         f->fmt.pix.quantization = channel->quantization;
3292         f->fmt.pix.xfer_func = channel->xfer_func;
3293
3294         f->fmt.pix.pixelformat = channel->codec;
3295         f->fmt.pix.bytesperline = 0;
3296         f->fmt.pix.sizeimage = channel->sizeimage_encoded;
3297
3298         return 0;
3299 }
3300
3301 static int allegro_try_fmt_vid_cap(struct file *file, void *fh,
3302                                    struct v4l2_format *f)
3303 {
3304         f->fmt.pix.field = V4L2_FIELD_NONE;
3305
3306         f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
3307                                    ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
3308         f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
3309                                     ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
3310
3311         if (f->fmt.pix.pixelformat != V4L2_PIX_FMT_HEVC &&
3312             f->fmt.pix.pixelformat != V4L2_PIX_FMT_H264)
3313                 f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
3314
3315         f->fmt.pix.bytesperline = 0;
3316         f->fmt.pix.sizeimage =
3317                 estimate_stream_size(f->fmt.pix.width, f->fmt.pix.height);
3318
3319         return 0;
3320 }
3321
3322 static int allegro_s_fmt_vid_cap(struct file *file, void *fh,
3323                                  struct v4l2_format *f)
3324 {
3325         struct allegro_channel *channel = fh_to_channel(fh);
3326         struct vb2_queue *vq;
3327         int err;
3328
3329         err = allegro_try_fmt_vid_cap(file, fh, f);
3330         if (err)
3331                 return err;
3332
3333         vq = v4l2_m2m_get_vq(channel->fh.m2m_ctx, f->type);
3334         if (!vq)
3335                 return -EINVAL;
3336         if (vb2_is_busy(vq))
3337                 return -EBUSY;
3338
3339         channel->codec = f->fmt.pix.pixelformat;
3340
3341         allegro_channel_adjust(channel);
3342
3343         return 0;
3344 }
3345
3346 static int allegro_g_fmt_vid_out(struct file *file, void *fh,
3347                                  struct v4l2_format *f)
3348 {
3349         struct allegro_channel *channel = fh_to_channel(fh);
3350
3351         f->fmt.pix.field = V4L2_FIELD_NONE;
3352
3353         f->fmt.pix.width = channel->width;
3354         f->fmt.pix.height = channel->height;
3355
3356         f->fmt.pix.colorspace = channel->colorspace;
3357         f->fmt.pix.ycbcr_enc = channel->ycbcr_enc;
3358         f->fmt.pix.quantization = channel->quantization;
3359         f->fmt.pix.xfer_func = channel->xfer_func;
3360
3361         f->fmt.pix.pixelformat = channel->pixelformat;
3362         f->fmt.pix.bytesperline = channel->stride;
3363         f->fmt.pix.sizeimage = channel->sizeimage_raw;
3364
3365         return 0;
3366 }
3367
3368 static int allegro_try_fmt_vid_out(struct file *file, void *fh,
3369                                    struct v4l2_format *f)
3370 {
3371         f->fmt.pix.field = V4L2_FIELD_NONE;
3372
3373         /*
3374          * The firmware of the Allegro codec handles the padding internally
3375          * and expects the visual frame size when configuring a channel.
3376          * Therefore, unlike other encoder drivers, this driver does not round
3377          * up the width and height to macroblock alignment and does not
3378          * implement the selection api.
3379          */
3380         f->fmt.pix.width = clamp_t(__u32, f->fmt.pix.width,
3381                                    ALLEGRO_WIDTH_MIN, ALLEGRO_WIDTH_MAX);
3382         f->fmt.pix.height = clamp_t(__u32, f->fmt.pix.height,
3383                                     ALLEGRO_HEIGHT_MIN, ALLEGRO_HEIGHT_MAX);
3384
3385         f->fmt.pix.pixelformat = V4L2_PIX_FMT_NV12;
3386         f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 32);
3387         f->fmt.pix.sizeimage =
3388                 f->fmt.pix.bytesperline * f->fmt.pix.height * 3 / 2;
3389
3390         return 0;
3391 }
3392
3393 static int allegro_s_fmt_vid_out(struct file *file, void *fh,
3394                                  struct v4l2_format *f)
3395 {
3396         struct allegro_channel *channel = fh_to_channel(fh);
3397         int err;
3398
3399         err = allegro_try_fmt_vid_out(file, fh, f);
3400         if (err)
3401                 return err;
3402
3403         channel->width = f->fmt.pix.width;
3404         channel->height = f->fmt.pix.height;
3405         channel->stride = f->fmt.pix.bytesperline;
3406         channel->sizeimage_raw = f->fmt.pix.sizeimage;
3407
3408         channel->colorspace = f->fmt.pix.colorspace;
3409         channel->ycbcr_enc = f->fmt.pix.ycbcr_enc;
3410         channel->quantization = f->fmt.pix.quantization;
3411         channel->xfer_func = f->fmt.pix.xfer_func;
3412
3413         allegro_channel_adjust(channel);
3414
3415         return 0;
3416 }
3417
3418 static int allegro_channel_cmd_stop(struct allegro_channel *channel)
3419 {
3420         if (v4l2_m2m_has_stopped(channel->fh.m2m_ctx))
3421                 allegro_channel_eos_event(channel);
3422
3423         return 0;
3424 }
3425
3426 static int allegro_channel_cmd_start(struct allegro_channel *channel)
3427 {
3428         if (v4l2_m2m_has_stopped(channel->fh.m2m_ctx))
3429                 vb2_clear_last_buffer_dequeued(&channel->fh.m2m_ctx->cap_q_ctx.q);
3430
3431         return 0;
3432 }
3433
3434 static int allegro_encoder_cmd(struct file *file, void *fh,
3435                                struct v4l2_encoder_cmd *cmd)
3436 {
3437         struct allegro_channel *channel = fh_to_channel(fh);
3438         int err;
3439
3440         err = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, cmd);
3441         if (err)
3442                 return err;
3443
3444         err = v4l2_m2m_ioctl_encoder_cmd(file, fh, cmd);
3445         if (err)
3446                 return err;
3447
3448         if (cmd->cmd == V4L2_ENC_CMD_STOP)
3449                 err = allegro_channel_cmd_stop(channel);
3450
3451         if (cmd->cmd == V4L2_ENC_CMD_START)
3452                 err = allegro_channel_cmd_start(channel);
3453
3454         return err;
3455 }
3456
3457 static int allegro_enum_framesizes(struct file *file, void *fh,
3458                                    struct v4l2_frmsizeenum *fsize)
3459 {
3460         switch (fsize->pixel_format) {
3461         case V4L2_PIX_FMT_HEVC:
3462         case V4L2_PIX_FMT_H264:
3463         case V4L2_PIX_FMT_NV12:
3464                 break;
3465         default:
3466                 return -EINVAL;
3467         }
3468
3469         if (fsize->index)
3470                 return -EINVAL;
3471
3472         fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
3473         fsize->stepwise.min_width = ALLEGRO_WIDTH_MIN;
3474         fsize->stepwise.max_width = ALLEGRO_WIDTH_MAX;
3475         fsize->stepwise.step_width = 1;
3476         fsize->stepwise.min_height = ALLEGRO_HEIGHT_MIN;
3477         fsize->stepwise.max_height = ALLEGRO_HEIGHT_MAX;
3478         fsize->stepwise.step_height = 1;
3479
3480         return 0;
3481 }
3482
3483 static int allegro_ioctl_streamon(struct file *file, void *priv,
3484                                   enum v4l2_buf_type type)
3485 {
3486         struct v4l2_fh *fh = file->private_data;
3487         struct allegro_channel *channel = fh_to_channel(fh);
3488         int err;
3489
3490         if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
3491                 err = allegro_create_channel(channel);
3492                 if (err)
3493                         return err;
3494         }
3495
3496         return v4l2_m2m_streamon(file, fh->m2m_ctx, type);
3497 }
3498
3499 static int allegro_g_parm(struct file *file, void *fh,
3500                           struct v4l2_streamparm *a)
3501 {
3502         struct allegro_channel *channel = fh_to_channel(fh);
3503         struct v4l2_fract *timeperframe;
3504
3505         if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
3506                 return -EINVAL;
3507
3508         a->parm.output.capability = V4L2_CAP_TIMEPERFRAME;
3509         timeperframe = &a->parm.output.timeperframe;
3510         timeperframe->numerator = channel->framerate.denominator;
3511         timeperframe->denominator = channel->framerate.numerator;
3512
3513         return 0;
3514 }
3515
3516 static int allegro_s_parm(struct file *file, void *fh,
3517                           struct v4l2_streamparm *a)
3518 {
3519         struct allegro_channel *channel = fh_to_channel(fh);
3520         struct v4l2_fract *timeperframe;
3521         int div;
3522
3523         if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
3524                 return -EINVAL;
3525
3526         a->parm.output.capability = V4L2_CAP_TIMEPERFRAME;
3527         timeperframe = &a->parm.output.timeperframe;
3528
3529         if (timeperframe->numerator == 0 || timeperframe->denominator == 0)
3530                 return allegro_g_parm(file, fh, a);
3531
3532         div = gcd(timeperframe->denominator, timeperframe->numerator);
3533         channel->framerate.numerator = timeperframe->denominator / div;
3534         channel->framerate.denominator = timeperframe->numerator / div;
3535
3536         return 0;
3537 }
3538
3539 static int allegro_subscribe_event(struct v4l2_fh *fh,
3540                                    const struct v4l2_event_subscription *sub)
3541 {
3542         switch (sub->type) {
3543         case V4L2_EVENT_EOS:
3544                 return v4l2_event_subscribe(fh, sub, 0, NULL);
3545         default:
3546                 return v4l2_ctrl_subscribe_event(fh, sub);
3547         }
3548 }
3549
3550 static const struct v4l2_ioctl_ops allegro_ioctl_ops = {
3551         .vidioc_querycap = allegro_querycap,
3552         .vidioc_enum_fmt_vid_cap = allegro_enum_fmt_vid,
3553         .vidioc_enum_fmt_vid_out = allegro_enum_fmt_vid,
3554         .vidioc_g_fmt_vid_cap = allegro_g_fmt_vid_cap,
3555         .vidioc_try_fmt_vid_cap = allegro_try_fmt_vid_cap,
3556         .vidioc_s_fmt_vid_cap = allegro_s_fmt_vid_cap,
3557         .vidioc_g_fmt_vid_out = allegro_g_fmt_vid_out,
3558         .vidioc_try_fmt_vid_out = allegro_try_fmt_vid_out,
3559         .vidioc_s_fmt_vid_out = allegro_s_fmt_vid_out,
3560
3561         .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
3562         .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
3563
3564         .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
3565         .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
3566         .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
3567         .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
3568         .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
3569
3570         .vidioc_streamon = allegro_ioctl_streamon,
3571         .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
3572
3573         .vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd,
3574         .vidioc_encoder_cmd = allegro_encoder_cmd,
3575         .vidioc_enum_framesizes = allegro_enum_framesizes,
3576
3577         .vidioc_g_parm          = allegro_g_parm,
3578         .vidioc_s_parm          = allegro_s_parm,
3579
3580         .vidioc_subscribe_event = allegro_subscribe_event,
3581         .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
3582 };
3583
3584 static const struct v4l2_file_operations allegro_fops = {
3585         .owner = THIS_MODULE,
3586         .open = allegro_open,
3587         .release = allegro_release,
3588         .poll = v4l2_m2m_fop_poll,
3589         .unlocked_ioctl = video_ioctl2,
3590         .mmap = v4l2_m2m_fop_mmap,
3591 };
3592
3593 static int allegro_register_device(struct allegro_dev *dev)
3594 {
3595         struct video_device *video_dev = &dev->video_dev;
3596
3597         strscpy(video_dev->name, "allegro", sizeof(video_dev->name));
3598         video_dev->fops = &allegro_fops;
3599         video_dev->ioctl_ops = &allegro_ioctl_ops;
3600         video_dev->release = video_device_release_empty;
3601         video_dev->lock = &dev->lock;
3602         video_dev->v4l2_dev = &dev->v4l2_dev;
3603         video_dev->vfl_dir = VFL_DIR_M2M;
3604         video_dev->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
3605         video_set_drvdata(video_dev, dev);
3606
3607         return video_register_device(video_dev, VFL_TYPE_VIDEO, 0);
3608 }
3609
3610 static void allegro_device_run(void *priv)
3611 {
3612         struct allegro_channel *channel = priv;
3613         struct allegro_dev *dev = channel->dev;
3614         struct vb2_v4l2_buffer *src_buf;
3615         struct vb2_v4l2_buffer *dst_buf;
3616         dma_addr_t src_y;
3617         dma_addr_t src_uv;
3618         dma_addr_t dst_addr;
3619         unsigned long dst_size;
3620         u64 src_handle;
3621         u64 dst_handle;
3622
3623         dst_buf = v4l2_m2m_dst_buf_remove(channel->fh.m2m_ctx);
3624         dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
3625         dst_size = vb2_plane_size(&dst_buf->vb2_buf, 0);
3626         dst_handle = allegro_put_buffer(channel, &channel->stream_shadow_list,
3627                                         dst_buf);
3628         allegro_mcu_send_put_stream_buffer(dev, channel, dst_addr, dst_size,
3629                                            dst_handle);
3630
3631         src_buf = v4l2_m2m_src_buf_remove(channel->fh.m2m_ctx);
3632         src_buf->sequence = channel->osequence++;
3633         src_y = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
3634         src_uv = src_y + (channel->stride * channel->height);
3635         src_handle = allegro_put_buffer(channel, &channel->source_shadow_list,
3636                                         src_buf);
3637         allegro_mcu_send_encode_frame(dev, channel, src_y, src_uv, src_handle);
3638
3639         v4l2_m2m_job_finish(dev->m2m_dev, channel->fh.m2m_ctx);
3640 }
3641
3642 static const struct v4l2_m2m_ops allegro_m2m_ops = {
3643         .device_run = allegro_device_run,
3644 };
3645
3646 static int allegro_mcu_hw_init(struct allegro_dev *dev,
3647                                const struct fw_info *info)
3648 {
3649         int err;
3650
3651         dev->mbox_command = allegro_mbox_init(dev, info->mailbox_cmd,
3652                                               info->mailbox_size);
3653         dev->mbox_status = allegro_mbox_init(dev, info->mailbox_status,
3654                                              info->mailbox_size);
3655         if (IS_ERR(dev->mbox_command) || IS_ERR(dev->mbox_status)) {
3656                 v4l2_err(&dev->v4l2_dev,
3657                          "failed to initialize mailboxes\n");
3658                 return -EIO;
3659         }
3660
3661         err = allegro_encoder_buffer_init(dev, &dev->encoder_buffer);
3662         dev->has_encoder_buffer = (err == 0);
3663         if (!dev->has_encoder_buffer)
3664                 v4l2_info(&dev->v4l2_dev, "encoder buffer not available\n");
3665
3666         allegro_mcu_enable_interrupts(dev);
3667
3668         /* The mcu sends INIT after reset. */
3669         allegro_mcu_start(dev);
3670         err = allegro_mcu_wait_for_init_timeout(dev, 5000);
3671         if (err < 0) {
3672                 v4l2_err(&dev->v4l2_dev,
3673                          "mcu did not send INIT after reset\n");
3674                 err = -EIO;
3675                 goto err_disable_interrupts;
3676         }
3677
3678         err = allegro_alloc_buffer(dev, &dev->suballocator,
3679                                    info->suballocator_size);
3680         if (err) {
3681                 v4l2_err(&dev->v4l2_dev,
3682                          "failed to allocate %zu bytes for suballocator\n",
3683                          info->suballocator_size);
3684                 goto err_reset_mcu;
3685         }
3686
3687         allegro_mcu_send_init(dev, dev->suballocator.paddr,
3688                               dev->suballocator.size);
3689         err = allegro_mcu_wait_for_init_timeout(dev, 5000);
3690         if (err < 0) {
3691                 v4l2_err(&dev->v4l2_dev,
3692                          "mcu failed to configure sub-allocator\n");
3693                 err = -EIO;
3694                 goto err_free_suballocator;
3695         }
3696
3697         return 0;
3698
3699 err_free_suballocator:
3700         allegro_free_buffer(dev, &dev->suballocator);
3701 err_reset_mcu:
3702         allegro_mcu_reset(dev);
3703 err_disable_interrupts:
3704         allegro_mcu_disable_interrupts(dev);
3705
3706         return err;
3707 }
3708
3709 static int allegro_mcu_hw_deinit(struct allegro_dev *dev)
3710 {
3711         int err;
3712
3713         err = allegro_mcu_reset(dev);
3714         if (err)
3715                 v4l2_warn(&dev->v4l2_dev,
3716                           "mcu failed to enter sleep state\n");
3717
3718         err = allegro_mcu_disable_interrupts(dev);
3719         if (err)
3720                 v4l2_warn(&dev->v4l2_dev,
3721                           "failed to disable interrupts\n");
3722
3723         allegro_free_buffer(dev, &dev->suballocator);
3724
3725         return 0;
3726 }
3727
3728 static void allegro_fw_callback(const struct firmware *fw, void *context)
3729 {
3730         struct allegro_dev *dev = context;
3731         const char *fw_codec_name = "/*(DEBLOBBED)*/";
3732         const struct firmware *fw_codec;
3733         int err;
3734
3735         if (!fw)
3736                 return;
3737
3738         v4l2_dbg(1, debug, &dev->v4l2_dev,
3739                  "requesting codec firmware '%s'\n", fw_codec_name);
3740         err = reject_firmware(&fw_codec, fw_codec_name, &dev->plat_dev->dev);
3741         if (err)
3742                 goto err_release_firmware;
3743
3744         dev->fw_info = allegro_get_firmware_info(dev, fw, fw_codec);
3745         if (!dev->fw_info) {
3746                 v4l2_err(&dev->v4l2_dev, "firmware is not supported\n");
3747                 goto err_release_firmware_codec;
3748         }
3749
3750         v4l2_info(&dev->v4l2_dev,
3751                   "using mcu firmware version '%s'\n", dev->fw_info->version);
3752
3753         pm_runtime_enable(&dev->plat_dev->dev);
3754         err = pm_runtime_resume_and_get(&dev->plat_dev->dev);
3755         if (err)
3756                 goto err_release_firmware_codec;
3757
3758         /* Ensure that the mcu is sleeping at the reset vector */
3759         err = allegro_mcu_reset(dev);
3760         if (err) {
3761                 v4l2_err(&dev->v4l2_dev, "failed to reset mcu\n");
3762                 goto err_suspend;
3763         }
3764
3765         allegro_copy_firmware(dev, fw->data, fw->size);
3766         allegro_copy_fw_codec(dev, fw_codec->data, fw_codec->size);
3767
3768         err = allegro_mcu_hw_init(dev, dev->fw_info);
3769         if (err) {
3770                 v4l2_err(&dev->v4l2_dev, "failed to initialize mcu\n");
3771                 goto err_free_fw_codec;
3772         }
3773
3774         dev->m2m_dev = v4l2_m2m_init(&allegro_m2m_ops);
3775         if (IS_ERR(dev->m2m_dev)) {
3776                 v4l2_err(&dev->v4l2_dev, "failed to init mem2mem device\n");
3777                 goto err_mcu_hw_deinit;
3778         }
3779
3780         err = allegro_register_device(dev);
3781         if (err) {
3782                 v4l2_err(&dev->v4l2_dev, "failed to register video device\n");
3783                 goto err_m2m_release;
3784         }
3785
3786         v4l2_dbg(1, debug, &dev->v4l2_dev,
3787                  "allegro codec registered as /dev/video%d\n",
3788                  dev->video_dev.num);
3789
3790         dev->initialized = true;
3791
3792         release_firmware(fw_codec);
3793         release_firmware(fw);
3794
3795         return;
3796
3797 err_m2m_release:
3798         v4l2_m2m_release(dev->m2m_dev);
3799         dev->m2m_dev = NULL;
3800 err_mcu_hw_deinit:
3801         allegro_mcu_hw_deinit(dev);
3802 err_free_fw_codec:
3803         allegro_free_fw_codec(dev);
3804 err_suspend:
3805         pm_runtime_put(&dev->plat_dev->dev);
3806         pm_runtime_disable(&dev->plat_dev->dev);
3807 err_release_firmware_codec:
3808         release_firmware(fw_codec);
3809 err_release_firmware:
3810         release_firmware(fw);
3811 }
3812
3813 static int allegro_firmware_request_nowait(struct allegro_dev *dev)
3814 {
3815         const char *fw = "/*(DEBLOBBED)*/";
3816
3817         v4l2_dbg(1, debug, &dev->v4l2_dev,
3818                  "requesting firmware '%s'\n", fw);
3819         return reject_firmware_nowait(THIS_MODULE, true, fw,
3820                                        &dev->plat_dev->dev, GFP_KERNEL, dev,
3821                                        allegro_fw_callback);
3822 }
3823
3824 static int allegro_probe(struct platform_device *pdev)
3825 {
3826         struct allegro_dev *dev;
3827         struct resource *res, *sram_res;
3828         int ret;
3829         int irq;
3830         void __iomem *regs, *sram_regs;
3831
3832         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
3833         if (!dev)
3834                 return -ENOMEM;
3835         dev->plat_dev = pdev;
3836         init_completion(&dev->init_complete);
3837         INIT_LIST_HEAD(&dev->channels);
3838
3839         mutex_init(&dev->lock);
3840
3841         dev->initialized = false;
3842
3843         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
3844         if (!res) {
3845                 dev_err(&pdev->dev,
3846                         "regs resource missing from device tree\n");
3847                 return -EINVAL;
3848         }
3849         regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3850         if (!regs) {
3851                 dev_err(&pdev->dev, "failed to map registers\n");
3852                 return -ENOMEM;
3853         }
3854         dev->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
3855                                             &allegro_regmap_config);
3856         if (IS_ERR(dev->regmap)) {
3857                 dev_err(&pdev->dev, "failed to init regmap\n");
3858                 return PTR_ERR(dev->regmap);
3859         }
3860
3861         sram_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
3862         if (!sram_res) {
3863                 dev_err(&pdev->dev,
3864                         "sram resource missing from device tree\n");
3865                 return -EINVAL;
3866         }
3867         sram_regs = devm_ioremap(&pdev->dev,
3868                                  sram_res->start,
3869                                  resource_size(sram_res));
3870         if (!sram_regs) {
3871                 dev_err(&pdev->dev, "failed to map sram\n");
3872                 return -ENOMEM;
3873         }
3874         dev->sram = devm_regmap_init_mmio(&pdev->dev, sram_regs,
3875                                           &allegro_sram_config);
3876         if (IS_ERR(dev->sram)) {
3877                 dev_err(&pdev->dev, "failed to init sram\n");
3878                 return PTR_ERR(dev->sram);
3879         }
3880
3881         dev->settings = syscon_regmap_lookup_by_compatible("xlnx,vcu-settings");
3882         if (IS_ERR(dev->settings))
3883                 dev_warn(&pdev->dev, "failed to open settings\n");
3884
3885         dev->clk_core = devm_clk_get(&pdev->dev, "core_clk");
3886         if (IS_ERR(dev->clk_core))
3887                 return PTR_ERR(dev->clk_core);
3888
3889         dev->clk_mcu = devm_clk_get(&pdev->dev, "mcu_clk");
3890         if (IS_ERR(dev->clk_mcu))
3891                 return PTR_ERR(dev->clk_mcu);
3892
3893         irq = platform_get_irq(pdev, 0);
3894         if (irq < 0)
3895                 return irq;
3896         ret = devm_request_threaded_irq(&pdev->dev, irq,
3897                                         allegro_hardirq,
3898                                         allegro_irq_thread,
3899                                         IRQF_SHARED, dev_name(&pdev->dev), dev);
3900         if (ret < 0) {
3901                 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
3902                 return ret;
3903         }
3904
3905         ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
3906         if (ret)
3907                 return ret;
3908
3909         platform_set_drvdata(pdev, dev);
3910
3911         ret = allegro_firmware_request_nowait(dev);
3912         if (ret < 0) {
3913                 v4l2_err(&dev->v4l2_dev,
3914                          "failed to request firmware: %d\n", ret);
3915                 return ret;
3916         }
3917
3918         return 0;
3919 }
3920
3921 static void allegro_remove(struct platform_device *pdev)
3922 {
3923         struct allegro_dev *dev = platform_get_drvdata(pdev);
3924
3925         if (dev->initialized) {
3926                 video_unregister_device(&dev->video_dev);
3927                 if (dev->m2m_dev)
3928                         v4l2_m2m_release(dev->m2m_dev);
3929                 allegro_mcu_hw_deinit(dev);
3930                 allegro_free_fw_codec(dev);
3931         }
3932
3933         pm_runtime_put(&dev->plat_dev->dev);
3934         pm_runtime_disable(&dev->plat_dev->dev);
3935
3936         v4l2_device_unregister(&dev->v4l2_dev);
3937 }
3938
3939 static int allegro_runtime_resume(struct device *device)
3940 {
3941         struct allegro_dev *dev = dev_get_drvdata(device);
3942         struct regmap *settings = dev->settings;
3943         unsigned int clk_mcu;
3944         unsigned int clk_core;
3945         int err;
3946
3947         if (!settings)
3948                 return -EINVAL;
3949
3950 #define MHZ_TO_HZ(freq) ((freq) * 1000 * 1000)
3951
3952         err = regmap_read(settings, VCU_CORE_CLK, &clk_core);
3953         if (err < 0)
3954                 return err;
3955         err = clk_set_rate(dev->clk_core, MHZ_TO_HZ(clk_core));
3956         if (err < 0)
3957                 return err;
3958         err = clk_prepare_enable(dev->clk_core);
3959         if (err)
3960                 return err;
3961
3962         err = regmap_read(settings, VCU_MCU_CLK, &clk_mcu);
3963         if (err < 0)
3964                 goto disable_clk_core;
3965         err = clk_set_rate(dev->clk_mcu, MHZ_TO_HZ(clk_mcu));
3966         if (err < 0)
3967                 goto disable_clk_core;
3968         err = clk_prepare_enable(dev->clk_mcu);
3969         if (err)
3970                 goto disable_clk_core;
3971
3972 #undef MHZ_TO_HZ
3973
3974         return 0;
3975
3976 disable_clk_core:
3977         clk_disable_unprepare(dev->clk_core);
3978
3979         return err;
3980 }
3981
3982 static int allegro_runtime_suspend(struct device *device)
3983 {
3984         struct allegro_dev *dev = dev_get_drvdata(device);
3985
3986         clk_disable_unprepare(dev->clk_mcu);
3987         clk_disable_unprepare(dev->clk_core);
3988
3989         return 0;
3990 }
3991
3992 static const struct of_device_id allegro_dt_ids[] = {
3993         { .compatible = "allegro,al5e-1.1" },
3994         { /* sentinel */ }
3995 };
3996
3997 MODULE_DEVICE_TABLE(of, allegro_dt_ids);
3998
3999 static const struct dev_pm_ops allegro_pm_ops = {
4000         .runtime_resume = allegro_runtime_resume,
4001         .runtime_suspend = allegro_runtime_suspend,
4002 };
4003
4004 static struct platform_driver allegro_driver = {
4005         .probe = allegro_probe,
4006         .remove_new = allegro_remove,
4007         .driver = {
4008                 .name = "allegro",
4009                 .of_match_table = allegro_dt_ids,
4010                 .pm = &allegro_pm_ops,
4011         },
4012 };
4013
4014 module_platform_driver(allegro_driver);
4015
4016 MODULE_LICENSE("GPL");
4017 MODULE_AUTHOR("Michael Tretter <kernel@pengutronix.de>");
4018 MODULE_DESCRIPTION("Allegro DVT encoder driver");