2 * ngene.h: nGene PCIe bridge driver
4 * Copyright (C) 2005-2007 Micronas
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * To obtain the license, point your browser to
17 * http://www.gnu.org/copyleft/gpl.html
23 #include <linux/types.h>
24 #include <linux/sched.h>
25 #include <linux/interrupt.h>
26 #include <linux/i2c.h>
28 #include <linux/scatterlist.h>
30 #include <linux/dvb/frontend.h>
34 #include "dvb_demux.h"
35 #include "dvb_ca_en50221.h"
36 #include "dvb_frontend.h"
37 #include "dvb_ringbuffer.h"
41 #define DEVICE_NAME "ngene"
43 #define NGENE_VID 0x18c3
44 #define NGENE_PID 0x0720
47 #define VIDEO_CAP_AVC 128
48 #define VIDEO_CAP_H264 128
49 #define VIDEO_CAP_VC1 256
50 #define VIDEO_CAP_WMV9 256
51 #define VIDEO_CAP_MPEG4 512
55 STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */
57 STREAM_AUDIOIN1, /* I2S or SPI Input */
64 SMODE_AUDIO_SPDIF = 0x20,
66 SMODE_TRANSPORT_STREAM = 0x08,
67 SMODE_AUDIO_CAPTURE = 0x04,
68 SMODE_VBI_CAPTURE = 0x02,
69 SMODE_VIDEO_CAPTURE = 0x01
72 enum STREAM_FLAG_BITS {
73 SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */
74 SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */
75 SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */
76 SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */
77 SFLAG_COLORBAR = 0x04, /* Select colorbar */
80 #define PROGRAM_ROM 0x0000
81 #define PROGRAM_SRAM 0x1000
82 #define PERIPHERALS0 0x8000
83 #define PERIPHERALS1 0x9000
84 #define SHARED_BUFFER 0xC000
86 #define HOST_TO_NGENE (SHARED_BUFFER+0x0000)
87 #define NGENE_TO_HOST (SHARED_BUFFER+0x0100)
88 #define NGENE_COMMAND (SHARED_BUFFER+0x0200)
89 #define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)
90 #define NGENE_STATUS (SHARED_BUFFER+0x0208)
91 #define NGENE_STATUS_HI (SHARED_BUFFER+0x020C)
92 #define NGENE_EVENT (SHARED_BUFFER+0x0210)
93 #define NGENE_EVENT_HI (SHARED_BUFFER+0x0214)
94 #define VARIABLES (SHARED_BUFFER+0x0210)
96 #define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260)
97 #define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264)
98 #define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268)
100 #define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800)
101 #define BUFFER_GP_RECV (SHARED_BUFFER+0x0900)
102 #define EEPROM_AREA (SHARED_BUFFER+0x0A00)
104 #define SG_V_IN_1 (SHARED_BUFFER+0x0A80)
105 #define SG_VBI_1 (SHARED_BUFFER+0x0B00)
106 #define SG_A_IN_1 (SHARED_BUFFER+0x0B80)
107 #define SG_V_IN_2 (SHARED_BUFFER+0x0C00)
108 #define SG_VBI_2 (SHARED_BUFFER+0x0C80)
109 #define SG_A_IN_2 (SHARED_BUFFER+0x0D00)
110 #define SG_V_OUT (SHARED_BUFFER+0x0D80)
111 #define SG_A_OUT2 (SHARED_BUFFER+0x0E00)
113 #define DATA_A_IN_1 (SHARED_BUFFER+0x0E80)
114 #define DATA_A_IN_2 (SHARED_BUFFER+0x0F00)
115 #define DATA_A_OUT (SHARED_BUFFER+0x0F80)
116 #define DATA_V_IN_1 (SHARED_BUFFER+0x1000)
117 #define DATA_V_IN_2 (SHARED_BUFFER+0x2000)
118 #define DATA_V_OUT (SHARED_BUFFER+0x3000)
120 #define DATA_FIFO_AREA (SHARED_BUFFER+0x1000)
122 #define TIMESTAMPS 0xA000
123 #define SCRATCHPAD 0xA080
124 #define FORCE_INT 0xA088
125 #define FORCE_NMI 0xA090
126 #define INT_STATUS 0xA0A0
128 #define DEV_VER 0x9004
130 #define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)
138 } __attribute__ ((__packed__));
140 struct SHARED_MEMORY {
153 u8 pad1[0xc260 - 0xc218];
160 u8 pad2[0xd000 - 0xc268];
162 } __attribute__ ((__packed__));
164 struct BUFFER_STREAM_RESULTS {
165 u32 Clock; /* Stream time in 100ns units */
166 u16 RemainingLines; /* Remaining lines in this field.
167 0 for complete field */
168 u8 FieldCount; /* Video field number */
169 u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,
171 u16 BlockCount; /* Audio block count (unused) */
174 } __attribute__ ((__packed__));
176 struct HW_SCATTER_GATHER_ELEMENT {
180 } __attribute__ ((__packed__));
182 struct BUFFER_HEADER {
184 struct BUFFER_STREAM_RESULTS SR;
186 u32 Number_of_entries_1;
188 u64 Address_of_first_entry_1;
190 u32 Number_of_entries_2;
192 u64 Address_of_first_entry_2;
193 } __attribute__ ((__packed__));
195 struct EVENT_BUFFER {
202 } __attribute__ ((__packed__));
204 /* Firmware commands. */
208 CMD_FWLOAD_PREPARE = 0x01,
209 CMD_FWLOAD_FINISH = 0x02,
211 CMD_I2C_WRITE = 0x04,
213 CMD_I2C_WRITE_NOSTOP = 0x05,
214 CMD_I2C_CONTINUE_WRITE = 0x06,
215 CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07,
217 CMD_DEBUG_OUTPUT = 0x09,
220 CMD_CONFIGURE_BUFFER = 0x11,
221 CMD_CONFIGURE_FREE_BUFFER = 0x12,
224 CMD_SPI_WRITE = 0x14,
227 CMD_MEM_WRITE = 0x21,
229 CMD_SFR_WRITE = 0x23,
230 CMD_IRAM_READ = 0x24,
231 CMD_IRAM_WRITE = 0x25,
232 CMD_SET_GPIO_PIN = 0x26,
233 CMD_SET_GPIO_INT = 0x27,
234 CMD_CONFIGURE_UART = 0x28,
235 CMD_WRITE_UART = 0x29,
247 } __attribute__ ((__packed__));
249 struct FW_I2C_WRITE {
250 struct FW_HEADER hdr;
253 } __attribute__ ((__packed__));
255 struct FW_I2C_CONTINUE_WRITE {
256 struct FW_HEADER hdr;
258 } __attribute__ ((__packed__));
261 struct FW_HEADER hdr;
263 u8 Data[252]; /* followed by two bytes of read data count */
264 } __attribute__ ((__packed__));
266 struct FW_SPI_WRITE {
267 struct FW_HEADER hdr;
270 } __attribute__ ((__packed__));
273 struct FW_HEADER hdr;
275 u8 Data[252]; /* followed by two bytes of read data count */
276 } __attribute__ ((__packed__));
278 struct FW_FWLOAD_PREPARE {
279 struct FW_HEADER hdr;
280 } __attribute__ ((__packed__));
282 struct FW_FWLOAD_FINISH {
283 struct FW_HEADER hdr;
284 u16 Address; /* address of final block */
286 } __attribute__ ((__packed__));
289 * Meaning of FW_STREAM_CONTROL::Mode bits:
290 * Bit 7: Loopback PEXin to PEXout using TVOut channel
292 * Bit 5: Audio select; 0=I2S, 1=SPDIF
294 * Bit 3: Enable transport stream
295 * Bit 2: Enable audio capture
296 * Bit 1: Enable ITU-Video VBI capture
297 * Bit 0: Enable ITU-Video capture
299 * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)
300 * Bit 7: continuous capture
301 * Bit 6: capture one field
302 * Bit 5: capture one frame
304 * Bit 3: starting field; 0=odd, 1=even
305 * Bit 2: sample size; 0=8-bit, 1=10-bit
306 * Bit 1: data format; 0=UYVY, 1=YUY2
307 * Bit 0: resets buffer pointers
311 SMODE_LOOPBACK = 0x80,
313 _SMODE_AUDIO_SPDIF = 0x20,
314 _SMODE_AVSYNC = 0x10,
315 _SMODE_TRANSPORT_STREAM = 0x08,
316 _SMODE_AUDIO_CAPTURE = 0x04,
317 _SMODE_VBI_CAPTURE = 0x02,
318 _SMODE_VIDEO_CAPTURE = 0x01
322 /* Meaning of FW_STREAM_CONTROL::Stream bits:
323 * Bit 3: Audio sample count: 0 = relative, 1 = absolute
324 * Bit 2: color bar select; 1=color bars, 0=CV3 decoder
325 * Bits 1-0: stream select, UVI1, UVI2, TVOUT
328 struct FW_STREAM_CONTROL {
329 struct FW_HEADER hdr;
330 u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */
331 u8 Control; /* Value written to UVI1_CTL */
332 u8 Mode; /* Controls clock source */
333 u8 SetupDataLen; /* Length of setup data, MSB=1 write
335 u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer
337 u64 Buffer_Address; /* Address of first buffer header */
338 u16 BytesPerVideoLine;
339 u16 MaxLinesPerField;
340 u16 MinLinesPerField;
343 u16 MaxVBILinesPerField;
344 u16 MinVBILinesPerField;
345 u16 SetupDataAddr; /* ngene relative address of setup data */
346 u8 SetupData[32]; /* setup data */
347 } __attribute__((__packed__));
349 #define AUDIO_BLOCK_SIZE 256
350 #define TS_BLOCK_SIZE 256
353 struct FW_HEADER hdr;
355 } __attribute__ ((__packed__));
357 struct FW_MEM_WRITE {
358 struct FW_HEADER hdr;
361 } __attribute__ ((__packed__));
363 struct FW_SFR_IRAM_READ {
364 struct FW_HEADER hdr;
366 } __attribute__ ((__packed__));
368 struct FW_SFR_IRAM_WRITE {
369 struct FW_HEADER hdr;
372 } __attribute__ ((__packed__));
374 struct FW_SET_GPIO_PIN {
375 struct FW_HEADER hdr;
377 } __attribute__ ((__packed__));
379 struct FW_SET_GPIO_INT {
380 struct FW_HEADER hdr;
382 } __attribute__ ((__packed__));
384 struct FW_SET_DEBUGMODE {
385 struct FW_HEADER hdr;
387 } __attribute__ ((__packed__));
389 struct FW_CONFIGURE_BUFFERS {
390 struct FW_HEADER hdr;
392 } __attribute__ ((__packed__));
394 enum _BUFFER_CONFIGS {
395 /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */
396 BUFFER_CONFIG_4422 = 0,
397 /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */
398 BUFFER_CONFIG_3333 = 1,
399 /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */
400 BUFFER_CONFIG_8022 = 2,
401 BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */
404 struct FW_CONFIGURE_FREE_BUFFERS {
405 struct FW_HEADER hdr;
407 u8 UVI1_BufferLength;
408 u8 UVI2_BufferLength;
410 u8 AUD1_BufferLength;
411 u8 AUD2_BufferLength;
414 } __attribute__ ((__packed__));
416 struct FW_CONFIGURE_UART {
417 struct FW_HEADER hdr;
419 } __attribute__ ((__packed__));
422 _UART_BAUDRATE_19200 = 0,
423 _UART_BAUDRATE_9600 = 1,
424 _UART_BAUDRATE_4800 = 2,
425 _UART_BAUDRATE_2400 = 3,
426 _UART_RX_ENABLE = 0x40,
427 _UART_TX_ENABLE = 0x80,
430 struct FW_WRITE_UART {
431 struct FW_HEADER hdr;
433 } __attribute__ ((__packed__));
436 struct ngene_command {
442 struct FW_HEADER hdr;
443 struct FW_I2C_WRITE I2CWrite;
444 struct FW_I2C_CONTINUE_WRITE I2CContinueWrite;
445 struct FW_I2C_READ I2CRead;
446 struct FW_STREAM_CONTROL StreamControl;
447 struct FW_FWLOAD_PREPARE FWLoadPrepare;
448 struct FW_FWLOAD_FINISH FWLoadFinish;
449 struct FW_MEM_READ MemoryRead;
450 struct FW_MEM_WRITE MemoryWrite;
451 struct FW_SFR_IRAM_READ SfrIramRead;
452 struct FW_SFR_IRAM_WRITE SfrIramWrite;
453 struct FW_SPI_WRITE SPIWrite;
454 struct FW_SPI_READ SPIRead;
455 struct FW_SET_GPIO_PIN SetGpioPin;
456 struct FW_SET_GPIO_INT SetGpioInt;
457 struct FW_SET_DEBUGMODE SetDebugMode;
458 struct FW_CONFIGURE_BUFFERS ConfigureBuffers;
459 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers;
460 struct FW_CONFIGURE_UART ConfigureUart;
461 struct FW_WRITE_UART WriteUart;
463 } __attribute__ ((__packed__));
465 #define NGENE_INTERFACE_VERSION 0x103
466 #define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */
467 #define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */
468 #define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */
469 #define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */
470 #define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page
471 Max: (1920x1080i60) */
473 #define OVERFLOW_BUFFER_SIZE (8192)
475 #define RING_SIZE_VIDEO 4
476 #define RING_SIZE_AUDIO 8
477 #define RING_SIZE_TS 8
479 #define NUM_SCATTER_GATHER_ENTRIES 8
481 #define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \
482 RING_SIZE_VIDEO * 2) + \
483 (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \
484 (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \
485 (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \
486 (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \
487 (RING_SIZE_TS * PAGE_SIZE * 4) + \
488 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)
490 #define EVENT_QUEUE_SIZE 16
492 /* Gathers the current state of a single channel. */
494 struct SBufferHeader {
495 struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */
496 struct SBufferHeader *Next;
498 struct HW_SCATTER_GATHER_ELEMENT *scList1;
500 struct HW_SCATTER_GATHER_ELEMENT *scList2;
503 /* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */
504 #define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)
520 struct SRingBufferDescriptor {
521 struct SBufferHeader *Head; /* Points to first buffer in ring buffer
523 u64 PAHead; /* Physical address of first buffer */
524 u32 MemSize; /* Memory size of allocated ring buffers
525 (needed for freeing) */
526 u32 NumBuffers; /* Number of buffers in the ring */
527 u32 Buffer1Length; /* Allocated length of Buffer 1 */
528 u32 Buffer2Length; /* Allocated length of Buffer 2 */
529 void *SCListMem; /* Memory to hold scatter gather lists for this
531 u64 PASCListMem; /* Physical address .. */
532 u32 SCListMemSize; /* Size of this memory */
535 enum STREAMMODEFLAGS {
536 StreamMode_NONE = 0, /* Stream not used */
537 StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */
538 StreamMode_TSIN = 2, /* Transport stream input (all) */
539 StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60
541 StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */
545 enum BufferExchangeFlags {
546 BEF_EVEN_FIELD = 0x00000001,
547 BEF_CONTINUATION = 0x00000002,
548 BEF_MORE_DATA = 0x00000004,
549 BEF_OVERFLOW = 0x00000008,
550 DF_SWAP32 = 0x00010000,
553 typedef void *(IBufferExchange)(void *, void *, u32, u32, u32);
555 struct MICI_STREAMINFO {
556 IBufferExchange *pExchange;
557 IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */
563 u16 nBytesPerLineVideo;
565 u16 nBytesPerLineVBI;
566 u32 CaptureLength; /* Used for audio and transport stream */
569 /****************************************************************************/
570 /* STRUCTS ******************************************************************/
571 /****************************************************************************/
573 /* sound hardware definition */
574 #define MIXER_ADDR_TVTUNER 0
575 #define MIXER_ADDR_LAST 0
577 struct ngene_channel;
579 /*struct sound chip*/
582 struct ngene_channel *chan;
583 struct snd_card *card;
585 struct snd_pcm_substream *substream;
589 spinlock_t mixer_lock;
591 int mixer_volume[MIXER_ADDR_LAST + 1][2];
592 int capture_source[MIXER_ADDR_LAST + 1][2];
596 struct ngene_overlay {
599 enum v4l2_field field;
600 struct v4l2_clip *clips;
605 struct ngene_tvnorm {
608 u16 swidth, sheight; /* scaled standard width, height */
614 struct ngene_channel *ch;
615 enum v4l2_priority prio;
619 struct videobuf_queue vbuf_q;
620 struct videobuf_queue vbi;
624 enum v4l2_buf_type type;
625 const struct ngene_format *fmt;
627 const struct ngene_format *ovfmt;
628 struct ngene_overlay ov;
632 struct ngene_channel {
633 struct device device;
634 struct i2c_adapter i2c_adapter;
643 int (*gate_ctrl)(struct dvb_frontend *, int);
645 struct dvb_frontend *fe;
646 struct dvb_frontend *fe2;
647 struct dmxdev dmxdev;
648 struct dvb_demux demux;
649 struct dvb_net dvbnet;
650 struct dmx_frontend hw_frontend;
651 struct dmx_frontend mem_frontend;
653 struct video_device *v4l_dev;
654 struct dvb_device *ci_dev;
655 struct tasklet_struct demux_tasklet;
657 struct SBufferHeader *nextBuffer;
659 enum HWSTATE HWState;
663 IBufferExchange *pBufferExchange;
664 IBufferExchange *pBufferExchange2;
666 spinlock_t state_lock;
670 u16 nBytesPerVBILine;
674 struct SRingBufferDescriptor RingBuffer;
675 struct SRingBufferDescriptor TSRingBuffer;
676 struct SRingBufferDescriptor TSIdleBuffer;
683 int (*set_tone)(struct dvb_frontend *, enum fe_sec_tone_mode);
686 /* stuff from analog driver */
689 struct mychip *mychip;
690 struct snd_card *soundcard;
695 int soundbuffisallocated;
702 struct ngene_tvnorm *tvnorms;
708 struct v4l2_prio_state prio;
709 struct ngene_vopen init;
711 struct v4l2_framebuffer fbuf;
712 struct ngene_buffer *screen; /* overlay */
713 struct list_head capture; /* video capture queue */
715 struct semaphore reslock;
723 struct device device;
724 struct i2c_adapter i2c_adapter;
727 struct dvb_ca_en50221 *en;
732 typedef void (rx_cb_t)(struct ngene *, u32, u8);
733 typedef void (tx_cb_t)(struct ngene *, u32);
737 struct pci_dev *pci_dev;
738 unsigned char __iomem *iomem;
740 /*struct i2c_adapter i2c_adapter;*/
743 u32 fw_interface_version;
746 bool cmd_timeout_workaround;
750 void *OverflowBuffer;
751 dma_addr_t PAOverflowBuffer;
752 void *FWInterfaceBuffer;
753 dma_addr_t PAFWInterfaceBuffer;
757 struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE];
758 int EventQueueOverflowCount;
759 int EventQueueOverflowFlag;
760 struct tasklet_struct event_tasklet;
761 struct EVENT_BUFFER *EventBuffer;
762 int EventQueueWriteIndex;
763 int EventQueueReadIndex;
765 wait_queue_head_t cmd_wq;
767 struct mutex cmd_mutex;
768 struct mutex stream_mutex;
769 struct semaphore pll_mutex;
770 struct mutex i2c_switch_mutex;
771 int i2c_current_channel;
775 struct dvb_adapter adapter[MAX_STREAM];
776 struct dvb_adapter *first_adapter; /* "one_adapter" modprobe opt */
777 struct ngene_channel channel[MAX_STREAM];
779 struct ngene_info *card_info;
781 tx_cb_t *TxEventNotify;
782 rx_cb_t *RxEventNotify;
784 wait_queue_head_t tx_wq;
785 wait_queue_head_t rx_wq;
786 #define UART_RBUF_LEN 4096
787 u8 uart_rbuf[UART_RBUF_LEN];
788 int uart_rp, uart_wp;
790 #define TS_FILLER 0x6f
793 #define TSOUT_BUF_SIZE (512*188*8)
794 struct dvb_ringbuffer tsout_rbuf;
797 #define TSIN_BUF_SIZE (512*188*8)
798 struct dvb_ringbuffer tsin_rbuf;
801 #define AIN_BUF_SIZE (128*1024)
802 struct dvb_ringbuffer ain_rbuf;
806 #define VIN_BUF_SIZE (4*1920*1080)
807 struct dvb_ringbuffer vin_rbuf;
809 unsigned long exp_val;
818 #define NGENE_TERRATEC 1
819 #define NGENE_SIDEWINDER 2
820 #define NGENE_RACER 3
821 #define NGENE_VIPER 4
822 #define NGENE_PYTHON 5
823 #define NGENE_VBOX_V1 6
824 #define NGENE_VBOX_V2 7
830 int io_type[MAX_STREAM];
831 #define NGENE_IO_NONE 0
832 #define NGENE_IO_TV 1
833 #define NGENE_IO_HDTV 2
834 #define NGENE_IO_TSIN 4
835 #define NGENE_IO_TSOUT 8
836 #define NGENE_IO_AIN 16
839 void *tuner_config[4];
841 int (*demod_attach[4])(struct ngene_channel *);
842 int (*tuner_attach[4])(struct ngene_channel *);
853 int (*gate_ctrl)(struct dvb_frontend *, int);
854 int (*switch_ctrl)(struct ngene_channel *, int, int);
858 struct ngene_format {
860 int fourcc; /* video4linux 2 */
861 int btformat; /* BT848_COLOR_FMT_* */
863 int btswap; /* BT848_COLOR_CTL_* */
864 int depth; /* bit/pixel */
866 int hshift, vshift; /* for planar modes */
870 #define RESOURCE_OVERLAY 1
871 #define RESOURCE_VIDEO 2
872 #define RESOURCE_VBI 4
874 struct ngene_buffer {
875 /* common v4l buffer stuff -- must be first */
876 struct videobuf_buffer vb;
879 const struct ngene_format *fmt;
887 /* Provided by ngene-core.c */
888 int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id);
889 void ngene_remove(struct pci_dev *pdev);
890 void ngene_shutdown(struct pci_dev *pdev);
891 int ngene_command(struct ngene *dev, struct ngene_command *com);
892 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level);
893 void set_transfer(struct ngene_channel *chan, int state);
894 void FillTSBuffer(void *Buffer, int Length, u32 Flags);
896 /* Provided by ngene-i2c.c */
897 int ngene_i2c_init(struct ngene *dev, int dev_nr);
899 /* Provided by ngene-dvb.c */
900 extern struct dvb_device ngene_dvbdev_ci;
901 void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
902 void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);
903 int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed);
904 int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed);
905 int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
906 int (*start_feed)(struct dvb_demux_feed *),
907 int (*stop_feed)(struct dvb_demux_feed *),
909 int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
910 struct dvb_demux *dvbdemux,
911 struct dmx_frontend *hw_frontend,
912 struct dmx_frontend *mem_frontend,
913 struct dvb_adapter *dvb_adapter);