1 // SPDX-License-Identifier: GPL-2.0-only
3 * ngene.c: nGene PCIe bridge driver
5 * Copyright (C) 2005-2007 Micronas
7 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
8 * Modifications for new nGene firmware,
9 * support for EEPROM-copying,
10 * support for new dual DVB-S2 card prototype
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
16 #include <linux/poll.h>
18 #include <asm/div64.h>
19 #include <linux/pci.h>
20 #include <linux/timer.h>
21 #include <linux/byteorder/generic.h>
22 #include <linux/firmware.h>
23 #include <linux/vmalloc.h>
27 static int one_adapter;
28 module_param(one_adapter, int, 0444);
29 MODULE_PARM_DESC(one_adapter, "Use only one adapter.");
31 static int shutdown_workaround;
32 module_param(shutdown_workaround, int, 0644);
33 MODULE_PARM_DESC(shutdown_workaround, "Activate workaround for shutdown problem with some chipsets.");
36 module_param(debug, int, 0444);
37 MODULE_PARM_DESC(debug, "Print debugging information.");
39 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
41 #define ngwriteb(dat, adr) writeb((dat), dev->iomem + (adr))
42 #define ngwritel(dat, adr) writel((dat), dev->iomem + (adr))
43 #define ngwriteb(dat, adr) writeb((dat), dev->iomem + (adr))
44 #define ngreadl(adr) readl(dev->iomem + (adr))
45 #define ngreadb(adr) readb(dev->iomem + (adr))
46 #define ngcpyto(adr, src, count) memcpy_toio(dev->iomem + (adr), (src), (count))
47 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), dev->iomem + (adr), (count))
49 /****************************************************************************/
50 /* nGene interrupt handler **************************************************/
51 /****************************************************************************/
53 static void event_tasklet(struct tasklet_struct *t)
55 struct ngene *dev = from_tasklet(dev, t, event_tasklet);
57 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) {
58 struct EVENT_BUFFER Event =
59 dev->EventQueue[dev->EventQueueReadIndex];
60 dev->EventQueueReadIndex =
61 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1);
63 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify))
64 dev->TxEventNotify(dev, Event.TimeStamp);
65 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify))
66 dev->RxEventNotify(dev, Event.TimeStamp,
71 static void demux_tasklet(struct tasklet_struct *t)
73 struct ngene_channel *chan = from_tasklet(chan, t, demux_tasklet);
74 struct device *pdev = &chan->dev->pci_dev->dev;
75 struct SBufferHeader *Cur = chan->nextBuffer;
77 spin_lock_irq(&chan->state_lock);
79 while (Cur->ngeneBuffer.SR.Flags & 0x80) {
80 if (chan->mode & NGENE_IO_TSOUT) {
81 u32 Flags = chan->DataFormatFlags;
82 if (Cur->ngeneBuffer.SR.Flags & 0x20)
83 Flags |= BEF_OVERFLOW;
84 if (chan->pBufferExchange) {
85 if (!chan->pBufferExchange(chan,
92 Clear in service flag to make sure we
93 get called on next interrupt again.
94 leave fill/empty (0x80) flag alone
95 to avoid hardware running out of
96 buffers during startup, we hold only
97 in run state ( the source may be late
101 if (chan->HWState == HWSTATE_RUN) {
102 Cur->ngeneBuffer.SR.Flags &=
105 /* Stop processing stream */
108 /* We got a valid buffer,
109 so switch to run state */
110 chan->HWState = HWSTATE_RUN;
113 dev_err(pdev, "OOPS\n");
114 if (chan->HWState == HWSTATE_RUN) {
115 Cur->ngeneBuffer.SR.Flags &= ~0x40;
116 break; /* Stop processing stream */
119 if (chan->AudioDTOUpdated) {
120 dev_info(pdev, "Update AudioDTO = %d\n",
121 chan->AudioDTOValue);
122 Cur->ngeneBuffer.SR.DTOUpdate =
124 chan->AudioDTOUpdated = 0;
127 if (chan->HWState == HWSTATE_RUN) {
128 u32 Flags = chan->DataFormatFlags;
129 IBufferExchange *exch1 = chan->pBufferExchange;
130 IBufferExchange *exch2 = chan->pBufferExchange2;
131 if (Cur->ngeneBuffer.SR.Flags & 0x01)
132 Flags |= BEF_EVEN_FIELD;
133 if (Cur->ngeneBuffer.SR.Flags & 0x20)
134 Flags |= BEF_OVERFLOW;
135 spin_unlock_irq(&chan->state_lock);
137 exch1(chan, Cur->Buffer1,
138 chan->Capture1Length,
139 Cur->ngeneBuffer.SR.Clock,
142 exch2(chan, Cur->Buffer2,
143 chan->Capture2Length,
144 Cur->ngeneBuffer.SR.Clock,
146 spin_lock_irq(&chan->state_lock);
147 } else if (chan->HWState != HWSTATE_STOP)
148 chan->HWState = HWSTATE_RUN;
150 Cur->ngeneBuffer.SR.Flags = 0x00;
153 chan->nextBuffer = Cur;
155 spin_unlock_irq(&chan->state_lock);
158 static irqreturn_t irq_handler(int irq, void *dev_id)
160 struct ngene *dev = (struct ngene *)dev_id;
161 struct device *pdev = &dev->pci_dev->dev;
163 irqreturn_t rc = IRQ_NONE;
167 if (dev->BootFirmware) {
168 icounts = ngreadl(NGENE_INT_COUNTS);
169 if (icounts != dev->icounts) {
170 ngwritel(0, FORCE_NMI);
172 wake_up(&dev->cmd_wq);
173 dev->icounts = icounts;
179 ngwritel(0, FORCE_NMI);
181 spin_lock(&dev->cmd_lock);
182 tmpCmdDoneByte = dev->CmdDoneByte;
183 if (tmpCmdDoneByte &&
185 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) {
186 dev->CmdDoneByte = NULL;
188 wake_up(&dev->cmd_wq);
191 spin_unlock(&dev->cmd_lock);
193 if (dev->EventBuffer->EventStatus & 0x80) {
195 (dev->EventQueueWriteIndex + 1) &
196 (EVENT_QUEUE_SIZE - 1);
197 if (nextWriteIndex != dev->EventQueueReadIndex) {
198 dev->EventQueue[dev->EventQueueWriteIndex] =
200 dev->EventQueueWriteIndex = nextWriteIndex;
202 dev_err(pdev, "event overflow\n");
203 dev->EventQueueOverflowCount += 1;
204 dev->EventQueueOverflowFlag = 1;
206 dev->EventBuffer->EventStatus &= ~0x80;
207 tasklet_schedule(&dev->event_tasklet);
213 spin_lock(&dev->channel[i].state_lock);
214 /* if (dev->channel[i].State>=KSSTATE_RUN) { */
215 if (dev->channel[i].nextBuffer) {
216 if ((dev->channel[i].nextBuffer->
217 ngeneBuffer.SR.Flags & 0xC0) == 0x80) {
218 dev->channel[i].nextBuffer->
219 ngeneBuffer.SR.Flags |= 0x40;
221 &dev->channel[i].demux_tasklet);
225 spin_unlock(&dev->channel[i].state_lock);
228 /* Request might have been processed by a previous call. */
232 /****************************************************************************/
233 /* nGene command interface **************************************************/
234 /****************************************************************************/
236 static void dump_command_io(struct ngene *dev)
238 struct device *pdev = &dev->pci_dev->dev;
241 ngcpyfrom(buf, HOST_TO_NGENE, 8);
242 dev_err(pdev, "host_to_ngene (%04x): %*ph\n", HOST_TO_NGENE, 8, buf);
244 ngcpyfrom(buf, NGENE_TO_HOST, 8);
245 dev_err(pdev, "ngene_to_host (%04x): %*ph\n", NGENE_TO_HOST, 8, buf);
247 b = dev->hosttongene;
248 dev_err(pdev, "dev->hosttongene (%p): %*ph\n", b, 8, b);
250 b = dev->ngenetohost;
251 dev_err(pdev, "dev->ngenetohost (%p): %*ph\n", b, 8, b);
254 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com)
256 struct device *pdev = &dev->pci_dev->dev;
262 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) {
263 dev->BootFirmware = 1;
264 dev->icounts = ngreadl(NGENE_INT_COUNTS);
265 ngwritel(0, NGENE_COMMAND);
266 ngwritel(0, NGENE_COMMAND_HI);
267 ngwritel(0, NGENE_STATUS);
268 ngwritel(0, NGENE_STATUS_HI);
269 ngwritel(0, NGENE_EVENT);
270 ngwritel(0, NGENE_EVENT_HI);
271 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) {
272 u64 fwio = dev->PAFWInterfaceBuffer;
274 ngwritel(fwio & 0xffffffff, NGENE_COMMAND);
275 ngwritel(fwio >> 32, NGENE_COMMAND_HI);
276 ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS);
277 ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI);
278 ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT);
279 ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI);
282 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2);
284 if (dev->BootFirmware)
285 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2);
287 spin_lock_irq(&dev->cmd_lock);
288 tmpCmdDoneByte = dev->ngenetohost + com->out_len;
292 dev->ngenetohost[0] = 0;
293 dev->ngenetohost[1] = 0;
294 dev->CmdDoneByte = tmpCmdDoneByte;
295 spin_unlock_irq(&dev->cmd_lock);
298 ngwritel(1, FORCE_INT);
300 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ);
302 /*ngwritel(0, FORCE_NMI);*/
304 dev_err(pdev, "Command timeout cmd=%02x prev=%02x\n",
305 com->cmd.hdr.Opcode, dev->prev_cmd);
306 dump_command_io(dev);
309 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH)
310 dev->BootFirmware = 0;
312 dev->prev_cmd = com->cmd.hdr.Opcode;
317 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len);
322 int ngene_command(struct ngene *dev, struct ngene_command *com)
326 mutex_lock(&dev->cmd_mutex);
327 result = ngene_command_mutex(dev, com);
328 mutex_unlock(&dev->cmd_mutex);
333 static int ngene_command_load_firmware(struct ngene *dev,
334 u8 *ngene_fw, u32 size)
336 #define FIRSTCHUNK (1024)
338 struct ngene_command com;
340 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE;
341 com.cmd.hdr.Length = 0;
345 ngene_command(dev, &com);
347 cleft = (size + 3) & ~3;
348 if (cleft > FIRSTCHUNK) {
349 ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK,
353 ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft);
355 memset(&com, 0, sizeof(struct ngene_command));
356 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH;
357 com.cmd.hdr.Length = 4;
358 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA;
359 com.cmd.FWLoadFinish.Length = (unsigned short)cleft;
363 return ngene_command(dev, &com);
367 static int ngene_command_config_buf(struct ngene *dev, u8 config)
369 struct ngene_command com;
371 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER;
372 com.cmd.hdr.Length = 1;
373 com.cmd.ConfigureBuffers.config = config;
377 if (ngene_command(dev, &com) < 0)
382 static int ngene_command_config_free_buf(struct ngene *dev, u8 *config)
384 struct ngene_command com;
386 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER;
387 com.cmd.hdr.Length = 6;
388 memcpy(&com.cmd.ConfigureFreeBuffers.config, config, 6);
392 if (ngene_command(dev, &com) < 0)
398 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level)
400 struct ngene_command com;
402 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN;
403 com.cmd.hdr.Length = 1;
404 com.cmd.SetGpioPin.select = select | (level << 7);
408 return ngene_command(dev, &com);
413 02000640 is sample on rising edge.
414 02000740 is sample on falling edge.
415 02000040 is ignore "valid" signal
417 0: FD_CTL1 Bit 7,6 must be 0,1
418 7 disable(fw controlled)
423 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
424 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
425 2: FD_STA is read-only. 0-sync
426 3: FD_INSYNC is number of 47s to trigger "in sync".
427 4: FD_OUTSYNC is number of 47s to trigger "out of sync".
428 5: FD_MAXBYTE1 is low-order of bytes per packet.
429 6: FD_MAXBYTE2 is high-order of bytes per packet.
430 7: Top byte is unused.
433 /****************************************************************************/
435 static u8 TSFeatureDecoderSetup[8 * 5] = {
436 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00,
437 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */
438 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */
439 0x72, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */
440 0x40, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* LGDT3303 */
443 /* Set NGENE I2S Config to 16 bit packed */
444 static u8 I2SConfiguration[] = {
445 0x00, 0x10, 0x00, 0x00,
446 0x80, 0x10, 0x00, 0x00,
449 static u8 SPDIFConfiguration[10] = {
450 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
453 /* Set NGENE I2S Config to transport stream compatible mode */
455 static u8 TS_I2SConfiguration[4] = { 0x3E, 0x18, 0x00, 0x00 };
457 static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x04, 0x00, 0x00 };
459 static u8 ITUDecoderSetup[4][16] = {
460 {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */
461 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00},
462 {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00,
463 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
464 {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */
465 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
466 {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */
467 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00},
472 * 27p50 9f 00 22 80 42 69 18 ...
473 * 27p60 93 00 22 80 82 69 1c ...
476 /* Maxbyte to 1144 (for raw data) */
477 static u8 ITUFeatureDecoderSetup[8] = {
478 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00
481 void FillTSBuffer(void *Buffer, int Length, u32 Flags)
485 memset(Buffer, TS_FILLER, Length);
487 if (Flags & DF_SWAP32)
497 static void flush_buffers(struct ngene_channel *chan)
503 spin_lock_irq(&chan->state_lock);
504 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80;
505 spin_unlock_irq(&chan->state_lock);
509 static void clear_buffers(struct ngene_channel *chan)
511 struct SBufferHeader *Cur = chan->nextBuffer;
514 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
515 if (chan->mode & NGENE_IO_TSOUT)
516 FillTSBuffer(Cur->Buffer1,
517 chan->Capture1Length,
518 chan->DataFormatFlags);
520 } while (Cur != chan->nextBuffer);
522 if (chan->mode & NGENE_IO_TSOUT) {
523 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate =
525 chan->AudioDTOUpdated = 0;
527 Cur = chan->TSIdleBuffer.Head;
530 memset(&Cur->ngeneBuffer.SR, 0,
531 sizeof(Cur->ngeneBuffer.SR));
532 FillTSBuffer(Cur->Buffer1,
533 chan->Capture1Length,
534 chan->DataFormatFlags);
536 } while (Cur != chan->TSIdleBuffer.Head);
540 static int ngene_command_stream_control(struct ngene *dev, u8 stream,
541 u8 control, u8 mode, u8 flags)
543 struct device *pdev = &dev->pci_dev->dev;
544 struct ngene_channel *chan = &dev->channel[stream];
545 struct ngene_command com;
546 u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300);
547 u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500);
548 u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700);
551 memset(&com, 0, sizeof(com));
552 com.cmd.hdr.Opcode = CMD_CONTROL;
553 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2;
554 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0);
555 if (chan->mode & NGENE_IO_TSOUT)
556 com.cmd.StreamControl.Stream |= 0x07;
557 com.cmd.StreamControl.Control = control |
558 (flags & SFLAG_ORDER_LUMA_CHROMA);
559 com.cmd.StreamControl.Mode = mode;
560 com.in_len = sizeof(struct FW_STREAM_CONTROL);
563 dev_dbg(pdev, "Stream=%02x, Control=%02x, Mode=%02x\n",
564 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control,
565 com.cmd.StreamControl.Mode);
569 if (!(control & 0x80)) {
570 spin_lock_irq(&chan->state_lock);
571 if (chan->State == KSSTATE_RUN) {
572 chan->State = KSSTATE_ACQUIRE;
573 chan->HWState = HWSTATE_STOP;
574 spin_unlock_irq(&chan->state_lock);
575 if (ngene_command(dev, &com) < 0)
577 /* clear_buffers(chan); */
581 spin_unlock_irq(&chan->state_lock);
585 if (mode & SMODE_AUDIO_CAPTURE) {
586 com.cmd.StreamControl.CaptureBlockCount =
587 chan->Capture1Length / AUDIO_BLOCK_SIZE;
588 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
589 } else if (mode & SMODE_TRANSPORT_STREAM) {
590 com.cmd.StreamControl.CaptureBlockCount =
591 chan->Capture1Length / TS_BLOCK_SIZE;
592 com.cmd.StreamControl.MaxLinesPerField =
593 chan->Capture1Length / TS_BLOCK_SIZE;
594 com.cmd.StreamControl.Buffer_Address =
595 chan->TSRingBuffer.PAHead;
596 if (chan->mode & NGENE_IO_TSOUT) {
597 com.cmd.StreamControl.BytesPerVBILine =
598 chan->Capture1Length / TS_BLOCK_SIZE;
599 com.cmd.StreamControl.Stream |= 0x07;
602 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine;
603 com.cmd.StreamControl.MaxLinesPerField = chan->nLines;
604 com.cmd.StreamControl.MinLinesPerField = 100;
605 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead;
607 if (mode & SMODE_VBI_CAPTURE) {
608 com.cmd.StreamControl.MaxVBILinesPerField =
610 com.cmd.StreamControl.MinVBILinesPerField = 0;
611 com.cmd.StreamControl.BytesPerVBILine =
612 chan->nBytesPerVBILine;
614 if (flags & SFLAG_COLORBAR)
615 com.cmd.StreamControl.Stream |= 0x04;
618 spin_lock_irq(&chan->state_lock);
619 if (mode & SMODE_AUDIO_CAPTURE) {
620 chan->nextBuffer = chan->RingBuffer.Head;
621 if (mode & SMODE_AUDIO_SPDIF) {
622 com.cmd.StreamControl.SetupDataLen =
623 sizeof(SPDIFConfiguration);
624 com.cmd.StreamControl.SetupDataAddr = BsSPI;
625 memcpy(com.cmd.StreamControl.SetupData,
626 SPDIFConfiguration, sizeof(SPDIFConfiguration));
628 com.cmd.StreamControl.SetupDataLen = 4;
629 com.cmd.StreamControl.SetupDataAddr = BsSDI;
630 memcpy(com.cmd.StreamControl.SetupData,
632 4 * dev->card_info->i2s[stream], 4);
634 } else if (mode & SMODE_TRANSPORT_STREAM) {
635 chan->nextBuffer = chan->TSRingBuffer.Head;
636 if (stream >= STREAM_AUDIOIN1) {
637 if (chan->mode & NGENE_IO_TSOUT) {
638 com.cmd.StreamControl.SetupDataLen =
639 sizeof(TS_I2SOutConfiguration);
640 com.cmd.StreamControl.SetupDataAddr = BsSDO;
641 memcpy(com.cmd.StreamControl.SetupData,
642 TS_I2SOutConfiguration,
643 sizeof(TS_I2SOutConfiguration));
645 com.cmd.StreamControl.SetupDataLen =
646 sizeof(TS_I2SConfiguration);
647 com.cmd.StreamControl.SetupDataAddr = BsSDI;
648 memcpy(com.cmd.StreamControl.SetupData,
650 sizeof(TS_I2SConfiguration));
653 com.cmd.StreamControl.SetupDataLen = 8;
654 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10;
655 memcpy(com.cmd.StreamControl.SetupData,
656 TSFeatureDecoderSetup +
657 8 * dev->card_info->tsf[stream], 8);
660 chan->nextBuffer = chan->RingBuffer.Head;
661 com.cmd.StreamControl.SetupDataLen =
662 16 + sizeof(ITUFeatureDecoderSetup);
663 com.cmd.StreamControl.SetupDataAddr = BsUVI;
664 memcpy(com.cmd.StreamControl.SetupData,
665 ITUDecoderSetup[chan->itumode], 16);
666 memcpy(com.cmd.StreamControl.SetupData + 16,
667 ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup));
670 chan->State = KSSTATE_RUN;
671 if (mode & SMODE_TRANSPORT_STREAM)
672 chan->HWState = HWSTATE_RUN;
674 chan->HWState = HWSTATE_STARTUP;
675 spin_unlock_irq(&chan->state_lock);
677 if (ngene_command(dev, &com) < 0)
683 void set_transfer(struct ngene_channel *chan, int state)
685 struct device *pdev = &chan->dev->pci_dev->dev;
686 u8 control = 0, mode = 0, flags = 0;
687 struct ngene *dev = chan->dev;
691 dev_info(pdev, "st %d\n", state);
697 dev_info(pdev, "already running\n");
701 if (!chan->running) {
702 dev_info(pdev, "already stopped\n");
707 if (dev->card_info->switch_ctrl)
708 dev->card_info->switch_ctrl(chan, 1, state ^ 1);
711 spin_lock_irq(&chan->state_lock);
713 /* dev_info(pdev, "lock=%08x\n",
715 dvb_ringbuffer_flush(&dev->tsout_rbuf);
717 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
718 chan->Capture1Length = 512 * 188;
719 mode = SMODE_TRANSPORT_STREAM;
721 if (chan->mode & NGENE_IO_TSOUT) {
722 chan->pBufferExchange = tsout_exchange;
723 /* 0x66666666 = 50MHz *2^33 /250MHz */
724 chan->AudioDTOValue = 0x80000000;
725 chan->AudioDTOUpdated = 1;
727 if (chan->mode & NGENE_IO_TSIN)
728 chan->pBufferExchange = tsin_exchange;
729 spin_unlock_irq(&chan->state_lock);
731 /* else dev_info(pdev, "lock=%08x\n",
734 mutex_lock(&dev->stream_mutex);
735 ret = ngene_command_stream_control(dev, chan->number,
736 control, mode, flags);
737 mutex_unlock(&dev->stream_mutex);
740 chan->running = state;
742 dev_err(pdev, "%s %d failed\n", __func__, state);
744 spin_lock_irq(&chan->state_lock);
745 chan->pBufferExchange = NULL;
746 dvb_ringbuffer_flush(&dev->tsout_rbuf);
747 spin_unlock_irq(&chan->state_lock);
752 /****************************************************************************/
753 /* nGene hardware init and release functions ********************************/
754 /****************************************************************************/
756 static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb)
758 struct SBufferHeader *Cur = rb->Head;
764 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) {
766 dma_free_coherent(&dev->pci_dev->dev,
767 rb->Buffer1Length, Cur->Buffer1,
768 Cur->scList1->Address);
771 dma_free_coherent(&dev->pci_dev->dev,
772 rb->Buffer2Length, Cur->Buffer2,
773 Cur->scList2->Address);
777 dma_free_coherent(&dev->pci_dev->dev, rb->SCListMemSize,
778 rb->SCListMem, rb->PASCListMem);
780 dma_free_coherent(&dev->pci_dev->dev, rb->MemSize, rb->Head,
784 static void free_idlebuffer(struct ngene *dev,
785 struct SRingBufferDescriptor *rb,
786 struct SRingBufferDescriptor *tb)
789 struct SBufferHeader *Cur = tb->Head;
793 free_ringbuffer(dev, rb);
794 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) {
797 Cur->ngeneBuffer.Address_of_first_entry_2 = 0;
798 Cur->ngeneBuffer.Number_of_entries_2 = 0;
802 static void free_common_buffers(struct ngene *dev)
805 struct ngene_channel *chan;
807 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
808 chan = &dev->channel[i];
809 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer);
810 free_ringbuffer(dev, &chan->RingBuffer);
811 free_ringbuffer(dev, &chan->TSRingBuffer);
814 if (dev->OverflowBuffer)
815 dma_free_coherent(&dev->pci_dev->dev, OVERFLOW_BUFFER_SIZE,
816 dev->OverflowBuffer, dev->PAOverflowBuffer);
818 if (dev->FWInterfaceBuffer)
819 dma_free_coherent(&dev->pci_dev->dev, 4096,
820 dev->FWInterfaceBuffer,
821 dev->PAFWInterfaceBuffer);
824 /****************************************************************************/
825 /* Ring buffer handling *****************************************************/
826 /****************************************************************************/
828 static int create_ring_buffer(struct pci_dev *pci_dev,
829 struct SRingBufferDescriptor *descr, u32 NumBuffers)
832 struct SBufferHeader *Head;
834 u32 MemSize = SIZEOF_SBufferHeader * NumBuffers;
835 u64 PARingBufferHead;
837 u64 PARingBufferNext;
838 struct SBufferHeader *Cur, *Next;
843 descr->NumBuffers = 0;
848 Head = dma_alloc_coherent(&pci_dev->dev, MemSize, &tmp, GFP_KERNEL);
849 PARingBufferHead = tmp;
854 PARingBufferCur = PARingBufferHead;
857 for (i = 0; i < NumBuffers - 1; i++) {
858 Next = (struct SBufferHeader *)
859 (((u8 *) Cur) + SIZEOF_SBufferHeader);
860 PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader;
862 Cur->ngeneBuffer.Next = PARingBufferNext;
864 PARingBufferCur = PARingBufferNext;
866 /* Last Buffer points back to first one */
868 Cur->ngeneBuffer.Next = PARingBufferHead;
871 descr->MemSize = MemSize;
872 descr->PAHead = PARingBufferHead;
873 descr->NumBuffers = NumBuffers;
878 static int AllocateRingBuffers(struct pci_dev *pci_dev,
880 struct SRingBufferDescriptor *pRingBuffer,
881 u32 Buffer1Length, u32 Buffer2Length)
885 u32 SCListMemSize = pRingBuffer->NumBuffers
886 * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) :
887 NUM_SCATTER_GATHER_ENTRIES)
888 * sizeof(struct HW_SCATTER_GATHER_ELEMENT);
891 struct HW_SCATTER_GATHER_ELEMENT *SCListEntry;
893 struct SBufferHeader *Cur;
896 if (SCListMemSize < 4096)
897 SCListMemSize = 4096;
899 SCListMem = dma_alloc_coherent(&pci_dev->dev, SCListMemSize, &tmp,
903 if (SCListMem == NULL)
906 pRingBuffer->SCListMem = SCListMem;
907 pRingBuffer->PASCListMem = PASCListMem;
908 pRingBuffer->SCListMemSize = SCListMemSize;
909 pRingBuffer->Buffer1Length = Buffer1Length;
910 pRingBuffer->Buffer2Length = Buffer2Length;
912 SCListEntry = SCListMem;
913 PASCListEntry = PASCListMem;
914 Cur = pRingBuffer->Head;
916 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) {
919 void *Buffer = dma_alloc_coherent(&pci_dev->dev,
920 Buffer1Length, &tmp, GFP_KERNEL);
926 Cur->Buffer1 = Buffer;
928 SCListEntry->Address = PABuffer;
929 SCListEntry->Length = Buffer1Length;
931 Cur->scList1 = SCListEntry;
932 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry;
933 Cur->ngeneBuffer.Number_of_entries_1 =
934 NUM_SCATTER_GATHER_ENTRIES;
937 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
939 #if NUM_SCATTER_GATHER_ENTRIES > 1
940 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) {
941 SCListEntry->Address = of;
942 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
945 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
952 Buffer = dma_alloc_coherent(&pci_dev->dev, Buffer2Length,
959 Cur->Buffer2 = Buffer;
961 SCListEntry->Address = PABuffer;
962 SCListEntry->Length = Buffer2Length;
964 Cur->scList2 = SCListEntry;
965 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry;
966 Cur->ngeneBuffer.Number_of_entries_2 =
967 NUM_SCATTER_GATHER_ENTRIES;
970 PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT);
972 #if NUM_SCATTER_GATHER_ENTRIES > 1
973 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) {
974 SCListEntry->Address = of;
975 SCListEntry->Length = OVERFLOW_BUFFER_SIZE;
978 sizeof(struct HW_SCATTER_GATHER_ELEMENT);
987 static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer,
988 struct SRingBufferDescriptor *pRingBuffer)
990 /* Copy pointer to scatter gather list in TSRingbuffer
991 structure for buffer 2
992 Load number of buffer
994 u32 n = pRingBuffer->NumBuffers;
996 /* Point to first buffer entry */
997 struct SBufferHeader *Cur = pRingBuffer->Head;
999 /* Loop through all buffer and set Buffer 2 pointers to TSIdlebuffer */
1000 for (i = 0; i < n; i++) {
1001 Cur->Buffer2 = pIdleBuffer->Head->Buffer1;
1002 Cur->scList2 = pIdleBuffer->Head->scList1;
1003 Cur->ngeneBuffer.Address_of_first_entry_2 =
1004 pIdleBuffer->Head->ngeneBuffer.
1005 Address_of_first_entry_1;
1006 Cur->ngeneBuffer.Number_of_entries_2 =
1007 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1;
1013 static u32 RingBufferSizes[MAX_STREAM] = {
1021 static u32 Buffer1Sizes[MAX_STREAM] = {
1022 MAX_VIDEO_BUFFER_SIZE,
1023 MAX_VIDEO_BUFFER_SIZE,
1024 MAX_AUDIO_BUFFER_SIZE,
1025 MAX_AUDIO_BUFFER_SIZE,
1026 MAX_AUDIO_BUFFER_SIZE
1029 static u32 Buffer2Sizes[MAX_STREAM] = {
1030 MAX_VBI_BUFFER_SIZE,
1031 MAX_VBI_BUFFER_SIZE,
1038 static int AllocCommonBuffers(struct ngene *dev)
1042 dev->FWInterfaceBuffer = dma_alloc_coherent(&dev->pci_dev->dev, 4096,
1043 &dev->PAFWInterfaceBuffer,
1045 if (!dev->FWInterfaceBuffer)
1047 dev->hosttongene = dev->FWInterfaceBuffer;
1048 dev->ngenetohost = dev->FWInterfaceBuffer + 256;
1049 dev->EventBuffer = dev->FWInterfaceBuffer + 512;
1051 dev->OverflowBuffer = dma_alloc_coherent(&dev->pci_dev->dev,
1052 OVERFLOW_BUFFER_SIZE,
1053 &dev->PAOverflowBuffer, GFP_KERNEL);
1054 if (!dev->OverflowBuffer)
1057 for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) {
1058 int type = dev->card_info->io_type[i];
1060 dev->channel[i].State = KSSTATE_STOP;
1062 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
1063 status = create_ring_buffer(dev->pci_dev,
1064 &dev->channel[i].RingBuffer,
1065 RingBufferSizes[i]);
1069 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
1070 status = AllocateRingBuffers(dev->pci_dev,
1079 } else if (type & NGENE_IO_HDTV) {
1080 status = AllocateRingBuffers(dev->pci_dev,
1085 MAX_HDTV_BUFFER_SIZE,
1092 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1094 status = create_ring_buffer(dev->pci_dev,
1096 TSRingBuffer, RING_SIZE_TS);
1100 status = AllocateRingBuffers(dev->pci_dev,
1101 dev->PAOverflowBuffer,
1104 MAX_TS_BUFFER_SIZE, 0);
1109 if (type & NGENE_IO_TSOUT) {
1110 status = create_ring_buffer(dev->pci_dev,
1115 status = AllocateRingBuffers(dev->pci_dev,
1116 dev->PAOverflowBuffer,
1119 MAX_TS_BUFFER_SIZE, 0);
1122 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer,
1123 &dev->channel[i].TSRingBuffer);
1129 static void ngene_release_buffers(struct ngene *dev)
1132 iounmap(dev->iomem);
1133 free_common_buffers(dev);
1134 vfree(dev->tsout_buf);
1135 vfree(dev->tsin_buf);
1136 vfree(dev->ain_buf);
1137 vfree(dev->vin_buf);
1141 static int ngene_get_buffers(struct ngene *dev)
1143 if (AllocCommonBuffers(dev))
1145 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) {
1146 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE);
1147 if (!dev->tsout_buf)
1149 dvb_ringbuffer_init(&dev->tsout_rbuf,
1150 dev->tsout_buf, TSOUT_BUF_SIZE);
1152 if (dev->card_info->io_type[2]&NGENE_IO_TSIN) {
1153 dev->tsin_buf = vmalloc(TSIN_BUF_SIZE);
1156 dvb_ringbuffer_init(&dev->tsin_rbuf,
1157 dev->tsin_buf, TSIN_BUF_SIZE);
1159 if (dev->card_info->io_type[2] & NGENE_IO_AIN) {
1160 dev->ain_buf = vmalloc(AIN_BUF_SIZE);
1163 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE);
1165 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) {
1166 dev->vin_buf = vmalloc(VIN_BUF_SIZE);
1169 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE);
1171 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0),
1172 pci_resource_len(dev->pci_dev, 0));
1179 static void ngene_init(struct ngene *dev)
1181 struct device *pdev = &dev->pci_dev->dev;
1184 tasklet_setup(&dev->event_tasklet, event_tasklet);
1186 memset_io(dev->iomem + 0xc000, 0x00, 0x220);
1187 memset_io(dev->iomem + 0xc400, 0x00, 0x100);
1189 for (i = 0; i < MAX_STREAM; i++) {
1190 dev->channel[i].dev = dev;
1191 dev->channel[i].number = i;
1194 dev->fw_interface_version = 0;
1196 ngwritel(0, NGENE_INT_ENABLE);
1198 dev->icounts = ngreadl(NGENE_INT_COUNTS);
1200 dev->device_version = ngreadl(DEV_VER) & 0x0f;
1201 dev_info(pdev, "Device version %d\n", dev->device_version);
1204 static int ngene_load_firm(struct ngene *dev)
1206 struct device *pdev = &dev->pci_dev->dev;
1208 const struct firmware *fw = NULL;
1213 version = dev->card_info->fw_version;
1220 fw_name = "/*(DEBLOBBED)*/";
1221 dev->cmd_timeout_workaround = true;
1225 fw_name = "/*(DEBLOBBED)*/";
1226 dev->cmd_timeout_workaround = true;
1230 fw_name = "/*(DEBLOBBED)*/";
1231 dev->cmd_timeout_workaround = true;
1235 fw_name = "/*(DEBLOBBED)*/";
1239 if (reject_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) {
1240 dev_err(pdev, "Could not load firmware file %s.\n", fw_name);
1241 dev_info(pdev, "Copy %s to your hotplug directory!\n",
1247 if (size != fw->size) {
1248 dev_err(pdev, "Firmware %s has invalid size!", fw_name);
1251 dev_info(pdev, "Loading firmware file %s.\n", fw_name);
1252 ngene_fw = (u8 *) fw->data;
1253 err = ngene_command_load_firmware(dev, ngene_fw, size);
1256 release_firmware(fw);
1261 static void ngene_stop(struct ngene *dev)
1263 mutex_destroy(&dev->cmd_mutex);
1264 i2c_del_adapter(&(dev->channel[0].i2c_adapter));
1265 i2c_del_adapter(&(dev->channel[1].i2c_adapter));
1266 ngwritel(0, NGENE_INT_ENABLE);
1267 ngwritel(0, NGENE_COMMAND);
1268 ngwritel(0, NGENE_COMMAND_HI);
1269 ngwritel(0, NGENE_STATUS);
1270 ngwritel(0, NGENE_STATUS_HI);
1271 ngwritel(0, NGENE_EVENT);
1272 ngwritel(0, NGENE_EVENT_HI);
1273 free_irq(dev->pci_dev->irq, dev);
1274 #ifdef CONFIG_PCI_MSI
1275 if (dev->msi_enabled)
1276 pci_disable_msi(dev->pci_dev);
1280 static int ngene_buffer_config(struct ngene *dev)
1284 if (dev->card_info->fw_version >= 17) {
1285 u8 tsin12_config[6] = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 };
1286 u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 };
1287 u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 };
1288 u8 *bconf = tsin12_config;
1290 if (dev->card_info->io_type[2]&NGENE_IO_TSIN &&
1291 dev->card_info->io_type[3]&NGENE_IO_TSIN) {
1292 bconf = tsin1234_config;
1293 if (dev->card_info->io_type[4]&NGENE_IO_TSOUT &&
1295 bconf = tsio1235_config;
1297 stat = ngene_command_config_free_buf(dev, bconf);
1299 int bconf = BUFFER_CONFIG_4422;
1301 if (dev->card_info->io_type[3] == NGENE_IO_TSIN)
1302 bconf = BUFFER_CONFIG_3333;
1303 stat = ngene_command_config_buf(dev, bconf);
1309 static int ngene_start(struct ngene *dev)
1314 pci_set_master(dev->pci_dev);
1317 stat = request_irq(dev->pci_dev->irq, irq_handler,
1318 IRQF_SHARED, "nGene",
1323 init_waitqueue_head(&dev->cmd_wq);
1324 init_waitqueue_head(&dev->tx_wq);
1325 init_waitqueue_head(&dev->rx_wq);
1326 mutex_init(&dev->cmd_mutex);
1327 mutex_init(&dev->stream_mutex);
1328 sema_init(&dev->pll_mutex, 1);
1329 mutex_init(&dev->i2c_switch_mutex);
1330 spin_lock_init(&dev->cmd_lock);
1331 for (i = 0; i < MAX_STREAM; i++)
1332 spin_lock_init(&dev->channel[i].state_lock);
1333 ngwritel(1, TIMESTAMPS);
1335 ngwritel(1, NGENE_INT_ENABLE);
1337 stat = ngene_load_firm(dev);
1341 #ifdef CONFIG_PCI_MSI
1342 /* enable MSI if kernel and card support it */
1343 if (pci_msi_enabled() && dev->card_info->msi_supported) {
1344 struct device *pdev = &dev->pci_dev->dev;
1345 unsigned long flags;
1347 ngwritel(0, NGENE_INT_ENABLE);
1348 free_irq(dev->pci_dev->irq, dev);
1349 stat = pci_enable_msi(dev->pci_dev);
1351 dev_info(pdev, "MSI not available\n");
1352 flags = IRQF_SHARED;
1355 dev->msi_enabled = true;
1357 stat = request_irq(dev->pci_dev->irq, irq_handler,
1358 flags, "nGene", dev);
1361 ngwritel(1, NGENE_INT_ENABLE);
1365 stat = ngene_i2c_init(dev, 0);
1369 stat = ngene_i2c_init(dev, 1);
1376 ngwritel(0, NGENE_INT_ENABLE);
1377 free_irq(dev->pci_dev->irq, dev);
1378 #ifdef CONFIG_PCI_MSI
1380 if (dev->msi_enabled)
1381 pci_disable_msi(dev->pci_dev);
1386 /****************************************************************************/
1387 /****************************************************************************/
1388 /****************************************************************************/
1390 static void release_channel(struct ngene_channel *chan)
1392 struct dvb_demux *dvbdemux = &chan->demux;
1393 struct ngene *dev = chan->dev;
1396 set_transfer(chan, 0);
1398 tasklet_kill(&chan->demux_tasklet);
1401 dvb_unregister_device(chan->ci_dev);
1402 chan->ci_dev = NULL;
1406 dvb_unregister_frontend(chan->fe2);
1409 dvb_unregister_frontend(chan->fe);
1411 /* release I2C client (tuner) if needed */
1412 if (chan->i2c_client_fe) {
1413 dvb_module_release(chan->i2c_client[0]);
1414 chan->i2c_client[0] = NULL;
1417 dvb_frontend_detach(chan->fe);
1421 if (chan->has_demux) {
1422 dvb_net_release(&chan->dvbnet);
1423 dvbdemux->dmx.close(&dvbdemux->dmx);
1424 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1425 &chan->hw_frontend);
1426 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx,
1427 &chan->mem_frontend);
1428 dvb_dmxdev_release(&chan->dmxdev);
1429 dvb_dmx_release(&chan->demux);
1430 chan->has_demux = false;
1433 if (chan->has_adapter) {
1434 dvb_unregister_adapter(&dev->adapter[chan->number]);
1435 chan->has_adapter = false;
1439 static int init_channel(struct ngene_channel *chan)
1441 int ret = 0, nr = chan->number;
1442 struct dvb_adapter *adapter = NULL;
1443 struct dvb_demux *dvbdemux = &chan->demux;
1444 struct ngene *dev = chan->dev;
1445 struct ngene_info *ni = dev->card_info;
1446 int io = ni->io_type[nr];
1448 tasklet_setup(&chan->demux_tasklet, demux_tasklet);
1451 chan->mode = chan->type; /* for now only one mode */
1452 chan->i2c_client_fe = 0; /* be sure this is set to zero */
1454 if (io & NGENE_IO_TSIN) {
1456 if (ni->demod_attach[nr]) {
1457 ret = ni->demod_attach[nr](chan);
1461 if (chan->fe && ni->tuner_attach[nr]) {
1462 ret = ni->tuner_attach[nr](chan);
1468 if (!dev->ci.en && (io & NGENE_IO_TSOUT))
1471 if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
1472 if (nr >= STREAM_AUDIOIN1)
1473 chan->DataFormatFlags = DF_SWAP32;
1475 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) {
1476 adapter = &dev->adapter[nr];
1477 ret = dvb_register_adapter(adapter, "nGene",
1479 &chan->dev->pci_dev->dev,
1483 if (dev->first_adapter == NULL)
1484 dev->first_adapter = adapter;
1485 chan->has_adapter = true;
1487 adapter = dev->first_adapter;
1490 if (dev->ci.en && (io & NGENE_IO_TSOUT)) {
1491 dvb_ca_en50221_init(adapter, dev->ci.en, 0, 1);
1492 set_transfer(chan, 1);
1493 chan->dev->channel[2].DataFormatFlags = DF_SWAP32;
1494 set_transfer(&chan->dev->channel[2], 1);
1495 dvb_register_device(adapter, &chan->ci_dev,
1496 &ngene_dvbdev_ci, (void *) chan,
1503 if (dvb_register_frontend(adapter, chan->fe) < 0)
1505 chan->has_demux = true;
1508 if (dvb_register_frontend(adapter, chan->fe2) < 0)
1511 chan->fe2->tuner_priv = chan->fe->tuner_priv;
1512 memcpy(&chan->fe2->ops.tuner_ops,
1513 &chan->fe->ops.tuner_ops,
1514 sizeof(struct dvb_tuner_ops));
1518 if (chan->has_demux) {
1519 ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
1521 ngene_stop_feed, chan);
1522 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux,
1524 &chan->mem_frontend, adapter);
1525 ret = dvb_net_init(adapter, &chan->dvbnet, &chan->demux.dmx);
1532 dvb_frontend_detach(chan->fe);
1535 release_channel(chan);
1539 static int init_channels(struct ngene *dev)
1543 for (i = 0; i < MAX_STREAM; i++) {
1544 dev->channel[i].number = i;
1545 if (init_channel(&dev->channel[i]) < 0) {
1546 for (j = i - 1; j >= 0; j--)
1547 release_channel(&dev->channel[j]);
1554 static const struct cxd2099_cfg cxd_cfgtmpl = {
1560 static void cxd_attach(struct ngene *dev)
1562 struct device *pdev = &dev->pci_dev->dev;
1563 struct ngene_ci *ci = &dev->ci;
1564 struct cxd2099_cfg cxd_cfg = cxd_cfgtmpl;
1565 struct i2c_client *client;
1569 /* check for CXD2099AR presence before attaching */
1570 ret = ngene_port_has_cxd2099(&dev->channel[0].i2c_adapter, &type);
1572 dev_dbg(pdev, "No CXD2099AR found\n");
1577 dev_warn(pdev, "CXD2099AR is uninitialized!\n");
1581 cxd_cfg.en = &ci->en;
1582 client = dvb_module_probe("cxd2099", NULL,
1583 &dev->channel[0].i2c_adapter,
1589 dev->channel[0].i2c_client[0] = client;
1593 dev_err(pdev, "CXD2099AR attach failed\n");
1597 static void cxd_detach(struct ngene *dev)
1599 struct ngene_ci *ci = &dev->ci;
1601 dvb_ca_en50221_release(ci->en);
1603 dvb_module_release(dev->channel[0].i2c_client[0]);
1604 dev->channel[0].i2c_client[0] = NULL;
1608 /***********************************/
1609 /* workaround for shutdown failure */
1610 /***********************************/
1612 static void ngene_unlink(struct ngene *dev)
1614 struct ngene_command com;
1616 com.cmd.hdr.Opcode = CMD_MEM_WRITE;
1617 com.cmd.hdr.Length = 3;
1618 com.cmd.MemoryWrite.address = 0x910c;
1619 com.cmd.MemoryWrite.data = 0xff;
1623 mutex_lock(&dev->cmd_mutex);
1624 ngwritel(0, NGENE_INT_ENABLE);
1625 ngene_command_mutex(dev, &com);
1626 mutex_unlock(&dev->cmd_mutex);
1629 void ngene_shutdown(struct pci_dev *pdev)
1631 struct ngene *dev = pci_get_drvdata(pdev);
1633 if (!dev || !shutdown_workaround)
1636 dev_info(&pdev->dev, "shutdown workaround...\n");
1638 pci_disable_device(pdev);
1641 /****************************************************************************/
1642 /* device probe/remove calls ************************************************/
1643 /****************************************************************************/
1645 void ngene_remove(struct pci_dev *pdev)
1647 struct ngene *dev = pci_get_drvdata(pdev);
1650 tasklet_kill(&dev->event_tasklet);
1651 for (i = MAX_STREAM - 1; i >= 0; i--)
1652 release_channel(&dev->channel[i]);
1656 ngene_release_buffers(dev);
1657 pci_disable_device(pdev);
1660 int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
1665 if (pci_enable_device(pci_dev) < 0)
1668 dev = vzalloc(sizeof(struct ngene));
1674 dev->pci_dev = pci_dev;
1675 dev->card_info = (struct ngene_info *)id->driver_data;
1676 dev_info(&pci_dev->dev, "Found %s\n", dev->card_info->name);
1678 pci_set_drvdata(pci_dev, dev);
1680 /* Alloc buffers and start nGene */
1681 stat = ngene_get_buffers(dev);
1684 stat = ngene_start(dev);
1690 stat = ngene_buffer_config(dev);
1695 dev->i2c_current_bus = -1;
1697 /* Register DVB adapters and devices for both channels */
1698 stat = init_channels(dev);
1707 ngene_release_buffers(dev);
1709 pci_disable_device(pci_dev);