2 * device driver for Conexant 2388x based TV cards
5 * (c) 2003 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
7 * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
9 * - video_ioctl2 conversion
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/slab.h>
30 #include <linux/kmod.h>
31 #include <linux/sound.h>
32 #include <linux/interrupt.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
35 #include <linux/videodev2.h>
36 #include <linux/mutex.h>
38 #include <media/v4l2-common.h>
39 #include <media/v4l2-ioctl.h>
41 MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards");
42 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
43 MODULE_LICENSE("GPL");
45 /* ------------------------------------------------------------------ */
47 unsigned int cx88_core_debug;
48 module_param_named(core_debug, cx88_core_debug, int, 0644);
49 MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
51 static unsigned int nicam;
52 module_param(nicam, int, 0644);
53 MODULE_PARM_DESC(nicam, "tv audio is nicam");
55 static unsigned int nocomb;
56 module_param(nocomb, int, 0644);
57 MODULE_PARM_DESC(nocomb, "disable comb filter");
59 #define dprintk0(fmt, arg...) \
60 printk(KERN_DEBUG pr_fmt("%s: core:" fmt), \
63 #define dprintk(level, fmt, arg...) do { \
64 if (cx88_core_debug >= level) \
65 printk(KERN_DEBUG pr_fmt("%s: core:" fmt), \
69 static unsigned int cx88_devcount;
70 static LIST_HEAD(cx88_devlist);
71 static DEFINE_MUTEX(devlist);
73 #define NO_SYNC_LINE (-1U)
76 * @lpi: lines per IRQ, or 0 to not generate irqs. Note: IRQ to be
77 * generated _after_ lpi lines are transferred.
79 static __le32 *cx88_risc_field(__le32 *rp, struct scatterlist *sglist,
80 unsigned int offset, u32 sync_line,
81 unsigned int bpl, unsigned int padding,
82 unsigned int lines, unsigned int lpi, bool jump)
84 struct scatterlist *sg;
85 unsigned int line, todo, sol;
88 (*rp++) = cpu_to_le32(RISC_JUMP);
92 /* sync instruction */
93 if (sync_line != NO_SYNC_LINE)
94 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
98 for (line = 0; line < lines; line++) {
99 while (offset && offset >= sg_dma_len(sg)) {
100 offset -= sg_dma_len(sg);
103 if (lpi && line > 0 && !(line % lpi))
104 sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
107 if (bpl <= sg_dma_len(sg) - offset) {
108 /* fits into current chunk */
109 *(rp++) = cpu_to_le32(RISC_WRITE | sol |
111 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
114 /* scanline needs to be split */
116 *(rp++) = cpu_to_le32(RISC_WRITE | sol |
117 (sg_dma_len(sg) - offset));
118 *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
119 todo -= (sg_dma_len(sg) - offset);
122 while (todo > sg_dma_len(sg)) {
123 *(rp++) = cpu_to_le32(RISC_WRITE |
125 *(rp++) = cpu_to_le32(sg_dma_address(sg));
126 todo -= sg_dma_len(sg);
129 *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
130 *(rp++) = cpu_to_le32(sg_dma_address(sg));
139 int cx88_risc_buffer(struct pci_dev *pci, struct cx88_riscmem *risc,
140 struct scatterlist *sglist,
141 unsigned int top_offset, unsigned int bottom_offset,
142 unsigned int bpl, unsigned int padding, unsigned int lines)
144 u32 instructions, fields;
148 if (top_offset != UNSET)
150 if (bottom_offset != UNSET)
154 * estimate risc mem: worst case is one write per page border +
155 * one write per scan line + syncs + jump (all 2 dwords). Padding
156 * can cause next bpl to start close to a page border. First DMA
157 * region may be smaller than PAGE_SIZE
159 instructions = fields * (1 + ((bpl + padding) * lines) /
162 risc->size = instructions * 8;
164 risc->cpu = pci_zalloc_consistent(pci, risc->size, &risc->dma);
168 /* write risc instructions */
170 if (top_offset != UNSET)
171 rp = cx88_risc_field(rp, sglist, top_offset, 0,
172 bpl, padding, lines, 0, true);
173 if (bottom_offset != UNSET)
174 rp = cx88_risc_field(rp, sglist, bottom_offset, 0x200,
175 bpl, padding, lines, 0,
176 top_offset == UNSET);
178 /* save pointer to jmp instruction address */
180 WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
183 EXPORT_SYMBOL(cx88_risc_buffer);
185 int cx88_risc_databuffer(struct pci_dev *pci, struct cx88_riscmem *risc,
186 struct scatterlist *sglist, unsigned int bpl,
187 unsigned int lines, unsigned int lpi)
193 * estimate risc mem: worst case is one write per page border +
194 * one write per scan line + syncs + jump (all 2 dwords). Here
195 * there is no padding and no sync. First DMA region may be smaller
198 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
200 risc->size = instructions * 8;
202 risc->cpu = pci_zalloc_consistent(pci, risc->size, &risc->dma);
206 /* write risc instructions */
208 rp = cx88_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0,
211 /* save pointer to jmp instruction address */
213 WARN_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
216 EXPORT_SYMBOL(cx88_risc_databuffer);
219 * our SRAM memory layout
223 * we are going to put all thr risc programs into host memory, so we
224 * can use the whole SDRAM for the DMA fifos. To simplify things, we
225 * use a static memory layout. That surely will waste memory in case
226 * we don't use all DMA channels at the same time (which will be the
227 * case most of the time). But that still gives us enough FIFO space
228 * to be able to deal with insane long pci latencies ...
230 * FIFO space allocations:
231 * channel 21 (y video) - 10.0k
232 * channel 22 (u video) - 2.0k
233 * channel 23 (v video) - 2.0k
234 * channel 24 (vbi) - 4.0k
235 * channels 25+26 (audio) - 4.0k
236 * channel 28 (mpeg) - 4.0k
237 * channel 27 (audio rds)- 3.0k
240 * Every channel has 160 bytes control data (64 bytes instruction
241 * queue and 6 CDT entries), which is close to 2k total.
244 * 0x0000 - 0x03ff CMDs / reserved
245 * 0x0400 - 0x0bff instruction queues + CDs
249 const struct sram_channel cx88_sram_channels[] = {
251 .name = "video y / packed",
252 .cmds_start = 0x180040,
253 .ctrl_start = 0x180400,
254 .cdt = 0x180400 + 64,
255 .fifo_start = 0x180c00,
256 .fifo_size = 0x002800,
257 .ptr1_reg = MO_DMA21_PTR1,
258 .ptr2_reg = MO_DMA21_PTR2,
259 .cnt1_reg = MO_DMA21_CNT1,
260 .cnt2_reg = MO_DMA21_CNT2,
264 .cmds_start = 0x180080,
265 .ctrl_start = 0x1804a0,
266 .cdt = 0x1804a0 + 64,
267 .fifo_start = 0x183400,
268 .fifo_size = 0x000800,
269 .ptr1_reg = MO_DMA22_PTR1,
270 .ptr2_reg = MO_DMA22_PTR2,
271 .cnt1_reg = MO_DMA22_CNT1,
272 .cnt2_reg = MO_DMA22_CNT2,
276 .cmds_start = 0x1800c0,
277 .ctrl_start = 0x180540,
278 .cdt = 0x180540 + 64,
279 .fifo_start = 0x183c00,
280 .fifo_size = 0x000800,
281 .ptr1_reg = MO_DMA23_PTR1,
282 .ptr2_reg = MO_DMA23_PTR2,
283 .cnt1_reg = MO_DMA23_CNT1,
284 .cnt2_reg = MO_DMA23_CNT2,
288 .cmds_start = 0x180100,
289 .ctrl_start = 0x1805e0,
290 .cdt = 0x1805e0 + 64,
291 .fifo_start = 0x184400,
292 .fifo_size = 0x001000,
293 .ptr1_reg = MO_DMA24_PTR1,
294 .ptr2_reg = MO_DMA24_PTR2,
295 .cnt1_reg = MO_DMA24_CNT1,
296 .cnt2_reg = MO_DMA24_CNT2,
299 .name = "audio from",
300 .cmds_start = 0x180140,
301 .ctrl_start = 0x180680,
302 .cdt = 0x180680 + 64,
303 .fifo_start = 0x185400,
304 .fifo_size = 0x001000,
305 .ptr1_reg = MO_DMA25_PTR1,
306 .ptr2_reg = MO_DMA25_PTR2,
307 .cnt1_reg = MO_DMA25_CNT1,
308 .cnt2_reg = MO_DMA25_CNT2,
312 .cmds_start = 0x180180,
313 .ctrl_start = 0x180720,
314 .cdt = 0x180680 + 64, /* same as audio IN */
315 .fifo_start = 0x185400, /* same as audio IN */
316 .fifo_size = 0x001000, /* same as audio IN */
317 .ptr1_reg = MO_DMA26_PTR1,
318 .ptr2_reg = MO_DMA26_PTR2,
319 .cnt1_reg = MO_DMA26_CNT1,
320 .cnt2_reg = MO_DMA26_CNT2,
324 .cmds_start = 0x180200,
325 .ctrl_start = 0x1807C0,
326 .cdt = 0x1807C0 + 64,
327 .fifo_start = 0x186400,
328 .fifo_size = 0x001000,
329 .ptr1_reg = MO_DMA28_PTR1,
330 .ptr2_reg = MO_DMA28_PTR2,
331 .cnt1_reg = MO_DMA28_CNT1,
332 .cnt2_reg = MO_DMA28_CNT2,
336 .cmds_start = 0x1801C0,
337 .ctrl_start = 0x180860,
338 .cdt = 0x180860 + 64,
339 .fifo_start = 0x187400,
340 .fifo_size = 0x000C00,
341 .ptr1_reg = MO_DMA27_PTR1,
342 .ptr2_reg = MO_DMA27_PTR2,
343 .cnt1_reg = MO_DMA27_CNT1,
344 .cnt2_reg = MO_DMA27_CNT2,
347 EXPORT_SYMBOL(cx88_sram_channels);
349 int cx88_sram_channel_setup(struct cx88_core *core,
350 const struct sram_channel *ch,
351 unsigned int bpl, u32 risc)
353 unsigned int i, lines;
356 bpl = (bpl + 7) & ~7; /* alignment */
358 lines = ch->fifo_size / bpl;
364 for (i = 0; i < lines; i++)
365 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
368 cx_write(ch->cmds_start + 0, risc);
369 cx_write(ch->cmds_start + 4, cdt);
370 cx_write(ch->cmds_start + 8, (lines * 16) >> 3);
371 cx_write(ch->cmds_start + 12, ch->ctrl_start);
372 cx_write(ch->cmds_start + 16, 64 >> 2);
373 for (i = 20; i < 64; i += 4)
374 cx_write(ch->cmds_start + i, 0);
377 cx_write(ch->ptr1_reg, ch->fifo_start);
378 cx_write(ch->ptr2_reg, cdt);
379 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
380 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
382 dprintk(2, "sram setup %s: bpl=%d lines=%d\n", ch->name, bpl, lines);
385 EXPORT_SYMBOL(cx88_sram_channel_setup);
387 /* ------------------------------------------------------------------ */
388 /* debug helper code */
390 static int cx88_risc_decode(u32 risc)
392 static const char * const instr[16] = {
393 [RISC_SYNC >> 28] = "sync",
394 [RISC_WRITE >> 28] = "write",
395 [RISC_WRITEC >> 28] = "writec",
396 [RISC_READ >> 28] = "read",
397 [RISC_READC >> 28] = "readc",
398 [RISC_JUMP >> 28] = "jump",
399 [RISC_SKIP >> 28] = "skip",
400 [RISC_WRITERM >> 28] = "writerm",
401 [RISC_WRITECM >> 28] = "writecm",
402 [RISC_WRITECR >> 28] = "writecr",
404 static int const incr[16] = {
405 [RISC_WRITE >> 28] = 2,
406 [RISC_JUMP >> 28] = 2,
407 [RISC_WRITERM >> 28] = 3,
408 [RISC_WRITECM >> 28] = 3,
409 [RISC_WRITECR >> 28] = 4,
411 static const char * const bits[] = {
412 "12", "13", "14", "resync",
413 "cnt0", "cnt1", "18", "19",
414 "20", "21", "22", "23",
415 "irq1", "irq2", "eol", "sol",
419 dprintk0("0x%08x [ %s", risc,
420 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
421 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
422 if (risc & (1 << (i + 12)))
423 pr_cont(" %s", bits[i]);
424 pr_cont(" count=%d ]\n", risc & 0xfff);
425 return incr[risc >> 28] ? incr[risc >> 28] : 1;
428 void cx88_sram_channel_dump(struct cx88_core *core,
429 const struct sram_channel *ch)
431 static const char * const name[] = {
445 unsigned int i, j, n;
447 dprintk0("%s - dma channel status dump\n", ch->name);
448 for (i = 0; i < ARRAY_SIZE(name); i++)
449 dprintk0(" cmds: %-12s: 0x%08x\n",
450 name[i], cx_read(ch->cmds_start + 4 * i));
451 for (n = 1, i = 0; i < 4; i++) {
452 risc = cx_read(ch->cmds_start + 4 * (i + 11));
453 pr_cont(" risc%d: ", i);
455 pr_cont("0x%08x [ arg #%d ]\n", risc, n);
457 n = cx88_risc_decode(risc);
459 for (i = 0; i < 16; i += n) {
460 risc = cx_read(ch->ctrl_start + 4 * i);
461 dprintk0(" iq %x: ", i);
462 n = cx88_risc_decode(risc);
463 for (j = 1; j < n; j++) {
464 risc = cx_read(ch->ctrl_start + 4 * (i + j));
465 pr_cont(" iq %x: 0x%08x [ arg #%d ]\n",
470 dprintk0("fifo: 0x%08x -> 0x%x\n",
471 ch->fifo_start, ch->fifo_start + ch->fifo_size);
472 dprintk0("ctrl: 0x%08x -> 0x%x\n",
473 ch->ctrl_start, ch->ctrl_start + 6 * 16);
474 dprintk0(" ptr1_reg: 0x%08x\n", cx_read(ch->ptr1_reg));
475 dprintk0(" ptr2_reg: 0x%08x\n", cx_read(ch->ptr2_reg));
476 dprintk0(" cnt1_reg: 0x%08x\n", cx_read(ch->cnt1_reg));
477 dprintk0(" cnt2_reg: 0x%08x\n", cx_read(ch->cnt2_reg));
479 EXPORT_SYMBOL(cx88_sram_channel_dump);
481 static const char *cx88_pci_irqs[32] = {
482 "vid", "aud", "ts", "vip", "hst", "5", "6", "tm1",
483 "src_dma", "dst_dma", "risc_rd_err", "risc_wr_err",
484 "brdg_err", "src_dma_err", "dst_dma_err", "ipb_dma_err",
485 "i2c", "i2c_rack", "ir_smp", "gpio0", "gpio1"
488 void cx88_print_irqbits(const char *tag, const char *strings[],
489 int len, u32 bits, u32 mask)
493 dprintk0("%s [0x%x]", tag, bits);
494 for (i = 0; i < len; i++) {
495 if (!(bits & (1 << i)))
498 pr_cont(" %s", strings[i]);
501 if (!(mask & (1 << i)))
507 EXPORT_SYMBOL(cx88_print_irqbits);
509 /* ------------------------------------------------------------------ */
511 int cx88_core_irq(struct cx88_core *core, u32 status)
515 if (status & PCI_INT_IR_SMPINT) {
520 cx88_print_irqbits("irq pci",
521 cx88_pci_irqs, ARRAY_SIZE(cx88_pci_irqs),
522 status, core->pci_irqmask);
525 EXPORT_SYMBOL(cx88_core_irq);
527 void cx88_wakeup(struct cx88_core *core,
528 struct cx88_dmaqueue *q, u32 count)
530 struct cx88_buffer *buf;
532 buf = list_entry(q->active.next,
533 struct cx88_buffer, list);
534 buf->vb.vb2_buf.timestamp = ktime_get_ns();
535 buf->vb.field = core->field;
536 buf->vb.sequence = q->count++;
537 list_del(&buf->list);
538 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
540 EXPORT_SYMBOL(cx88_wakeup);
542 void cx88_shutdown(struct cx88_core *core)
544 /* disable RISC controller + IRQs */
545 cx_write(MO_DEV_CNTRL2, 0);
547 /* stop dma transfers */
548 cx_write(MO_VID_DMACNTRL, 0x0);
549 cx_write(MO_AUD_DMACNTRL, 0x0);
550 cx_write(MO_TS_DMACNTRL, 0x0);
551 cx_write(MO_VIP_DMACNTRL, 0x0);
552 cx_write(MO_GPHST_DMACNTRL, 0x0);
554 /* stop interrupts */
555 cx_write(MO_PCI_INTMSK, 0x0);
556 cx_write(MO_VID_INTMSK, 0x0);
557 cx_write(MO_AUD_INTMSK, 0x0);
558 cx_write(MO_TS_INTMSK, 0x0);
559 cx_write(MO_VIP_INTMSK, 0x0);
560 cx_write(MO_GPHST_INTMSK, 0x0);
563 cx_write(VID_CAPTURE_CONTROL, 0);
565 EXPORT_SYMBOL(cx88_shutdown);
567 int cx88_reset(struct cx88_core *core)
572 /* clear irq status */
573 cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int
574 cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int
575 cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int
581 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21],
583 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH22], 128, 0);
584 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH23], 128, 0);
585 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH24], 128, 0);
586 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], 128, 0);
587 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], 128, 0);
588 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28],
590 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27], 128, 0);
593 cx_write(MO_INPUT_FORMAT, ((1 << 13) | // agc enable
594 (1 << 12) | // agc gain
595 (1 << 11) | // adaptibe agc
596 (0 << 10) | // chroma agc
597 (0 << 9) | // ckillen
600 /* setup image format */
601 cx_andor(MO_COLOR_CTRL, 0x4000, 0x4000);
603 /* setup FIFO Thresholds */
604 cx_write(MO_PDMA_STHRSH, 0x0807);
605 cx_write(MO_PDMA_DTHRSH, 0x0807);
607 /* fixes flashing of image */
608 cx_write(MO_AGC_SYNC_TIP1, 0x0380000F);
609 cx_write(MO_AGC_BACK_VBI, 0x00E00555);
611 cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int
612 cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int
613 cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int
615 /* Reset on-board parts */
616 cx_write(MO_SRST_IO, 0);
617 usleep_range(10000, 20000);
618 cx_write(MO_SRST_IO, 1);
622 EXPORT_SYMBOL(cx88_reset);
624 /* ------------------------------------------------------------------ */
626 static inline unsigned int norm_swidth(v4l2_std_id norm)
628 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
631 static inline unsigned int norm_hdelay(v4l2_std_id norm)
633 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 135 : 186;
636 static inline unsigned int norm_vdelay(v4l2_std_id norm)
638 return (norm & V4L2_STD_625_50) ? 0x24 : 0x18;
641 static inline unsigned int norm_fsc8(v4l2_std_id norm)
643 if (norm & V4L2_STD_PAL_M)
644 return 28604892; // 3.575611 MHz
646 if (norm & (V4L2_STD_PAL_Nc))
647 return 28656448; // 3.582056 MHz
649 if (norm & V4L2_STD_NTSC) // All NTSC/M and variants
650 return 28636360; // 3.57954545 MHz +/- 10 Hz
653 * SECAM have also different sub carrier for chroma,
654 * but step_db and step_dr, at cx88_set_tvnorm already handles that.
656 * The same FSC applies to PAL/BGDKIH, PAL/60, NTSC/4.43 and PAL/N
659 return 35468950; // 4.43361875 MHz +/- 5 Hz
662 static inline unsigned int norm_htotal(v4l2_std_id norm)
664 unsigned int fsc4 = norm_fsc8(norm) / 2;
666 /* returns 4*FSC / vtotal / frames per seconds */
667 return (norm & V4L2_STD_625_50) ?
668 ((fsc4 + 312) / 625 + 12) / 25 :
669 ((fsc4 + 262) / 525 * 1001 + 15000) / 30000;
672 static inline unsigned int norm_vbipack(v4l2_std_id norm)
674 return (norm & V4L2_STD_625_50) ? 511 : 400;
677 int cx88_set_scale(struct cx88_core *core, unsigned int width,
678 unsigned int height, enum v4l2_field field)
680 unsigned int swidth = norm_swidth(core->tvnorm);
681 unsigned int sheight = norm_maxh(core->tvnorm);
684 dprintk(1, "set_scale: %dx%d [%s%s,%s]\n", width, height,
685 V4L2_FIELD_HAS_TOP(field) ? "T" : "",
686 V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "",
687 v4l2_norm_to_name(core->tvnorm));
688 if (!V4L2_FIELD_HAS_BOTH(field))
691 // recalc H delay and scale registers
692 value = (width * norm_hdelay(core->tvnorm)) / swidth;
694 cx_write(MO_HDELAY_EVEN, value);
695 cx_write(MO_HDELAY_ODD, value);
696 dprintk(1, "set_scale: hdelay 0x%04x (width %d)\n", value, swidth);
698 value = (swidth * 4096 / width) - 4096;
699 cx_write(MO_HSCALE_EVEN, value);
700 cx_write(MO_HSCALE_ODD, value);
701 dprintk(1, "set_scale: hscale 0x%04x\n", value);
703 cx_write(MO_HACTIVE_EVEN, width);
704 cx_write(MO_HACTIVE_ODD, width);
705 dprintk(1, "set_scale: hactive 0x%04x\n", width);
707 // recalc V scale Register (delay is constant)
708 cx_write(MO_VDELAY_EVEN, norm_vdelay(core->tvnorm));
709 cx_write(MO_VDELAY_ODD, norm_vdelay(core->tvnorm));
710 dprintk(1, "set_scale: vdelay 0x%04x\n", norm_vdelay(core->tvnorm));
712 value = (0x10000 - (sheight * 512 / height - 512)) & 0x1fff;
713 cx_write(MO_VSCALE_EVEN, value);
714 cx_write(MO_VSCALE_ODD, value);
715 dprintk(1, "set_scale: vscale 0x%04x\n", value);
717 cx_write(MO_VACTIVE_EVEN, sheight);
718 cx_write(MO_VACTIVE_ODD, sheight);
719 dprintk(1, "set_scale: vactive 0x%04x\n", sheight);
723 value |= (1 << 19); // CFILT (default)
724 if (core->tvnorm & V4L2_STD_SECAM) {
728 if (INPUT(core->input).type == CX88_VMUX_SVIDEO)
729 value |= (1 << 13) | (1 << 5);
730 if (field == V4L2_FIELD_INTERLACED)
731 value |= (1 << 3); // VINT (interlaced vertical scaling)
733 value |= (1 << 0); // 3-tap interpolation
735 value |= (1 << 1); // 5-tap interpolation
737 value |= (3 << 5); // disable comb filter
739 cx_andor(MO_FILTER_EVEN, 0x7ffc7f, value); /* preserve PEAKEN, PSEL */
740 cx_andor(MO_FILTER_ODD, 0x7ffc7f, value);
741 dprintk(1, "set_scale: filter 0x%04x\n", value);
745 EXPORT_SYMBOL(cx88_set_scale);
747 static const u32 xtal = 28636363;
749 static int set_pll(struct cx88_core *core, int prescale, u32 ofreq)
751 static const u32 pre[] = { 0, 0, 0, 3, 2, 1 };
761 pll = ofreq * 8 * prescale * (u64)(1 << 20);
763 reg = (pll & 0x3ffffff) | (pre[prescale] << 26);
764 if (((reg >> 20) & 0x3f) < 14) {
765 pr_err("pll out of range\n");
769 dprintk(1, "set_pll: MO_PLL_REG 0x%08x [old=0x%08x,freq=%d]\n",
770 reg, cx_read(MO_PLL_REG), ofreq);
771 cx_write(MO_PLL_REG, reg);
772 for (i = 0; i < 100; i++) {
773 reg = cx_read(MO_DEVICE_STATUS);
774 if (reg & (1 << 2)) {
775 dprintk(1, "pll locked [pre=%d,ofreq=%d]\n",
779 dprintk(1, "pll not locked yet, waiting ...\n");
780 usleep_range(10000, 20000);
782 dprintk(1, "pll NOT locked [pre=%d,ofreq=%d]\n", prescale, ofreq);
786 int cx88_start_audio_dma(struct cx88_core *core)
788 /* constant 128 made buzz in analog Nicam-stereo for bigger fifo_size */
789 int bpl = cx88_sram_channels[SRAM_CH25].fifo_size / 4;
791 int rds_bpl = cx88_sram_channels[SRAM_CH27].fifo_size / AUD_RDS_LINES;
793 /* If downstream RISC is enabled, bail out; ALSA is managing DMA */
794 if (cx_read(MO_AUD_DMACNTRL) & 0x10)
797 /* setup fifo + format */
798 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], bpl, 0);
799 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], bpl, 0);
800 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27],
803 cx_write(MO_AUDD_LNGTH, bpl); /* fifo bpl size */
804 cx_write(MO_AUDR_LNGTH, rds_bpl); /* fifo bpl size */
806 /* enable Up, Down and Audio RDS fifo */
807 cx_write(MO_AUD_DMACNTRL, 0x0007);
812 int cx88_stop_audio_dma(struct cx88_core *core)
814 /* If downstream RISC is enabled, bail out; ALSA is managing DMA */
815 if (cx_read(MO_AUD_DMACNTRL) & 0x10)
819 cx_write(MO_AUD_DMACNTRL, 0x0000);
824 static int set_tvaudio(struct cx88_core *core)
826 v4l2_std_id norm = core->tvnorm;
828 if (INPUT(core->input).type != CX88_VMUX_TELEVISION &&
829 INPUT(core->input).type != CX88_VMUX_CABLE)
832 if (V4L2_STD_PAL_BG & norm) {
833 core->tvaudio = WW_BG;
835 } else if (V4L2_STD_PAL_DK & norm) {
836 core->tvaudio = WW_DK;
838 } else if (V4L2_STD_PAL_I & norm) {
839 core->tvaudio = WW_I;
841 } else if (V4L2_STD_SECAM_L & norm) {
842 core->tvaudio = WW_L;
844 } else if ((V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H) &
846 core->tvaudio = WW_BG;
848 } else if (V4L2_STD_SECAM_DK & norm) {
849 core->tvaudio = WW_DK;
851 } else if ((V4L2_STD_NTSC_M & norm) ||
852 (V4L2_STD_PAL_M & norm)) {
853 core->tvaudio = WW_BTSC;
855 } else if (V4L2_STD_NTSC_M_JP & norm) {
856 core->tvaudio = WW_EIAJ;
859 pr_info("tvaudio support needs work for this tv norm [%s], sorry\n",
860 v4l2_norm_to_name(core->tvnorm));
861 core->tvaudio = WW_NONE;
865 cx_andor(MO_AFECFG_IO, 0x1f, 0x0);
866 cx88_set_tvaudio(core);
867 /* cx88_set_stereo(dev,V4L2_TUNER_MODE_STEREO); */
870 * This should be needed only on cx88-alsa. It seems that some cx88 chips have
871 * bugs and does require DMA enabled for it to work.
873 cx88_start_audio_dma(core);
877 int cx88_set_tvnorm(struct cx88_core *core, v4l2_std_id norm)
882 u32 step_db, step_dr;
884 u32 bdelay, agcdelay, htotal;
885 u32 cxiformat, cxoformat;
887 if (norm == core->tvnorm)
889 if (core->v4ldev && (vb2_is_busy(&core->v4ldev->vb2_vidq) ||
890 vb2_is_busy(&core->v4ldev->vb2_vbiq)))
892 if (core->dvbdev && vb2_is_busy(&core->dvbdev->vb2_mpegq))
895 fsc8 = norm_fsc8(norm);
901 if (norm & V4L2_STD_NTSC_M_JP) {
902 cxiformat = VideoFormatNTSCJapan;
903 cxoformat = 0x181f0008;
904 } else if (norm & V4L2_STD_NTSC_443) {
905 cxiformat = VideoFormatNTSC443;
906 cxoformat = 0x181f0008;
907 } else if (norm & V4L2_STD_PAL_M) {
908 cxiformat = VideoFormatPALM;
909 cxoformat = 0x1c1f0008;
910 } else if (norm & V4L2_STD_PAL_N) {
911 cxiformat = VideoFormatPALN;
912 cxoformat = 0x1c1f0008;
913 } else if (norm & V4L2_STD_PAL_Nc) {
914 cxiformat = VideoFormatPALNC;
915 cxoformat = 0x1c1f0008;
916 } else if (norm & V4L2_STD_PAL_60) {
917 cxiformat = VideoFormatPAL60;
918 cxoformat = 0x181f0008;
919 } else if (norm & V4L2_STD_NTSC) {
920 cxiformat = VideoFormatNTSC;
921 cxoformat = 0x181f0008;
922 } else if (norm & V4L2_STD_SECAM) {
923 step_db = 4250000 * 8;
924 step_dr = 4406250 * 8;
926 cxiformat = VideoFormatSECAM;
927 cxoformat = 0x181f0008;
929 cxiformat = VideoFormatPAL;
930 cxoformat = 0x181f0008;
933 dprintk(1, "set_tvnorm: \"%s\" fsc8=%d adc=%d vdec=%d db/dr=%d/%d\n",
934 v4l2_norm_to_name(core->tvnorm), fsc8, adc_clock, vdec_clock,
936 set_pll(core, 2, vdec_clock);
938 dprintk(1, "set_tvnorm: MO_INPUT_FORMAT 0x%08x [old=0x%08x]\n",
939 cxiformat, cx_read(MO_INPUT_FORMAT) & 0x0f);
941 * Chroma AGC must be disabled if SECAM is used, we enable it
942 * by default on PAL and NTSC
944 cx_andor(MO_INPUT_FORMAT, 0x40f,
945 norm & V4L2_STD_SECAM ? cxiformat : cxiformat | 0x400);
947 // FIXME: as-is from DScaler
948 dprintk(1, "set_tvnorm: MO_OUTPUT_FORMAT 0x%08x [old=0x%08x]\n",
949 cxoformat, cx_read(MO_OUTPUT_FORMAT));
950 cx_write(MO_OUTPUT_FORMAT, cxoformat);
952 // MO_SCONV_REG = adc clock / video dec clock * 2^17
953 tmp64 = adc_clock * (u64)(1 << 17);
954 do_div(tmp64, vdec_clock);
955 dprintk(1, "set_tvnorm: MO_SCONV_REG 0x%08x [old=0x%08x]\n",
956 (u32)tmp64, cx_read(MO_SCONV_REG));
957 cx_write(MO_SCONV_REG, (u32)tmp64);
959 // MO_SUB_STEP = 8 * fsc / video dec clock * 2^22
960 tmp64 = step_db * (u64)(1 << 22);
961 do_div(tmp64, vdec_clock);
962 dprintk(1, "set_tvnorm: MO_SUB_STEP 0x%08x [old=0x%08x]\n",
963 (u32)tmp64, cx_read(MO_SUB_STEP));
964 cx_write(MO_SUB_STEP, (u32)tmp64);
966 // MO_SUB_STEP_DR = 8 * 4406250 / video dec clock * 2^22
967 tmp64 = step_dr * (u64)(1 << 22);
968 do_div(tmp64, vdec_clock);
969 dprintk(1, "set_tvnorm: MO_SUB_STEP_DR 0x%08x [old=0x%08x]\n",
970 (u32)tmp64, cx_read(MO_SUB_STEP_DR));
971 cx_write(MO_SUB_STEP_DR, (u32)tmp64);
974 bdelay = vdec_clock * 65 / 20000000 + 21;
975 agcdelay = vdec_clock * 68 / 20000000 + 15;
977 "set_tvnorm: MO_AGC_BURST 0x%08x [old=0x%08x,bdelay=%d,agcdelay=%d]\n",
978 (bdelay << 8) | agcdelay, cx_read(MO_AGC_BURST),
980 cx_write(MO_AGC_BURST, (bdelay << 8) | agcdelay);
983 tmp64 = norm_htotal(norm) * (u64)vdec_clock;
987 "set_tvnorm: MO_HTOTAL 0x%08x [old=0x%08x,htotal=%d]\n",
988 htotal, cx_read(MO_HTOTAL), (u32)tmp64);
989 cx_andor(MO_HTOTAL, 0x07ff, htotal);
991 // vbi stuff, set vbi offset to 10 (for 20 Clk*2 pixels), this makes
992 // the effective vbi offset ~244 samples, the same as the Bt8x8
993 cx_write(MO_VBI_PACKET, (10 << 11) | norm_vbipack(norm));
995 // this is needed as well to set all tvnorm parameter
996 cx88_set_scale(core, 320, 240, V4L2_FIELD_INTERLACED);
1002 call_all(core, video, s_std, norm);
1005 * The chroma_agc control should be inaccessible
1006 * if the video format is SECAM
1008 v4l2_ctrl_grab(core->chroma_agc, cxiformat == VideoFormatSECAM);
1013 EXPORT_SYMBOL(cx88_set_tvnorm);
1015 /* ------------------------------------------------------------------ */
1017 void cx88_vdev_init(struct cx88_core *core,
1018 struct pci_dev *pci,
1019 struct video_device *vfd,
1020 const struct video_device *template_,
1026 * The dev pointer of v4l2_device is NULL, instead we set the
1027 * video_device dev_parent pointer to the correct PCI bus device.
1028 * This driver is a rare example where there is one v4l2_device,
1029 * but the video nodes have different parent (PCI) devices.
1031 vfd->v4l2_dev = &core->v4l2_dev;
1032 vfd->dev_parent = &pci->dev;
1033 vfd->release = video_device_release_empty;
1034 vfd->lock = &core->lock;
1035 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)",
1036 core->name, type, core->board.name);
1038 EXPORT_SYMBOL(cx88_vdev_init);
1040 struct cx88_core *cx88_core_get(struct pci_dev *pci)
1042 struct cx88_core *core;
1044 mutex_lock(&devlist);
1045 list_for_each_entry(core, &cx88_devlist, devlist) {
1046 if (pci->bus->number != core->pci_bus)
1048 if (PCI_SLOT(pci->devfn) != core->pci_slot)
1051 if (cx88_get_resources(core, pci) != 0) {
1052 mutex_unlock(&devlist);
1055 refcount_inc(&core->refcount);
1056 mutex_unlock(&devlist);
1060 core = cx88_core_create(pci, cx88_devcount);
1063 list_add_tail(&core->devlist, &cx88_devlist);
1066 mutex_unlock(&devlist);
1069 EXPORT_SYMBOL(cx88_core_get);
1071 void cx88_core_put(struct cx88_core *core, struct pci_dev *pci)
1073 release_mem_region(pci_resource_start(pci, 0),
1074 pci_resource_len(pci, 0));
1076 if (!refcount_dec_and_test(&core->refcount))
1079 mutex_lock(&devlist);
1081 if (core->i2c_rc == 0) {
1083 i2c_unregister_device(core->i2c_rtc);
1084 i2c_del_adapter(&core->i2c_adap);
1086 list_del(&core->devlist);
1087 iounmap(core->lmmio);
1089 mutex_unlock(&devlist);
1090 v4l2_ctrl_handler_free(&core->video_hdl);
1091 v4l2_ctrl_handler_free(&core->audio_hdl);
1092 v4l2_device_unregister(&core->v4l2_dev);
1095 EXPORT_SYMBOL(cx88_core_put);