2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include "cx25821-medusa-video.h"
23 #include "cx25821-biffuncs.h"
26 * medusa_enable_bluefield_output()
28 * Enable the generation of blue filed output if no video
31 static void medusa_enable_bluefield_output(struct cx25821_dev *dev, int channel,
36 int out_ctrl = OUT_CTRL1;
37 int out_ctrl_ns = OUT_CTRL_NS;
44 out_ctrl = VDEC_B_OUT_CTRL1;
45 out_ctrl_ns = VDEC_B_OUT_CTRL_NS;
48 out_ctrl = VDEC_C_OUT_CTRL1;
49 out_ctrl_ns = VDEC_C_OUT_CTRL_NS;
52 out_ctrl = VDEC_D_OUT_CTRL1;
53 out_ctrl_ns = VDEC_D_OUT_CTRL_NS;
56 out_ctrl = VDEC_E_OUT_CTRL1;
57 out_ctrl_ns = VDEC_E_OUT_CTRL_NS;
60 out_ctrl = VDEC_F_OUT_CTRL1;
61 out_ctrl_ns = VDEC_F_OUT_CTRL_NS;
64 out_ctrl = VDEC_G_OUT_CTRL1;
65 out_ctrl_ns = VDEC_G_OUT_CTRL_NS;
68 out_ctrl = VDEC_H_OUT_CTRL1;
69 out_ctrl_ns = VDEC_H_OUT_CTRL_NS;
73 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp);
74 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */
76 value |= 0x00000080; /* set BLUE_FIELD_EN */
77 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value);
79 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp);
82 value |= 0x00000080; /* set BLUE_FIELD_EN */
83 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value);
86 static int medusa_initialize_ntsc(struct cx25821_dev *dev)
93 for (i = 0; i < MAX_DECODERS; i++) {
94 /* set video format NTSC-M */
95 value = cx25821_i2c_read(&dev->i2c_bus[0],
96 MODE_CTRL + (0x200 * i), &tmp);
98 /* enable the fast locking mode bit[16] */
100 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
101 MODE_CTRL + (0x200 * i), value);
103 /* resolution NTSC 720x480 */
104 value = cx25821_i2c_read(&dev->i2c_bus[0],
105 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
108 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
109 HORIZ_TIM_CTRL + (0x200 * i), value);
111 value = cx25821_i2c_read(&dev->i2c_bus[0],
112 VERT_TIM_CTRL + (0x200 * i), &tmp);
114 value |= 0x1C1E001A; /* vblank_cnt + 2 to get camera ID */
115 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
116 VERT_TIM_CTRL + (0x200 * i), value);
118 /* chroma subcarrier step size */
119 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
120 SC_STEP_SIZE + (0x200 * i), 0x43E00000);
122 /* enable VIP optional active */
123 value = cx25821_i2c_read(&dev->i2c_bus[0],
124 OUT_CTRL_NS + (0x200 * i), &tmp);
127 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
128 OUT_CTRL_NS + (0x200 * i), value);
130 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
131 value = cx25821_i2c_read(&dev->i2c_bus[0],
132 OUT_CTRL1 + (0x200 * i), &tmp);
135 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
136 OUT_CTRL1 + (0x200 * i), value);
139 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
140 * when the input switching rate < 16 fields
142 value = cx25821_i2c_read(&dev->i2c_bus[0],
143 MISC_TIM_CTRL + (0x200 * i), &tmp);
144 /* disable special play detection */
145 value = setBitAtPos(value, 14);
146 value = clearBitAtPos(value, 15);
147 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
148 MISC_TIM_CTRL + (0x200 * i), value);
150 /* set vbi_gate_en to 0 */
151 value = cx25821_i2c_read(&dev->i2c_bus[0],
152 DFE_CTRL1 + (0x200 * i), &tmp);
153 value = clearBitAtPos(value, 29);
154 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
155 DFE_CTRL1 + (0x200 * i), value);
157 /* Enable the generation of blue field output if no video */
158 medusa_enable_bluefield_output(dev, i, 1);
161 for (i = 0; i < MAX_ENCODERS; i++) {
163 value = cx25821_i2c_read(&dev->i2c_bus[0],
164 DENC_A_REG_1 + (0x100 * i), &tmp);
167 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
168 DENC_A_REG_1 + (0x100 * i), value);
170 /* burst begin and burst end */
171 value = cx25821_i2c_read(&dev->i2c_bus[0],
172 DENC_A_REG_2 + (0x100 * i), &tmp);
175 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
176 DENC_A_REG_2 + (0x100 * i), value);
178 value = cx25821_i2c_read(&dev->i2c_bus[0],
179 DENC_A_REG_3 + (0x100 * i), &tmp);
182 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
183 DENC_A_REG_3 + (0x100 * i), value);
185 /* set NTSC vblank, no phase alternation, 7.5 IRE pedestal */
186 value = cx25821_i2c_read(&dev->i2c_bus[0],
187 DENC_A_REG_4 + (0x100 * i), &tmp);
190 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
191 DENC_A_REG_4 + (0x100 * i), value);
193 value = cx25821_i2c_read(&dev->i2c_bus[0],
194 DENC_A_REG_5 + (0x100 * i), &tmp);
197 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
198 DENC_A_REG_5 + (0x100 * i), value);
200 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
201 DENC_A_REG_6 + (0x100 * i), 0x009A89C1);
203 /* Subcarrier Increment */
204 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
205 DENC_A_REG_7 + (0x100 * i), 0x21F07C1F);
208 /* set picture resolutions */
210 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
212 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
214 /* set Bypass input format to NTSC 525 lines */
215 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
217 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
222 static int medusa_PALCombInit(struct cx25821_dev *dev, int dec)
225 u32 value = 0, tmp = 0;
227 /* Setup for 2D threshold */
228 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
229 COMB_2D_HFS_CFG + (0x200 * dec), 0x20002861);
230 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
231 COMB_2D_HFD_CFG + (0x200 * dec), 0x20002861);
232 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
233 COMB_2D_LF_CFG + (0x200 * dec), 0x200A1023);
235 /* Setup flat chroma and luma thresholds */
236 value = cx25821_i2c_read(&dev->i2c_bus[0],
237 COMB_FLAT_THRESH_CTRL + (0x200 * dec), &tmp);
239 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
240 COMB_FLAT_THRESH_CTRL + (0x200 * dec), value);
242 /* set comb 2D blend */
243 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
244 COMB_2D_BLEND + (0x200 * dec), 0x210F0F0F);
246 /* COMB MISC CONTROL */
247 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
248 COMB_MISC_CTRL + (0x200 * dec), 0x41120A7F);
253 static int medusa_initialize_pal(struct cx25821_dev *dev)
260 for (i = 0; i < MAX_DECODERS; i++) {
261 /* set video format PAL-BDGHI */
262 value = cx25821_i2c_read(&dev->i2c_bus[0],
263 MODE_CTRL + (0x200 * i), &tmp);
265 /* enable the fast locking mode bit[16] */
267 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
268 MODE_CTRL + (0x200 * i), value);
270 /* resolution PAL 720x576 */
271 value = cx25821_i2c_read(&dev->i2c_bus[0],
272 HORIZ_TIM_CTRL + (0x200 * i), &tmp);
275 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
276 HORIZ_TIM_CTRL + (0x200 * i), value);
278 /* vblank656_cnt=x26, vactive_cnt=240h, vblank_cnt=x24 */
279 value = cx25821_i2c_read(&dev->i2c_bus[0],
280 VERT_TIM_CTRL + (0x200 * i), &tmp);
282 value |= 0x28240026; /* vblank_cnt + 2 to get camera ID */
283 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
284 VERT_TIM_CTRL + (0x200 * i), value);
286 /* chroma subcarrier step size */
287 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
288 SC_STEP_SIZE + (0x200 * i), 0x5411E2D0);
290 /* enable VIP optional active */
291 value = cx25821_i2c_read(&dev->i2c_bus[0],
292 OUT_CTRL_NS + (0x200 * i), &tmp);
295 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
296 OUT_CTRL_NS + (0x200 * i), value);
298 /* enable VIP optional active (VIP_OPT_AL) for direct output. */
299 value = cx25821_i2c_read(&dev->i2c_bus[0],
300 OUT_CTRL1 + (0x200 * i), &tmp);
303 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
304 OUT_CTRL1 + (0x200 * i), value);
307 * clear VPRES_VERT_EN bit, fixes the chroma run away problem
308 * when the input switching rate < 16 fields
310 value = cx25821_i2c_read(&dev->i2c_bus[0],
311 MISC_TIM_CTRL + (0x200 * i), &tmp);
312 /* disable special play detection */
313 value = setBitAtPos(value, 14);
314 value = clearBitAtPos(value, 15);
315 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
316 MISC_TIM_CTRL + (0x200 * i), value);
318 /* set vbi_gate_en to 0 */
319 value = cx25821_i2c_read(&dev->i2c_bus[0],
320 DFE_CTRL1 + (0x200 * i), &tmp);
321 value = clearBitAtPos(value, 29);
322 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
323 DFE_CTRL1 + (0x200 * i), value);
325 medusa_PALCombInit(dev, i);
327 /* Enable the generation of blue field output if no video */
328 medusa_enable_bluefield_output(dev, i, 1);
331 for (i = 0; i < MAX_ENCODERS; i++) {
333 value = cx25821_i2c_read(&dev->i2c_bus[0],
334 DENC_A_REG_1 + (0x100 * i), &tmp);
337 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
338 DENC_A_REG_1 + (0x100 * i), value);
340 /* burst begin and burst end */
341 value = cx25821_i2c_read(&dev->i2c_bus[0],
342 DENC_A_REG_2 + (0x100 * i), &tmp);
345 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
346 DENC_A_REG_2 + (0x100 * i), value);
348 /* hblank and vactive */
349 value = cx25821_i2c_read(&dev->i2c_bus[0],
350 DENC_A_REG_3 + (0x100 * i), &tmp);
353 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
354 DENC_A_REG_3 + (0x100 * i), value);
356 /* set PAL vblank, phase alternation, 0 IRE pedestal */
357 value = cx25821_i2c_read(&dev->i2c_bus[0],
358 DENC_A_REG_4 + (0x100 * i), &tmp);
361 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
362 DENC_A_REG_4 + (0x100 * i), value);
364 value = cx25821_i2c_read(&dev->i2c_bus[0],
365 DENC_A_REG_5 + (0x100 * i), &tmp);
368 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
369 DENC_A_REG_5 + (0x100 * i), value);
371 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
372 DENC_A_REG_6 + (0x100 * i), 0x00A493CF);
374 /* Subcarrier Increment */
375 ret_val = cx25821_i2c_write(&dev->i2c_bus[0],
376 DENC_A_REG_7 + (0x100 * i), 0x2A098ACB);
379 /* set picture resolutions */
381 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], HSCALE_CTRL, 0x0);
383 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], VSCALE_CTRL, 0x0);
385 /* set Bypass input format to PAL 625 lines */
386 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
388 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
393 int medusa_set_videostandard(struct cx25821_dev *dev)
396 u32 value = 0, tmp = 0;
398 if (dev->tvnorm & V4L2_STD_PAL_BG || dev->tvnorm & V4L2_STD_PAL_DK)
399 status = medusa_initialize_pal(dev);
401 status = medusa_initialize_ntsc(dev);
403 /* Enable DENC_A output */
404 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_A_REG_4, &tmp);
405 value = setBitAtPos(value, 4);
406 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_A_REG_4, value);
408 /* Enable DENC_B output */
409 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_B_REG_4, &tmp);
410 value = setBitAtPos(value, 4);
411 status = cx25821_i2c_write(&dev->i2c_bus[0], DENC_B_REG_4, value);
416 void medusa_set_resolution(struct cx25821_dev *dev, int width,
420 int decoder_count = 0;
423 const int MAX_WIDTH = 720;
425 /* validate the width */
426 if (width > MAX_WIDTH) {
427 pr_info("%s(): width %d > MAX_WIDTH %d ! resetting to MAX_WIDTH\n",
428 __func__, width, MAX_WIDTH);
432 if (decoder_select <= 7 && decoder_select >= 0) {
433 decoder = decoder_select;
434 decoder_count = decoder_select + 1;
437 decoder_count = dev->_max_num_decoders;
467 for (; decoder < decoder_count; decoder++) {
468 /* write scaling values for each decoder */
469 cx25821_i2c_write(&dev->i2c_bus[0],
470 HSCALE_CTRL + (0x200 * decoder), hscale);
471 cx25821_i2c_write(&dev->i2c_bus[0],
472 VSCALE_CTRL + (0x200 * decoder), vscale);
476 static void medusa_set_decoderduration(struct cx25821_dev *dev, int decoder,
481 u32 disp_cnt_reg = DISP_AB_CNT;
484 if (decoder < VDEC_A || decoder > VDEC_H) {
493 disp_cnt_reg = DISP_CD_CNT;
497 disp_cnt_reg = DISP_EF_CNT;
501 disp_cnt_reg = DISP_GH_CNT;
505 /* update hardware */
506 fld_cnt = cx25821_i2c_read(&dev->i2c_bus[0], disp_cnt_reg, &tmp);
508 if (!(decoder % 2)) { /* EVEN decoder */
509 fld_cnt &= 0xFFFF0000;
512 fld_cnt &= 0x0000FFFF;
513 fld_cnt |= ((u32) duration) << 16;
516 cx25821_i2c_write(&dev->i2c_bus[0], disp_cnt_reg, fld_cnt);
519 /* Map to Medusa register setting */
520 static int mapM(int srcMin, int srcMax, int srcVal, int dstMin, int dstMax,
527 if ((srcMin == srcMax) || (srcVal < srcMin) || (srcVal > srcMax))
530 * This is the overall expression used:
532 * (srcVal - srcMin)*(dstMax - dstMin) / (srcMax - srcMin) + dstMin;
533 * but we need to account for rounding so below we use the modulus
534 * operator to find the remainder and increment if necessary.
536 numerator = (srcVal - srcMin) * (dstMax - dstMin);
537 denominator = srcMax - srcMin;
538 quotient = numerator / denominator;
540 if (2 * (numerator % denominator) >= denominator)
543 *dstVal = quotient + dstMin;
548 static unsigned long convert_to_twos(long numeric, unsigned long bits_len)
555 temp = ~(abs(numeric) & 0xFF);
561 int medusa_set_brightness(struct cx25821_dev *dev, int brightness, int decoder)
565 u32 val = 0, tmp = 0;
567 if ((brightness > VIDEO_PROCAMP_MAX) ||
568 (brightness < VIDEO_PROCAMP_MIN)) {
571 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, brightness,
572 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
573 value = convert_to_twos(value, 8);
574 val = cx25821_i2c_read(&dev->i2c_bus[0],
575 VDEC_A_BRITE_CTRL + (0x200 * decoder), &tmp);
577 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
578 VDEC_A_BRITE_CTRL + (0x200 * decoder), val | value);
582 int medusa_set_contrast(struct cx25821_dev *dev, int contrast, int decoder)
586 u32 val = 0, tmp = 0;
588 if ((contrast > VIDEO_PROCAMP_MAX) || (contrast < VIDEO_PROCAMP_MIN)) {
592 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, contrast,
593 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
594 val = cx25821_i2c_read(&dev->i2c_bus[0],
595 VDEC_A_CNTRST_CTRL + (0x200 * decoder), &tmp);
597 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
598 VDEC_A_CNTRST_CTRL + (0x200 * decoder), val | value);
603 int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder)
607 u32 val = 0, tmp = 0;
609 if ((hue > VIDEO_PROCAMP_MAX) || (hue < VIDEO_PROCAMP_MIN)) {
613 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, hue,
614 SIGNED_BYTE_MIN, SIGNED_BYTE_MAX, &value);
616 value = convert_to_twos(value, 8);
617 val = cx25821_i2c_read(&dev->i2c_bus[0],
618 VDEC_A_HUE_CTRL + (0x200 * decoder), &tmp);
621 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
622 VDEC_A_HUE_CTRL + (0x200 * decoder), val | value);
627 int medusa_set_saturation(struct cx25821_dev *dev, int saturation, int decoder)
631 u32 val = 0, tmp = 0;
633 if ((saturation > VIDEO_PROCAMP_MAX) ||
634 (saturation < VIDEO_PROCAMP_MIN)) {
638 ret_val = mapM(VIDEO_PROCAMP_MIN, VIDEO_PROCAMP_MAX, saturation,
639 UNSIGNED_BYTE_MIN, UNSIGNED_BYTE_MAX, &value);
641 val = cx25821_i2c_read(&dev->i2c_bus[0],
642 VDEC_A_USAT_CTRL + (0x200 * decoder), &tmp);
644 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
645 VDEC_A_USAT_CTRL + (0x200 * decoder), val | value);
647 val = cx25821_i2c_read(&dev->i2c_bus[0],
648 VDEC_A_VSAT_CTRL + (0x200 * decoder), &tmp);
650 ret_val |= cx25821_i2c_write(&dev->i2c_bus[0],
651 VDEC_A_VSAT_CTRL + (0x200 * decoder), val | value);
656 /* Program the display sequence and monitor output. */
658 int medusa_video_init(struct cx25821_dev *dev)
660 u32 value = 0, tmp = 0;
664 /* disable Auto source selection on all video decoders */
665 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
667 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
672 /* Turn off Master source switch enable */
673 value = cx25821_i2c_read(&dev->i2c_bus[0], MON_A_CTRL, &tmp);
675 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], MON_A_CTRL, value);
681 * FIXME: due to a coding bug the duration was always 0. It's
682 * likely that it really should be something else, but due to the
683 * lack of documentation I have no idea what it should be. For
684 * now just fill in 0 as the duration.
686 for (i = 0; i < dev->_max_num_decoders; i++)
687 medusa_set_decoderduration(dev, i, 0);
689 /* Select monitor as DENC A input, power up the DAC */
690 value = cx25821_i2c_read(&dev->i2c_bus[0], DENC_AB_CTRL, &tmp);
692 value |= 0x00090008; /* set en_active */
693 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], DENC_AB_CTRL, value);
698 /* enable input is VIP/656 */
699 value = cx25821_i2c_read(&dev->i2c_bus[0], BYP_AB_CTRL, &tmp);
700 value |= 0x00040100; /* enable VIP */
701 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], BYP_AB_CTRL, value);
706 /* select AFE clock to output mode */
707 value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
709 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL,
715 /* Turn on all of the data out and control output pins. */
716 value = cx25821_i2c_read(&dev->i2c_bus[0], PIN_OE_CTRL, &tmp);
718 if (dev->_max_num_decoders == MAX_DECODERS) {
720 * Note: The octal board does not support control pins(bit16-19)
721 * These bits are ignored in the octal board.
723 * disable VDEC A-C port, default to Mobilygen Interface
727 /* disable VDEC A-C port, default to Mobilygen Interface */
732 ret_val = cx25821_i2c_write(&dev->i2c_bus[0], PIN_OE_CTRL, value);
737 ret_val = medusa_set_videostandard(dev);