drivers/media/pci/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  */
  17
  18 #include "cx23885.h"
  19
  20 #include <linux/init.h>
  21 #include <linux/list.h>
  22 #include <linux/module.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/kmod.h>
  25 #include <linux/kernel.h>
  26 #include <linux/slab.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <asm/div64.h>
  30 #include <linux/firmware.h>
  31
  32 #include "cimax2.h"
  33 #include "altera-ci.h"
  34 #include "cx23888-ir.h"
  35 #include "cx23885-ir.h"
  36 #include "cx23885-av.h"
  37 #include "cx23885-input.h"
  38
  39 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  40 MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
  41 MODULE_LICENSE("GPL");
  42 MODULE_VERSION(CX23885_VERSION);
  43
  44 static unsigned int debug;
  45 module_param(debug, int, 0644);
  46 MODULE_PARM_DESC(debug, "enable debug messages");
  47
  48 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  49 module_param_array(card,  int, NULL, 0444);
  50 MODULE_PARM_DESC(card, "card type");
  51
  52 #define dprintk(level, fmt, arg...)\
  53         do { if (debug >= level)\
  54                 printk(KERN_DEBUG pr_fmt("%s: " fmt), \
  55                        __func__, ##arg); \
  56         } while (0)
  57
  58 static unsigned int cx23885_devcount;
  59
  60 #define NO_SYNC_LINE (-1U)
  61
  62 /* FIXME, these allocations will change when
  63  * analog arrives. The be reviewed.
  64  * CX23887 Assumptions
  65  * 1 line = 16 bytes of CDT
  66  * cmds size = 80
  67  * cdt size = 16 * linesize
  68  * iqsize = 64
  69  * maxlines = 6
  70  *
  71  * Address Space:
  72  * 0x00000000 0x00008fff FIFO clusters
  73  * 0x00010000 0x000104af Channel Management Data Structures
  74  * 0x000104b0 0x000104ff Free
  75  * 0x00010500 0x000108bf 15 channels * iqsize
  76  * 0x000108c0 0x000108ff Free
  77  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  78  *                       15 channels * (iqsize + (maxlines * linesize))
  79  * 0x00010ea0 0x00010xxx Free
  80  */
  81
  82 static struct sram_channel cx23885_sram_channels[] = {
  83         [SRAM_CH01] = {
  84                 .name           = "VID A",
  85                 .cmds_start     = 0x10000,
  86                 .ctrl_start     = 0x10380,
  87                 .cdt            = 0x104c0,
  88                 .fifo_start     = 0x40,
  89                 .fifo_size      = 0x2800,
  90                 .ptr1_reg       = DMA1_PTR1,
  91                 .ptr2_reg       = DMA1_PTR2,
  92                 .cnt1_reg       = DMA1_CNT1,
  93                 .cnt2_reg       = DMA1_CNT2,
  94         },
  95         [SRAM_CH02] = {
  96                 .name           = "ch2",
  97                 .cmds_start     = 0x0,
  98                 .ctrl_start     = 0x0,
  99                 .cdt            = 0x0,
 100                 .fifo_start     = 0x0,
 101                 .fifo_size      = 0x0,
 102                 .ptr1_reg       = DMA2_PTR1,
 103                 .ptr2_reg       = DMA2_PTR2,
 104                 .cnt1_reg       = DMA2_CNT1,
 105                 .cnt2_reg       = DMA2_CNT2,
 106         },
 107         [SRAM_CH03] = {
 108                 .name           = "TS1 B",
 109                 .cmds_start     = 0x100A0,
 110                 .ctrl_start     = 0x10400,
 111                 .cdt            = 0x10580,
 112                 .fifo_start     = 0x5000,
 113                 .fifo_size      = 0x1000,
 114                 .ptr1_reg       = DMA3_PTR1,
 115                 .ptr2_reg       = DMA3_PTR2,
 116                 .cnt1_reg       = DMA3_CNT1,
 117                 .cnt2_reg       = DMA3_CNT2,
 118         },
 119         [SRAM_CH04] = {
 120                 .name           = "ch4",
 121                 .cmds_start     = 0x0,
 122                 .ctrl_start     = 0x0,
 123                 .cdt            = 0x0,
 124                 .fifo_start     = 0x0,
 125                 .fifo_size      = 0x0,
 126                 .ptr1_reg       = DMA4_PTR1,
 127                 .ptr2_reg       = DMA4_PTR2,
 128                 .cnt1_reg       = DMA4_CNT1,
 129                 .cnt2_reg       = DMA4_CNT2,
 130         },
 131         [SRAM_CH05] = {
 132                 .name           = "ch5",
 133                 .cmds_start     = 0x0,
 134                 .ctrl_start     = 0x0,
 135                 .cdt            = 0x0,
 136                 .fifo_start     = 0x0,
 137                 .fifo_size      = 0x0,
 138                 .ptr1_reg       = DMA5_PTR1,
 139                 .ptr2_reg       = DMA5_PTR2,
 140                 .cnt1_reg       = DMA5_CNT1,
 141                 .cnt2_reg       = DMA5_CNT2,
 142         },
 143         [SRAM_CH06] = {
 144                 .name           = "TS2 C",
 145                 .cmds_start     = 0x10140,
 146                 .ctrl_start     = 0x10440,
 147                 .cdt            = 0x105e0,
 148                 .fifo_start     = 0x6000,
 149                 .fifo_size      = 0x1000,
 150                 .ptr1_reg       = DMA5_PTR1,
 151                 .ptr2_reg       = DMA5_PTR2,
 152                 .cnt1_reg       = DMA5_CNT1,
 153                 .cnt2_reg       = DMA5_CNT2,
 154         },
 155         [SRAM_CH07] = {
 156                 .name           = "TV Audio",
 157                 .cmds_start     = 0x10190,
 158                 .ctrl_start     = 0x10480,
 159                 .cdt            = 0x10a00,
 160                 .fifo_start     = 0x7000,
 161                 .fifo_size      = 0x1000,
 162                 .ptr1_reg       = DMA6_PTR1,
 163                 .ptr2_reg       = DMA6_PTR2,
 164                 .cnt1_reg       = DMA6_CNT1,
 165                 .cnt2_reg       = DMA6_CNT2,
 166         },
 167         [SRAM_CH08] = {
 168                 .name           = "ch8",
 169                 .cmds_start     = 0x0,
 170                 .ctrl_start     = 0x0,
 171                 .cdt            = 0x0,
 172                 .fifo_start     = 0x0,
 173                 .fifo_size      = 0x0,
 174                 .ptr1_reg       = DMA7_PTR1,
 175                 .ptr2_reg       = DMA7_PTR2,
 176                 .cnt1_reg       = DMA7_CNT1,
 177                 .cnt2_reg       = DMA7_CNT2,
 178         },
 179         [SRAM_CH09] = {
 180                 .name           = "ch9",
 181                 .cmds_start     = 0x0,
 182                 .ctrl_start     = 0x0,
 183                 .cdt            = 0x0,
 184                 .fifo_start     = 0x0,
 185                 .fifo_size      = 0x0,
 186                 .ptr1_reg       = DMA8_PTR1,
 187                 .ptr2_reg       = DMA8_PTR2,
 188                 .cnt1_reg       = DMA8_CNT1,
 189                 .cnt2_reg       = DMA8_CNT2,
 190         },
 191 };
 192
 193 static struct sram_channel cx23887_sram_channels[] = {
 194         [SRAM_CH01] = {
 195                 .name           = "VID A",
 196                 .cmds_start     = 0x10000,
 197                 .ctrl_start     = 0x105b0,
 198                 .cdt            = 0x107b0,
 199                 .fifo_start     = 0x40,
 200                 .fifo_size      = 0x2800,
 201                 .ptr1_reg       = DMA1_PTR1,
 202                 .ptr2_reg       = DMA1_PTR2,
 203                 .cnt1_reg       = DMA1_CNT1,
 204                 .cnt2_reg       = DMA1_CNT2,
 205         },
 206         [SRAM_CH02] = {
 207                 .name           = "VID A (VBI)",
 208                 .cmds_start     = 0x10050,
 209                 .ctrl_start     = 0x105F0,
 210                 .cdt            = 0x10810,
 211                 .fifo_start     = 0x3000,
 212                 .fifo_size      = 0x1000,
 213                 .ptr1_reg       = DMA2_PTR1,
 214                 .ptr2_reg       = DMA2_PTR2,
 215                 .cnt1_reg       = DMA2_CNT1,
 216                 .cnt2_reg       = DMA2_CNT2,
 217         },
 218         [SRAM_CH03] = {
 219                 .name           = "TS1 B",
 220                 .cmds_start     = 0x100A0,
 221                 .ctrl_start     = 0x10630,
 222                 .cdt            = 0x10870,
 223                 .fifo_start     = 0x5000,
 224                 .fifo_size      = 0x1000,
 225                 .ptr1_reg       = DMA3_PTR1,
 226                 .ptr2_reg       = DMA3_PTR2,
 227                 .cnt1_reg       = DMA3_CNT1,
 228                 .cnt2_reg       = DMA3_CNT2,
 229         },
 230         [SRAM_CH04] = {
 231                 .name           = "ch4",
 232                 .cmds_start     = 0x0,
 233                 .ctrl_start     = 0x0,
 234                 .cdt            = 0x0,
 235                 .fifo_start     = 0x0,
 236                 .fifo_size      = 0x0,
 237                 .ptr1_reg       = DMA4_PTR1,
 238                 .ptr2_reg       = DMA4_PTR2,
 239                 .cnt1_reg       = DMA4_CNT1,
 240                 .cnt2_reg       = DMA4_CNT2,
 241         },
 242         [SRAM_CH05] = {
 243                 .name           = "ch5",
 244                 .cmds_start     = 0x0,
 245                 .ctrl_start     = 0x0,
 246                 .cdt            = 0x0,
 247                 .fifo_start     = 0x0,
 248                 .fifo_size      = 0x0,
 249                 .ptr1_reg       = DMA5_PTR1,
 250                 .ptr2_reg       = DMA5_PTR2,
 251                 .cnt1_reg       = DMA5_CNT1,
 252                 .cnt2_reg       = DMA5_CNT2,
 253         },
 254         [SRAM_CH06] = {
 255                 .name           = "TS2 C",
 256                 .cmds_start     = 0x10140,
 257                 .ctrl_start     = 0x10670,
 258                 .cdt            = 0x108d0,
 259                 .fifo_start     = 0x6000,
 260                 .fifo_size      = 0x1000,
 261                 .ptr1_reg       = DMA5_PTR1,
 262                 .ptr2_reg       = DMA5_PTR2,
 263                 .cnt1_reg       = DMA5_CNT1,
 264                 .cnt2_reg       = DMA5_CNT2,
 265         },
 266         [SRAM_CH07] = {
 267                 .name           = "TV Audio",
 268                 .cmds_start     = 0x10190,
 269                 .ctrl_start     = 0x106B0,
 270                 .cdt            = 0x10930,
 271                 .fifo_start     = 0x7000,
 272                 .fifo_size      = 0x1000,
 273                 .ptr1_reg       = DMA6_PTR1,
 274                 .ptr2_reg       = DMA6_PTR2,
 275                 .cnt1_reg       = DMA6_CNT1,
 276                 .cnt2_reg       = DMA6_CNT2,
 277         },
 278         [SRAM_CH08] = {
 279                 .name           = "ch8",
 280                 .cmds_start     = 0x0,
 281                 .ctrl_start     = 0x0,
 282                 .cdt            = 0x0,
 283                 .fifo_start     = 0x0,
 284                 .fifo_size      = 0x0,
 285                 .ptr1_reg       = DMA7_PTR1,
 286                 .ptr2_reg       = DMA7_PTR2,
 287                 .cnt1_reg       = DMA7_CNT1,
 288                 .cnt2_reg       = DMA7_CNT2,
 289         },
 290         [SRAM_CH09] = {
 291                 .name           = "ch9",
 292                 .cmds_start     = 0x0,
 293                 .ctrl_start     = 0x0,
 294                 .cdt            = 0x0,
 295                 .fifo_start     = 0x0,
 296                 .fifo_size      = 0x0,
 297                 .ptr1_reg       = DMA8_PTR1,
 298                 .ptr2_reg       = DMA8_PTR2,
 299                 .cnt1_reg       = DMA8_CNT1,
 300                 .cnt2_reg       = DMA8_CNT2,
 301         },
 302 };
 303
 304 static void cx23885_irq_add(struct cx23885_dev *dev, u32 mask)
 305 {
 306         unsigned long flags;
 307         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 308
 309         dev->pci_irqmask |= mask;
 310
 311         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 312 }
 313
 314 void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask)
 315 {
 316         unsigned long flags;
 317         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 318
 319         dev->pci_irqmask |= mask;
 320         cx_set(PCI_INT_MSK, mask);
 321
 322         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 323 }
 324
 325 void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask)
 326 {
 327         u32 v;
 328         unsigned long flags;
 329         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 330
 331         v = mask & dev->pci_irqmask;
 332         if (v)
 333                 cx_set(PCI_INT_MSK, v);
 334
 335         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 336 }
 337
 338 static inline void cx23885_irq_enable_all(struct cx23885_dev *dev)
 339 {
 340         cx23885_irq_enable(dev, 0xffffffff);
 341 }
 342
 343 void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask)
 344 {
 345         unsigned long flags;
 346         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 347
 348         cx_clear(PCI_INT_MSK, mask);
 349
 350         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 351 }
 352
 353 static inline void cx23885_irq_disable_all(struct cx23885_dev *dev)
 354 {
 355         cx23885_irq_disable(dev, 0xffffffff);
 356 }
 357
 358 void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask)
 359 {
 360         unsigned long flags;
 361         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 362
 363         dev->pci_irqmask &= ~mask;
 364         cx_clear(PCI_INT_MSK, mask);
 365
 366         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 367 }
 368
 369 static u32 cx23885_irq_get_mask(struct cx23885_dev *dev)
 370 {
 371         u32 v;
 372         unsigned long flags;
 373         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 374
 375         v = cx_read(PCI_INT_MSK);
 376
 377         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 378         return v;
 379 }
 380
 381 static int cx23885_risc_decode(u32 risc)
 382 {
 383         static char *instr[16] = {
 384                 [RISC_SYNC    >> 28] = "sync",
 385                 [RISC_WRITE   >> 28] = "write",
 386                 [RISC_WRITEC  >> 28] = "writec",
 387                 [RISC_READ    >> 28] = "read",
 388                 [RISC_READC   >> 28] = "readc",
 389                 [RISC_JUMP    >> 28] = "jump",
 390                 [RISC_SKIP    >> 28] = "skip",
 391                 [RISC_WRITERM >> 28] = "writerm",
 392                 [RISC_WRITECM >> 28] = "writecm",
 393                 [RISC_WRITECR >> 28] = "writecr",
 394         };
 395         static int incr[16] = {
 396                 [RISC_WRITE   >> 28] = 3,
 397                 [RISC_JUMP    >> 28] = 3,
 398                 [RISC_SKIP    >> 28] = 1,
 399                 [RISC_SYNC    >> 28] = 1,
 400                 [RISC_WRITERM >> 28] = 3,
 401                 [RISC_WRITECM >> 28] = 3,
 402                 [RISC_WRITECR >> 28] = 4,
 403         };
 404         static char *bits[] = {
 405                 "12",   "13",   "14",   "resync",
 406                 "cnt0", "cnt1", "18",   "19",
 407                 "20",   "21",   "22",   "23",
 408                 "irq1", "irq2", "eol",  "sol",
 409         };
 410         int i;
 411
 412         printk(KERN_DEBUG "0x%08x [ %s", risc,
 413                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 414         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
 415                 if (risc & (1 << (i + 12)))
 416                         pr_cont(" %s", bits[i]);
 417         pr_cont(" count=%d ]\n", risc & 0xfff);
 418         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 419 }
 420
 421 static void cx23885_wakeup(struct cx23885_tsport *port,
 422                            struct cx23885_dmaqueue *q, u32 count)
 423 {
 424         struct cx23885_buffer *buf;
 425
 426         if (list_empty(&q->active))
 427                 return;
 428         buf = list_entry(q->active.next,
 429                          struct cx23885_buffer, queue);
 430
 431         buf->vb.vb2_buf.timestamp = ktime_get_ns();
 432         buf->vb.sequence = q->count++;
 433         dprintk(1, "[%p/%d] wakeup reg=%d buf=%d\n", buf,
 434                 buf->vb.vb2_buf.index,
 435                 count, q->count);
 436         list_del(&buf->queue);
 437         vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
 438 }
 439
 440 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 441                                       struct sram_channel *ch,
 442                                       unsigned int bpl, u32 risc)
 443 {
 444         unsigned int i, lines;
 445         u32 cdt;
 446
 447         if (ch->cmds_start == 0) {
 448                 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
 449                         ch->name);
 450                 cx_write(ch->ptr1_reg, 0);
 451                 cx_write(ch->ptr2_reg, 0);
 452                 cx_write(ch->cnt2_reg, 0);
 453                 cx_write(ch->cnt1_reg, 0);
 454                 return 0;
 455         } else {
 456                 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
 457                         ch->name);
 458         }
 459
 460         bpl   = (bpl + 7) & ~7; /* alignment */
 461         cdt   = ch->cdt;
 462         lines = ch->fifo_size / bpl;
 463         if (lines > 6)
 464                 lines = 6;
 465         BUG_ON(lines < 2);
 466
 467         cx_write(8 + 0, RISC_JUMP | RISC_CNT_RESET);
 468         cx_write(8 + 4, 12);
 469         cx_write(8 + 8, 0);
 470
 471         /* write CDT */
 472         for (i = 0; i < lines; i++) {
 473                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
 474                         ch->fifo_start + bpl*i);
 475                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 476                 cx_write(cdt + 16*i +  4, 0);
 477                 cx_write(cdt + 16*i +  8, 0);
 478                 cx_write(cdt + 16*i + 12, 0);
 479         }
 480
 481         /* write CMDS */
 482         if (ch->jumponly)
 483                 cx_write(ch->cmds_start + 0, 8);
 484         else
 485                 cx_write(ch->cmds_start + 0, risc);
 486         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 487         cx_write(ch->cmds_start +  8, cdt);
 488         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 489         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 490         if (ch->jumponly)
 491                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
 492         else
 493                 cx_write(ch->cmds_start + 20, 64 >> 2);
 494         for (i = 24; i < 80; i += 4)
 495                 cx_write(ch->cmds_start + i, 0);
 496
 497         /* fill registers */
 498         cx_write(ch->ptr1_reg, ch->fifo_start);
 499         cx_write(ch->ptr2_reg, cdt);
 500         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 501         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
 502
 503         dprintk(2, "[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 504                 dev->bridge,
 505                 ch->name,
 506                 bpl,
 507                 lines);
 508
 509         return 0;
 510 }
 511
 512 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 513                                       struct sram_channel *ch)
 514 {
 515         static char *name[] = {
 516                 "init risc lo",
 517                 "init risc hi",
 518                 "cdt base",
 519                 "cdt size",
 520                 "iq base",
 521                 "iq size",
 522                 "risc pc lo",
 523                 "risc pc hi",
 524                 "iq wr ptr",
 525                 "iq rd ptr",
 526                 "cdt current",
 527                 "pci target lo",
 528                 "pci target hi",
 529                 "line / byte",
 530         };
 531         u32 risc;
 532         unsigned int i, j, n;
 533
 534         pr_warn("%s: %s - dma channel status dump\n",
 535                 dev->name, ch->name);
 536         for (i = 0; i < ARRAY_SIZE(name); i++)
 537                 pr_warn("%s:   cmds: %-15s: 0x%08x\n",
 538                         dev->name, name[i],
 539                         cx_read(ch->cmds_start + 4*i));
 540
 541         for (i = 0; i < 4; i++) {
 542                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 543                 pr_warn("%s:   risc%d: ", dev->name, i);
 544                 cx23885_risc_decode(risc);
 545         }
 546         for (i = 0; i < (64 >> 2); i += n) {
 547                 risc = cx_read(ch->ctrl_start + 4 * i);
 548                 /* No consideration for bits 63-32 */
 549
 550                 pr_warn("%s:   (0x%08x) iq %x: ", dev->name,
 551                         ch->ctrl_start + 4 * i, i);
 552                 n = cx23885_risc_decode(risc);
 553                 for (j = 1; j < n; j++) {
 554                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 555                         pr_warn("%s:   iq %x: 0x%08x [ arg #%d ]\n",
 556                                 dev->name, i+j, risc, j);
 557                 }
 558         }
 559
 560         pr_warn("%s: fifo: 0x%08x -> 0x%x\n",
 561                 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 562         pr_warn("%s: ctrl: 0x%08x -> 0x%x\n",
 563                 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
 564         pr_warn("%s:   ptr1_reg: 0x%08x\n",
 565                 dev->name, cx_read(ch->ptr1_reg));
 566         pr_warn("%s:   ptr2_reg: 0x%08x\n",
 567                 dev->name, cx_read(ch->ptr2_reg));
 568         pr_warn("%s:   cnt1_reg: 0x%08x\n",
 569                 dev->name, cx_read(ch->cnt1_reg));
 570         pr_warn("%s:   cnt2_reg: 0x%08x\n",
 571                 dev->name, cx_read(ch->cnt2_reg));
 572 }
 573
 574 static void cx23885_risc_disasm(struct cx23885_tsport *port,
 575                                 struct cx23885_riscmem *risc)
 576 {
 577         struct cx23885_dev *dev = port->dev;
 578         unsigned int i, j, n;
 579
 580         pr_info("%s: risc disasm: %p [dma=0x%08lx]\n",
 581                dev->name, risc->cpu, (unsigned long)risc->dma);
 582         for (i = 0; i < (risc->size >> 2); i += n) {
 583                 pr_info("%s:   %04d: ", dev->name, i);
 584                 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
 585                 for (j = 1; j < n; j++)
 586                         pr_info("%s:   %04d: 0x%08x [ arg #%d ]\n",
 587                                 dev->name, i + j, risc->cpu[i + j], j);
 588                 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
 589                         break;
 590         }
 591 }
 592
 593 static void cx23885_shutdown(struct cx23885_dev *dev)
 594 {
 595         /* disable RISC controller */
 596         cx_write(DEV_CNTRL2, 0);
 597
 598         /* Disable all IR activity */
 599         cx_write(IR_CNTRL_REG, 0);
 600
 601         /* Disable Video A/B activity */
 602         cx_write(VID_A_DMA_CTL, 0);
 603         cx_write(VID_B_DMA_CTL, 0);
 604         cx_write(VID_C_DMA_CTL, 0);
 605
 606         /* Disable Audio activity */
 607         cx_write(AUD_INT_DMA_CTL, 0);
 608         cx_write(AUD_EXT_DMA_CTL, 0);
 609
 610         /* Disable Serial port */
 611         cx_write(UART_CTL, 0);
 612
 613         /* Disable Interrupts */
 614         cx23885_irq_disable_all(dev);
 615         cx_write(VID_A_INT_MSK, 0);
 616         cx_write(VID_B_INT_MSK, 0);
 617         cx_write(VID_C_INT_MSK, 0);
 618         cx_write(AUDIO_INT_INT_MSK, 0);
 619         cx_write(AUDIO_EXT_INT_MSK, 0);
 620
 621 }
 622
 623 static void cx23885_reset(struct cx23885_dev *dev)
 624 {
 625         dprintk(1, "%s()\n", __func__);
 626
 627         cx23885_shutdown(dev);
 628
 629         cx_write(PCI_INT_STAT, 0xffffffff);
 630         cx_write(VID_A_INT_STAT, 0xffffffff);
 631         cx_write(VID_B_INT_STAT, 0xffffffff);
 632         cx_write(VID_C_INT_STAT, 0xffffffff);
 633         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 634         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 635         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 636         cx_write(PAD_CTRL, 0x00500300);
 637
 638         mdelay(100);
 639
 640         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
 641                 720*4, 0);
 642         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
 643         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
 644                 188*4, 0);
 645         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
 646         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
 647         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
 648                 188*4, 0);
 649         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
 650         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
 651         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
 652
 653         cx23885_gpio_setup(dev);
 654 }
 655
 656
 657 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 658 {
 659         dprintk(1, "%s()\n", __func__);
 660
 661         /* The cx23885 bridge has a weird bug which causes NMI to be asserted
 662          * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
 663          * occur on the cx23887 bridge.
 664          */
 665         if (dev->bridge == CX23885_BRIDGE_885)
 666                 cx_clear(RDR_TLCTL0, 1 << 4);
 667
 668         return 0;
 669 }
 670
 671 static int get_resources(struct cx23885_dev *dev)
 672 {
 673         if (request_mem_region(pci_resource_start(dev->pci, 0),
 674                                pci_resource_len(dev->pci, 0),
 675                                dev->name))
 676                 return 0;
 677
 678         pr_err("%s: can't get MMIO memory @ 0x%llx\n",
 679                dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
 680
 681         return -EBUSY;
 682 }
 683
 684 static int cx23885_init_tsport(struct cx23885_dev *dev,
 685         struct cx23885_tsport *port, int portno)
 686 {
 687         dprintk(1, "%s(portno=%d)\n", __func__, portno);
 688
 689         /* Transport bus init dma queue  - Common settings */
 690         port->dma_ctl_val        = 0x11; /* Enable RISC controller and Fifo */
 691         port->ts_int_msk_val     = 0x1111; /* TS port bits for RISC */
 692         port->vld_misc_val       = 0x0;
 693         port->hw_sop_ctrl_val    = (0x47 << 16 | 188 << 4);
 694
 695         spin_lock_init(&port->slock);
 696         port->dev = dev;
 697         port->nr = portno;
 698
 699         INIT_LIST_HEAD(&port->mpegq.active);
 700         mutex_init(&port->frontends.lock);
 701         INIT_LIST_HEAD(&port->frontends.felist);
 702         port->frontends.active_fe_id = 0;
 703
 704         /* This should be hardcoded allow a single frontend
 705          * attachment to this tsport, keeping the -dvb.c
 706          * code clean and safe.
 707          */
 708         if (!port->num_frontends)
 709                 port->num_frontends = 1;
 710
 711         switch (portno) {
 712         case 1:
 713                 port->reg_gpcnt          = VID_B_GPCNT;
 714                 port->reg_gpcnt_ctl      = VID_B_GPCNT_CTL;
 715                 port->reg_dma_ctl        = VID_B_DMA_CTL;
 716                 port->reg_lngth          = VID_B_LNGTH;
 717                 port->reg_hw_sop_ctrl    = VID_B_HW_SOP_CTL;
 718                 port->reg_gen_ctrl       = VID_B_GEN_CTL;
 719                 port->reg_bd_pkt_status  = VID_B_BD_PKT_STATUS;
 720                 port->reg_sop_status     = VID_B_SOP_STATUS;
 721                 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
 722                 port->reg_vld_misc       = VID_B_VLD_MISC;
 723                 port->reg_ts_clk_en      = VID_B_TS_CLK_EN;
 724                 port->reg_src_sel        = VID_B_SRC_SEL;
 725                 port->reg_ts_int_msk     = VID_B_INT_MSK;
 726                 port->reg_ts_int_stat    = VID_B_INT_STAT;
 727                 port->sram_chno          = SRAM_CH03; /* VID_B */
 728                 port->pci_irqmask        = 0x02; /* VID_B bit1 */
 729                 break;
 730         case 2:
 731                 port->reg_gpcnt          = VID_C_GPCNT;
 732                 port->reg_gpcnt_ctl      = VID_C_GPCNT_CTL;
 733                 port->reg_dma_ctl        = VID_C_DMA_CTL;
 734                 port->reg_lngth          = VID_C_LNGTH;
 735                 port->reg_hw_sop_ctrl    = VID_C_HW_SOP_CTL;
 736                 port->reg_gen_ctrl       = VID_C_GEN_CTL;
 737                 port->reg_bd_pkt_status  = VID_C_BD_PKT_STATUS;
 738                 port->reg_sop_status     = VID_C_SOP_STATUS;
 739                 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 740                 port->reg_vld_misc       = VID_C_VLD_MISC;
 741                 port->reg_ts_clk_en      = VID_C_TS_CLK_EN;
 742                 port->reg_src_sel        = 0;
 743                 port->reg_ts_int_msk     = VID_C_INT_MSK;
 744                 port->reg_ts_int_stat    = VID_C_INT_STAT;
 745                 port->sram_chno          = SRAM_CH06; /* VID_C */
 746                 port->pci_irqmask        = 0x04; /* VID_C bit2 */
 747                 break;
 748         default:
 749                 BUG();
 750         }
 751
 752         return 0;
 753 }
 754
 755 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
 756 {
 757         switch (cx_read(RDR_CFG2) & 0xff) {
 758         case 0x00:
 759                 /* cx23885 */
 760                 dev->hwrevision = 0xa0;
 761                 break;
 762         case 0x01:
 763                 /* CX23885-12Z */
 764                 dev->hwrevision = 0xa1;
 765                 break;
 766         case 0x02:
 767                 /* CX23885-13Z/14Z */
 768                 dev->hwrevision = 0xb0;
 769                 break;
 770         case 0x03:
 771                 if (dev->pci->device == 0x8880) {
 772                         /* CX23888-21Z/22Z */
 773                         dev->hwrevision = 0xc0;
 774                 } else {
 775                         /* CX23885-14Z */
 776                         dev->hwrevision = 0xa4;
 777                 }
 778                 break;
 779         case 0x04:
 780                 if (dev->pci->device == 0x8880) {
 781                         /* CX23888-31Z */
 782                         dev->hwrevision = 0xd0;
 783                 } else {
 784                         /* CX23885-15Z, CX23888-31Z */
 785                         dev->hwrevision = 0xa5;
 786                 }
 787                 break;
 788         case 0x0e:
 789                 /* CX23887-15Z */
 790                 dev->hwrevision = 0xc0;
 791                 break;
 792         case 0x0f:
 793                 /* CX23887-14Z */
 794                 dev->hwrevision = 0xb1;
 795                 break;
 796         default:
 797                 pr_err("%s() New hardware revision found 0x%x\n",
 798                        __func__, dev->hwrevision);
 799         }
 800         if (dev->hwrevision)
 801                 pr_info("%s() Hardware revision = 0x%02x\n",
 802                         __func__, dev->hwrevision);
 803         else
 804                 pr_err("%s() Hardware revision unknown 0x%x\n",
 805                        __func__, dev->hwrevision);
 806 }
 807
 808 /* Find the first v4l2_subdev member of the group id in hw */
 809 struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw)
 810 {
 811         struct v4l2_subdev *result = NULL;
 812         struct v4l2_subdev *sd;
 813
 814         spin_lock(&dev->v4l2_dev.lock);
 815         v4l2_device_for_each_subdev(sd, &dev->v4l2_dev) {
 816                 if (sd->grp_id == hw) {
 817                         result = sd;
 818                         break;
 819                 }
 820         }
 821         spin_unlock(&dev->v4l2_dev.lock);
 822         return result;
 823 }
 824
 825 static int cx23885_dev_setup(struct cx23885_dev *dev)
 826 {
 827         int i;
 828
 829         spin_lock_init(&dev->pci_irqmask_lock);
 830         spin_lock_init(&dev->slock);
 831
 832         mutex_init(&dev->lock);
 833         mutex_init(&dev->gpio_lock);
 834
 835         atomic_inc(&dev->refcount);
 836
 837         dev->nr = cx23885_devcount++;
 838         sprintf(dev->name, "cx23885[%d]", dev->nr);
 839
 840         /* Configure the internal memory */
 841         if (dev->pci->device == 0x8880) {
 842                 /* Could be 887 or 888, assume a default */
 843                 dev->bridge = CX23885_BRIDGE_887;
 844                 /* Apply a sensible clock frequency for the PCIe bridge */
 845                 dev->clk_freq = 25000000;
 846                 dev->sram_channels = cx23887_sram_channels;
 847         } else
 848         if (dev->pci->device == 0x8852) {
 849                 dev->bridge = CX23885_BRIDGE_885;
 850                 /* Apply a sensible clock frequency for the PCIe bridge */
 851                 dev->clk_freq = 28000000;
 852                 dev->sram_channels = cx23885_sram_channels;
 853         } else
 854                 BUG();
 855
 856         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
 857                 __func__, dev->bridge);
 858
 859         /* board config */
 860         dev->board = UNSET;
 861         if (card[dev->nr] < cx23885_bcount)
 862                 dev->board = card[dev->nr];
 863         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 864                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 865                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 866                         dev->board = cx23885_subids[i].card;
 867         if (UNSET == dev->board) {
 868                 dev->board = CX23885_BOARD_UNKNOWN;
 869                 cx23885_card_list(dev);
 870         }
 871
 872         /* If the user specific a clk freq override, apply it */
 873         if (cx23885_boards[dev->board].clk_freq > 0)
 874                 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
 875
 876         if (dev->board == CX23885_BOARD_HAUPPAUGE_IMPACTVCBE &&
 877                 dev->pci->subsystem_device == 0x7137) {
 878                 /* Hauppauge ImpactVCBe device ID 0x7137 is populated
 879                  * with an 888, and a 25Mhz crystal, instead of the
 880                  * usual third overtone 50Mhz. The default clock rate must
 881                  * be overridden so the cx25840 is properly configured
 882                  */
 883                 dev->clk_freq = 25000000;
 884         }
 885
 886         dev->pci_bus  = dev->pci->bus->number;
 887         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 888         cx23885_irq_add(dev, 0x001f00);
 889
 890         /* External Master 1 Bus */
 891         dev->i2c_bus[0].nr = 0;
 892         dev->i2c_bus[0].dev = dev;
 893         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 894         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 895         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 896         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 897         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 898         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 899
 900         /* External Master 2 Bus */
 901         dev->i2c_bus[1].nr = 1;
 902         dev->i2c_bus[1].dev = dev;
 903         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 904         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 905         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 906         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 907         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 908         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 909
 910         /* Internal Master 3 Bus */
 911         dev->i2c_bus[2].nr = 2;
 912         dev->i2c_bus[2].dev = dev;
 913         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 914         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 915         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 916         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 917         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 918         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 919
 920         if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
 921                 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
 922                 cx23885_init_tsport(dev, &dev->ts1, 1);
 923
 924         if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
 925                 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
 926                 cx23885_init_tsport(dev, &dev->ts2, 2);
 927
 928         if (get_resources(dev) < 0) {
 929                 pr_err("CORE %s No more PCIe resources for subsystem: %04x:%04x\n",
 930                        dev->name, dev->pci->subsystem_vendor,
 931                        dev->pci->subsystem_device);
 932
 933                 cx23885_devcount--;
 934                 return -ENODEV;
 935         }
 936
 937         /* PCIe stuff */
 938         dev->lmmio = ioremap(pci_resource_start(dev->pci, 0),
 939                              pci_resource_len(dev->pci, 0));
 940
 941         dev->bmmio = (u8 __iomem *)dev->lmmio;
 942
 943         pr_info("CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 944                 dev->name, dev->pci->subsystem_vendor,
 945                 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 946                 dev->board, card[dev->nr] == dev->board ?
 947                 "insmod option" : "autodetected");
 948
 949         cx23885_pci_quirks(dev);
 950
 951         /* Assume some sensible defaults */
 952         dev->tuner_type = cx23885_boards[dev->board].tuner_type;
 953         dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
 954         dev->tuner_bus = cx23885_boards[dev->board].tuner_bus;
 955         dev->radio_type = cx23885_boards[dev->board].radio_type;
 956         dev->radio_addr = cx23885_boards[dev->board].radio_addr;
 957
 958         dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x tuner_bus = %d\n",
 959                 __func__, dev->tuner_type, dev->tuner_addr, dev->tuner_bus);
 960         dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
 961                 __func__, dev->radio_type, dev->radio_addr);
 962
 963         /* The cx23417 encoder has GPIO's that need to be initialised
 964          * before DVB, so that demodulators and tuners are out of
 965          * reset before DVB uses them.
 966          */
 967         if ((cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) ||
 968                 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
 969                         cx23885_mc417_init(dev);
 970
 971         /* init hardware */
 972         cx23885_reset(dev);
 973
 974         cx23885_i2c_register(&dev->i2c_bus[0]);
 975         cx23885_i2c_register(&dev->i2c_bus[1]);
 976         cx23885_i2c_register(&dev->i2c_bus[2]);
 977         cx23885_card_setup(dev);
 978         call_all(dev, core, s_power, 0);
 979         cx23885_ir_init(dev);
 980
 981         if (dev->board == CX23885_BOARD_VIEWCAST_460E) {
 982                 /*
 983                  * GPIOs 9/8 are input detection bits for the breakout video
 984                  * (gpio 8) and audio (gpio 9) cables. When they're attached,
 985                  * this gpios are pulled high. Make sure these GPIOs are marked
 986                  * as inputs.
 987                  */
 988                 cx23885_gpio_enable(dev, 0x300, 0);
 989         }
 990
 991         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
 992                 if (cx23885_video_register(dev) < 0) {
 993                         pr_err("%s() Failed to register analog video adapters on VID_A\n",
 994                                __func__);
 995                 }
 996         }
 997
 998         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
 999                 if (cx23885_boards[dev->board].num_fds_portb)
1000                         dev->ts1.num_frontends =
1001                                 cx23885_boards[dev->board].num_fds_portb;
1002                 if (cx23885_dvb_register(&dev->ts1) < 0) {
1003                         pr_err("%s() Failed to register dvb adapters on VID_B\n",
1004                                __func__);
1005                 }
1006         } else
1007         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1008                 if (cx23885_417_register(dev) < 0) {
1009                         pr_err("%s() Failed to register 417 on VID_B\n",
1010                                __func__);
1011                 }
1012         }
1013
1014         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1015                 if (cx23885_boards[dev->board].num_fds_portc)
1016                         dev->ts2.num_frontends =
1017                                 cx23885_boards[dev->board].num_fds_portc;
1018                 if (cx23885_dvb_register(&dev->ts2) < 0) {
1019                         pr_err("%s() Failed to register dvb on VID_C\n",
1020                                __func__);
1021                 }
1022         } else
1023         if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
1024                 if (cx23885_417_register(dev) < 0) {
1025                         pr_err("%s() Failed to register 417 on VID_C\n",
1026                                __func__);
1027                 }
1028         }
1029
1030         cx23885_dev_checkrevision(dev);
1031
1032         /* disable MSI for NetUP cards, otherwise CI is not working */
1033         if (cx23885_boards[dev->board].ci_type > 0)
1034                 cx_clear(RDR_RDRCTL1, 1 << 8);
1035
1036         switch (dev->board) {
1037         case CX23885_BOARD_TEVII_S470:
1038         case CX23885_BOARD_TEVII_S471:
1039                 cx_clear(RDR_RDRCTL1, 1 << 8);
1040                 break;
1041         }
1042
1043         return 0;
1044 }
1045
1046 static void cx23885_dev_unregister(struct cx23885_dev *dev)
1047 {
1048         release_mem_region(pci_resource_start(dev->pci, 0),
1049                            pci_resource_len(dev->pci, 0));
1050
1051         if (!atomic_dec_and_test(&dev->refcount))
1052                 return;
1053
1054         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
1055                 cx23885_video_unregister(dev);
1056
1057         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1058                 cx23885_dvb_unregister(&dev->ts1);
1059
1060         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1061                 cx23885_417_unregister(dev);
1062
1063         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1064                 cx23885_dvb_unregister(&dev->ts2);
1065
1066         if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1067                 cx23885_417_unregister(dev);
1068
1069         cx23885_i2c_unregister(&dev->i2c_bus[2]);
1070         cx23885_i2c_unregister(&dev->i2c_bus[1]);
1071         cx23885_i2c_unregister(&dev->i2c_bus[0]);
1072
1073         iounmap(dev->lmmio);
1074 }
1075
1076 static __le32 *cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
1077                                unsigned int offset, u32 sync_line,
1078                                unsigned int bpl, unsigned int padding,
1079                                unsigned int lines,  unsigned int lpi, bool jump)
1080 {
1081         struct scatterlist *sg;
1082         unsigned int line, todo, sol;
1083
1084
1085         if (jump) {
1086                 *(rp++) = cpu_to_le32(RISC_JUMP);
1087                 *(rp++) = cpu_to_le32(0);
1088                 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1089         }
1090
1091         /* sync instruction */
1092         if (sync_line != NO_SYNC_LINE)
1093                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1094
1095         /* scan lines */
1096         sg = sglist;
1097         for (line = 0; line < lines; line++) {
1098                 while (offset && offset >= sg_dma_len(sg)) {
1099                         offset -= sg_dma_len(sg);
1100                         sg = sg_next(sg);
1101                 }
1102
1103                 if (lpi && line > 0 && !(line % lpi))
1104                         sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
1105                 else
1106                         sol = RISC_SOL;
1107
1108                 if (bpl <= sg_dma_len(sg)-offset) {
1109                         /* fits into current chunk */
1110                         *(rp++) = cpu_to_le32(RISC_WRITE|sol|RISC_EOL|bpl);
1111                         *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1112                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1113                         offset += bpl;
1114                 } else {
1115                         /* scanline needs to be split */
1116                         todo = bpl;
1117                         *(rp++) = cpu_to_le32(RISC_WRITE|sol|
1118                                             (sg_dma_len(sg)-offset));
1119                         *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1120                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1121                         todo -= (sg_dma_len(sg)-offset);
1122                         offset = 0;
1123                         sg = sg_next(sg);
1124                         while (todo > sg_dma_len(sg)) {
1125                                 *(rp++) = cpu_to_le32(RISC_WRITE|
1126                                                     sg_dma_len(sg));
1127                                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1128                                 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1129                                 todo -= sg_dma_len(sg);
1130                                 sg = sg_next(sg);
1131                         }
1132                         *(rp++) = cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
1133                         *(rp++) = cpu_to_le32(sg_dma_address(sg));
1134                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1135                         offset += todo;
1136                 }
1137                 offset += padding;
1138         }
1139
1140         return rp;
1141 }
1142
1143 int cx23885_risc_buffer(struct pci_dev *pci, struct cx23885_riscmem *risc,
1144                         struct scatterlist *sglist, unsigned int top_offset,
1145                         unsigned int bottom_offset, unsigned int bpl,
1146                         unsigned int padding, unsigned int lines)
1147 {
1148         u32 instructions, fields;
1149         __le32 *rp;
1150
1151         fields = 0;
1152         if (UNSET != top_offset)
1153                 fields++;
1154         if (UNSET != bottom_offset)
1155                 fields++;
1156
1157         /* estimate risc mem: worst case is one write per page border +
1158            one write per scan line + syncs + jump (all 2 dwords).  Padding
1159            can cause next bpl to start close to a page border.  First DMA
1160            region may be smaller than PAGE_SIZE */
1161         /* write and jump need and extra dword */
1162         instructions  = fields * (1 + ((bpl + padding) * lines)
1163                 / PAGE_SIZE + lines);
1164         instructions += 5;
1165         risc->size = instructions * 12;
1166         risc->cpu = pci_alloc_consistent(pci, risc->size, &risc->dma);
1167         if (risc->cpu == NULL)
1168                 return -ENOMEM;
1169
1170         /* write risc instructions */
1171         rp = risc->cpu;
1172         if (UNSET != top_offset)
1173                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1174                                         bpl, padding, lines, 0, true);
1175         if (UNSET != bottom_offset)
1176                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1177                                         bpl, padding, lines, 0, UNSET == top_offset);
1178
1179         /* save pointer to jmp instruction address */
1180         risc->jmp = rp;
1181         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1182         return 0;
1183 }
1184
1185 int cx23885_risc_databuffer(struct pci_dev *pci,
1186                                    struct cx23885_riscmem *risc,
1187                                    struct scatterlist *sglist,
1188                                    unsigned int bpl,
1189                                    unsigned int lines, unsigned int lpi)
1190 {
1191         u32 instructions;
1192         __le32 *rp;
1193
1194         /* estimate risc mem: worst case is one write per page border +
1195            one write per scan line + syncs + jump (all 2 dwords).  Here
1196            there is no padding and no sync.  First DMA region may be smaller
1197            than PAGE_SIZE */
1198         /* Jump and write need an extra dword */
1199         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
1200         instructions += 4;
1201
1202         risc->size = instructions * 12;
1203         risc->cpu = pci_alloc_consistent(pci, risc->size, &risc->dma);
1204         if (risc->cpu == NULL)
1205                 return -ENOMEM;
1206
1207         /* write risc instructions */
1208         rp = risc->cpu;
1209         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE,
1210                                 bpl, 0, lines, lpi, lpi == 0);
1211
1212         /* save pointer to jmp instruction address */
1213         risc->jmp = rp;
1214         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1215         return 0;
1216 }
1217
1218 int cx23885_risc_vbibuffer(struct pci_dev *pci, struct cx23885_riscmem *risc,
1219                         struct scatterlist *sglist, unsigned int top_offset,
1220                         unsigned int bottom_offset, unsigned int bpl,
1221                         unsigned int padding, unsigned int lines)
1222 {
1223         u32 instructions, fields;
1224         __le32 *rp;
1225
1226         fields = 0;
1227         if (UNSET != top_offset)
1228                 fields++;
1229         if (UNSET != bottom_offset)
1230                 fields++;
1231
1232         /* estimate risc mem: worst case is one write per page border +
1233            one write per scan line + syncs + jump (all 2 dwords).  Padding
1234            can cause next bpl to start close to a page border.  First DMA
1235            region may be smaller than PAGE_SIZE */
1236         /* write and jump need and extra dword */
1237         instructions  = fields * (1 + ((bpl + padding) * lines)
1238                 / PAGE_SIZE + lines);
1239         instructions += 5;
1240         risc->size = instructions * 12;
1241         risc->cpu = pci_alloc_consistent(pci, risc->size, &risc->dma);
1242         if (risc->cpu == NULL)
1243                 return -ENOMEM;
1244         /* write risc instructions */
1245         rp = risc->cpu;
1246
1247         /* Sync to line 6, so US CC line 21 will appear in line '12'
1248          * in the userland vbi payload */
1249         if (UNSET != top_offset)
1250                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1251                                         bpl, padding, lines, 0, true);
1252
1253         if (UNSET != bottom_offset)
1254                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1255                                         bpl, padding, lines, 0, UNSET == top_offset);
1256
1257
1258
1259         /* save pointer to jmp instruction address */
1260         risc->jmp = rp;
1261         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1262         return 0;
1263 }
1264
1265
1266 void cx23885_free_buffer(struct cx23885_dev *dev, struct cx23885_buffer *buf)
1267 {
1268         struct cx23885_riscmem *risc = &buf->risc;
1269
1270         BUG_ON(in_interrupt());
1271         pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma);
1272 }
1273
1274 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1275 {
1276         struct cx23885_dev *dev = port->dev;
1277
1278         dprintk(1, "%s() Register Dump\n", __func__);
1279         dprintk(1, "%s() DEV_CNTRL2               0x%08X\n", __func__,
1280                 cx_read(DEV_CNTRL2));
1281         dprintk(1, "%s() PCI_INT_MSK              0x%08X\n", __func__,
1282                 cx23885_irq_get_mask(dev));
1283         dprintk(1, "%s() AUD_INT_INT_MSK          0x%08X\n", __func__,
1284                 cx_read(AUDIO_INT_INT_MSK));
1285         dprintk(1, "%s() AUD_INT_DMA_CTL          0x%08X\n", __func__,
1286                 cx_read(AUD_INT_DMA_CTL));
1287         dprintk(1, "%s() AUD_EXT_INT_MSK          0x%08X\n", __func__,
1288                 cx_read(AUDIO_EXT_INT_MSK));
1289         dprintk(1, "%s() AUD_EXT_DMA_CTL          0x%08X\n", __func__,
1290                 cx_read(AUD_EXT_DMA_CTL));
1291         dprintk(1, "%s() PAD_CTRL                 0x%08X\n", __func__,
1292                 cx_read(PAD_CTRL));
1293         dprintk(1, "%s() ALT_PIN_OUT_SEL          0x%08X\n", __func__,
1294                 cx_read(ALT_PIN_OUT_SEL));
1295         dprintk(1, "%s() GPIO2                    0x%08X\n", __func__,
1296                 cx_read(GPIO2));
1297         dprintk(1, "%s() gpcnt(0x%08X)          0x%08X\n", __func__,
1298                 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1299         dprintk(1, "%s() gpcnt_ctl(0x%08X)      0x%08x\n", __func__,
1300                 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1301         dprintk(1, "%s() dma_ctl(0x%08X)        0x%08x\n", __func__,
1302                 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1303         if (port->reg_src_sel)
1304                 dprintk(1, "%s() src_sel(0x%08X)        0x%08x\n", __func__,
1305                         port->reg_src_sel, cx_read(port->reg_src_sel));
1306         dprintk(1, "%s() lngth(0x%08X)          0x%08x\n", __func__,
1307                 port->reg_lngth, cx_read(port->reg_lngth));
1308         dprintk(1, "%s() hw_sop_ctrl(0x%08X)    0x%08x\n", __func__,
1309                 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1310         dprintk(1, "%s() gen_ctrl(0x%08X)       0x%08x\n", __func__,
1311                 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1312         dprintk(1, "%s() bd_pkt_status(0x%08X)  0x%08x\n", __func__,
1313                 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1314         dprintk(1, "%s() sop_status(0x%08X)     0x%08x\n", __func__,
1315                 port->reg_sop_status, cx_read(port->reg_sop_status));
1316         dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1317                 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1318         dprintk(1, "%s() vld_misc(0x%08X)       0x%08x\n", __func__,
1319                 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1320         dprintk(1, "%s() ts_clk_en(0x%08X)      0x%08x\n", __func__,
1321                 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1322         dprintk(1, "%s() ts_int_msk(0x%08X)     0x%08x\n", __func__,
1323                 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1324 }
1325
1326 int cx23885_start_dma(struct cx23885_tsport *port,
1327                              struct cx23885_dmaqueue *q,
1328                              struct cx23885_buffer   *buf)
1329 {
1330         struct cx23885_dev *dev = port->dev;
1331         u32 reg;
1332
1333         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1334                 dev->width, dev->height, dev->field);
1335
1336         /* Stop the fifo and risc engine for this port */
1337         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1338
1339         /* setup fifo + format */
1340         cx23885_sram_channel_setup(dev,
1341                                    &dev->sram_channels[port->sram_chno],
1342                                    port->ts_packet_size, buf->risc.dma);
1343         if (debug > 5) {
1344                 cx23885_sram_channel_dump(dev,
1345                         &dev->sram_channels[port->sram_chno]);
1346                 cx23885_risc_disasm(port, &buf->risc);
1347         }
1348
1349         /* write TS length to chip */
1350         cx_write(port->reg_lngth, port->ts_packet_size);
1351
1352         if ((!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1353                 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB))) {
1354                 pr_err("%s() Unsupported .portb/c (0x%08x)/(0x%08x)\n",
1355                         __func__,
1356                         cx23885_boards[dev->board].portb,
1357                         cx23885_boards[dev->board].portc);
1358                 return -EINVAL;
1359         }
1360
1361         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1362                 cx23885_av_clk(dev, 0);
1363
1364         udelay(100);
1365
1366         /* If the port supports SRC SELECT, configure it */
1367         if (port->reg_src_sel)
1368                 cx_write(port->reg_src_sel, port->src_sel_val);
1369
1370         cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
1371         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1372         cx_write(port->reg_vld_misc, port->vld_misc_val);
1373         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1374         udelay(100);
1375
1376         /* NOTE: this is 2 (reserved) for portb, does it matter? */
1377         /* reset counter to zero */
1378         cx_write(port->reg_gpcnt_ctl, 3);
1379         q->count = 0;
1380
1381         /* Set VIDB pins to input */
1382         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1383                 reg = cx_read(PAD_CTRL);
1384                 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1385                 cx_write(PAD_CTRL, reg);
1386         }
1387
1388         /* Set VIDC pins to input */
1389         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1390                 reg = cx_read(PAD_CTRL);
1391                 reg &= ~0x4; /* Clear TS2_SOP_OE */
1392                 cx_write(PAD_CTRL, reg);
1393         }
1394
1395         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1396
1397                 reg = cx_read(PAD_CTRL);
1398                 reg = reg & ~0x1;    /* Clear TS1_OE */
1399
1400                 /* FIXME, bit 2 writing here is questionable */
1401                 /* set TS1_SOP_OE and TS1_OE_HI */
1402                 reg = reg | 0xa;
1403                 cx_write(PAD_CTRL, reg);
1404
1405                 /* FIXME and these two registers should be documented. */
1406                 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1407                 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1408         }
1409
1410         switch (dev->bridge) {
1411         case CX23885_BRIDGE_885:
1412         case CX23885_BRIDGE_887:
1413         case CX23885_BRIDGE_888:
1414                 /* enable irqs */
1415                 dprintk(1, "%s() enabling TS int's and DMA\n", __func__);
1416                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1417                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1418                 cx23885_irq_add(dev, port->pci_irqmask);
1419                 cx23885_irq_enable_all(dev);
1420                 break;
1421         default:
1422                 BUG();
1423         }
1424
1425         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1426
1427         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1428                 cx23885_av_clk(dev, 1);
1429
1430         if (debug > 4)
1431                 cx23885_tsport_reg_dump(port);
1432
1433         return 0;
1434 }
1435
1436 static int cx23885_stop_dma(struct cx23885_tsport *port)
1437 {
1438         struct cx23885_dev *dev = port->dev;
1439         u32 reg;
1440
1441         dprintk(1, "%s()\n", __func__);
1442
1443         /* Stop interrupts and DMA */
1444         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1445         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1446
1447         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1448
1449                 reg = cx_read(PAD_CTRL);
1450
1451                 /* Set TS1_OE */
1452                 reg = reg | 0x1;
1453
1454                 /* clear TS1_SOP_OE and TS1_OE_HI */
1455                 reg = reg & ~0xa;
1456                 cx_write(PAD_CTRL, reg);
1457                 cx_write(port->reg_src_sel, 0);
1458                 cx_write(port->reg_gen_ctrl, 8);
1459
1460         }
1461
1462         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1463                 cx23885_av_clk(dev, 0);
1464
1465         return 0;
1466 }
1467
1468 /* ------------------------------------------------------------------ */
1469
1470 int cx23885_buf_prepare(struct cx23885_buffer *buf, struct cx23885_tsport *port)
1471 {
1472         struct cx23885_dev *dev = port->dev;
1473         int size = port->ts_packet_size * port->ts_packet_count;
1474         struct sg_table *sgt = vb2_dma_sg_plane_desc(&buf->vb.vb2_buf, 0);
1475
1476         dprintk(1, "%s: %p\n", __func__, buf);
1477         if (vb2_plane_size(&buf->vb.vb2_buf, 0) < size)
1478                 return -EINVAL;
1479         vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
1480
1481         cx23885_risc_databuffer(dev->pci, &buf->risc,
1482                                 sgt->sgl,
1483                                 port->ts_packet_size, port->ts_packet_count, 0);
1484         return 0;
1485 }
1486
1487 /*
1488  * The risc program for each buffer works as follows: it starts with a simple
1489  * 'JUMP to addr + 12', which is effectively a NOP. Then the code to DMA the
1490  * buffer follows and at the end we have a JUMP back to the start + 12 (skipping
1491  * the initial JUMP).
1492  *
1493  * This is the risc program of the first buffer to be queued if the active list
1494  * is empty and it just keeps DMAing this buffer without generating any
1495  * interrupts.
1496  *
1497  * If a new buffer is added then the initial JUMP in the code for that buffer
1498  * will generate an interrupt which signals that the previous buffer has been
1499  * DMAed successfully and that it can be returned to userspace.
1500  *
1501  * It also sets the final jump of the previous buffer to the start of the new
1502  * buffer, thus chaining the new buffer into the DMA chain. This is a single
1503  * atomic u32 write, so there is no race condition.
1504  *
1505  * The end-result of all this that you only get an interrupt when a buffer
1506  * is ready, so the control flow is very easy.
1507  */
1508 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1509 {
1510         struct cx23885_buffer    *prev;
1511         struct cx23885_dev *dev = port->dev;
1512         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1513         unsigned long flags;
1514
1515         buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12);
1516         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
1517         buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12);
1518         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1519
1520         spin_lock_irqsave(&dev->slock, flags);
1521         if (list_empty(&cx88q->active)) {
1522                 list_add_tail(&buf->queue, &cx88q->active);
1523                 dprintk(1, "[%p/%d] %s - first active\n",
1524                         buf, buf->vb.vb2_buf.index, __func__);
1525         } else {
1526                 buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
1527                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1528                                   queue);
1529                 list_add_tail(&buf->queue, &cx88q->active);
1530                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1531                 dprintk(1, "[%p/%d] %s - append to active\n",
1532                          buf, buf->vb.vb2_buf.index, __func__);
1533         }
1534         spin_unlock_irqrestore(&dev->slock, flags);
1535 }
1536
1537 /* ----------------------------------------------------------- */
1538
1539 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason)
1540 {
1541         struct cx23885_dmaqueue *q = &port->mpegq;
1542         struct cx23885_buffer *buf;
1543         unsigned long flags;
1544
1545         spin_lock_irqsave(&port->slock, flags);
1546         while (!list_empty(&q->active)) {
1547                 buf = list_entry(q->active.next, struct cx23885_buffer,
1548                                  queue);
1549                 list_del(&buf->queue);
1550                 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1551                 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1552                         buf, buf->vb.vb2_buf.index, reason,
1553                         (unsigned long)buf->risc.dma);
1554         }
1555         spin_unlock_irqrestore(&port->slock, flags);
1556 }
1557
1558 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1559 {
1560         dprintk(1, "%s()\n", __func__);
1561         cx23885_stop_dma(port);
1562         do_cancel_buffers(port, "cancel");
1563 }
1564
1565 int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1566 {
1567         /* FIXME: port1 assumption here. */
1568         struct cx23885_tsport *port = &dev->ts1;
1569         int count = 0;
1570         int handled = 0;
1571
1572         if (status == 0)
1573                 return handled;
1574
1575         count = cx_read(port->reg_gpcnt);
1576         dprintk(7, "status: 0x%08x  mask: 0x%08x count: 0x%x\n",
1577                 status, cx_read(port->reg_ts_int_msk), count);
1578
1579         if ((status & VID_B_MSK_BAD_PKT)         ||
1580                 (status & VID_B_MSK_OPC_ERR)     ||
1581                 (status & VID_B_MSK_VBI_OPC_ERR) ||
1582                 (status & VID_B_MSK_SYNC)        ||
1583                 (status & VID_B_MSK_VBI_SYNC)    ||
1584                 (status & VID_B_MSK_OF)          ||
1585                 (status & VID_B_MSK_VBI_OF)) {
1586                 pr_err("%s: V4L mpeg risc op code error, status = 0x%x\n",
1587                        dev->name, status);
1588                 if (status & VID_B_MSK_BAD_PKT)
1589                         dprintk(1, "        VID_B_MSK_BAD_PKT\n");
1590                 if (status & VID_B_MSK_OPC_ERR)
1591                         dprintk(1, "        VID_B_MSK_OPC_ERR\n");
1592                 if (status & VID_B_MSK_VBI_OPC_ERR)
1593                         dprintk(1, "        VID_B_MSK_VBI_OPC_ERR\n");
1594                 if (status & VID_B_MSK_SYNC)
1595                         dprintk(1, "        VID_B_MSK_SYNC\n");
1596                 if (status & VID_B_MSK_VBI_SYNC)
1597                         dprintk(1, "        VID_B_MSK_VBI_SYNC\n");
1598                 if (status & VID_B_MSK_OF)
1599                         dprintk(1, "        VID_B_MSK_OF\n");
1600                 if (status & VID_B_MSK_VBI_OF)
1601                         dprintk(1, "        VID_B_MSK_VBI_OF\n");
1602
1603                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1604                 cx23885_sram_channel_dump(dev,
1605                         &dev->sram_channels[port->sram_chno]);
1606                 cx23885_417_check_encoder(dev);
1607         } else if (status & VID_B_MSK_RISCI1) {
1608                 dprintk(7, "        VID_B_MSK_RISCI1\n");
1609                 spin_lock(&port->slock);
1610                 cx23885_wakeup(port, &port->mpegq, count);
1611                 spin_unlock(&port->slock);
1612         }
1613         if (status) {
1614                 cx_write(port->reg_ts_int_stat, status);
1615                 handled = 1;
1616         }
1617
1618         return handled;
1619 }
1620
1621 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1622 {
1623         struct cx23885_dev *dev = port->dev;
1624         int handled = 0;
1625         u32 count;
1626
1627         if ((status & VID_BC_MSK_OPC_ERR) ||
1628                 (status & VID_BC_MSK_BAD_PKT) ||
1629                 (status & VID_BC_MSK_SYNC) ||
1630                 (status & VID_BC_MSK_OF)) {
1631
1632                 if (status & VID_BC_MSK_OPC_ERR)
1633                         dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n",
1634                                 VID_BC_MSK_OPC_ERR);
1635
1636                 if (status & VID_BC_MSK_BAD_PKT)
1637                         dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n",
1638                                 VID_BC_MSK_BAD_PKT);
1639
1640                 if (status & VID_BC_MSK_SYNC)
1641                         dprintk(7, " (VID_BC_MSK_SYNC    0x%08x)\n",
1642                                 VID_BC_MSK_SYNC);
1643
1644                 if (status & VID_BC_MSK_OF)
1645                         dprintk(7, " (VID_BC_MSK_OF      0x%08x)\n",
1646                                 VID_BC_MSK_OF);
1647
1648                 pr_err("%s: mpeg risc op code error\n", dev->name);
1649
1650                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1651                 cx23885_sram_channel_dump(dev,
1652                         &dev->sram_channels[port->sram_chno]);
1653
1654         } else if (status & VID_BC_MSK_RISCI1) {
1655
1656                 dprintk(7, " (RISCI1            0x%08x)\n", VID_BC_MSK_RISCI1);
1657
1658                 spin_lock(&port->slock);
1659                 count = cx_read(port->reg_gpcnt);
1660                 cx23885_wakeup(port, &port->mpegq, count);
1661                 spin_unlock(&port->slock);
1662
1663         }
1664         if (status) {
1665                 cx_write(port->reg_ts_int_stat, status);
1666                 handled = 1;
1667         }
1668
1669         return handled;
1670 }
1671
1672 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1673 {
1674         struct cx23885_dev *dev = dev_id;
1675         struct cx23885_tsport *ts1 = &dev->ts1;
1676         struct cx23885_tsport *ts2 = &dev->ts2;
1677         u32 pci_status, pci_mask;
1678         u32 vida_status, vida_mask;
1679         u32 audint_status, audint_mask;
1680         u32 ts1_status, ts1_mask;
1681         u32 ts2_status, ts2_mask;
1682         int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1683         int audint_count = 0;
1684         bool subdev_handled;
1685
1686         pci_status = cx_read(PCI_INT_STAT);
1687         pci_mask = cx23885_irq_get_mask(dev);
1688         vida_status = cx_read(VID_A_INT_STAT);
1689         vida_mask = cx_read(VID_A_INT_MSK);
1690         audint_status = cx_read(AUDIO_INT_INT_STAT);
1691         audint_mask = cx_read(AUDIO_INT_INT_MSK);
1692         ts1_status = cx_read(VID_B_INT_STAT);
1693         ts1_mask = cx_read(VID_B_INT_MSK);
1694         ts2_status = cx_read(VID_C_INT_STAT);
1695         ts2_mask = cx_read(VID_C_INT_MSK);
1696
1697         if ((pci_status == 0) && (ts2_status == 0) && (ts1_status == 0))
1698                 goto out;
1699
1700         vida_count = cx_read(VID_A_GPCNT);
1701         audint_count = cx_read(AUD_INT_A_GPCNT);
1702         ts1_count = cx_read(ts1->reg_gpcnt);
1703         ts2_count = cx_read(ts2->reg_gpcnt);
1704         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n",
1705                 pci_status, pci_mask);
1706         dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1707                 vida_status, vida_mask, vida_count);
1708         dprintk(7, "audint_status: 0x%08x audint_mask: 0x%08x count: 0x%x\n",
1709                 audint_status, audint_mask, audint_count);
1710         dprintk(7, "ts1_status: 0x%08x  ts1_mask: 0x%08x count: 0x%x\n",
1711                 ts1_status, ts1_mask, ts1_count);
1712         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n",
1713                 ts2_status, ts2_mask, ts2_count);
1714
1715         if (pci_status & (PCI_MSK_RISC_RD | PCI_MSK_RISC_WR |
1716                           PCI_MSK_AL_RD   | PCI_MSK_AL_WR   | PCI_MSK_APB_DMA |
1717                           PCI_MSK_VID_C   | PCI_MSK_VID_B   | PCI_MSK_VID_A   |
1718                           PCI_MSK_AUD_INT | PCI_MSK_AUD_EXT |
1719                           PCI_MSK_GPIO0   | PCI_MSK_GPIO1   |
1720                           PCI_MSK_AV_CORE | PCI_MSK_IR)) {
1721
1722                 if (pci_status & PCI_MSK_RISC_RD)
1723                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n",
1724                                 PCI_MSK_RISC_RD);
1725
1726                 if (pci_status & PCI_MSK_RISC_WR)
1727                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n",
1728                                 PCI_MSK_RISC_WR);
1729
1730                 if (pci_status & PCI_MSK_AL_RD)
1731                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n",
1732                                 PCI_MSK_AL_RD);
1733
1734                 if (pci_status & PCI_MSK_AL_WR)
1735                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n",
1736                                 PCI_MSK_AL_WR);
1737
1738                 if (pci_status & PCI_MSK_APB_DMA)
1739                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n",
1740                                 PCI_MSK_APB_DMA);
1741
1742                 if (pci_status & PCI_MSK_VID_C)
1743                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n",
1744                                 PCI_MSK_VID_C);
1745
1746                 if (pci_status & PCI_MSK_VID_B)
1747                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n",
1748                                 PCI_MSK_VID_B);
1749
1750                 if (pci_status & PCI_MSK_VID_A)
1751                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n",
1752                                 PCI_MSK_VID_A);
1753
1754                 if (pci_status & PCI_MSK_AUD_INT)
1755                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n",
1756                                 PCI_MSK_AUD_INT);
1757
1758                 if (pci_status & PCI_MSK_AUD_EXT)
1759                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n",
1760                                 PCI_MSK_AUD_EXT);
1761
1762                 if (pci_status & PCI_MSK_GPIO0)
1763                         dprintk(7, " (PCI_MSK_GPIO0     0x%08x)\n",
1764                                 PCI_MSK_GPIO0);
1765
1766                 if (pci_status & PCI_MSK_GPIO1)
1767                         dprintk(7, " (PCI_MSK_GPIO1     0x%08x)\n",
1768                                 PCI_MSK_GPIO1);
1769
1770                 if (pci_status & PCI_MSK_AV_CORE)
1771                         dprintk(7, " (PCI_MSK_AV_CORE   0x%08x)\n",
1772                                 PCI_MSK_AV_CORE);
1773
1774                 if (pci_status & PCI_MSK_IR)
1775                         dprintk(7, " (PCI_MSK_IR        0x%08x)\n",
1776                                 PCI_MSK_IR);
1777         }
1778
1779         if (cx23885_boards[dev->board].ci_type == 1 &&
1780                         (pci_status & (PCI_MSK_GPIO1 | PCI_MSK_GPIO0)))
1781                 handled += netup_ci_slot_status(dev, pci_status);
1782
1783         if (cx23885_boards[dev->board].ci_type == 2 &&
1784                         (pci_status & PCI_MSK_GPIO0))
1785                 handled += altera_ci_irq(dev);
1786
1787         if (ts1_status) {
1788                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1789                         handled += cx23885_irq_ts(ts1, ts1_status);
1790                 else
1791                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1792                         handled += cx23885_irq_417(dev, ts1_status);
1793         }
1794
1795         if (ts2_status) {
1796                 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1797                         handled += cx23885_irq_ts(ts2, ts2_status);
1798                 else
1799                 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1800                         handled += cx23885_irq_417(dev, ts2_status);
1801         }
1802
1803         if (vida_status)
1804                 handled += cx23885_video_irq(dev, vida_status);
1805
1806         if (audint_status)
1807                 handled += cx23885_audio_irq(dev, audint_status, audint_mask);
1808
1809         if (pci_status & PCI_MSK_IR) {
1810                 subdev_handled = false;
1811                 v4l2_subdev_call(dev->sd_ir, core, interrupt_service_routine,
1812                                  pci_status, &subdev_handled);
1813                 if (subdev_handled)
1814                         handled++;
1815         }
1816
1817         if ((pci_status & pci_mask) & PCI_MSK_AV_CORE) {
1818                 cx23885_irq_disable(dev, PCI_MSK_AV_CORE);
1819                 schedule_work(&dev->cx25840_work);
1820                 handled++;
1821         }
1822
1823         if (handled)
1824                 cx_write(PCI_INT_STAT, pci_status);
1825 out:
1826         return IRQ_RETVAL(handled);
1827 }
1828
1829 static void cx23885_v4l2_dev_notify(struct v4l2_subdev *sd,
1830                                     unsigned int notification, void *arg)
1831 {
1832         struct cx23885_dev *dev;
1833
1834         if (sd == NULL)
1835                 return;
1836
1837         dev = to_cx23885(sd->v4l2_dev);
1838
1839         switch (notification) {
1840         case V4L2_SUBDEV_IR_RX_NOTIFY: /* Possibly called in an IRQ context */
1841                 if (sd == dev->sd_ir)
1842                         cx23885_ir_rx_v4l2_dev_notify(sd, *(u32 *)arg);
1843                 break;
1844         case V4L2_SUBDEV_IR_TX_NOTIFY: /* Possibly called in an IRQ context */
1845                 if (sd == dev->sd_ir)
1846                         cx23885_ir_tx_v4l2_dev_notify(sd, *(u32 *)arg);
1847                 break;
1848         }
1849 }
1850
1851 static void cx23885_v4l2_dev_notify_init(struct cx23885_dev *dev)
1852 {
1853         INIT_WORK(&dev->cx25840_work, cx23885_av_work_handler);
1854         INIT_WORK(&dev->ir_rx_work, cx23885_ir_rx_work_handler);
1855         INIT_WORK(&dev->ir_tx_work, cx23885_ir_tx_work_handler);
1856         dev->v4l2_dev.notify = cx23885_v4l2_dev_notify;
1857 }
1858
1859 static inline int encoder_on_portb(struct cx23885_dev *dev)
1860 {
1861         return cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER;
1862 }
1863
1864 static inline int encoder_on_portc(struct cx23885_dev *dev)
1865 {
1866         return cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER;
1867 }
1868
1869 /* Mask represents 32 different GPIOs, GPIO's are split into multiple
1870  * registers depending on the board configuration (and whether the
1871  * 417 encoder (wi it's own GPIO's) are present. Each GPIO bit will
1872  * be pushed into the correct hardware register, regardless of the
1873  * physical location. Certain registers are shared so we sanity check
1874  * and report errors if we think we're tampering with a GPIo that might
1875  * be assigned to the encoder (and used for the host bus).
1876  *
1877  * GPIO  2 thru  0 - On the cx23885 bridge
1878  * GPIO 18 thru  3 - On the cx23417 host bus interface
1879  * GPIO 23 thru 19 - On the cx25840 a/v core
1880  */
1881 void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask)
1882 {
1883         if (mask & 0x7)
1884                 cx_set(GP0_IO, mask & 0x7);
1885
1886         if (mask & 0x0007fff8) {
1887                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1888                         pr_err("%s: Setting GPIO on encoder ports\n",
1889                                 dev->name);
1890                 cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
1891         }
1892
1893         /* TODO: 23-19 */
1894         if (mask & 0x00f80000)
1895                 pr_info("%s: Unsupported\n", dev->name);
1896 }
1897
1898 void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask)
1899 {
1900         if (mask & 0x00000007)
1901                 cx_clear(GP0_IO, mask & 0x7);
1902
1903         if (mask & 0x0007fff8) {
1904                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1905                         pr_err("%s: Clearing GPIO moving on encoder ports\n",
1906                                 dev->name);
1907                 cx_clear(MC417_RWD, (mask & 0x7fff8) >> 3);
1908         }
1909
1910         /* TODO: 23-19 */
1911         if (mask & 0x00f80000)
1912                 pr_info("%s: Unsupported\n", dev->name);
1913 }
1914
1915 u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask)
1916 {
1917         if (mask & 0x00000007)
1918                 return (cx_read(GP0_IO) >> 8) & mask & 0x7;
1919
1920         if (mask & 0x0007fff8) {
1921                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1922                         pr_err("%s: Reading GPIO moving on encoder ports\n",
1923                                 dev->name);
1924                 return (cx_read(MC417_RWD) & ((mask & 0x7fff8) >> 3)) << 3;
1925         }
1926
1927         /* TODO: 23-19 */
1928         if (mask & 0x00f80000)
1929                 pr_info("%s: Unsupported\n", dev->name);
1930
1931         return 0;
1932 }
1933
1934 void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
1935 {
1936         if ((mask & 0x00000007) && asoutput)
1937                 cx_set(GP0_IO, (mask & 0x7) << 16);
1938         else if ((mask & 0x00000007) && !asoutput)
1939                 cx_clear(GP0_IO, (mask & 0x7) << 16);
1940
1941         if (mask & 0x0007fff8) {
1942                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1943                         pr_err("%s: Enabling GPIO on encoder ports\n",
1944                                 dev->name);
1945         }
1946
1947         /* MC417_OEN is active low for output, write 1 for an input */
1948         if ((mask & 0x0007fff8) && asoutput)
1949                 cx_clear(MC417_OEN, (mask & 0x7fff8) >> 3);
1950
1951         else if ((mask & 0x0007fff8) && !asoutput)
1952                 cx_set(MC417_OEN, (mask & 0x7fff8) >> 3);
1953
1954         /* TODO: 23-19 */
1955 }
1956
1957 static int cx23885_initdev(struct pci_dev *pci_dev,
1958                            const struct pci_device_id *pci_id)
1959 {
1960         struct cx23885_dev *dev;
1961         struct v4l2_ctrl_handler *hdl;
1962         int err;
1963
1964         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1965         if (NULL == dev)
1966                 return -ENOMEM;
1967
1968         err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1969         if (err < 0)
1970                 goto fail_free;
1971
1972         hdl = &dev->ctrl_handler;
1973         v4l2_ctrl_handler_init(hdl, 6);
1974         if (hdl->error) {
1975                 err = hdl->error;
1976                 goto fail_ctrl;
1977         }
1978         dev->v4l2_dev.ctrl_handler = hdl;
1979
1980         /* Prepare to handle notifications from subdevices */
1981         cx23885_v4l2_dev_notify_init(dev);
1982
1983         /* pci init */
1984         dev->pci = pci_dev;
1985         if (pci_enable_device(pci_dev)) {
1986                 err = -EIO;
1987                 goto fail_ctrl;
1988         }
1989
1990         if (cx23885_dev_setup(dev) < 0) {
1991                 err = -EINVAL;
1992                 goto fail_ctrl;
1993         }
1994
1995         /* print pci info */
1996         dev->pci_rev = pci_dev->revision;
1997         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
1998         pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
1999                dev->name,
2000                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
2001                dev->pci_lat,
2002                 (unsigned long long)pci_resource_start(pci_dev, 0));
2003
2004         pci_set_master(pci_dev);
2005         err = pci_set_dma_mask(pci_dev, 0xffffffff);
2006         if (err) {
2007                 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
2008                 goto fail_ctrl;
2009         }
2010
2011         err = request_irq(pci_dev->irq, cx23885_irq,
2012                           IRQF_SHARED, dev->name, dev);
2013         if (err < 0) {
2014                 pr_err("%s: can't get IRQ %d\n",
2015                        dev->name, pci_dev->irq);
2016                 goto fail_irq;
2017         }
2018
2019         switch (dev->board) {
2020         case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2021                 cx23885_irq_add_enable(dev, PCI_MSK_GPIO1 | PCI_MSK_GPIO0);
2022                 break;
2023         case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
2024                 cx23885_irq_add_enable(dev, PCI_MSK_GPIO0);
2025                 break;
2026         }
2027
2028         /*
2029          * The CX2388[58] IR controller can start firing interrupts when
2030          * enabled, so these have to take place after the cx23885_irq() handler
2031          * is hooked up by the call to request_irq() above.
2032          */
2033         cx23885_ir_pci_int_enable(dev);
2034         cx23885_input_init(dev);
2035
2036         return 0;
2037
2038 fail_irq:
2039         cx23885_dev_unregister(dev);
2040 fail_ctrl:
2041         v4l2_ctrl_handler_free(hdl);
2042         v4l2_device_unregister(&dev->v4l2_dev);
2043 fail_free:
2044         kfree(dev);
2045         return err;
2046 }
2047
2048 static void cx23885_finidev(struct pci_dev *pci_dev)
2049 {
2050         struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
2051         struct cx23885_dev *dev = to_cx23885(v4l2_dev);
2052
2053         cx23885_input_fini(dev);
2054         cx23885_ir_fini(dev);
2055
2056         cx23885_shutdown(dev);
2057
2058         /* unregister stuff */
2059         free_irq(pci_dev->irq, dev);
2060
2061         pci_disable_device(pci_dev);
2062
2063         cx23885_dev_unregister(dev);
2064         v4l2_ctrl_handler_free(&dev->ctrl_handler);
2065         v4l2_device_unregister(v4l2_dev);
2066         kfree(dev);
2067 }
2068
2069 static const struct pci_device_id cx23885_pci_tbl[] = {
2070         {
2071                 /* CX23885 */
2072                 .vendor       = 0x14f1,
2073                 .device       = 0x8852,
2074                 .subvendor    = PCI_ANY_ID,
2075                 .subdevice    = PCI_ANY_ID,
2076         }, {
2077                 /* CX23887 Rev 2 */
2078                 .vendor       = 0x14f1,
2079                 .device       = 0x8880,
2080                 .subvendor    = PCI_ANY_ID,
2081                 .subdevice    = PCI_ANY_ID,
2082         }, {
2083                 /* --- end of list --- */
2084         }
2085 };
2086 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
2087
2088 static struct pci_driver cx23885_pci_driver = {
2089         .name     = "cx23885",
2090         .id_table = cx23885_pci_tbl,
2091         .probe    = cx23885_initdev,
2092         .remove   = cx23885_finidev,
2093         /* TODO */
2094         .suspend  = NULL,
2095         .resume   = NULL,
2096 };
2097
2098 static int __init cx23885_init(void)
2099 {
2100         pr_info("cx23885 driver version %s loaded\n",
2101                 CX23885_VERSION);
2102         return pci_register_driver(&cx23885_pci_driver);
2103 }
2104
2105 static void __exit cx23885_fini(void)
2106 {
2107         pci_unregister_driver(&cx23885_pci_driver);
2108 }
2109
2110 module_init(cx23885_init);
2111 module_exit(cx23885_fini);