1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor
4 * with embedded SoC ISP.
6 * Copyright (C) 2013, Samsung Electronics Co., Ltd.
7 * Andrzej Hajda <a.hajda@samsung.com>
9 * Based on S5K6AA driver authored by Sylwester Nawrocki
10 * Copyright (C) 2013, Samsung Electronics Co., Ltd.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/firmware.h>
16 #include <linux/gpio.h>
17 #include <linux/i2c.h>
18 #include <linux/media.h>
19 #include <linux/module.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_graph.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
25 #include <media/media-entity.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-subdev.h>
29 #include <media/v4l2-mediabus.h>
30 #include <media/v4l2-fwnode.h>
33 module_param(debug, int, 0644);
35 #define S5K5BAF_DRIVER_NAME "s5k5baf"
36 #define S5K5BAF_DEFAULT_MCLK_FREQ 24000000U
37 #define S5K5BAF_CLK_NAME "mclk"
39 #define S5K5BAF_FW_FILENAME "/*(DEBLOBBED)*/"
40 #define S5K5BAF_FW_TAG "SF00"
41 #define S5K5BAG_FW_TAG_LEN 2
42 #define S5K5BAG_FW_MAX_COUNT 16
44 #define S5K5BAF_CIS_WIDTH 1600
45 #define S5K5BAF_CIS_HEIGHT 1200
46 #define S5K5BAF_WIN_WIDTH_MIN 8
47 #define S5K5BAF_WIN_HEIGHT_MIN 8
48 #define S5K5BAF_GAIN_RED_DEF 127
49 #define S5K5BAF_GAIN_GREEN_DEF 95
50 #define S5K5BAF_GAIN_BLUE_DEF 180
51 /* Default number of MIPI CSI-2 data lanes used */
52 #define S5K5BAF_DEF_NUM_LANES 1
54 #define AHB_MSB_ADDR_PTR 0xfcfc
57 * Register interface pages (the most significant word of the address)
59 #define PAGE_IF_HW 0xd000
60 #define PAGE_IF_SW 0x7000
63 * H/W register Interface (PAGE_IF_HW)
65 #define REG_SW_LOAD_COMPLETE 0x0014
66 #define REG_CMDWR_PAGE 0x0028
67 #define REG_CMDWR_ADDR 0x002a
68 #define REG_CMDRD_PAGE 0x002c
69 #define REG_CMDRD_ADDR 0x002e
70 #define REG_CMD_BUF 0x0f12
71 #define REG_SET_HOST_INT 0x1000
72 #define REG_CLEAR_HOST_INT 0x1030
73 #define REG_PATTERN_SET 0x3100
74 #define REG_PATTERN_WIDTH 0x3118
75 #define REG_PATTERN_HEIGHT 0x311a
76 #define REG_PATTERN_PARAM 0x311c
79 * S/W register interface (PAGE_IF_SW)
82 /* Firmware revision information */
83 #define REG_FW_APIVER 0x012e
84 #define S5K5BAF_FW_APIVER 0x0001
85 #define REG_FW_REVISION 0x0130
86 #define REG_FW_SENSOR_ID 0x0152
88 /* Initialization parameters */
89 /* Master clock frequency in KHz */
90 #define REG_I_INCLK_FREQ_L 0x01b8
91 #define REG_I_INCLK_FREQ_H 0x01ba
92 #define MIN_MCLK_FREQ_KHZ 6000U
93 #define MAX_MCLK_FREQ_KHZ 48000U
94 #define REG_I_USE_NPVI_CLOCKS 0x01c6
96 #define REG_I_USE_NMIPI_CLOCKS 0x01c8
97 #define NMIPI_CLOCKS 1
98 #define REG_I_BLOCK_INTERNAL_PLL_CALC 0x01ca
100 /* Clock configurations, n = 0..2. REG_I_* frequency unit is 4 kHz. */
101 #define REG_I_OPCLK_4KHZ(n) ((n) * 6 + 0x01cc)
102 #define REG_I_MIN_OUTRATE_4KHZ(n) ((n) * 6 + 0x01ce)
103 #define REG_I_MAX_OUTRATE_4KHZ(n) ((n) * 6 + 0x01d0)
104 #define SCLK_PVI_FREQ 24000
105 #define SCLK_MIPI_FREQ 48000
106 #define PCLK_MIN_FREQ 6000
107 #define PCLK_MAX_FREQ 48000
108 #define REG_I_USE_REGS_API 0x01de
109 #define REG_I_INIT_PARAMS_UPDATED 0x01e0
110 #define REG_I_ERROR_INFO 0x01e2
112 /* General purpose parameters */
113 #define REG_USER_BRIGHTNESS 0x01e4
114 #define REG_USER_CONTRAST 0x01e6
115 #define REG_USER_SATURATION 0x01e8
116 #define REG_USER_SHARPBLUR 0x01ea
118 #define REG_G_SPEC_EFFECTS 0x01ee
119 #define REG_G_ENABLE_PREV 0x01f0
120 #define REG_G_ENABLE_PREV_CHG 0x01f2
121 #define REG_G_NEW_CFG_SYNC 0x01f8
122 #define REG_G_PREVREQ_IN_WIDTH 0x01fa
123 #define REG_G_PREVREQ_IN_HEIGHT 0x01fc
124 #define REG_G_PREVREQ_IN_XOFFS 0x01fe
125 #define REG_G_PREVREQ_IN_YOFFS 0x0200
126 #define REG_G_PREVZOOM_IN_WIDTH 0x020a
127 #define REG_G_PREVZOOM_IN_HEIGHT 0x020c
128 #define REG_G_PREVZOOM_IN_XOFFS 0x020e
129 #define REG_G_PREVZOOM_IN_YOFFS 0x0210
130 #define REG_G_INPUTS_CHANGE_REQ 0x021a
131 #define REG_G_ACTIVE_PREV_CFG 0x021c
132 #define REG_G_PREV_CFG_CHG 0x021e
133 #define REG_G_PREV_OPEN_AFTER_CH 0x0220
134 #define REG_G_PREV_CFG_ERROR 0x0222
135 #define CFG_ERROR_RANGE 0x0b
136 #define REG_G_PREV_CFG_BYPASS_CHANGED 0x022a
137 #define REG_G_ACTUAL_P_FR_TIME 0x023a
138 #define REG_G_ACTUAL_P_OUT_RATE 0x023c
139 #define REG_G_ACTUAL_C_FR_TIME 0x023e
140 #define REG_G_ACTUAL_C_OUT_RATE 0x0240
142 /* Preview control section. n = 0...4. */
143 #define PREG(n, x) ((n) * 0x26 + x)
144 #define REG_P_OUT_WIDTH(n) PREG(n, 0x0242)
145 #define REG_P_OUT_HEIGHT(n) PREG(n, 0x0244)
146 #define REG_P_FMT(n) PREG(n, 0x0246)
147 #define REG_P_MAX_OUT_RATE(n) PREG(n, 0x0248)
148 #define REG_P_MIN_OUT_RATE(n) PREG(n, 0x024a)
149 #define REG_P_PVI_MASK(n) PREG(n, 0x024c)
150 #define PVI_MASK_MIPI 0x52
151 #define REG_P_CLK_INDEX(n) PREG(n, 0x024e)
152 #define CLK_PVI_INDEX 0
153 #define CLK_MIPI_INDEX NPVI_CLOCKS
154 #define REG_P_FR_RATE_TYPE(n) PREG(n, 0x0250)
155 #define FR_RATE_DYNAMIC 0
156 #define FR_RATE_FIXED 1
157 #define FR_RATE_FIXED_ACCURATE 2
158 #define REG_P_FR_RATE_Q_TYPE(n) PREG(n, 0x0252)
159 #define FR_RATE_Q_DYNAMIC 0
160 #define FR_RATE_Q_BEST_FRRATE 1 /* Binning enabled */
161 #define FR_RATE_Q_BEST_QUALITY 2 /* Binning disabled */
162 /* Frame period in 0.1 ms units */
163 #define REG_P_MAX_FR_TIME(n) PREG(n, 0x0254)
164 #define REG_P_MIN_FR_TIME(n) PREG(n, 0x0256)
165 #define S5K5BAF_MIN_FR_TIME 333 /* x100 us */
166 #define S5K5BAF_MAX_FR_TIME 6500 /* x100 us */
167 /* The below 5 registers are for "device correction" values */
168 #define REG_P_SATURATION(n) PREG(n, 0x0258)
169 #define REG_P_SHARP_BLUR(n) PREG(n, 0x025a)
170 #define REG_P_GLAMOUR(n) PREG(n, 0x025c)
171 #define REG_P_COLORTEMP(n) PREG(n, 0x025e)
172 #define REG_P_GAMMA_INDEX(n) PREG(n, 0x0260)
173 #define REG_P_PREV_MIRROR(n) PREG(n, 0x0262)
174 #define REG_P_CAP_MIRROR(n) PREG(n, 0x0264)
175 #define REG_P_CAP_ROTATION(n) PREG(n, 0x0266)
177 /* Extended image property controls */
178 /* Exposure time in 10 us units */
179 #define REG_SF_USR_EXPOSURE_L 0x03bc
180 #define REG_SF_USR_EXPOSURE_H 0x03be
181 #define REG_SF_USR_EXPOSURE_CHG 0x03c0
182 #define REG_SF_USR_TOT_GAIN 0x03c2
183 #define REG_SF_USR_TOT_GAIN_CHG 0x03c4
184 #define REG_SF_RGAIN 0x03c6
185 #define REG_SF_RGAIN_CHG 0x03c8
186 #define REG_SF_GGAIN 0x03ca
187 #define REG_SF_GGAIN_CHG 0x03cc
188 #define REG_SF_BGAIN 0x03ce
189 #define REG_SF_BGAIN_CHG 0x03d0
190 #define REG_SF_WBGAIN_CHG 0x03d2
191 #define REG_SF_FLICKER_QUANT 0x03d4
192 #define REG_SF_FLICKER_QUANT_CHG 0x03d6
194 /* Output interface (parallel/MIPI) setup */
195 #define REG_OIF_EN_MIPI_LANES 0x03f2
196 #define REG_OIF_EN_PACKETS 0x03f4
197 #define EN_PACKETS_CSI2 0xc3
198 #define REG_OIF_CFG_CHG 0x03f6
200 /* Auto-algorithms enable mask */
201 #define REG_DBG_AUTOALG_EN 0x03f8
202 #define AALG_ALL_EN BIT(0)
203 #define AALG_AE_EN BIT(1)
204 #define AALG_DIVLEI_EN BIT(2)
205 #define AALG_WB_EN BIT(3)
206 #define AALG_USE_WB_FOR_ISP BIT(4)
207 #define AALG_FLICKER_EN BIT(5)
208 #define AALG_FIT_EN BIT(6)
209 #define AALG_WRHW_EN BIT(7)
211 /* Pointers to color correction matrices */
212 #define REG_PTR_CCM_HORIZON 0x06d0
213 #define REG_PTR_CCM_INCANDESCENT 0x06d4
214 #define REG_PTR_CCM_WARM_WHITE 0x06d8
215 #define REG_PTR_CCM_COOL_WHITE 0x06dc
216 #define REG_PTR_CCM_DL50 0x06e0
217 #define REG_PTR_CCM_DL65 0x06e4
218 #define REG_PTR_CCM_OUTDOOR 0x06ec
220 #define REG_ARR_CCM(n) (0x2800 + 36 * (n))
222 static const char * const s5k5baf_supply_names[] = {
223 "vdda", /* Analog power supply 2.8V (2.6V to 3.0V) */
224 "vddreg", /* Regulator input power supply 1.8V (1.7V to 1.9V)
225 or 2.8V (2.6V to 3.0) */
226 "vddio", /* I/O power supply 1.8V (1.65V to 1.95V)
227 or 2.8V (2.5V to 3.1V) */
229 #define S5K5BAF_NUM_SUPPLIES ARRAY_SIZE(s5k5baf_supply_names)
231 struct s5k5baf_gpio {
236 enum s5k5baf_gpio_id {
244 #define NUM_CIS_PADS 1
245 #define NUM_ISP_PADS 2
247 struct s5k5baf_pixfmt {
250 /* REG_P_FMT(x) register value */
254 struct s5k5baf_ctrls {
255 struct v4l2_ctrl_handler handler;
256 struct { /* Auto / manual white balance cluster */
257 struct v4l2_ctrl *awb;
258 struct v4l2_ctrl *gain_red;
259 struct v4l2_ctrl *gain_blue;
261 struct { /* Mirror cluster */
262 struct v4l2_ctrl *hflip;
263 struct v4l2_ctrl *vflip;
265 struct { /* Auto exposure / manual exposure and gain cluster */
266 struct v4l2_ctrl *auto_exp;
267 struct v4l2_ctrl *exposure;
268 struct v4l2_ctrl *gain;
287 struct s5k5baf_gpio gpios[NUM_GPIOS];
288 enum v4l2_mbus_type bus_type;
290 struct regulator_bulk_data supplies[S5K5BAF_NUM_SUPPLIES];
295 struct s5k5baf_fw *fw;
297 struct v4l2_subdev cis_sd;
298 struct media_pad cis_pad;
300 struct v4l2_subdev sd;
301 struct media_pad pads[NUM_ISP_PADS];
303 /* protects the struct members below */
308 struct v4l2_rect crop_sink;
309 struct v4l2_rect compose;
310 struct v4l2_rect crop_source;
311 /* index to s5k5baf_formats array */
313 /* actual frame interval in 100us */
315 /* requested frame interval in 100us */
317 /* cache for REG_DBG_AUTOALG_EN register */
320 struct s5k5baf_ctrls ctrls;
322 unsigned int streaming:1;
323 unsigned int apply_cfg:1;
324 unsigned int apply_crop:1;
325 unsigned int valid_auto_alg:1;
329 static const struct s5k5baf_pixfmt s5k5baf_formats[] = {
330 { MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG, 5 },
332 { MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_REC709, 6 },
333 { MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_JPEG, 0 },
336 static struct v4l2_rect s5k5baf_cis_rect = {
337 0, 0, S5K5BAF_CIS_WIDTH, S5K5BAF_CIS_HEIGHT
340 /* Setfile contains set of I2C command sequences. Each sequence has its ID.
343 * u16 count; number of sequences
345 * u16 id; sequence id
346 * u16 offset; sequence offset in data array
348 * u16 data[*]; array containing sequences
351 static int s5k5baf_fw_parse(struct device *dev, struct s5k5baf_fw **fw,
352 size_t count, const __le16 *data)
354 struct s5k5baf_fw *f;
358 if (count < S5K5BAG_FW_TAG_LEN + 1) {
359 dev_err(dev, "firmware file too short (%zu)\n", count);
363 ret = memcmp(data, S5K5BAF_FW_TAG, S5K5BAG_FW_TAG_LEN * sizeof(u16));
365 dev_err(dev, "invalid firmware magic number\n");
369 data += S5K5BAG_FW_TAG_LEN;
370 count -= S5K5BAG_FW_TAG_LEN;
372 d = devm_kcalloc(dev, count, sizeof(u16), GFP_KERNEL);
376 for (i = 0; i < count; ++i)
377 d[i] = le16_to_cpu(data[i]);
379 f = (struct s5k5baf_fw *)d;
380 if (count < 1 + 2 * f->count) {
381 dev_err(dev, "invalid firmware header (count=%d size=%zu)\n",
382 f->count, 2 * (count + S5K5BAG_FW_TAG_LEN));
386 d += 1 + 2 * f->count;
388 for (i = 0; i < f->count; ++i) {
389 if (f->seq[i].offset + d <= end)
391 dev_err(dev, "invalid firmware header (seq=%d)\n", i);
400 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
402 return &container_of(ctrl->handler, struct s5k5baf, ctrls.handler)->sd;
405 static inline bool s5k5baf_is_cis_subdev(struct v4l2_subdev *sd)
407 return sd->entity.function == MEDIA_ENT_F_CAM_SENSOR;
410 static inline struct s5k5baf *to_s5k5baf(struct v4l2_subdev *sd)
412 if (s5k5baf_is_cis_subdev(sd))
413 return container_of(sd, struct s5k5baf, cis_sd);
415 return container_of(sd, struct s5k5baf, sd);
418 static u16 s5k5baf_i2c_read(struct s5k5baf *state, u16 addr)
420 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
423 struct i2c_msg msg[] = {
424 { .addr = c->addr, .flags = 0,
425 .len = 2, .buf = (u8 *)&w },
426 { .addr = c->addr, .flags = I2C_M_RD,
427 .len = 2, .buf = (u8 *)&r },
434 w = cpu_to_be16(addr);
435 ret = i2c_transfer(c->adapter, msg, 2);
436 res = be16_to_cpu(r);
438 v4l2_dbg(3, debug, c, "i2c_read: 0x%04x : 0x%04x\n", addr, res);
441 v4l2_err(c, "i2c_read: error during transfer (%d)\n", ret);
447 static void s5k5baf_i2c_write(struct s5k5baf *state, u16 addr, u16 val)
449 u8 buf[4] = { addr >> 8, addr & 0xFF, val >> 8, val & 0xFF };
450 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
456 ret = i2c_master_send(c, buf, 4);
457 v4l2_dbg(3, debug, c, "i2c_write: 0x%04x : 0x%04x\n", addr, val);
460 v4l2_err(c, "i2c_write: error during transfer (%d)\n", ret);
465 static u16 s5k5baf_read(struct s5k5baf *state, u16 addr)
467 s5k5baf_i2c_write(state, REG_CMDRD_ADDR, addr);
468 return s5k5baf_i2c_read(state, REG_CMD_BUF);
471 static void s5k5baf_write(struct s5k5baf *state, u16 addr, u16 val)
473 s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr);
474 s5k5baf_i2c_write(state, REG_CMD_BUF, val);
477 static void s5k5baf_write_arr_seq(struct s5k5baf *state, u16 addr,
478 u16 count, const u16 *seq)
480 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
483 s5k5baf_i2c_write(state, REG_CMDWR_ADDR, addr);
487 v4l2_dbg(3, debug, c, "i2c_write_seq(count=%d): %*ph\n", count,
488 min(2 * count, 64), seq);
490 buf[0] = cpu_to_be16(REG_CMD_BUF);
493 int n = min_t(int, count, ARRAY_SIZE(buf) - 1);
496 for (i = 1; i <= n; ++i)
497 buf[i] = cpu_to_be16(*seq++);
500 ret = i2c_master_send(c, (char *)buf, i);
502 v4l2_err(c, "i2c_write_seq: error during transfer (%d)\n", ret);
511 #define s5k5baf_write_seq(state, addr, seq...) \
512 s5k5baf_write_arr_seq(state, addr, sizeof((char[]){ seq }), \
513 (const u16 []){ seq })
515 /* add items count at the beginning of the list */
516 #define NSEQ(seq...) sizeof((char[]){ seq }), seq
519 * s5k5baf_write_nseq() - Writes sequences of values to sensor memory via i2c
520 * @nseq: sequence of u16 words in format:
521 * (N, address, value[1]...value[N-1])*,0
523 * u16 seq[] = { NSEQ(0x4000, 1, 1), NSEQ(0x4010, 640, 480), 0 };
524 * ret = s5k5baf_write_nseq(c, seq);
526 static void s5k5baf_write_nseq(struct s5k5baf *state, const u16 *nseq)
530 while ((count = *nseq++)) {
534 s5k5baf_write_arr_seq(state, addr, count, nseq);
539 static void s5k5baf_synchronize(struct s5k5baf *state, int timeout, u16 addr)
541 unsigned long end = jiffies + msecs_to_jiffies(timeout);
544 s5k5baf_write(state, addr, 1);
546 reg = s5k5baf_read(state, addr);
547 if (state->error || !reg)
549 usleep_range(5000, 10000);
550 } while (time_is_after_jiffies(end));
552 v4l2_err(&state->sd, "timeout on register synchronize (%#x)\n", addr);
553 state->error = -ETIMEDOUT;
556 static u16 *s5k5baf_fw_get_seq(struct s5k5baf *state, u16 seq_id)
558 struct s5k5baf_fw *fw = state->fw;
565 data = &fw->seq[0].id + 2 * fw->count;
567 for (i = 0; i < fw->count; ++i) {
568 if (fw->seq[i].id == seq_id)
569 return data + fw->seq[i].offset;
575 static void s5k5baf_hw_patch(struct s5k5baf *state)
577 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_PATCH);
580 s5k5baf_write_nseq(state, seq);
583 static void s5k5baf_hw_set_clocks(struct s5k5baf *state)
585 unsigned long mclk = state->mclk_frequency / 1000;
587 static const u16 nseq_clk_cfg[] = {
588 NSEQ(REG_I_USE_NPVI_CLOCKS,
589 NPVI_CLOCKS, NMIPI_CLOCKS, 0,
590 SCLK_PVI_FREQ / 4, PCLK_MIN_FREQ / 4, PCLK_MAX_FREQ / 4,
591 SCLK_MIPI_FREQ / 4, PCLK_MIN_FREQ / 4, PCLK_MAX_FREQ / 4),
592 NSEQ(REG_I_USE_REGS_API, 1),
596 s5k5baf_write_seq(state, REG_I_INCLK_FREQ_L, mclk & 0xffff, mclk >> 16);
597 s5k5baf_write_nseq(state, nseq_clk_cfg);
599 s5k5baf_synchronize(state, 250, REG_I_INIT_PARAMS_UPDATED);
600 status = s5k5baf_read(state, REG_I_ERROR_INFO);
601 if (!state->error && status) {
602 v4l2_err(&state->sd, "error configuring PLL (%d)\n", status);
603 state->error = -EINVAL;
607 /* set custom color correction matrices for various illuminations */
608 static void s5k5baf_hw_set_ccm(struct s5k5baf *state)
610 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CCM);
613 s5k5baf_write_nseq(state, seq);
616 /* CIS sensor tuning, based on undocumented android driver code */
617 static void s5k5baf_hw_set_cis(struct s5k5baf *state)
619 u16 *seq = s5k5baf_fw_get_seq(state, S5K5BAF_FW_ID_CIS);
624 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_HW);
625 s5k5baf_write_nseq(state, seq);
626 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW);
629 static void s5k5baf_hw_sync_cfg(struct s5k5baf *state)
631 s5k5baf_write(state, REG_G_PREV_CFG_CHG, 1);
632 if (state->apply_crop) {
633 s5k5baf_write(state, REG_G_INPUTS_CHANGE_REQ, 1);
634 s5k5baf_write(state, REG_G_PREV_CFG_BYPASS_CHANGED, 1);
636 s5k5baf_synchronize(state, 500, REG_G_NEW_CFG_SYNC);
638 /* Set horizontal and vertical image flipping */
639 static void s5k5baf_hw_set_mirror(struct s5k5baf *state)
641 u16 flip = state->ctrls.vflip->val | (state->ctrls.vflip->val << 1);
643 s5k5baf_write(state, REG_P_PREV_MIRROR(0), flip);
644 if (state->streaming)
645 s5k5baf_hw_sync_cfg(state);
648 static void s5k5baf_hw_set_alg(struct s5k5baf *state, u16 alg, bool enable)
650 u16 cur_alg, new_alg;
652 if (!state->valid_auto_alg)
653 cur_alg = s5k5baf_read(state, REG_DBG_AUTOALG_EN);
655 cur_alg = state->auto_alg;
657 new_alg = enable ? (cur_alg | alg) : (cur_alg & ~alg);
659 if (new_alg != cur_alg)
660 s5k5baf_write(state, REG_DBG_AUTOALG_EN, new_alg);
665 state->valid_auto_alg = 1;
666 state->auto_alg = new_alg;
669 /* Configure auto/manual white balance and R/G/B gains */
670 static void s5k5baf_hw_set_awb(struct s5k5baf *state, int awb)
672 struct s5k5baf_ctrls *ctrls = &state->ctrls;
675 s5k5baf_write_seq(state, REG_SF_RGAIN,
676 ctrls->gain_red->val, 1,
677 S5K5BAF_GAIN_GREEN_DEF, 1,
678 ctrls->gain_blue->val, 1,
681 s5k5baf_hw_set_alg(state, AALG_WB_EN, awb);
684 /* Program FW with exposure time, 'exposure' in us units */
685 static void s5k5baf_hw_set_user_exposure(struct s5k5baf *state, int exposure)
687 unsigned int time = exposure / 10;
689 s5k5baf_write_seq(state, REG_SF_USR_EXPOSURE_L,
690 time & 0xffff, time >> 16, 1);
693 static void s5k5baf_hw_set_user_gain(struct s5k5baf *state, int gain)
695 s5k5baf_write_seq(state, REG_SF_USR_TOT_GAIN, gain, 1);
698 /* Set auto/manual exposure and total gain */
699 static void s5k5baf_hw_set_auto_exposure(struct s5k5baf *state, int value)
701 if (value == V4L2_EXPOSURE_AUTO) {
702 s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, true);
704 unsigned int exp_time = state->ctrls.exposure->val;
706 s5k5baf_hw_set_user_exposure(state, exp_time);
707 s5k5baf_hw_set_user_gain(state, state->ctrls.gain->val);
708 s5k5baf_hw_set_alg(state, AALG_AE_EN | AALG_DIVLEI_EN, false);
712 static void s5k5baf_hw_set_anti_flicker(struct s5k5baf *state, int v)
714 if (v == V4L2_CID_POWER_LINE_FREQUENCY_AUTO) {
715 s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, true);
717 /* The V4L2_CID_LINE_FREQUENCY control values match
718 * the register values */
719 s5k5baf_write_seq(state, REG_SF_FLICKER_QUANT, v, 1);
720 s5k5baf_hw_set_alg(state, AALG_FLICKER_EN, false);
724 static void s5k5baf_hw_set_colorfx(struct s5k5baf *state, int val)
726 static const u16 colorfx[] = {
727 [V4L2_COLORFX_NONE] = 0,
728 [V4L2_COLORFX_BW] = 1,
729 [V4L2_COLORFX_NEGATIVE] = 2,
730 [V4L2_COLORFX_SEPIA] = 3,
731 [V4L2_COLORFX_SKY_BLUE] = 4,
732 [V4L2_COLORFX_SKETCH] = 5,
735 s5k5baf_write(state, REG_G_SPEC_EFFECTS, colorfx[val]);
738 static int s5k5baf_find_pixfmt(struct v4l2_mbus_framefmt *mf)
742 for (i = 0; i < ARRAY_SIZE(s5k5baf_formats); i++) {
743 if (mf->colorspace != s5k5baf_formats[i].colorspace)
745 if (mf->code == s5k5baf_formats[i].code)
750 return (c < 0) ? 0 : c;
753 static int s5k5baf_clear_error(struct s5k5baf *state)
755 int ret = state->error;
761 static int s5k5baf_hw_set_video_bus(struct s5k5baf *state)
765 if (state->bus_type == V4L2_MBUS_CSI2_DPHY)
766 en_pkts = EN_PACKETS_CSI2;
770 s5k5baf_write_seq(state, REG_OIF_EN_MIPI_LANES,
771 state->nlanes, en_pkts, 1);
773 return s5k5baf_clear_error(state);
776 static u16 s5k5baf_get_cfg_error(struct s5k5baf *state)
778 u16 err = s5k5baf_read(state, REG_G_PREV_CFG_ERROR);
780 s5k5baf_write(state, REG_G_PREV_CFG_ERROR, 0);
784 static void s5k5baf_hw_set_fiv(struct s5k5baf *state, u16 fiv)
786 s5k5baf_write(state, REG_P_MAX_FR_TIME(0), fiv);
787 s5k5baf_hw_sync_cfg(state);
790 static void s5k5baf_hw_find_min_fiv(struct s5k5baf *state)
795 fiv = s5k5baf_read(state, REG_G_ACTUAL_P_FR_TIME);
799 for (n = 5; n > 0; --n) {
800 s5k5baf_hw_set_fiv(state, fiv);
801 err = s5k5baf_get_cfg_error(state);
805 case CFG_ERROR_RANGE:
810 v4l2_info(&state->sd,
811 "found valid frame interval: %d00us\n", fiv);
815 "error setting frame interval: %d\n", err);
816 state->error = -EINVAL;
819 v4l2_err(&state->sd, "cannot find correct frame interval\n");
820 state->error = -ERANGE;
823 static void s5k5baf_hw_validate_cfg(struct s5k5baf *state)
827 err = s5k5baf_get_cfg_error(state);
833 state->apply_cfg = 1;
835 case CFG_ERROR_RANGE:
836 s5k5baf_hw_find_min_fiv(state);
838 state->apply_cfg = 1;
842 "error setting format: %d\n", err);
843 state->error = -EINVAL;
847 static void s5k5baf_rescale(struct v4l2_rect *r, const struct v4l2_rect *v,
848 const struct v4l2_rect *n,
849 const struct v4l2_rect *d)
851 r->left = v->left * n->width / d->width;
852 r->top = v->top * n->height / d->height;
853 r->width = v->width * n->width / d->width;
854 r->height = v->height * n->height / d->height;
857 static int s5k5baf_hw_set_crop_rects(struct s5k5baf *state)
859 struct v4l2_rect *p, r;
863 p = &state->crop_sink;
864 s5k5baf_write_seq(state, REG_G_PREVREQ_IN_WIDTH, p->width, p->height,
867 s5k5baf_rescale(&r, &state->crop_source, &state->crop_sink,
869 s5k5baf_write_seq(state, REG_G_PREVZOOM_IN_WIDTH, r.width, r.height,
872 s5k5baf_synchronize(state, 500, REG_G_INPUTS_CHANGE_REQ);
873 s5k5baf_synchronize(state, 500, REG_G_PREV_CFG_BYPASS_CHANGED);
874 err = s5k5baf_get_cfg_error(state);
875 ret = s5k5baf_clear_error(state);
882 case CFG_ERROR_RANGE:
883 /* retry crop with frame interval set to max */
884 s5k5baf_hw_set_fiv(state, S5K5BAF_MAX_FR_TIME);
885 err = s5k5baf_get_cfg_error(state);
886 ret = s5k5baf_clear_error(state);
891 "crop error on max frame interval: %d\n", err);
892 state->error = -EINVAL;
894 s5k5baf_hw_set_fiv(state, state->req_fiv);
895 s5k5baf_hw_validate_cfg(state);
898 v4l2_err(&state->sd, "crop error: %d\n", err);
902 if (!state->apply_cfg)
905 p = &state->crop_source;
906 s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0), p->width, p->height);
907 s5k5baf_hw_set_fiv(state, state->req_fiv);
908 s5k5baf_hw_validate_cfg(state);
910 return s5k5baf_clear_error(state);
913 static void s5k5baf_hw_set_config(struct s5k5baf *state)
915 u16 reg_fmt = s5k5baf_formats[state->pixfmt].reg_p_fmt;
916 struct v4l2_rect *r = &state->crop_source;
918 s5k5baf_write_seq(state, REG_P_OUT_WIDTH(0),
919 r->width, r->height, reg_fmt,
920 PCLK_MAX_FREQ >> 2, PCLK_MIN_FREQ >> 2,
921 PVI_MASK_MIPI, CLK_MIPI_INDEX,
922 FR_RATE_FIXED, FR_RATE_Q_DYNAMIC,
923 state->req_fiv, S5K5BAF_MIN_FR_TIME);
924 s5k5baf_hw_sync_cfg(state);
925 s5k5baf_hw_validate_cfg(state);
929 static void s5k5baf_hw_set_test_pattern(struct s5k5baf *state, int id)
931 s5k5baf_i2c_write(state, REG_PATTERN_WIDTH, 800);
932 s5k5baf_i2c_write(state, REG_PATTERN_HEIGHT, 511);
933 s5k5baf_i2c_write(state, REG_PATTERN_PARAM, 0);
934 s5k5baf_i2c_write(state, REG_PATTERN_SET, id);
937 static void s5k5baf_gpio_assert(struct s5k5baf *state, int id)
939 struct s5k5baf_gpio *gpio = &state->gpios[id];
941 gpio_set_value(gpio->gpio, gpio->level);
944 static void s5k5baf_gpio_deassert(struct s5k5baf *state, int id)
946 struct s5k5baf_gpio *gpio = &state->gpios[id];
948 gpio_set_value(gpio->gpio, !gpio->level);
951 static int s5k5baf_power_on(struct s5k5baf *state)
955 ret = regulator_bulk_enable(S5K5BAF_NUM_SUPPLIES, state->supplies);
959 ret = clk_set_rate(state->clock, state->mclk_frequency);
963 ret = clk_prepare_enable(state->clock);
967 v4l2_dbg(1, debug, &state->sd, "clock frequency: %ld\n",
968 clk_get_rate(state->clock));
970 s5k5baf_gpio_deassert(state, STBY);
971 usleep_range(50, 100);
972 s5k5baf_gpio_deassert(state, RSET);
976 regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES, state->supplies);
978 v4l2_err(&state->sd, "%s() failed (%d)\n", __func__, ret);
982 static int s5k5baf_power_off(struct s5k5baf *state)
986 state->streaming = 0;
987 state->apply_cfg = 0;
988 state->apply_crop = 0;
990 s5k5baf_gpio_assert(state, RSET);
991 s5k5baf_gpio_assert(state, STBY);
993 if (!IS_ERR(state->clock))
994 clk_disable_unprepare(state->clock);
996 ret = regulator_bulk_disable(S5K5BAF_NUM_SUPPLIES,
999 v4l2_err(&state->sd, "failed to disable regulators\n");
1004 static void s5k5baf_hw_init(struct s5k5baf *state)
1006 s5k5baf_i2c_write(state, AHB_MSB_ADDR_PTR, PAGE_IF_HW);
1007 s5k5baf_i2c_write(state, REG_CLEAR_HOST_INT, 0);
1008 s5k5baf_i2c_write(state, REG_SW_LOAD_COMPLETE, 1);
1009 s5k5baf_i2c_write(state, REG_CMDRD_PAGE, PAGE_IF_SW);
1010 s5k5baf_i2c_write(state, REG_CMDWR_PAGE, PAGE_IF_SW);
1014 * V4L2 subdev core and video operations
1017 static void s5k5baf_initialize_data(struct s5k5baf *state)
1020 state->req_fiv = 10000 / 15;
1021 state->fiv = state->req_fiv;
1022 state->valid_auto_alg = 0;
1025 static int s5k5baf_load_setfile(struct s5k5baf *state)
1027 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1028 const struct firmware *fw;
1031 ret = reject_firmware(&fw, S5K5BAF_FW_FILENAME, &c->dev);
1033 dev_warn(&c->dev, "firmware file (%s) not loaded\n",
1034 S5K5BAF_FW_FILENAME);
1038 ret = s5k5baf_fw_parse(&c->dev, &state->fw, fw->size / 2,
1039 (__le16 *)fw->data);
1041 release_firmware(fw);
1046 static int s5k5baf_set_power(struct v4l2_subdev *sd, int on)
1048 struct s5k5baf *state = to_s5k5baf(sd);
1051 mutex_lock(&state->lock);
1053 if (state->power != !on)
1057 if (state->fw == NULL)
1058 s5k5baf_load_setfile(state);
1060 s5k5baf_initialize_data(state);
1061 ret = s5k5baf_power_on(state);
1065 s5k5baf_hw_init(state);
1066 s5k5baf_hw_patch(state);
1067 s5k5baf_i2c_write(state, REG_SET_HOST_INT, 1);
1068 s5k5baf_hw_set_clocks(state);
1070 ret = s5k5baf_hw_set_video_bus(state);
1074 s5k5baf_hw_set_cis(state);
1075 s5k5baf_hw_set_ccm(state);
1077 ret = s5k5baf_clear_error(state);
1081 s5k5baf_power_off(state);
1086 mutex_unlock(&state->lock);
1089 ret = v4l2_ctrl_handler_setup(&state->ctrls.handler);
1094 static void s5k5baf_hw_set_stream(struct s5k5baf *state, int enable)
1096 s5k5baf_write_seq(state, REG_G_ENABLE_PREV, enable, 1);
1099 static int s5k5baf_s_stream(struct v4l2_subdev *sd, int on)
1101 struct s5k5baf *state = to_s5k5baf(sd);
1104 mutex_lock(&state->lock);
1106 if (state->streaming == !!on) {
1112 s5k5baf_hw_set_config(state);
1113 ret = s5k5baf_hw_set_crop_rects(state);
1116 s5k5baf_hw_set_stream(state, 1);
1117 s5k5baf_i2c_write(state, 0xb0cc, 0x000b);
1119 s5k5baf_hw_set_stream(state, 0);
1121 ret = s5k5baf_clear_error(state);
1123 state->streaming = !state->streaming;
1126 mutex_unlock(&state->lock);
1131 static int s5k5baf_g_frame_interval(struct v4l2_subdev *sd,
1132 struct v4l2_subdev_frame_interval *fi)
1134 struct s5k5baf *state = to_s5k5baf(sd);
1136 mutex_lock(&state->lock);
1137 fi->interval.numerator = state->fiv;
1138 fi->interval.denominator = 10000;
1139 mutex_unlock(&state->lock);
1144 static void s5k5baf_set_frame_interval(struct s5k5baf *state,
1145 struct v4l2_subdev_frame_interval *fi)
1147 struct v4l2_fract *i = &fi->interval;
1149 if (fi->interval.denominator == 0)
1150 state->req_fiv = S5K5BAF_MAX_FR_TIME;
1152 state->req_fiv = clamp_t(u32,
1153 i->numerator * 10000 / i->denominator,
1154 S5K5BAF_MIN_FR_TIME,
1155 S5K5BAF_MAX_FR_TIME);
1157 state->fiv = state->req_fiv;
1158 if (state->apply_cfg) {
1159 s5k5baf_hw_set_fiv(state, state->req_fiv);
1160 s5k5baf_hw_validate_cfg(state);
1162 *i = (struct v4l2_fract){ state->fiv, 10000 };
1163 if (state->fiv == state->req_fiv)
1164 v4l2_info(&state->sd, "frame interval changed to %d00us\n",
1168 static int s5k5baf_s_frame_interval(struct v4l2_subdev *sd,
1169 struct v4l2_subdev_frame_interval *fi)
1171 struct s5k5baf *state = to_s5k5baf(sd);
1173 mutex_lock(&state->lock);
1174 s5k5baf_set_frame_interval(state, fi);
1175 mutex_unlock(&state->lock);
1180 * V4L2 subdev pad level and video operations
1182 static int s5k5baf_enum_frame_interval(struct v4l2_subdev *sd,
1183 struct v4l2_subdev_state *sd_state,
1184 struct v4l2_subdev_frame_interval_enum *fie)
1186 if (fie->index > S5K5BAF_MAX_FR_TIME - S5K5BAF_MIN_FR_TIME ||
1187 fie->pad != PAD_CIS)
1190 v4l_bound_align_image(&fie->width, S5K5BAF_WIN_WIDTH_MIN,
1191 S5K5BAF_CIS_WIDTH, 1,
1192 &fie->height, S5K5BAF_WIN_HEIGHT_MIN,
1193 S5K5BAF_CIS_HEIGHT, 1, 0);
1195 fie->interval.numerator = S5K5BAF_MIN_FR_TIME + fie->index;
1196 fie->interval.denominator = 10000;
1201 static int s5k5baf_enum_mbus_code(struct v4l2_subdev *sd,
1202 struct v4l2_subdev_state *sd_state,
1203 struct v4l2_subdev_mbus_code_enum *code)
1205 if (code->pad == PAD_CIS) {
1206 if (code->index > 0)
1208 code->code = MEDIA_BUS_FMT_FIXED;
1212 if (code->index >= ARRAY_SIZE(s5k5baf_formats))
1215 code->code = s5k5baf_formats[code->index].code;
1219 static int s5k5baf_enum_frame_size(struct v4l2_subdev *sd,
1220 struct v4l2_subdev_state *sd_state,
1221 struct v4l2_subdev_frame_size_enum *fse)
1228 if (fse->pad == PAD_CIS) {
1229 fse->code = MEDIA_BUS_FMT_FIXED;
1230 fse->min_width = S5K5BAF_CIS_WIDTH;
1231 fse->max_width = S5K5BAF_CIS_WIDTH;
1232 fse->min_height = S5K5BAF_CIS_HEIGHT;
1233 fse->max_height = S5K5BAF_CIS_HEIGHT;
1237 i = ARRAY_SIZE(s5k5baf_formats);
1239 if (fse->code == s5k5baf_formats[i].code)
1241 fse->code = s5k5baf_formats[i].code;
1242 fse->min_width = S5K5BAF_WIN_WIDTH_MIN;
1243 fse->max_width = S5K5BAF_CIS_WIDTH;
1244 fse->max_height = S5K5BAF_WIN_HEIGHT_MIN;
1245 fse->min_height = S5K5BAF_CIS_HEIGHT;
1250 static void s5k5baf_try_cis_format(struct v4l2_mbus_framefmt *mf)
1252 mf->width = S5K5BAF_CIS_WIDTH;
1253 mf->height = S5K5BAF_CIS_HEIGHT;
1254 mf->code = MEDIA_BUS_FMT_FIXED;
1255 mf->colorspace = V4L2_COLORSPACE_JPEG;
1256 mf->field = V4L2_FIELD_NONE;
1259 static int s5k5baf_try_isp_format(struct v4l2_mbus_framefmt *mf)
1263 v4l_bound_align_image(&mf->width, S5K5BAF_WIN_WIDTH_MIN,
1264 S5K5BAF_CIS_WIDTH, 1,
1265 &mf->height, S5K5BAF_WIN_HEIGHT_MIN,
1266 S5K5BAF_CIS_HEIGHT, 1, 0);
1268 pixfmt = s5k5baf_find_pixfmt(mf);
1270 mf->colorspace = s5k5baf_formats[pixfmt].colorspace;
1271 mf->code = s5k5baf_formats[pixfmt].code;
1272 mf->field = V4L2_FIELD_NONE;
1277 static int s5k5baf_get_fmt(struct v4l2_subdev *sd,
1278 struct v4l2_subdev_state *sd_state,
1279 struct v4l2_subdev_format *fmt)
1281 struct s5k5baf *state = to_s5k5baf(sd);
1282 const struct s5k5baf_pixfmt *pixfmt;
1283 struct v4l2_mbus_framefmt *mf;
1285 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1286 mf = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
1292 if (fmt->pad == PAD_CIS) {
1293 s5k5baf_try_cis_format(mf);
1296 mf->field = V4L2_FIELD_NONE;
1297 mutex_lock(&state->lock);
1298 pixfmt = &s5k5baf_formats[state->pixfmt];
1299 mf->width = state->crop_source.width;
1300 mf->height = state->crop_source.height;
1301 mf->code = pixfmt->code;
1302 mf->colorspace = pixfmt->colorspace;
1303 mutex_unlock(&state->lock);
1308 static int s5k5baf_set_fmt(struct v4l2_subdev *sd,
1309 struct v4l2_subdev_state *sd_state,
1310 struct v4l2_subdev_format *fmt)
1312 struct v4l2_mbus_framefmt *mf = &fmt->format;
1313 struct s5k5baf *state = to_s5k5baf(sd);
1314 const struct s5k5baf_pixfmt *pixfmt;
1317 mf->field = V4L2_FIELD_NONE;
1319 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1320 *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = *mf;
1324 if (fmt->pad == PAD_CIS) {
1325 s5k5baf_try_cis_format(mf);
1329 mutex_lock(&state->lock);
1331 if (state->streaming) {
1332 mutex_unlock(&state->lock);
1336 state->pixfmt = s5k5baf_try_isp_format(mf);
1337 pixfmt = &s5k5baf_formats[state->pixfmt];
1338 mf->code = pixfmt->code;
1339 mf->colorspace = pixfmt->colorspace;
1340 mf->width = state->crop_source.width;
1341 mf->height = state->crop_source.height;
1343 mutex_unlock(&state->lock);
1347 enum selection_rect { R_CIS, R_CROP_SINK, R_COMPOSE, R_CROP_SOURCE, R_INVALID };
1349 static enum selection_rect s5k5baf_get_sel_rect(u32 pad, u32 target)
1352 case V4L2_SEL_TGT_CROP_BOUNDS:
1353 return pad ? R_COMPOSE : R_CIS;
1354 case V4L2_SEL_TGT_CROP:
1355 return pad ? R_CROP_SOURCE : R_CROP_SINK;
1356 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1357 return pad ? R_INVALID : R_CROP_SINK;
1358 case V4L2_SEL_TGT_COMPOSE:
1359 return pad ? R_INVALID : R_COMPOSE;
1365 static int s5k5baf_is_bound_target(u32 target)
1367 return target == V4L2_SEL_TGT_CROP_BOUNDS ||
1368 target == V4L2_SEL_TGT_COMPOSE_BOUNDS;
1371 static int s5k5baf_get_selection(struct v4l2_subdev *sd,
1372 struct v4l2_subdev_state *sd_state,
1373 struct v4l2_subdev_selection *sel)
1375 enum selection_rect rtype;
1376 struct s5k5baf *state = to_s5k5baf(sd);
1378 rtype = s5k5baf_get_sel_rect(sel->pad, sel->target);
1384 sel->r = s5k5baf_cis_rect;
1390 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1391 if (rtype == R_COMPOSE)
1392 sel->r = *v4l2_subdev_get_try_compose(sd, sd_state,
1395 sel->r = *v4l2_subdev_get_try_crop(sd, sd_state,
1400 mutex_lock(&state->lock);
1403 sel->r = state->crop_sink;
1406 sel->r = state->compose;
1409 sel->r = state->crop_source;
1414 if (s5k5baf_is_bound_target(sel->target)) {
1418 mutex_unlock(&state->lock);
1423 /* bounds range [start, start+len) to [0, max) and aligns to 2 */
1424 static void s5k5baf_bound_range(u32 *start, u32 *len, u32 max)
1428 if (*start + *len > max)
1429 *start = max - *len;
1432 if (*len < S5K5BAF_WIN_WIDTH_MIN)
1433 *len = S5K5BAF_WIN_WIDTH_MIN;
1436 static void s5k5baf_bound_rect(struct v4l2_rect *r, u32 width, u32 height)
1438 s5k5baf_bound_range(&r->left, &r->width, width);
1439 s5k5baf_bound_range(&r->top, &r->height, height);
1442 static void s5k5baf_set_rect_and_adjust(struct v4l2_rect **rects,
1443 enum selection_rect first,
1444 struct v4l2_rect *v)
1446 struct v4l2_rect *r, *br;
1447 enum selection_rect i = first;
1453 s5k5baf_bound_rect(r, br->width, br->height);
1454 } while (++i != R_INVALID);
1458 static bool s5k5baf_cmp_rect(const struct v4l2_rect *r1,
1459 const struct v4l2_rect *r2)
1461 return !memcmp(r1, r2, sizeof(*r1));
1464 static int s5k5baf_set_selection(struct v4l2_subdev *sd,
1465 struct v4l2_subdev_state *sd_state,
1466 struct v4l2_subdev_selection *sel)
1468 static enum selection_rect rtype;
1469 struct s5k5baf *state = to_s5k5baf(sd);
1470 struct v4l2_rect **rects;
1473 rtype = s5k5baf_get_sel_rect(sel->pad, sel->target);
1474 if (rtype == R_INVALID || s5k5baf_is_bound_target(sel->target))
1477 /* allow only scaling on compose */
1478 if (rtype == R_COMPOSE) {
1483 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1484 rects = (struct v4l2_rect * []) {
1486 v4l2_subdev_get_try_crop(sd, sd_state,
1488 v4l2_subdev_get_try_compose(sd, sd_state,
1490 v4l2_subdev_get_try_crop(sd, sd_state,
1493 s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r);
1497 rects = (struct v4l2_rect * []) {
1503 mutex_lock(&state->lock);
1504 if (state->streaming) {
1505 /* adjust sel->r to avoid output resolution change */
1506 if (rtype < R_CROP_SOURCE) {
1507 if (sel->r.width < state->crop_source.width)
1508 sel->r.width = state->crop_source.width;
1509 if (sel->r.height < state->crop_source.height)
1510 sel->r.height = state->crop_source.height;
1512 sel->r.width = state->crop_source.width;
1513 sel->r.height = state->crop_source.height;
1516 s5k5baf_set_rect_and_adjust(rects, rtype, &sel->r);
1517 if (!s5k5baf_cmp_rect(&state->crop_sink, &s5k5baf_cis_rect) ||
1518 !s5k5baf_cmp_rect(&state->compose, &s5k5baf_cis_rect))
1519 state->apply_crop = 1;
1520 if (state->streaming)
1521 ret = s5k5baf_hw_set_crop_rects(state);
1522 mutex_unlock(&state->lock);
1527 static const struct v4l2_subdev_pad_ops s5k5baf_cis_pad_ops = {
1528 .enum_mbus_code = s5k5baf_enum_mbus_code,
1529 .enum_frame_size = s5k5baf_enum_frame_size,
1530 .get_fmt = s5k5baf_get_fmt,
1531 .set_fmt = s5k5baf_set_fmt,
1534 static const struct v4l2_subdev_pad_ops s5k5baf_pad_ops = {
1535 .enum_mbus_code = s5k5baf_enum_mbus_code,
1536 .enum_frame_size = s5k5baf_enum_frame_size,
1537 .enum_frame_interval = s5k5baf_enum_frame_interval,
1538 .get_fmt = s5k5baf_get_fmt,
1539 .set_fmt = s5k5baf_set_fmt,
1540 .get_selection = s5k5baf_get_selection,
1541 .set_selection = s5k5baf_set_selection,
1544 static const struct v4l2_subdev_video_ops s5k5baf_video_ops = {
1545 .g_frame_interval = s5k5baf_g_frame_interval,
1546 .s_frame_interval = s5k5baf_s_frame_interval,
1547 .s_stream = s5k5baf_s_stream,
1551 * V4L2 subdev controls
1554 static int s5k5baf_s_ctrl(struct v4l2_ctrl *ctrl)
1556 struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
1557 struct s5k5baf *state = to_s5k5baf(sd);
1560 v4l2_dbg(1, debug, sd, "ctrl: %s, value: %d\n", ctrl->name, ctrl->val);
1562 mutex_lock(&state->lock);
1564 if (state->power == 0)
1568 case V4L2_CID_AUTO_WHITE_BALANCE:
1569 s5k5baf_hw_set_awb(state, ctrl->val);
1572 case V4L2_CID_BRIGHTNESS:
1573 s5k5baf_write(state, REG_USER_BRIGHTNESS, ctrl->val);
1576 case V4L2_CID_COLORFX:
1577 s5k5baf_hw_set_colorfx(state, ctrl->val);
1580 case V4L2_CID_CONTRAST:
1581 s5k5baf_write(state, REG_USER_CONTRAST, ctrl->val);
1584 case V4L2_CID_EXPOSURE_AUTO:
1585 s5k5baf_hw_set_auto_exposure(state, ctrl->val);
1588 case V4L2_CID_HFLIP:
1589 s5k5baf_hw_set_mirror(state);
1592 case V4L2_CID_POWER_LINE_FREQUENCY:
1593 s5k5baf_hw_set_anti_flicker(state, ctrl->val);
1596 case V4L2_CID_SATURATION:
1597 s5k5baf_write(state, REG_USER_SATURATION, ctrl->val);
1600 case V4L2_CID_SHARPNESS:
1601 s5k5baf_write(state, REG_USER_SHARPBLUR, ctrl->val);
1604 case V4L2_CID_WHITE_BALANCE_TEMPERATURE:
1605 s5k5baf_write(state, REG_P_COLORTEMP(0), ctrl->val);
1606 if (state->apply_cfg)
1607 s5k5baf_hw_sync_cfg(state);
1610 case V4L2_CID_TEST_PATTERN:
1611 s5k5baf_hw_set_test_pattern(state, ctrl->val);
1615 ret = s5k5baf_clear_error(state);
1616 mutex_unlock(&state->lock);
1620 static const struct v4l2_ctrl_ops s5k5baf_ctrl_ops = {
1621 .s_ctrl = s5k5baf_s_ctrl,
1624 static const char * const s5k5baf_test_pattern_menu[] = {
1634 static int s5k5baf_initialize_ctrls(struct s5k5baf *state)
1636 const struct v4l2_ctrl_ops *ops = &s5k5baf_ctrl_ops;
1637 struct s5k5baf_ctrls *ctrls = &state->ctrls;
1638 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1641 ret = v4l2_ctrl_handler_init(hdl, 16);
1643 v4l2_err(&state->sd, "cannot init ctrl handler (%d)\n", ret);
1647 /* Auto white balance cluster */
1648 ctrls->awb = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_WHITE_BALANCE,
1650 ctrls->gain_red = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
1651 0, 255, 1, S5K5BAF_GAIN_RED_DEF);
1652 ctrls->gain_blue = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
1653 0, 255, 1, S5K5BAF_GAIN_BLUE_DEF);
1654 v4l2_ctrl_auto_cluster(3, &ctrls->awb, 0, false);
1656 ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1657 ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1658 v4l2_ctrl_cluster(2, &ctrls->hflip);
1660 ctrls->auto_exp = v4l2_ctrl_new_std_menu(hdl, ops,
1661 V4L2_CID_EXPOSURE_AUTO,
1662 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1663 /* Exposure time: x 1 us */
1664 ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
1665 0, 6000000U, 1, 100000U);
1666 /* Total gain: 256 <=> 1x */
1667 ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN,
1669 v4l2_ctrl_auto_cluster(3, &ctrls->auto_exp, 0, false);
1671 v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY,
1672 V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
1673 V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
1675 v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX,
1676 V4L2_COLORFX_SKY_BLUE, ~0x6f, V4L2_COLORFX_NONE);
1678 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_WHITE_BALANCE_TEMPERATURE,
1681 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, -127, 127, 1, 0);
1682 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -127, 127, 1, 0);
1683 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -127, 127, 1, 0);
1684 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS, -127, 127, 1, 0);
1686 v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
1687 ARRAY_SIZE(s5k5baf_test_pattern_menu) - 1,
1688 0, 0, s5k5baf_test_pattern_menu);
1691 v4l2_err(&state->sd, "error creating controls (%d)\n",
1694 v4l2_ctrl_handler_free(hdl);
1698 state->sd.ctrl_handler = hdl;
1703 * V4L2 subdev internal operations
1705 static int s5k5baf_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1707 struct v4l2_mbus_framefmt *mf;
1709 mf = v4l2_subdev_get_try_format(sd, fh->state, PAD_CIS);
1710 s5k5baf_try_cis_format(mf);
1712 if (s5k5baf_is_cis_subdev(sd))
1715 mf = v4l2_subdev_get_try_format(sd, fh->state, PAD_OUT);
1716 mf->colorspace = s5k5baf_formats[0].colorspace;
1717 mf->code = s5k5baf_formats[0].code;
1718 mf->width = s5k5baf_cis_rect.width;
1719 mf->height = s5k5baf_cis_rect.height;
1720 mf->field = V4L2_FIELD_NONE;
1722 *v4l2_subdev_get_try_crop(sd, fh->state, PAD_CIS) = s5k5baf_cis_rect;
1723 *v4l2_subdev_get_try_compose(sd, fh->state, PAD_CIS) = s5k5baf_cis_rect;
1724 *v4l2_subdev_get_try_crop(sd, fh->state, PAD_OUT) = s5k5baf_cis_rect;
1729 static int s5k5baf_check_fw_revision(struct s5k5baf *state)
1731 u16 api_ver = 0, fw_rev = 0, s_id = 0;
1734 api_ver = s5k5baf_read(state, REG_FW_APIVER);
1735 fw_rev = s5k5baf_read(state, REG_FW_REVISION) & 0xff;
1736 s_id = s5k5baf_read(state, REG_FW_SENSOR_ID);
1737 ret = s5k5baf_clear_error(state);
1741 v4l2_info(&state->sd, "FW API=%#x, revision=%#x sensor_id=%#x\n",
1742 api_ver, fw_rev, s_id);
1744 if (api_ver != S5K5BAF_FW_APIVER) {
1745 v4l2_err(&state->sd, "FW API version not supported\n");
1752 static int s5k5baf_registered(struct v4l2_subdev *sd)
1754 struct s5k5baf *state = to_s5k5baf(sd);
1757 ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->cis_sd);
1759 v4l2_err(sd, "failed to register subdev %s\n",
1760 state->cis_sd.name);
1762 ret = media_create_pad_link(&state->cis_sd.entity, PAD_CIS,
1763 &state->sd.entity, PAD_CIS,
1764 MEDIA_LNK_FL_IMMUTABLE |
1765 MEDIA_LNK_FL_ENABLED);
1769 static void s5k5baf_unregistered(struct v4l2_subdev *sd)
1771 struct s5k5baf *state = to_s5k5baf(sd);
1772 v4l2_device_unregister_subdev(&state->cis_sd);
1775 static const struct v4l2_subdev_ops s5k5baf_cis_subdev_ops = {
1776 .pad = &s5k5baf_cis_pad_ops,
1779 static const struct v4l2_subdev_internal_ops s5k5baf_cis_subdev_internal_ops = {
1780 .open = s5k5baf_open,
1783 static const struct v4l2_subdev_internal_ops s5k5baf_subdev_internal_ops = {
1784 .registered = s5k5baf_registered,
1785 .unregistered = s5k5baf_unregistered,
1786 .open = s5k5baf_open,
1789 static const struct v4l2_subdev_core_ops s5k5baf_core_ops = {
1790 .s_power = s5k5baf_set_power,
1791 .log_status = v4l2_ctrl_subdev_log_status,
1794 static const struct v4l2_subdev_ops s5k5baf_subdev_ops = {
1795 .core = &s5k5baf_core_ops,
1796 .pad = &s5k5baf_pad_ops,
1797 .video = &s5k5baf_video_ops,
1800 static int s5k5baf_configure_gpios(struct s5k5baf *state)
1802 static const char * const name[] = { "S5K5BAF_STBY", "S5K5BAF_RST" };
1803 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1804 struct s5k5baf_gpio *g = state->gpios;
1807 for (i = 0; i < NUM_GPIOS; ++i) {
1808 int flags = GPIOF_DIR_OUT;
1810 flags |= GPIOF_INIT_HIGH;
1811 ret = devm_gpio_request_one(&c->dev, g[i].gpio, flags, name[i]);
1813 v4l2_err(c, "failed to request gpio %s\n", name[i]);
1820 static int s5k5baf_parse_gpios(struct s5k5baf_gpio *gpios, struct device *dev)
1822 static const char * const names[] = {
1826 struct device_node *node = dev->of_node;
1827 enum of_gpio_flags flags;
1830 for (i = 0; i < NUM_GPIOS; ++i) {
1831 ret = of_get_named_gpio_flags(node, names[i], 0, &flags);
1833 dev_err(dev, "no %s GPIO pin provided\n", names[i]);
1836 gpios[i].gpio = ret;
1837 gpios[i].level = !(flags & OF_GPIO_ACTIVE_LOW);
1843 static int s5k5baf_parse_device_node(struct s5k5baf *state, struct device *dev)
1845 struct device_node *node = dev->of_node;
1846 struct device_node *node_ep;
1847 struct v4l2_fwnode_endpoint ep = { .bus_type = 0 };
1851 dev_err(dev, "no device-tree node provided\n");
1855 ret = of_property_read_u32(node, "clock-frequency",
1856 &state->mclk_frequency);
1858 state->mclk_frequency = S5K5BAF_DEFAULT_MCLK_FREQ;
1859 dev_info(dev, "using default %u Hz clock frequency\n",
1860 state->mclk_frequency);
1863 ret = s5k5baf_parse_gpios(state->gpios, dev);
1867 node_ep = of_graph_get_next_endpoint(node, NULL);
1869 dev_err(dev, "no endpoint defined at node %pOF\n", node);
1873 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(node_ep), &ep);
1874 of_node_put(node_ep);
1878 state->bus_type = ep.bus_type;
1880 switch (state->bus_type) {
1881 case V4L2_MBUS_CSI2_DPHY:
1882 state->nlanes = ep.bus.mipi_csi2.num_data_lanes;
1884 case V4L2_MBUS_PARALLEL:
1887 dev_err(dev, "unsupported bus in endpoint defined at node %pOF\n",
1895 static int s5k5baf_configure_subdevs(struct s5k5baf *state,
1896 struct i2c_client *c)
1898 struct v4l2_subdev *sd;
1901 sd = &state->cis_sd;
1902 v4l2_subdev_init(sd, &s5k5baf_cis_subdev_ops);
1903 sd->owner = THIS_MODULE;
1904 v4l2_set_subdevdata(sd, state);
1905 snprintf(sd->name, sizeof(sd->name), "S5K5BAF-CIS %d-%04x",
1906 i2c_adapter_id(c->adapter), c->addr);
1908 sd->internal_ops = &s5k5baf_cis_subdev_internal_ops;
1909 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1911 state->cis_pad.flags = MEDIA_PAD_FL_SOURCE;
1912 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1913 ret = media_entity_pads_init(&sd->entity, NUM_CIS_PADS, &state->cis_pad);
1918 v4l2_i2c_subdev_init(sd, c, &s5k5baf_subdev_ops);
1919 snprintf(sd->name, sizeof(sd->name), "S5K5BAF-ISP %d-%04x",
1920 i2c_adapter_id(c->adapter), c->addr);
1922 sd->internal_ops = &s5k5baf_subdev_internal_ops;
1923 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1925 state->pads[PAD_CIS].flags = MEDIA_PAD_FL_SINK;
1926 state->pads[PAD_OUT].flags = MEDIA_PAD_FL_SOURCE;
1927 sd->entity.function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN;
1928 ret = media_entity_pads_init(&sd->entity, NUM_ISP_PADS, state->pads);
1933 media_entity_cleanup(&state->cis_sd.entity);
1935 dev_err(&c->dev, "cannot init media entity %s\n", sd->name);
1939 static int s5k5baf_configure_regulators(struct s5k5baf *state)
1941 struct i2c_client *c = v4l2_get_subdevdata(&state->sd);
1945 for (i = 0; i < S5K5BAF_NUM_SUPPLIES; i++)
1946 state->supplies[i].supply = s5k5baf_supply_names[i];
1948 ret = devm_regulator_bulk_get(&c->dev, S5K5BAF_NUM_SUPPLIES,
1951 v4l2_err(c, "failed to get regulators\n");
1955 static int s5k5baf_probe(struct i2c_client *c)
1957 struct s5k5baf *state;
1960 state = devm_kzalloc(&c->dev, sizeof(*state), GFP_KERNEL);
1964 mutex_init(&state->lock);
1965 state->crop_sink = s5k5baf_cis_rect;
1966 state->compose = s5k5baf_cis_rect;
1967 state->crop_source = s5k5baf_cis_rect;
1969 ret = s5k5baf_parse_device_node(state, &c->dev);
1973 ret = s5k5baf_configure_subdevs(state, c);
1977 ret = s5k5baf_configure_gpios(state);
1981 ret = s5k5baf_configure_regulators(state);
1985 state->clock = devm_clk_get(state->sd.dev, S5K5BAF_CLK_NAME);
1986 if (IS_ERR(state->clock)) {
1987 ret = -EPROBE_DEFER;
1991 ret = s5k5baf_power_on(state);
1993 ret = -EPROBE_DEFER;
1996 s5k5baf_hw_init(state);
1997 ret = s5k5baf_check_fw_revision(state);
1999 s5k5baf_power_off(state);
2003 ret = s5k5baf_initialize_ctrls(state);
2007 ret = v4l2_async_register_subdev(&state->sd);
2014 v4l2_ctrl_handler_free(state->sd.ctrl_handler);
2016 media_entity_cleanup(&state->sd.entity);
2017 media_entity_cleanup(&state->cis_sd.entity);
2021 static void s5k5baf_remove(struct i2c_client *c)
2023 struct v4l2_subdev *sd = i2c_get_clientdata(c);
2024 struct s5k5baf *state = to_s5k5baf(sd);
2026 v4l2_async_unregister_subdev(sd);
2027 v4l2_ctrl_handler_free(sd->ctrl_handler);
2028 media_entity_cleanup(&sd->entity);
2030 sd = &state->cis_sd;
2031 v4l2_device_unregister_subdev(sd);
2032 media_entity_cleanup(&sd->entity);
2035 static const struct i2c_device_id s5k5baf_id[] = {
2036 { S5K5BAF_DRIVER_NAME, 0 },
2039 MODULE_DEVICE_TABLE(i2c, s5k5baf_id);
2041 static const struct of_device_id s5k5baf_of_match[] = {
2042 { .compatible = "samsung,s5k5baf" },
2045 MODULE_DEVICE_TABLE(of, s5k5baf_of_match);
2047 static struct i2c_driver s5k5baf_i2c_driver = {
2049 .of_match_table = s5k5baf_of_match,
2050 .name = S5K5BAF_DRIVER_NAME
2052 .probe_new = s5k5baf_probe,
2053 .remove = s5k5baf_remove,
2054 .id_table = s5k5baf_id,
2057 module_i2c_driver(s5k5baf_i2c_driver);
2059 MODULE_DESCRIPTION("Samsung S5K5BAF(X) UXGA camera driver");
2060 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
2061 MODULE_LICENSE("GPL v2");