2 * Omnivision OV9650/OV9652 CMOS Image Sensor driver
4 * Copyright (C) 2013, Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
6 * Register definitions and initial settings based on a driver written
8 * Copyright (c) 2010, Vladimir Fonov
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 #include <linux/delay.h>
15 #include <linux/gpio.h>
16 #include <linux/i2c.h>
17 #include <linux/kernel.h>
18 #include <linux/media.h>
19 #include <linux/module.h>
20 #include <linux/ratelimit.h>
21 #include <linux/slab.h>
22 #include <linux/string.h>
23 #include <linux/videodev2.h>
25 #include <media/media-entity.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-event.h>
30 #include <media/v4l2-image-sizes.h>
31 #include <media/v4l2-subdev.h>
32 #include <media/v4l2-mediabus.h>
33 #include <media/i2c/ov9650.h>
36 module_param(debug, int, 0644);
37 MODULE_PARM_DESC(debug, "Debug level (0-2)");
39 #define DRIVER_NAME "OV9650"
42 * OV9650/OV9652 register definitions
44 #define REG_GAIN 0x00 /* Gain control, AGC[7:0] */
45 #define REG_BLUE 0x01 /* AWB - Blue chanel gain */
46 #define REG_RED 0x02 /* AWB - Red chanel gain */
47 #define REG_VREF 0x03 /* [7:6] - AGC[9:8], [5:3]/[2:0] */
48 #define VREF_GAIN_MASK 0xc0 /* - VREF end/start low 3 bits */
50 #define COM1_CCIR656 0x40
51 #define REG_B_AVE 0x05
52 #define REG_GB_AVE 0x06
53 #define REG_GR_AVE 0x07
54 #define REG_R_AVE 0x08
56 #define REG_PID 0x0a /* Product ID MSB */
57 #define REG_VER 0x0b /* Product ID LSB */
59 #define COM3_SWAP 0x40
60 #define COM3_VARIOPIXEL1 0x04
61 #define REG_COM4 0x0d /* Vario Pixels */
62 #define COM4_VARIOPIXEL2 0x80
63 #define REG_COM5 0x0e /* System clock options */
64 #define COM5_SLAVE_MODE 0x10
65 #define COM5_SYSTEMCLOCK48MHZ 0x80
66 #define REG_COM6 0x0f /* HREF & ADBLC options */
67 #define REG_AECH 0x10 /* Exposure value, AEC[9:2] */
68 #define REG_CLKRC 0x11 /* Clock control */
69 #define CLK_EXT 0x40 /* Use external clock directly */
70 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
71 #define REG_COM7 0x12 /* SCCB reset, output format */
72 #define COM7_RESET 0x80
73 #define COM7_FMT_MASK 0x38
74 #define COM7_FMT_VGA 0x40
75 #define COM7_FMT_CIF 0x20
76 #define COM7_FMT_QVGA 0x10
77 #define COM7_FMT_QCIF 0x08
80 #define COM7_BAYER 0x01
81 #define COM7_PBAYER 0x05
82 #define REG_COM8 0x13 /* AGC/AEC options */
83 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
84 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
85 #define COM8_BFILT 0x20 /* Band filter enable */
86 #define COM8_AGC 0x04 /* Auto gain enable */
87 #define COM8_AWB 0x02 /* White balance enable */
88 #define COM8_AEC 0x01 /* Auto exposure enable */
89 #define REG_COM9 0x14 /* Gain ceiling */
90 #define COM9_GAIN_CEIL_MASK 0x70 /* */
91 #define REG_COM10 0x15 /* PCLK, HREF, HSYNC signals polarity */
92 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
93 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
94 #define COM10_HREF_REV 0x08 /* Reverse HREF */
95 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
96 #define COM10_VS_NEG 0x02 /* VSYNC negative */
97 #define COM10_HS_NEG 0x01 /* HSYNC negative */
98 #define REG_HSTART 0x17 /* Horiz start high bits */
99 #define REG_HSTOP 0x18 /* Horiz stop high bits */
100 #define REG_VSTART 0x19 /* Vert start high bits */
101 #define REG_VSTOP 0x1a /* Vert stop high bits */
102 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
103 #define REG_MIDH 0x1c /* Manufacturer ID MSB */
104 #define REG_MIDL 0x1d /* Manufufacturer ID LSB */
105 #define REG_MVFP 0x1e /* Image mirror/flip */
106 #define MVFP_MIRROR 0x20 /* Mirror image */
107 #define MVFP_FLIP 0x10 /* Vertical flip */
108 #define REG_BOS 0x20 /* B channel Offset */
109 #define REG_GBOS 0x21 /* Gb channel Offset */
110 #define REG_GROS 0x22 /* Gr channel Offset */
111 #define REG_ROS 0x23 /* R channel Offset */
112 #define REG_AEW 0x24 /* AGC upper limit */
113 #define REG_AEB 0x25 /* AGC lower limit */
114 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
115 #define REG_BBIAS 0x27 /* B channel output bias */
116 #define REG_GBBIAS 0x28 /* Gb channel output bias */
117 #define REG_GRCOM 0x29 /* Analog BLC & regulator */
118 #define REG_EXHCH 0x2a /* Dummy pixel insert MSB */
119 #define REG_EXHCL 0x2b /* Dummy pixel insert LSB */
120 #define REG_RBIAS 0x2c /* R channel output bias */
121 #define REG_ADVFL 0x2d /* LSB of dummy line insert */
122 #define REG_ADVFH 0x2e /* MSB of dummy line insert */
123 #define REG_YAVE 0x2f /* Y/G channel average value */
124 #define REG_HSYST 0x30 /* HSYNC rising edge delay LSB*/
125 #define REG_HSYEN 0x31 /* HSYNC falling edge delay LSB*/
126 #define REG_HREF 0x32 /* HREF pieces */
127 #define REG_CHLF 0x33 /* reserved */
128 #define REG_ADC 0x37 /* reserved */
129 #define REG_ACOM 0x38 /* reserved */
130 #define REG_OFON 0x39 /* Power down register */
131 #define OFON_PWRDN 0x08 /* Power down bit */
132 #define REG_TSLB 0x3a /* YUVU format */
133 #define TSLB_YUYV_MASK 0x0c /* UYVY or VYUY - see com13 */
134 #define REG_COM11 0x3b /* Night mode, banding filter enable */
135 #define COM11_NIGHT 0x80 /* Night mode enable */
136 #define COM11_NMFR 0x60 /* Two bit NM frame rate */
137 #define COM11_BANDING 0x01 /* Banding filter */
138 #define COM11_AEC_REF_MASK 0x18 /* AEC reference area selection */
139 #define REG_COM12 0x3c /* HREF option, UV average */
140 #define COM12_HREF 0x80 /* HREF always */
141 #define REG_COM13 0x3d /* Gamma selection, Color matrix en. */
142 #define COM13_GAMMA 0x80 /* Gamma enable */
143 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
144 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
145 #define REG_COM14 0x3e /* Edge enhancement options */
146 #define COM14_EDGE_EN 0x02
147 #define COM14_EEF_X2 0x01
148 #define REG_EDGE 0x3f /* Edge enhancement factor */
149 #define EDGE_FACTOR_MASK 0x0f
150 #define REG_COM15 0x40 /* Output range, RGB 555/565 */
151 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
152 #define COM15_R01FE 0x80 /* 01 to FE */
153 #define COM15_R00FF 0xc0 /* 00 to FF */
154 #define COM15_RGB565 0x10 /* RGB565 output */
155 #define COM15_RGB555 0x30 /* RGB555 output */
156 #define COM15_SWAPRB 0x04 /* Swap R&B */
157 #define REG_COM16 0x41 /* Color matrix coeff options */
158 #define REG_COM17 0x42 /* Single frame out, banding filter */
159 /* n = 1...9, 0x4f..0x57 */
160 #define REG_MTX(__n) (0x4f + (__n) - 1)
161 #define REG_MTXS 0x58
162 /* Lens Correction Option 1...5, __n = 0...5 */
163 #define REG_LCC(__n) (0x62 + (__n) - 1)
164 #define LCC5_LCC_ENABLE 0x01 /* LCC5, enable lens correction */
165 #define LCC5_LCC_COLOR 0x04
166 #define REG_MANU 0x67 /* Manual U value */
167 #define REG_MANV 0x68 /* Manual V value */
168 #define REG_HV 0x69 /* Manual banding filter MSB */
169 #define REG_MBD 0x6a /* Manual banding filter value */
170 #define REG_DBLV 0x6b /* reserved */
171 #define REG_GSP 0x6c /* Gamma curve */
173 #define REG_GST 0x7c /* Gamma curve */
175 #define REG_COM21 0x8b
176 #define REG_COM22 0x8c /* Edge enhancement, denoising */
177 #define COM22_WHTPCOR 0x02 /* White pixel correction enable */
178 #define COM22_WHTPCOROPT 0x01 /* White pixel correction option */
179 #define COM22_DENOISE 0x10 /* White pixel correction option */
180 #define REG_COM23 0x8d /* Color bar test, color gain */
181 #define COM23_TEST_MODE 0x10
182 #define REG_DBLC1 0x8f /* Digital BLC */
183 #define REG_DBLC_B 0x90 /* Digital BLC B channel offset */
184 #define REG_DBLC_R 0x91 /* Digital BLC R channel offset */
185 #define REG_DM_LNL 0x92 /* Dummy line low 8 bits */
186 #define REG_DM_LNH 0x93 /* Dummy line high 8 bits */
187 #define REG_LCCFB 0x9d /* Lens Correction B channel */
188 #define REG_LCCFR 0x9e /* Lens Correction R channel */
189 #define REG_DBLC_GB 0x9f /* Digital BLC GB chan offset */
190 #define REG_DBLC_GR 0xa0 /* Digital BLC GR chan offset */
191 #define REG_AECHM 0xa1 /* Exposure value - bits AEC[15:10] */
192 #define REG_BD50ST 0xa2 /* Banding filter value for 50Hz */
193 #define REG_BD60ST 0xa3 /* Banding filter value for 60Hz */
194 #define REG_NULL 0xff /* Array end token */
196 #define DEF_CLKRC 0x80
198 #define OV965X_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
199 #define OV9650_ID 0x9650
200 #define OV9652_ID 0x9652
202 struct ov965x_ctrls {
203 struct v4l2_ctrl_handler handler;
205 struct v4l2_ctrl *auto_exp;
206 struct v4l2_ctrl *exposure;
209 struct v4l2_ctrl *auto_wb;
210 struct v4l2_ctrl *blue_balance;
211 struct v4l2_ctrl *red_balance;
214 struct v4l2_ctrl *hflip;
215 struct v4l2_ctrl *vflip;
218 struct v4l2_ctrl *auto_gain;
219 struct v4l2_ctrl *gain;
221 struct v4l2_ctrl *brightness;
222 struct v4l2_ctrl *saturation;
223 struct v4l2_ctrl *sharpness;
224 struct v4l2_ctrl *light_freq;
228 struct ov965x_framesize {
235 struct ov965x_interval {
236 struct v4l2_fract interval;
237 /* Maximum resolution for this interval */
238 struct v4l2_frmsize_discrete size;
249 struct v4l2_subdev sd;
250 struct media_pad pad;
251 enum v4l2_mbus_type bus_type;
252 int gpios[NUM_GPIOS];
253 /* External master clock frequency */
254 unsigned long mclk_frequency;
256 /* Protects the struct fields below */
259 struct i2c_client *client;
261 /* Exposure row interval in us */
262 unsigned int exp_row_interval;
265 const struct ov965x_framesize *frame_size;
266 /* YUYV sequence (pixel format) control register */
268 struct v4l2_mbus_framefmt format;
270 struct ov965x_ctrls ctrls;
271 /* Pointer to frame rate control data structure */
272 const struct ov965x_interval *fiv;
285 static const struct i2c_rv ov965x_init_regs[] = {
286 { REG_COM2, 0x10 }, /* Set soft sleep mode */
287 { REG_COM5, 0x00 }, /* System clock options */
288 { REG_COM2, 0x01 }, /* Output drive, soft sleep mode */
289 { REG_COM10, 0x00 }, /* Slave mode, HREF vs HSYNC, signals negate */
290 { REG_EDGE, 0xa6 }, /* Edge enhancement treshhold and factor */
291 { REG_COM16, 0x02 }, /* Color matrix coeff double option */
292 { REG_COM17, 0x08 }, /* Single frame out, banding filter */
294 { REG_CHLF, 0xc0 }, /* Reserved */
299 { REG_COM12, 0x77 }, /* HREF option, UV average */
304 { REG_COM15, 0xc1 }, /* Output range, RGB 555/565 */
305 { REG_GRCOM, 0x2f }, /* Analog BLC & regulator */
306 { REG_COM6, 0x43 }, /* HREF & ADBLC options */
307 { REG_COM8, 0xe5 }, /* AGC/AEC options */
308 { REG_COM13, 0x90 }, /* Gamma selection, colour matrix, UV delay */
309 { REG_HV, 0x80 }, /* Manual banding filter MSB */
310 { 0x5c, 0x96 }, /* Reserved up to 0xa5 */
326 { 0xa4, 0x74 }, /* reserved */
327 { REG_COM23, 0x02 }, /* Color gain analog/_digital_ */
328 { REG_COM8, 0xe7 }, /* Enable AEC, AWB, AEC */
329 { REG_COM22, 0x23 }, /* Edge enhancement, denoising */
333 { REG_DBLC1, 0xdf }, /* Digital BLC */
334 { REG_DBLC_B, 0x00 }, /* Digital BLC B chan offset */
335 { REG_DBLC_R, 0x00 }, /* Digital BLC R chan offset */
336 { REG_DBLC_GB, 0x00 }, /* Digital BLC GB chan offset */
337 { REG_DBLC_GR, 0x00 },
338 { REG_COM9, 0x3a }, /* Gain ceiling 16x */
342 #define NUM_FMT_REGS 14
344 * COM7, COM3, COM4, HSTART, HSTOP, HREF, VSTART, VSTOP, VREF,
345 * EXHCH, EXHCL, ADC, OCOM, OFON
347 static const u8 frame_size_reg_addr[NUM_FMT_REGS] = {
348 0x12, 0x0c, 0x0d, 0x17, 0x18, 0x32, 0x19, 0x1a, 0x03,
349 0x2a, 0x2b, 0x37, 0x38, 0x39,
352 static const u8 ov965x_sxga_regs[NUM_FMT_REGS] = {
353 0x00, 0x00, 0x00, 0x1e, 0xbe, 0xbf, 0x01, 0x81, 0x12,
354 0x10, 0x34, 0x81, 0x93, 0x51,
357 static const u8 ov965x_vga_regs[NUM_FMT_REGS] = {
358 0x40, 0x04, 0x80, 0x26, 0xc6, 0xed, 0x01, 0x3d, 0x00,
359 0x10, 0x40, 0x91, 0x12, 0x43,
362 /* Determined empirically. */
363 static const u8 ov965x_qvga_regs[NUM_FMT_REGS] = {
364 0x10, 0x04, 0x80, 0x25, 0xc5, 0xbf, 0x00, 0x80, 0x12,
365 0x10, 0x40, 0x91, 0x12, 0x43,
368 static const struct ov965x_framesize ov965x_framesizes[] = {
371 .height = SXGA_HEIGHT,
372 .regs = ov965x_sxga_regs,
373 .max_exp_lines = 1048,
376 .height = VGA_HEIGHT,
377 .regs = ov965x_vga_regs,
378 .max_exp_lines = 498,
381 .height = QVGA_HEIGHT,
382 .regs = ov965x_qvga_regs,
383 .max_exp_lines = 248,
387 struct ov965x_pixfmt {
390 /* REG_TSLB value, only bits [3:2] may be set. */
394 static const struct ov965x_pixfmt ov965x_formats[] = {
395 { MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG, 0x00},
396 { MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG, 0x04},
397 { MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG, 0x0c},
398 { MEDIA_BUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG, 0x08},
402 * This table specifies possible frame resolution and interval
403 * combinations. Default CLKRC[5:0] divider values are valid
404 * only for 24 MHz external clock frequency.
406 static struct ov965x_interval ov965x_intervals[] = {
407 {{ 100, 625 }, { SXGA_WIDTH, SXGA_HEIGHT }, 0 }, /* 6.25 fps */
408 {{ 10, 125 }, { VGA_WIDTH, VGA_HEIGHT }, 1 }, /* 12.5 fps */
409 {{ 10, 125 }, { QVGA_WIDTH, QVGA_HEIGHT }, 3 }, /* 12.5 fps */
410 {{ 1, 25 }, { VGA_WIDTH, VGA_HEIGHT }, 0 }, /* 25 fps */
411 {{ 1, 25 }, { QVGA_WIDTH, QVGA_HEIGHT }, 1 }, /* 25 fps */
414 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
416 return &container_of(ctrl->handler, struct ov965x, ctrls.handler)->sd;
419 static inline struct ov965x *to_ov965x(struct v4l2_subdev *sd)
421 return container_of(sd, struct ov965x, sd);
424 static int ov965x_read(struct i2c_client *client, u8 addr, u8 *val)
427 struct i2c_msg msg = {
428 .addr = client->addr,
435 ret = i2c_transfer(client->adapter, &msg, 1);
437 msg.flags = I2C_M_RD;
438 ret = i2c_transfer(client->adapter, &msg, 1);
444 v4l2_dbg(2, debug, client, "%s: 0x%02x @ 0x%02x. (%d)\n",
445 __func__, *val, addr, ret);
447 return ret == 1 ? 0 : ret;
450 static int ov965x_write(struct i2c_client *client, u8 addr, u8 val)
452 u8 buf[2] = { addr, val };
454 int ret = i2c_master_send(client, buf, 2);
456 v4l2_dbg(2, debug, client, "%s: 0x%02x @ 0x%02X (%d)\n",
457 __func__, val, addr, ret);
459 return ret == 2 ? 0 : ret;
462 static int ov965x_write_array(struct i2c_client *client,
463 const struct i2c_rv *regs)
467 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
468 ret = ov965x_write(client, regs[i].addr, regs[i].value);
473 static int ov965x_set_default_gamma_curve(struct ov965x *ov965x)
475 static const u8 gamma_curve[] = {
476 /* Values taken from OV application note. */
477 0x40, 0x30, 0x4b, 0x60, 0x70, 0x70, 0x70, 0x70,
478 0x60, 0x60, 0x50, 0x48, 0x3a, 0x2e, 0x28, 0x22,
479 0x04, 0x07, 0x10, 0x28, 0x36, 0x44, 0x52, 0x60,
480 0x6c, 0x78, 0x8c, 0x9e, 0xbb, 0xd2, 0xe6
485 for (i = 0; i < ARRAY_SIZE(gamma_curve); i++) {
486 int ret = ov965x_write(ov965x->client, addr, gamma_curve[i]);
496 static int ov965x_set_color_matrix(struct ov965x *ov965x)
498 static const u8 mtx[] = {
499 /* MTX1..MTX9, MTXS */
500 0x3a, 0x3d, 0x03, 0x12, 0x26, 0x38, 0x40, 0x40, 0x40, 0x0d
502 u8 addr = REG_MTX(1);
505 for (i = 0; i < ARRAY_SIZE(mtx); i++) {
506 int ret = ov965x_write(ov965x->client, addr, mtx[i]);
516 static void ov965x_gpio_set(int gpio, int val)
518 if (gpio_is_valid(gpio))
519 gpio_set_value(gpio, val);
522 static void __ov965x_set_power(struct ov965x *ov965x, int on)
525 ov965x_gpio_set(ov965x->gpios[GPIO_PWDN], 0);
526 ov965x_gpio_set(ov965x->gpios[GPIO_RST], 0);
529 ov965x_gpio_set(ov965x->gpios[GPIO_RST], 1);
530 ov965x_gpio_set(ov965x->gpios[GPIO_PWDN], 1);
533 ov965x->streaming = 0;
536 static int ov965x_s_power(struct v4l2_subdev *sd, int on)
538 struct ov965x *ov965x = to_ov965x(sd);
539 struct i2c_client *client = ov965x->client;
542 v4l2_dbg(1, debug, client, "%s: on: %d\n", __func__, on);
544 mutex_lock(&ov965x->lock);
545 if (ov965x->power == !on) {
546 __ov965x_set_power(ov965x, on);
548 ret = ov965x_write_array(client,
550 ov965x->apply_frame_fmt = 1;
551 ov965x->ctrls.update = 1;
555 ov965x->power += on ? 1 : -1;
557 WARN_ON(ov965x->power < 0);
558 mutex_unlock(&ov965x->lock);
566 static void ov965x_update_exposure_ctrl(struct ov965x *ov965x)
568 struct v4l2_ctrl *ctrl = ov965x->ctrls.exposure;
569 unsigned long fint, trow;
573 mutex_lock(&ov965x->lock);
574 if (WARN_ON(!ctrl || !ov965x->frame_size)) {
575 mutex_unlock(&ov965x->lock);
578 clkrc = DEF_CLKRC + ov965x->fiv->clkrc_div;
579 /* Calculate internal clock frequency */
580 fint = ov965x->mclk_frequency * ((clkrc >> 7) + 1) /
581 ((2 * ((clkrc & 0x3f) + 1)));
582 /* and the row interval (in us). */
583 trow = (2 * 1520 * 1000000UL) / fint;
584 max = ov965x->frame_size->max_exp_lines * trow;
585 ov965x->exp_row_interval = trow;
586 mutex_unlock(&ov965x->lock);
588 v4l2_dbg(1, debug, &ov965x->sd, "clkrc: %#x, fi: %lu, tr: %lu, %d\n",
589 clkrc, fint, trow, max);
591 /* Update exposure time range to match current frame format. */
592 min = (trow + 100) / 100;
593 max = (max - 100) / 100;
594 def = min + (max - min) / 2;
596 if (v4l2_ctrl_modify_range(ctrl, min, max, 1, def))
597 v4l2_err(&ov965x->sd, "Exposure ctrl range update failed\n");
600 static int ov965x_set_banding_filter(struct ov965x *ov965x, int value)
602 unsigned long mbd, light_freq;
606 ret = ov965x_read(ov965x->client, REG_COM8, ®);
608 if (value == V4L2_CID_POWER_LINE_FREQUENCY_DISABLED)
612 ret = ov965x_write(ov965x->client, REG_COM8, reg);
614 if (value == V4L2_CID_POWER_LINE_FREQUENCY_DISABLED)
616 if (WARN_ON(!ov965x->fiv))
618 /* Set minimal exposure time for 50/60 HZ lighting */
619 if (value == V4L2_CID_POWER_LINE_FREQUENCY_50HZ)
623 mbd = (1000UL * ov965x->fiv->interval.denominator *
624 ov965x->frame_size->max_exp_lines) /
625 ov965x->fiv->interval.numerator;
626 mbd = ((mbd / (light_freq * 2)) + 500) / 1000UL;
628 return ov965x_write(ov965x->client, REG_MBD, mbd);
631 static int ov965x_set_white_balance(struct ov965x *ov965x, int awb)
636 ret = ov965x_read(ov965x->client, REG_COM8, ®);
638 reg = awb ? reg | REG_COM8 : reg & ~REG_COM8;
639 ret = ov965x_write(ov965x->client, REG_COM8, reg);
642 ret = ov965x_write(ov965x->client, REG_BLUE,
643 ov965x->ctrls.blue_balance->val);
646 ret = ov965x_write(ov965x->client, REG_RED,
647 ov965x->ctrls.red_balance->val);
652 #define NUM_BR_LEVELS 7
653 #define NUM_BR_REGS 3
655 static int ov965x_set_brightness(struct ov965x *ov965x, int val)
657 static const u8 regs[NUM_BR_LEVELS + 1][NUM_BR_REGS] = {
658 { REG_AEW, REG_AEB, REG_VPT },
659 { 0x1c, 0x12, 0x50 }, /* -3 */
660 { 0x3d, 0x30, 0x71 }, /* -2 */
661 { 0x50, 0x44, 0x92 }, /* -1 */
662 { 0x70, 0x64, 0xc3 }, /* 0 */
663 { 0x90, 0x84, 0xd4 }, /* +1 */
664 { 0xc4, 0xbf, 0xf9 }, /* +2 */
665 { 0xd8, 0xd0, 0xfa }, /* +3 */
669 val += (NUM_BR_LEVELS / 2 + 1);
670 if (val > NUM_BR_LEVELS)
673 for (i = 0; i < NUM_BR_REGS && !ret; i++)
674 ret = ov965x_write(ov965x->client, regs[0][i],
679 static int ov965x_set_gain(struct ov965x *ov965x, int auto_gain)
681 struct i2c_client *client = ov965x->client;
682 struct ov965x_ctrls *ctrls = &ov965x->ctrls;
686 * For manual mode we need to disable AGC first, so
687 * gain value in REG_VREF, REG_GAIN is not overwritten.
689 if (ctrls->auto_gain->is_new) {
690 ret = ov965x_read(client, REG_COM8, ®);
693 if (ctrls->auto_gain->val)
697 ret = ov965x_write(client, REG_COM8, reg);
702 if (ctrls->gain->is_new && !auto_gain) {
703 unsigned int gain = ctrls->gain->val;
707 * Convert gain control value to the sensor's gain
708 * registers (VREF[7:6], GAIN[7:0]) format.
710 for (m = 6; m >= 0; m--)
711 if (gain >= (1 << m) * 16)
714 /* Sanity check: don't adjust the gain with a negative value */
718 rgain = (gain - ((1 << m) * 16)) / (1 << m);
719 rgain |= (((1 << m) - 1) << 4);
721 ret = ov965x_write(client, REG_GAIN, rgain & 0xff);
724 ret = ov965x_read(client, REG_VREF, ®);
727 reg &= ~VREF_GAIN_MASK;
728 reg |= (((rgain >> 8) & 0x3) << 6);
729 ret = ov965x_write(client, REG_VREF, reg);
732 /* Return updated control's value to userspace */
733 ctrls->gain->val = (1 << m) * (16 + (rgain & 0xf));
739 static int ov965x_set_sharpness(struct ov965x *ov965x, unsigned int value)
744 ret = ov965x_read(ov965x->client, REG_COM14, &com14);
747 ret = ov965x_read(ov965x->client, REG_EDGE, &edge);
750 com14 = value ? com14 | COM14_EDGE_EN : com14 & ~COM14_EDGE_EN;
753 com14 |= COM14_EEF_X2;
756 com14 &= ~COM14_EEF_X2;
758 ret = ov965x_write(ov965x->client, REG_COM14, com14);
762 edge &= ~EDGE_FACTOR_MASK;
763 edge |= ((u8)value & 0x0f);
765 return ov965x_write(ov965x->client, REG_EDGE, edge);
768 static int ov965x_set_exposure(struct ov965x *ov965x, int exp)
770 struct i2c_client *client = ov965x->client;
771 struct ov965x_ctrls *ctrls = &ov965x->ctrls;
772 bool auto_exposure = (exp == V4L2_EXPOSURE_AUTO);
776 if (ctrls->auto_exp->is_new) {
777 ret = ov965x_read(client, REG_COM8, ®);
781 reg |= (COM8_AEC | COM8_AGC);
783 reg &= ~(COM8_AEC | COM8_AGC);
784 ret = ov965x_write(client, REG_COM8, reg);
789 if (!auto_exposure && ctrls->exposure->is_new) {
790 unsigned int exposure = (ctrls->exposure->val * 100)
791 / ov965x->exp_row_interval;
793 * Manual exposure value
794 * [b15:b0] - AECHM (b15:b10), AECH (b9:b2), COM1 (b1:b0)
796 ret = ov965x_write(client, REG_COM1, exposure & 0x3);
798 ret = ov965x_write(client, REG_AECH,
799 (exposure >> 2) & 0xff);
801 ret = ov965x_write(client, REG_AECHM,
802 (exposure >> 10) & 0x3f);
803 /* Update the value to minimize rounding errors */
804 ctrls->exposure->val = ((exposure * ov965x->exp_row_interval)
810 v4l2_ctrl_activate(ov965x->ctrls.brightness, !exp);
814 static int ov965x_set_flip(struct ov965x *ov965x)
818 if (ov965x->ctrls.hflip->val)
821 if (ov965x->ctrls.vflip->val)
824 return ov965x_write(ov965x->client, REG_MVFP, mvfp);
827 #define NUM_SAT_LEVELS 5
828 #define NUM_SAT_REGS 6
830 static int ov965x_set_saturation(struct ov965x *ov965x, int val)
832 static const u8 regs[NUM_SAT_LEVELS][NUM_SAT_REGS] = {
833 /* MTX(1)...MTX(6) */
834 { 0x1d, 0x1f, 0x02, 0x09, 0x13, 0x1c }, /* -2 */
835 { 0x2e, 0x31, 0x02, 0x0e, 0x1e, 0x2d }, /* -1 */
836 { 0x3a, 0x3d, 0x03, 0x12, 0x26, 0x38 }, /* 0 */
837 { 0x46, 0x49, 0x04, 0x16, 0x2e, 0x43 }, /* +1 */
838 { 0x57, 0x5c, 0x05, 0x1b, 0x39, 0x54 }, /* +2 */
840 u8 addr = REG_MTX(1);
843 val += (NUM_SAT_LEVELS / 2);
844 if (val >= NUM_SAT_LEVELS)
847 for (i = 0; i < NUM_SAT_REGS && !ret; i++)
848 ret = ov965x_write(ov965x->client, addr + i, regs[val][i]);
853 static int ov965x_set_test_pattern(struct ov965x *ov965x, int value)
858 ret = ov965x_read(ov965x->client, REG_COM23, ®);
861 reg = value ? reg | COM23_TEST_MODE : reg & ~COM23_TEST_MODE;
862 return ov965x_write(ov965x->client, REG_COM23, reg);
865 static int __g_volatile_ctrl(struct ov965x *ov965x, struct v4l2_ctrl *ctrl)
867 struct i2c_client *client = ov965x->client;
868 unsigned int exposure, gain, m;
876 case V4L2_CID_AUTOGAIN:
879 ret = ov965x_read(client, REG_GAIN, ®0);
882 ret = ov965x_read(client, REG_VREF, ®1);
885 gain = ((reg1 >> 6) << 8) | reg0;
886 m = 0x01 << fls(gain >> 4);
887 ov965x->ctrls.gain->val = m * (16 + (gain & 0xf));
890 case V4L2_CID_EXPOSURE_AUTO:
891 if (ctrl->val == V4L2_EXPOSURE_MANUAL)
893 ret = ov965x_read(client, REG_COM1, ®0);
895 ret = ov965x_read(client, REG_AECH, ®1);
897 ret = ov965x_read(client, REG_AECHM, ®2);
900 exposure = ((reg2 & 0x3f) << 10) | (reg1 << 2) |
902 ov965x->ctrls.exposure->val = ((exposure *
903 ov965x->exp_row_interval) + 50) / 100;
910 static int ov965x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
912 struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
913 struct ov965x *ov965x = to_ov965x(sd);
916 v4l2_dbg(1, debug, sd, "g_ctrl: %s\n", ctrl->name);
918 mutex_lock(&ov965x->lock);
919 ret = __g_volatile_ctrl(ov965x, ctrl);
920 mutex_unlock(&ov965x->lock);
924 static int ov965x_s_ctrl(struct v4l2_ctrl *ctrl)
926 struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
927 struct ov965x *ov965x = to_ov965x(sd);
930 v4l2_dbg(1, debug, sd, "s_ctrl: %s, value: %d. power: %d\n",
931 ctrl->name, ctrl->val, ov965x->power);
933 mutex_lock(&ov965x->lock);
935 * If the device is not powered up now postpone applying control's
936 * value to the hardware, until it is ready to accept commands.
938 if (ov965x->power == 0) {
939 mutex_unlock(&ov965x->lock);
944 case V4L2_CID_AUTO_WHITE_BALANCE:
945 ret = ov965x_set_white_balance(ov965x, ctrl->val);
948 case V4L2_CID_BRIGHTNESS:
949 ret = ov965x_set_brightness(ov965x, ctrl->val);
952 case V4L2_CID_EXPOSURE_AUTO:
953 ret = ov965x_set_exposure(ov965x, ctrl->val);
956 case V4L2_CID_AUTOGAIN:
957 ret = ov965x_set_gain(ov965x, ctrl->val);
961 ret = ov965x_set_flip(ov965x);
964 case V4L2_CID_POWER_LINE_FREQUENCY:
965 ret = ov965x_set_banding_filter(ov965x, ctrl->val);
968 case V4L2_CID_SATURATION:
969 ret = ov965x_set_saturation(ov965x, ctrl->val);
972 case V4L2_CID_SHARPNESS:
973 ret = ov965x_set_sharpness(ov965x, ctrl->val);
976 case V4L2_CID_TEST_PATTERN:
977 ret = ov965x_set_test_pattern(ov965x, ctrl->val);
981 mutex_unlock(&ov965x->lock);
985 static const struct v4l2_ctrl_ops ov965x_ctrl_ops = {
986 .g_volatile_ctrl = ov965x_g_volatile_ctrl,
987 .s_ctrl = ov965x_s_ctrl,
990 static const char * const test_pattern_menu[] = {
996 static int ov965x_initialize_controls(struct ov965x *ov965x)
998 const struct v4l2_ctrl_ops *ops = &ov965x_ctrl_ops;
999 struct ov965x_ctrls *ctrls = &ov965x->ctrls;
1000 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1003 ret = v4l2_ctrl_handler_init(hdl, 16);
1007 /* Auto/manual white balance */
1008 ctrls->auto_wb = v4l2_ctrl_new_std(hdl, ops,
1009 V4L2_CID_AUTO_WHITE_BALANCE,
1011 ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
1013 ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
1015 /* Auto/manual exposure */
1017 v4l2_ctrl_new_std_menu(hdl, ops,
1018 V4L2_CID_EXPOSURE_AUTO,
1019 V4L2_EXPOSURE_MANUAL, 0,
1020 V4L2_EXPOSURE_AUTO);
1021 /* Exposure time, in 100 us units. min/max is updated dynamically. */
1022 ctrls->exposure = v4l2_ctrl_new_std(hdl, ops,
1023 V4L2_CID_EXPOSURE_ABSOLUTE,
1025 /* Auto/manual gain */
1026 ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTOGAIN,
1028 ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN,
1029 16, 64 * (16 + 15), 1, 64 * 16);
1031 ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
1033 ctrls->brightness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS,
1035 ctrls->sharpness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS,
1038 ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1039 ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1042 v4l2_ctrl_new_std_menu(hdl, ops,
1043 V4L2_CID_POWER_LINE_FREQUENCY,
1044 V4L2_CID_POWER_LINE_FREQUENCY_60HZ, ~0x7,
1045 V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
1047 v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
1048 ARRAY_SIZE(test_pattern_menu) - 1, 0, 0,
1052 v4l2_ctrl_handler_free(hdl);
1056 ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
1057 ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
1059 v4l2_ctrl_auto_cluster(3, &ctrls->auto_wb, 0, false);
1060 v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true);
1061 v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true);
1062 v4l2_ctrl_cluster(2, &ctrls->hflip);
1064 ov965x->sd.ctrl_handler = hdl;
1069 * V4L2 subdev video and pad level operations
1071 static void ov965x_get_default_format(struct v4l2_mbus_framefmt *mf)
1073 mf->width = ov965x_framesizes[0].width;
1074 mf->height = ov965x_framesizes[0].height;
1075 mf->colorspace = ov965x_formats[0].colorspace;
1076 mf->code = ov965x_formats[0].code;
1077 mf->field = V4L2_FIELD_NONE;
1080 static int ov965x_enum_mbus_code(struct v4l2_subdev *sd,
1081 struct v4l2_subdev_pad_config *cfg,
1082 struct v4l2_subdev_mbus_code_enum *code)
1084 if (code->index >= ARRAY_SIZE(ov965x_formats))
1087 code->code = ov965x_formats[code->index].code;
1091 static int ov965x_enum_frame_sizes(struct v4l2_subdev *sd,
1092 struct v4l2_subdev_pad_config *cfg,
1093 struct v4l2_subdev_frame_size_enum *fse)
1095 int i = ARRAY_SIZE(ov965x_formats);
1097 if (fse->index >= ARRAY_SIZE(ov965x_framesizes))
1101 if (fse->code == ov965x_formats[i].code)
1104 fse->code = ov965x_formats[i].code;
1106 fse->min_width = ov965x_framesizes[fse->index].width;
1107 fse->max_width = fse->min_width;
1108 fse->max_height = ov965x_framesizes[fse->index].height;
1109 fse->min_height = fse->max_height;
1114 static int ov965x_g_frame_interval(struct v4l2_subdev *sd,
1115 struct v4l2_subdev_frame_interval *fi)
1117 struct ov965x *ov965x = to_ov965x(sd);
1119 mutex_lock(&ov965x->lock);
1120 fi->interval = ov965x->fiv->interval;
1121 mutex_unlock(&ov965x->lock);
1126 static int __ov965x_set_frame_interval(struct ov965x *ov965x,
1127 struct v4l2_subdev_frame_interval *fi)
1129 struct v4l2_mbus_framefmt *mbus_fmt = &ov965x->format;
1130 const struct ov965x_interval *fiv = &ov965x_intervals[0];
1131 u64 req_int, err, min_err = ~0ULL;
1134 if (fi->interval.denominator == 0)
1137 req_int = (u64)(fi->interval.numerator * 10000) /
1138 fi->interval.denominator;
1140 for (i = 0; i < ARRAY_SIZE(ov965x_intervals); i++) {
1141 const struct ov965x_interval *iv = &ov965x_intervals[i];
1143 if (mbus_fmt->width != iv->size.width ||
1144 mbus_fmt->height != iv->size.height)
1146 err = abs((u64)(iv->interval.numerator * 10000) /
1147 iv->interval.denominator - req_int);
1148 if (err < min_err) {
1155 v4l2_dbg(1, debug, &ov965x->sd, "Changed frame interval to %u us\n",
1156 fiv->interval.numerator * 1000000 / fiv->interval.denominator);
1161 static int ov965x_s_frame_interval(struct v4l2_subdev *sd,
1162 struct v4l2_subdev_frame_interval *fi)
1164 struct ov965x *ov965x = to_ov965x(sd);
1167 v4l2_dbg(1, debug, sd, "Setting %d/%d frame interval\n",
1168 fi->interval.numerator, fi->interval.denominator);
1170 mutex_lock(&ov965x->lock);
1171 ret = __ov965x_set_frame_interval(ov965x, fi);
1172 ov965x->apply_frame_fmt = 1;
1173 mutex_unlock(&ov965x->lock);
1177 static int ov965x_get_fmt(struct v4l2_subdev *sd,
1178 struct v4l2_subdev_pad_config *cfg,
1179 struct v4l2_subdev_format *fmt)
1181 struct ov965x *ov965x = to_ov965x(sd);
1182 struct v4l2_mbus_framefmt *mf;
1184 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1185 mf = v4l2_subdev_get_try_format(sd, cfg, 0);
1190 mutex_lock(&ov965x->lock);
1191 fmt->format = ov965x->format;
1192 mutex_unlock(&ov965x->lock);
1197 static void __ov965x_try_frame_size(struct v4l2_mbus_framefmt *mf,
1198 const struct ov965x_framesize **size)
1200 const struct ov965x_framesize *fsize = &ov965x_framesizes[0],
1202 int i = ARRAY_SIZE(ov965x_framesizes);
1203 unsigned int min_err = UINT_MAX;
1206 int err = abs(fsize->width - mf->width)
1207 + abs(fsize->height - mf->height);
1208 if (err < min_err) {
1215 match = &ov965x_framesizes[0];
1216 mf->width = match->width;
1217 mf->height = match->height;
1222 static int ov965x_set_fmt(struct v4l2_subdev *sd,
1223 struct v4l2_subdev_pad_config *cfg,
1224 struct v4l2_subdev_format *fmt)
1226 unsigned int index = ARRAY_SIZE(ov965x_formats);
1227 struct v4l2_mbus_framefmt *mf = &fmt->format;
1228 struct ov965x *ov965x = to_ov965x(sd);
1229 const struct ov965x_framesize *size = NULL;
1232 __ov965x_try_frame_size(mf, &size);
1235 if (ov965x_formats[index].code == mf->code)
1238 mf->colorspace = V4L2_COLORSPACE_JPEG;
1239 mf->code = ov965x_formats[index].code;
1240 mf->field = V4L2_FIELD_NONE;
1242 mutex_lock(&ov965x->lock);
1244 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1246 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1250 if (ov965x->streaming) {
1253 ov965x->frame_size = size;
1254 ov965x->format = fmt->format;
1255 ov965x->tslb_reg = ov965x_formats[index].tslb_reg;
1256 ov965x->apply_frame_fmt = 1;
1260 if (!ret && fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
1261 struct v4l2_subdev_frame_interval fiv = {
1262 .interval = { 0, 1 }
1264 /* Reset to minimum possible frame interval */
1265 __ov965x_set_frame_interval(ov965x, &fiv);
1267 mutex_unlock(&ov965x->lock);
1270 ov965x_update_exposure_ctrl(ov965x);
1275 static int ov965x_set_frame_size(struct ov965x *ov965x)
1279 for (i = 0; ret == 0 && i < NUM_FMT_REGS; i++)
1280 ret = ov965x_write(ov965x->client, frame_size_reg_addr[i],
1281 ov965x->frame_size->regs[i]);
1285 static int __ov965x_set_params(struct ov965x *ov965x)
1287 struct i2c_client *client = ov965x->client;
1288 struct ov965x_ctrls *ctrls = &ov965x->ctrls;
1292 if (ov965x->apply_frame_fmt) {
1293 reg = DEF_CLKRC + ov965x->fiv->clkrc_div;
1294 ret = ov965x_write(client, REG_CLKRC, reg);
1297 ret = ov965x_set_frame_size(ov965x);
1300 ret = ov965x_read(client, REG_TSLB, ®);
1303 reg &= ~TSLB_YUYV_MASK;
1304 reg |= ov965x->tslb_reg;
1305 ret = ov965x_write(client, REG_TSLB, reg);
1309 ret = ov965x_set_default_gamma_curve(ov965x);
1312 ret = ov965x_set_color_matrix(ov965x);
1316 * Select manual banding filter, the filter will
1317 * be enabled further if required.
1319 ret = ov965x_read(client, REG_COM11, ®);
1321 reg |= COM11_BANDING;
1322 ret = ov965x_write(client, REG_COM11, reg);
1326 * Banding filter (REG_MBD value) needs to match selected
1327 * resolution and frame rate, so it's always updated here.
1329 return ov965x_set_banding_filter(ov965x, ctrls->light_freq->val);
1332 static int ov965x_s_stream(struct v4l2_subdev *sd, int on)
1334 struct i2c_client *client = v4l2_get_subdevdata(sd);
1335 struct ov965x *ov965x = to_ov965x(sd);
1336 struct ov965x_ctrls *ctrls = &ov965x->ctrls;
1339 v4l2_dbg(1, debug, client, "%s: on: %d\n", __func__, on);
1341 mutex_lock(&ov965x->lock);
1342 if (ov965x->streaming == !on) {
1344 ret = __ov965x_set_params(ov965x);
1346 if (!ret && ctrls->update) {
1348 * ov965x_s_ctrl callback takes the mutex
1349 * so it needs to be released here.
1351 mutex_unlock(&ov965x->lock);
1352 ret = v4l2_ctrl_handler_setup(&ctrls->handler);
1354 mutex_lock(&ov965x->lock);
1359 ret = ov965x_write(client, REG_COM2,
1363 ov965x->streaming += on ? 1 : -1;
1365 WARN_ON(ov965x->streaming < 0);
1366 mutex_unlock(&ov965x->lock);
1372 * V4L2 subdev internal operations
1374 static int ov965x_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1376 struct v4l2_mbus_framefmt *mf =
1377 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1379 ov965x_get_default_format(mf);
1383 static const struct v4l2_subdev_pad_ops ov965x_pad_ops = {
1384 .enum_mbus_code = ov965x_enum_mbus_code,
1385 .enum_frame_size = ov965x_enum_frame_sizes,
1386 .get_fmt = ov965x_get_fmt,
1387 .set_fmt = ov965x_set_fmt,
1390 static const struct v4l2_subdev_video_ops ov965x_video_ops = {
1391 .s_stream = ov965x_s_stream,
1392 .g_frame_interval = ov965x_g_frame_interval,
1393 .s_frame_interval = ov965x_s_frame_interval,
1397 static const struct v4l2_subdev_internal_ops ov965x_sd_internal_ops = {
1398 .open = ov965x_open,
1401 static const struct v4l2_subdev_core_ops ov965x_core_ops = {
1402 .s_power = ov965x_s_power,
1403 .log_status = v4l2_ctrl_subdev_log_status,
1404 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1405 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1408 static const struct v4l2_subdev_ops ov965x_subdev_ops = {
1409 .core = &ov965x_core_ops,
1410 .pad = &ov965x_pad_ops,
1411 .video = &ov965x_video_ops,
1415 * Reset and power down GPIOs configuration
1417 static int ov965x_configure_gpios(struct ov965x *ov965x,
1418 const struct ov9650_platform_data *pdata)
1422 ov965x->gpios[GPIO_PWDN] = pdata->gpio_pwdn;
1423 ov965x->gpios[GPIO_RST] = pdata->gpio_reset;
1425 for (i = 0; i < ARRAY_SIZE(ov965x->gpios); i++) {
1426 int gpio = ov965x->gpios[i];
1428 if (!gpio_is_valid(gpio))
1430 ret = devm_gpio_request_one(&ov965x->client->dev, gpio,
1431 GPIOF_OUT_INIT_HIGH, "OV965X");
1434 v4l2_dbg(1, debug, &ov965x->sd, "set gpio %d to 1\n", gpio);
1436 gpio_set_value(gpio, 1);
1437 gpio_export(gpio, 0);
1438 ov965x->gpios[i] = gpio;
1444 static int ov965x_detect_sensor(struct v4l2_subdev *sd)
1446 struct i2c_client *client = v4l2_get_subdevdata(sd);
1447 struct ov965x *ov965x = to_ov965x(sd);
1451 mutex_lock(&ov965x->lock);
1452 __ov965x_set_power(ov965x, 1);
1455 /* Check sensor revision */
1456 ret = ov965x_read(client, REG_PID, &pid);
1458 ret = ov965x_read(client, REG_VER, &ver);
1460 __ov965x_set_power(ov965x, 0);
1463 ov965x->id = OV965X_ID(pid, ver);
1464 if (ov965x->id == OV9650_ID || ov965x->id == OV9652_ID) {
1465 v4l2_info(sd, "Found OV%04X sensor\n", ov965x->id);
1467 v4l2_err(sd, "Sensor detection failed (%04X, %d)\n",
1472 mutex_unlock(&ov965x->lock);
1477 static int ov965x_probe(struct i2c_client *client,
1478 const struct i2c_device_id *id)
1480 const struct ov9650_platform_data *pdata = client->dev.platform_data;
1481 struct v4l2_subdev *sd;
1482 struct ov965x *ov965x;
1486 dev_err(&client->dev, "platform data not specified\n");
1490 if (pdata->mclk_frequency == 0) {
1491 dev_err(&client->dev, "MCLK frequency not specified\n");
1495 ov965x = devm_kzalloc(&client->dev, sizeof(*ov965x), GFP_KERNEL);
1499 mutex_init(&ov965x->lock);
1500 ov965x->client = client;
1501 ov965x->mclk_frequency = pdata->mclk_frequency;
1504 v4l2_i2c_subdev_init(sd, client, &ov965x_subdev_ops);
1505 strlcpy(sd->name, DRIVER_NAME, sizeof(sd->name));
1507 sd->internal_ops = &ov965x_sd_internal_ops;
1508 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1509 V4L2_SUBDEV_FL_HAS_EVENTS;
1511 ret = ov965x_configure_gpios(ov965x, pdata);
1515 ov965x->pad.flags = MEDIA_PAD_FL_SOURCE;
1516 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1517 ret = media_entity_pads_init(&sd->entity, 1, &ov965x->pad);
1521 ret = ov965x_initialize_controls(ov965x);
1525 ov965x_get_default_format(&ov965x->format);
1526 ov965x->frame_size = &ov965x_framesizes[0];
1527 ov965x->fiv = &ov965x_intervals[0];
1529 ret = ov965x_detect_sensor(sd);
1533 /* Update exposure time min/max to match frame format */
1534 ov965x_update_exposure_ctrl(ov965x);
1536 ret = v4l2_async_register_subdev(sd);
1542 v4l2_ctrl_handler_free(sd->ctrl_handler);
1544 media_entity_cleanup(&sd->entity);
1546 mutex_destroy(&ov965x->lock);
1550 static int ov965x_remove(struct i2c_client *client)
1552 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1553 struct ov965x *ov965x = to_ov965x(sd);
1555 v4l2_async_unregister_subdev(sd);
1556 v4l2_ctrl_handler_free(sd->ctrl_handler);
1557 media_entity_cleanup(&sd->entity);
1558 mutex_destroy(&ov965x->lock);
1563 static const struct i2c_device_id ov965x_id[] = {
1568 MODULE_DEVICE_TABLE(i2c, ov965x_id);
1570 static struct i2c_driver ov965x_i2c_driver = {
1572 .name = DRIVER_NAME,
1574 .probe = ov965x_probe,
1575 .remove = ov965x_remove,
1576 .id_table = ov965x_id,
1579 module_i2c_driver(ov965x_i2c_driver);
1581 MODULE_AUTHOR("Sylwester Nawrocki <sylvester.nawrocki@gmail.com>");
1582 MODULE_DESCRIPTION("OV9650/OV9652 CMOS Image Sensor driver");
1583 MODULE_LICENSE("GPL");