2 * A V4L2 driver for OmniVision OV7670 cameras.
4 * Copyright 2006 One Laptop Per Child Association, Inc. Written
5 * by Jonathan Corbet with substantial inspiration from Mark
6 * McClelland's ovcamchip code.
8 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10 * This file may be distributed under the terms of the GNU General
11 * Public License, version 2.
13 #include <linux/clk.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/i2c.h>
18 #include <linux/delay.h>
19 #include <linux/videodev2.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-mediabus.h>
25 #include <media/v4l2-image-sizes.h>
26 #include <media/i2c/ov7670.h>
28 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
29 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
30 MODULE_LICENSE("GPL");
33 module_param(debug, bool, 0644);
34 MODULE_PARM_DESC(debug, "Debug level (0-1)");
37 * The 7670 sits on i2c with ID 0x42
39 #define OV7670_I2C_ADDR 0x42
44 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
45 #define REG_BLUE 0x01 /* blue gain */
46 #define REG_RED 0x02 /* red gain */
47 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
48 #define REG_COM1 0x04 /* Control 1 */
49 #define COM1_CCIR656 0x40 /* CCIR656 enable */
50 #define REG_BAVE 0x05 /* U/B Average level */
51 #define REG_GbAVE 0x06 /* Y/Gb Average level */
52 #define REG_AECHH 0x07 /* AEC MS 5 bits */
53 #define REG_RAVE 0x08 /* V/R Average level */
54 #define REG_COM2 0x09 /* Control 2 */
55 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
56 #define REG_PID 0x0a /* Product ID MSB */
57 #define REG_VER 0x0b /* Product ID LSB */
58 #define REG_COM3 0x0c /* Control 3 */
59 #define COM3_SWAP 0x40 /* Byte swap */
60 #define COM3_SCALEEN 0x08 /* Enable scaling */
61 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
62 #define REG_COM4 0x0d /* Control 4 */
63 #define REG_COM5 0x0e /* All "reserved" */
64 #define REG_COM6 0x0f /* Control 6 */
65 #define REG_AECH 0x10 /* More bits of AEC value */
66 #define REG_CLKRC 0x11 /* Clocl control */
67 #define CLK_EXT 0x40 /* Use external clock directly */
68 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
69 #define REG_COM7 0x12 /* Control 7 */
70 #define COM7_RESET 0x80 /* Register reset */
71 #define COM7_FMT_MASK 0x38
72 #define COM7_FMT_VGA 0x00
73 #define COM7_FMT_CIF 0x20 /* CIF format */
74 #define COM7_FMT_QVGA 0x10 /* QVGA format */
75 #define COM7_FMT_QCIF 0x08 /* QCIF format */
76 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
77 #define COM7_YUV 0x00 /* YUV */
78 #define COM7_BAYER 0x01 /* Bayer format */
79 #define COM7_PBAYER 0x05 /* "Processed bayer" */
80 #define REG_COM8 0x13 /* Control 8 */
81 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
82 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
83 #define COM8_BFILT 0x20 /* Band filter enable */
84 #define COM8_AGC 0x04 /* Auto gain enable */
85 #define COM8_AWB 0x02 /* White balance enable */
86 #define COM8_AEC 0x01 /* Auto exposure enable */
87 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
88 #define REG_COM10 0x15 /* Control 10 */
89 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
90 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
91 #define COM10_HREF_REV 0x08 /* Reverse HREF */
92 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
93 #define COM10_VS_NEG 0x02 /* VSYNC negative */
94 #define COM10_HS_NEG 0x01 /* HSYNC negative */
95 #define REG_HSTART 0x17 /* Horiz start high bits */
96 #define REG_HSTOP 0x18 /* Horiz stop high bits */
97 #define REG_VSTART 0x19 /* Vert start high bits */
98 #define REG_VSTOP 0x1a /* Vert stop high bits */
99 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
100 #define REG_MIDH 0x1c /* Manuf. ID high */
101 #define REG_MIDL 0x1d /* Manuf. ID low */
102 #define REG_MVFP 0x1e /* Mirror / vflip */
103 #define MVFP_MIRROR 0x20 /* Mirror image */
104 #define MVFP_FLIP 0x10 /* Vertical flip */
106 #define REG_AEW 0x24 /* AGC upper limit */
107 #define REG_AEB 0x25 /* AGC lower limit */
108 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
109 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
110 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
111 #define REG_HREF 0x32 /* HREF pieces */
112 #define REG_TSLB 0x3a /* lots of stuff */
113 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
114 #define REG_COM11 0x3b /* Control 11 */
115 #define COM11_NIGHT 0x80 /* NIght mode enable */
116 #define COM11_NMFR 0x60 /* Two bit NM frame rate */
117 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
118 #define COM11_50HZ 0x08 /* Manual 50Hz select */
119 #define COM11_EXP 0x02
120 #define REG_COM12 0x3c /* Control 12 */
121 #define COM12_HREF 0x80 /* HREF always */
122 #define REG_COM13 0x3d /* Control 13 */
123 #define COM13_GAMMA 0x80 /* Gamma enable */
124 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
125 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
126 #define REG_COM14 0x3e /* Control 14 */
127 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
128 #define REG_EDGE 0x3f /* Edge enhancement factor */
129 #define REG_COM15 0x40 /* Control 15 */
130 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
131 #define COM15_R01FE 0x80 /* 01 to FE */
132 #define COM15_R00FF 0xc0 /* 00 to FF */
133 #define COM15_RGB565 0x10 /* RGB565 output */
134 #define COM15_RGB555 0x30 /* RGB555 output */
135 #define REG_COM16 0x41 /* Control 16 */
136 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
137 #define REG_COM17 0x42 /* Control 17 */
138 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
139 #define COM17_CBAR 0x08 /* DSP Color bar */
142 * This matrix defines how the colors are generated, must be
143 * tweaked to adjust hue and saturation.
145 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
147 * They are nine-bit signed quantities, with the sign bit
148 * stored in 0x58. Sign for v-red is bit 0, and up from there.
150 #define REG_CMATRIX_BASE 0x4f
151 #define CMATRIX_LEN 6
152 #define REG_CMATRIX_SIGN 0x58
155 #define REG_BRIGHT 0x55 /* Brightness */
156 #define REG_CONTRAS 0x56 /* Contrast control */
158 #define REG_GFIX 0x69 /* Fix gain control */
160 #define REG_DBLV 0x6b /* PLL control an debugging */
161 #define DBLV_BYPASS 0x0a /* Bypass PLL */
162 #define DBLV_X4 0x4a /* clock x4 */
163 #define DBLV_X6 0x8a /* clock x6 */
164 #define DBLV_X8 0xca /* clock x8 */
166 #define REG_REG76 0x76 /* OV's name */
167 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
168 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
170 #define REG_RGB444 0x8c /* RGB 444 control */
171 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
172 #define R444_RGBX 0x01 /* Empty nibble at end */
174 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
175 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
177 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
178 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
179 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
180 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
181 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
182 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
183 #define REG_BD60MAX 0xab /* 60hz banding step limit */
190 struct ov7670_win_size {
193 unsigned char com7_bit;
194 int hstart; /* Start/stop values for the camera. Note */
195 int hstop; /* that they do not always make complete */
196 int vstart; /* sense to humans, but evidently the sensor */
197 int vstop; /* will do the right thing... */
198 struct regval_list *regs; /* Regs to tweak */
201 struct ov7670_devtype {
202 /* formats supported for each model */
203 struct ov7670_win_size *win_sizes;
204 unsigned int n_win_sizes;
205 /* callbacks for frame rate control */
206 int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
207 void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
211 * Information we maintain about a known sensor.
213 struct ov7670_format_struct; /* coming later */
215 struct v4l2_subdev sd;
216 struct v4l2_ctrl_handler hdl;
219 struct v4l2_ctrl *auto_gain;
220 struct v4l2_ctrl *gain;
223 /* exposure cluster */
224 struct v4l2_ctrl *auto_exposure;
225 struct v4l2_ctrl *exposure;
228 /* saturation/hue cluster */
229 struct v4l2_ctrl *saturation;
230 struct v4l2_ctrl *hue;
232 struct ov7670_format_struct *fmt; /* Current format */
234 struct gpio_desc *resetb_gpio;
235 struct gpio_desc *pwdn_gpio;
236 int min_width; /* Filter out smaller sizes */
237 int min_height; /* Filter out smaller sizes */
238 int clock_speed; /* External clock speed (MHz) */
239 u8 clkrc; /* Clock divider value */
240 bool use_smbus; /* Use smbus I/O instead of I2C */
242 bool pclk_hb_disable;
243 const struct ov7670_devtype *devtype; /* Device specifics */
246 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
248 return container_of(sd, struct ov7670_info, sd);
251 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
253 return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd;
259 * The default register settings, as obtained from OmniVision. There
260 * is really no making sense of most of these - lots of "reserved" values
263 * These settings give VGA YUYV.
267 unsigned char reg_num;
271 static struct regval_list ov7670_default_regs[] = {
272 { REG_COM7, COM7_RESET },
274 * Clock scale: 3 = 15fps
278 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */
279 { REG_TSLB, 0x04 }, /* OV */
280 { REG_COM7, 0 }, /* VGA */
282 * Set the hardware window. These values from OV don't entirely
283 * make sense - hstop is less than hstart. But they work...
285 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
286 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
287 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
289 { REG_COM3, 0 }, { REG_COM14, 0 },
290 /* Mystery scaling numbers */
291 { 0x70, 0x3a }, { 0x71, 0x35 },
292 { 0x72, 0x11 }, { 0x73, 0xf0 },
293 { 0xa2, 0x02 }, { REG_COM10, 0x0 },
295 /* Gamma curve values */
296 { 0x7a, 0x20 }, { 0x7b, 0x10 },
297 { 0x7c, 0x1e }, { 0x7d, 0x35 },
298 { 0x7e, 0x5a }, { 0x7f, 0x69 },
299 { 0x80, 0x76 }, { 0x81, 0x80 },
300 { 0x82, 0x88 }, { 0x83, 0x8f },
301 { 0x84, 0x96 }, { 0x85, 0xa3 },
302 { 0x86, 0xaf }, { 0x87, 0xc4 },
303 { 0x88, 0xd7 }, { 0x89, 0xe8 },
305 /* AGC and AEC parameters. Note we start by disabling those features,
306 then turn them only after tweaking the values. */
307 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
308 { REG_GAIN, 0 }, { REG_AECH, 0 },
309 { REG_COM4, 0x40 }, /* magic reserved bit */
310 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
311 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
312 { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
313 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
314 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
315 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
316 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
317 { REG_HAECC7, 0x94 },
318 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
320 /* Almost all of these are magic "reserved" values. */
321 { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
322 { 0x16, 0x02 }, { REG_MVFP, 0x07 },
323 { 0x21, 0x02 }, { 0x22, 0x91 },
324 { 0x29, 0x07 }, { 0x33, 0x0b },
325 { 0x35, 0x0b }, { 0x37, 0x1d },
326 { 0x38, 0x71 }, { 0x39, 0x2a },
327 { REG_COM12, 0x78 }, { 0x4d, 0x40 },
328 { 0x4e, 0x20 }, { REG_GFIX, 0 },
329 { 0x6b, 0x4a }, { 0x74, 0x10 },
330 { 0x8d, 0x4f }, { 0x8e, 0 },
331 { 0x8f, 0 }, { 0x90, 0 },
332 { 0x91, 0 }, { 0x96, 0 },
333 { 0x9a, 0 }, { 0xb0, 0x84 },
334 { 0xb1, 0x0c }, { 0xb2, 0x0e },
335 { 0xb3, 0x82 }, { 0xb8, 0x0a },
337 /* More reserved magic, some of which tweaks white balance */
338 { 0x43, 0x0a }, { 0x44, 0xf0 },
339 { 0x45, 0x34 }, { 0x46, 0x58 },
340 { 0x47, 0x28 }, { 0x48, 0x3a },
341 { 0x59, 0x88 }, { 0x5a, 0x88 },
342 { 0x5b, 0x44 }, { 0x5c, 0x67 },
343 { 0x5d, 0x49 }, { 0x5e, 0x0e },
344 { 0x6c, 0x0a }, { 0x6d, 0x55 },
345 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */
346 { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
348 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
350 /* Matrix coefficients */
351 { 0x4f, 0x80 }, { 0x50, 0x80 },
352 { 0x51, 0 }, { 0x52, 0x22 },
353 { 0x53, 0x5e }, { 0x54, 0x80 },
356 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
357 { 0x75, 0x05 }, { 0x76, 0xe1 },
358 { 0x4c, 0 }, { 0x77, 0x01 },
359 { REG_COM13, 0xc3 }, { 0x4b, 0x09 },
360 { 0xc9, 0x60 }, { REG_COM16, 0x38 },
363 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO },
364 { 0xa4, 0x88 }, { 0x96, 0 },
365 { 0x97, 0x30 }, { 0x98, 0x20 },
366 { 0x99, 0x30 }, { 0x9a, 0x84 },
367 { 0x9b, 0x29 }, { 0x9c, 0x03 },
368 { 0x9d, 0x4c }, { 0x9e, 0x3f },
371 /* Extra-weird stuff. Some sort of multiplexor register */
372 { 0x79, 0x01 }, { 0xc8, 0xf0 },
373 { 0x79, 0x0f }, { 0xc8, 0x00 },
374 { 0x79, 0x10 }, { 0xc8, 0x7e },
375 { 0x79, 0x0a }, { 0xc8, 0x80 },
376 { 0x79, 0x0b }, { 0xc8, 0x01 },
377 { 0x79, 0x0c }, { 0xc8, 0x0f },
378 { 0x79, 0x0d }, { 0xc8, 0x20 },
379 { 0x79, 0x09 }, { 0xc8, 0x80 },
380 { 0x79, 0x02 }, { 0xc8, 0xc0 },
381 { 0x79, 0x03 }, { 0xc8, 0x40 },
382 { 0x79, 0x05 }, { 0xc8, 0x30 },
385 { 0xff, 0xff }, /* END MARKER */
390 * Here we'll try to encapsulate the changes for just the output
393 * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
395 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
399 static struct regval_list ov7670_fmt_yuv422[] = {
400 { REG_COM7, 0x0 }, /* Selects YUV mode */
401 { REG_RGB444, 0 }, /* No RGB444 please */
402 { REG_COM1, 0 }, /* CCIR601 */
403 { REG_COM15, COM15_R00FF },
404 { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */
405 { 0x4f, 0x80 }, /* "matrix coefficient 1" */
406 { 0x50, 0x80 }, /* "matrix coefficient 2" */
407 { 0x51, 0 }, /* vb */
408 { 0x52, 0x22 }, /* "matrix coefficient 4" */
409 { 0x53, 0x5e }, /* "matrix coefficient 5" */
410 { 0x54, 0x80 }, /* "matrix coefficient 6" */
411 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
415 static struct regval_list ov7670_fmt_rgb565[] = {
416 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
417 { REG_RGB444, 0 }, /* No RGB444 please */
418 { REG_COM1, 0x0 }, /* CCIR601 */
419 { REG_COM15, COM15_RGB565 },
420 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
421 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
422 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
423 { 0x51, 0 }, /* vb */
424 { 0x52, 0x3d }, /* "matrix coefficient 4" */
425 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
426 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
427 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
431 static struct regval_list ov7670_fmt_rgb444[] = {
432 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
433 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */
434 { REG_COM1, 0x0 }, /* CCIR601 */
435 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
436 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
437 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
438 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
439 { 0x51, 0 }, /* vb */
440 { 0x52, 0x3d }, /* "matrix coefficient 4" */
441 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
442 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
443 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */
447 static struct regval_list ov7670_fmt_raw[] = {
448 { REG_COM7, COM7_BAYER },
449 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
450 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */
451 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
458 * Low-level register I/O.
460 * Note that there are two versions of these. On the XO 1, the
461 * i2c controller only does SMBUS, so that's what we use. The
462 * ov7670 is not really an SMBUS device, though, so the communication
463 * is not always entirely reliable.
465 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg,
466 unsigned char *value)
468 struct i2c_client *client = v4l2_get_subdevdata(sd);
471 ret = i2c_smbus_read_byte_data(client, reg);
473 *value = (unsigned char)ret;
480 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg,
483 struct i2c_client *client = v4l2_get_subdevdata(sd);
484 int ret = i2c_smbus_write_byte_data(client, reg, value);
486 if (reg == REG_COM7 && (value & COM7_RESET))
487 msleep(5); /* Wait for reset to run */
492 * On most platforms, we'd rather do straight i2c I/O.
494 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg,
495 unsigned char *value)
497 struct i2c_client *client = v4l2_get_subdevdata(sd);
503 * Send out the register address...
505 msg.addr = client->addr;
509 ret = i2c_transfer(client->adapter, &msg, 1);
511 printk(KERN_ERR "Error %d on register write\n", ret);
515 * ...then read back the result.
517 msg.flags = I2C_M_RD;
518 ret = i2c_transfer(client->adapter, &msg, 1);
527 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg,
530 struct i2c_client *client = v4l2_get_subdevdata(sd);
532 unsigned char data[2] = { reg, value };
535 msg.addr = client->addr;
539 ret = i2c_transfer(client->adapter, &msg, 1);
542 if (reg == REG_COM7 && (value & COM7_RESET))
543 msleep(5); /* Wait for reset to run */
547 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
548 unsigned char *value)
550 struct ov7670_info *info = to_state(sd);
552 return ov7670_read_smbus(sd, reg, value);
554 return ov7670_read_i2c(sd, reg, value);
557 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
560 struct ov7670_info *info = to_state(sd);
562 return ov7670_write_smbus(sd, reg, value);
564 return ov7670_write_i2c(sd, reg, value);
568 * Write a list of register settings; ff/ff stops the process.
570 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
572 while (vals->reg_num != 0xff || vals->value != 0xff) {
573 int ret = ov7670_write(sd, vals->reg_num, vals->value);
583 * Stuff that knows about the sensor.
585 static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
587 ov7670_write(sd, REG_COM7, COM7_RESET);
593 static int ov7670_init(struct v4l2_subdev *sd, u32 val)
595 return ov7670_write_array(sd, ov7670_default_regs);
598 static int ov7670_detect(struct v4l2_subdev *sd)
603 ret = ov7670_init(sd, 0);
606 ret = ov7670_read(sd, REG_MIDH, &v);
609 if (v != 0x7f) /* OV manuf. id. */
611 ret = ov7670_read(sd, REG_MIDL, &v);
617 * OK, we know we have an OmniVision chip...but which one?
619 ret = ov7670_read(sd, REG_PID, &v);
622 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */
624 ret = ov7670_read(sd, REG_VER, &v);
627 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */
634 * Store information about the video data format. The color matrix
635 * is deeply tied into the format, so keep the relevant values here.
636 * The magic matrix numbers come from OmniVision.
638 static struct ov7670_format_struct {
640 enum v4l2_colorspace colorspace;
641 struct regval_list *regs;
642 int cmatrix[CMATRIX_LEN];
643 } ov7670_formats[] = {
645 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
646 .colorspace = V4L2_COLORSPACE_SRGB,
647 .regs = ov7670_fmt_yuv422,
648 .cmatrix = { 128, -128, 0, -34, -94, 128 },
651 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
652 .colorspace = V4L2_COLORSPACE_SRGB,
653 .regs = ov7670_fmt_rgb444,
654 .cmatrix = { 179, -179, 0, -61, -176, 228 },
657 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
658 .colorspace = V4L2_COLORSPACE_SRGB,
659 .regs = ov7670_fmt_rgb565,
660 .cmatrix = { 179, -179, 0, -61, -176, 228 },
663 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
664 .colorspace = V4L2_COLORSPACE_SRGB,
665 .regs = ov7670_fmt_raw,
666 .cmatrix = { 0, 0, 0, 0, 0, 0 },
669 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
673 * Then there is the issue of window sizes. Try to capture the info here.
677 * QCIF mode is done (by OV) in a very strange way - it actually looks like
678 * VGA with weird scaling options - they do *not* use the canned QCIF mode
679 * which is allegedly provided by the sensor. So here's the weird register
682 static struct regval_list ov7670_qcif_regs[] = {
683 { REG_COM3, COM3_SCALEEN|COM3_DCWEN },
684 { REG_COM3, COM3_DCWEN },
685 { REG_COM14, COM14_DCWEN | 0x01},
701 static struct ov7670_win_size ov7670_win_sizes[] = {
705 .height = VGA_HEIGHT,
706 .com7_bit = COM7_FMT_VGA,
707 .hstart = 158, /* These values from */
708 .hstop = 14, /* Omnivision */
716 .height = CIF_HEIGHT,
717 .com7_bit = COM7_FMT_CIF,
718 .hstart = 170, /* Empirically determined */
727 .height = QVGA_HEIGHT,
728 .com7_bit = COM7_FMT_QVGA,
729 .hstart = 168, /* Empirically determined */
738 .height = QCIF_HEIGHT,
739 .com7_bit = COM7_FMT_VGA, /* see comment above */
740 .hstart = 456, /* Empirically determined */
744 .regs = ov7670_qcif_regs,
748 static struct ov7670_win_size ov7675_win_sizes[] = {
750 * Currently, only VGA is supported. Theoretically it could be possible
751 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a
752 * base and tweak them empirically could be required.
756 .height = VGA_HEIGHT,
757 .com7_bit = COM7_FMT_VGA,
758 .hstart = 158, /* These values from */
759 .hstop = 14, /* Omnivision */
760 .vstart = 14, /* Empirically determined */
766 static void ov7675_get_framerate(struct v4l2_subdev *sd,
767 struct v4l2_fract *tpf)
769 struct ov7670_info *info = to_state(sd);
770 u32 clkrc = info->clkrc;
773 if (info->pll_bypass)
776 pll_factor = PLL_FACTOR;
779 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
780 clkrc = (clkrc >> 1);
783 tpf->denominator = (5 * pll_factor * info->clock_speed) /
787 static int ov7675_set_framerate(struct v4l2_subdev *sd,
788 struct v4l2_fract *tpf)
790 struct ov7670_info *info = to_state(sd);
796 * The formula is fps = 5/4*pixclk for YUV/RGB and
797 * fps = 5/2*pixclk for RAW.
799 * pixclk = clock_speed / (clkrc + 1) * PLLfactor
802 if (info->pll_bypass) {
804 ret = ov7670_write(sd, REG_DBLV, DBLV_BYPASS);
806 pll_factor = PLL_FACTOR;
807 ret = ov7670_write(sd, REG_DBLV, DBLV_X4);
812 if (tpf->numerator == 0 || tpf->denominator == 0) {
815 clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) /
816 (4 * tpf->denominator);
817 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
818 clkrc = (clkrc << 1);
823 * The datasheet claims that clkrc = 0 will divide the input clock by 1
824 * but we've checked with an oscilloscope that it divides by 2 instead.
825 * So, if clkrc = 0 just bypass the divider.
829 else if (clkrc > CLK_SCALE)
833 /* Recalculate frame rate */
834 ov7675_get_framerate(sd, tpf);
836 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
843 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd,
844 struct v4l2_fract *tpf)
846 struct ov7670_info *info = to_state(sd);
849 tpf->denominator = info->clock_speed;
850 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1)
851 tpf->denominator /= (info->clkrc & CLK_SCALE);
854 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd,
855 struct v4l2_fract *tpf)
857 struct ov7670_info *info = to_state(sd);
860 if (tpf->numerator == 0 || tpf->denominator == 0)
861 div = 1; /* Reset to full rate */
863 div = (tpf->numerator * info->clock_speed) / tpf->denominator;
866 else if (div > CLK_SCALE)
868 info->clkrc = (info->clkrc & 0x80) | div;
870 tpf->denominator = info->clock_speed / div;
871 return ov7670_write(sd, REG_CLKRC, info->clkrc);
875 * Store a set of start/stop values into the camera.
877 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
878 int vstart, int vstop)
883 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
884 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
885 * a mystery "edge offset" value in the top two bits of href.
887 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
888 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
889 ret += ov7670_read(sd, REG_HREF, &v);
890 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
892 ret += ov7670_write(sd, REG_HREF, v);
894 * Vertical: similar arrangement, but only 10 bits.
896 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
897 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
898 ret += ov7670_read(sd, REG_VREF, &v);
899 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
901 ret += ov7670_write(sd, REG_VREF, v);
906 static int ov7670_enum_mbus_code(struct v4l2_subdev *sd,
907 struct v4l2_subdev_pad_config *cfg,
908 struct v4l2_subdev_mbus_code_enum *code)
910 if (code->pad || code->index >= N_OV7670_FMTS)
913 code->code = ov7670_formats[code->index].mbus_code;
917 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
918 struct v4l2_mbus_framefmt *fmt,
919 struct ov7670_format_struct **ret_fmt,
920 struct ov7670_win_size **ret_wsize)
923 struct ov7670_win_size *wsize;
924 struct ov7670_info *info = to_state(sd);
925 unsigned int n_win_sizes = info->devtype->n_win_sizes;
926 unsigned int win_sizes_limit = n_win_sizes;
928 for (index = 0; index < N_OV7670_FMTS; index++)
929 if (ov7670_formats[index].mbus_code == fmt->code)
931 if (index >= N_OV7670_FMTS) {
932 /* default to first format */
934 fmt->code = ov7670_formats[0].mbus_code;
937 *ret_fmt = ov7670_formats + index;
939 * Fields: the OV devices claim to be progressive.
941 fmt->field = V4L2_FIELD_NONE;
944 * Don't consider values that don't match min_height and min_width
947 if (info->min_width || info->min_height)
948 for (i = 0; i < n_win_sizes; i++) {
949 wsize = info->devtype->win_sizes + i;
951 if (wsize->width < info->min_width ||
952 wsize->height < info->min_height) {
958 * Round requested image size down to the nearest
959 * we support, but not below the smallest.
961 for (wsize = info->devtype->win_sizes;
962 wsize < info->devtype->win_sizes + win_sizes_limit; wsize++)
963 if (fmt->width >= wsize->width && fmt->height >= wsize->height)
965 if (wsize >= info->devtype->win_sizes + win_sizes_limit)
966 wsize--; /* Take the smallest one */
967 if (ret_wsize != NULL)
970 * Note the size we'll actually handle.
972 fmt->width = wsize->width;
973 fmt->height = wsize->height;
974 fmt->colorspace = ov7670_formats[index].colorspace;
981 static int ov7670_set_fmt(struct v4l2_subdev *sd,
982 struct v4l2_subdev_pad_config *cfg,
983 struct v4l2_subdev_format *format)
985 struct ov7670_format_struct *ovfmt;
986 struct ov7670_win_size *wsize;
987 struct ov7670_info *info = to_state(sd);
994 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
995 ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL);
998 cfg->try_fmt = format->format;
1002 ret = ov7670_try_fmt_internal(sd, &format->format, &ovfmt, &wsize);
1007 * COM7 is a pain in the ass, it doesn't like to be read then
1008 * quickly written afterward. But we have everything we need
1009 * to set it absolutely here, as long as the format-specific
1010 * register sets list it first.
1012 com7 = ovfmt->regs[0].value;
1013 com7 |= wsize->com7_bit;
1014 ov7670_write(sd, REG_COM7, com7);
1016 * Now write the rest of the array. Also store start/stops
1018 ov7670_write_array(sd, ovfmt->regs + 1);
1019 ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
1023 ret = ov7670_write_array(sd, wsize->regs);
1027 * If we're running RGB565, we must rewrite clkrc after setting
1028 * the other parameters or the image looks poor. If we're *not*
1029 * doing RGB565, we must not rewrite clkrc or the image looks
1032 * (Update) Now that we retain clkrc state, we should be able
1033 * to write it unconditionally, and that will make the frame
1034 * rate persistent too.
1037 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
1042 * Implement G/S_PARM. There is a "high quality" mode we could try
1043 * to do someday; for now, we just do the frame rate tweak.
1045 static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
1047 struct v4l2_captureparm *cp = &parms->parm.capture;
1048 struct ov7670_info *info = to_state(sd);
1050 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1053 cp->capability = V4L2_CAP_TIMEPERFRAME;
1054 info->devtype->get_framerate(sd, &cp->timeperframe);
1059 static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
1061 struct v4l2_captureparm *cp = &parms->parm.capture;
1062 struct v4l2_fract *tpf = &cp->timeperframe;
1063 struct ov7670_info *info = to_state(sd);
1065 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1068 cp->capability = V4L2_CAP_TIMEPERFRAME;
1069 return info->devtype->set_framerate(sd, tpf);
1074 * Frame intervals. Since frame rates are controlled with the clock
1075 * divider, we can only do 30/n for integer n values. So no continuous
1076 * or stepwise options. Here we just pick a handful of logical values.
1079 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 };
1081 static int ov7670_enum_frame_interval(struct v4l2_subdev *sd,
1082 struct v4l2_subdev_pad_config *cfg,
1083 struct v4l2_subdev_frame_interval_enum *fie)
1085 struct ov7670_info *info = to_state(sd);
1086 unsigned int n_win_sizes = info->devtype->n_win_sizes;
1091 if (fie->index >= ARRAY_SIZE(ov7670_frame_rates))
1095 * Check if the width/height is valid.
1097 * If a minimum width/height was requested, filter out the capture
1098 * windows that fall outside that.
1100 for (i = 0; i < n_win_sizes; i++) {
1101 struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1103 if (info->min_width && win->width < info->min_width)
1105 if (info->min_height && win->height < info->min_height)
1107 if (fie->width == win->width && fie->height == win->height)
1110 if (i == n_win_sizes)
1112 fie->interval.numerator = 1;
1113 fie->interval.denominator = ov7670_frame_rates[fie->index];
1118 * Frame size enumeration
1120 static int ov7670_enum_frame_size(struct v4l2_subdev *sd,
1121 struct v4l2_subdev_pad_config *cfg,
1122 struct v4l2_subdev_frame_size_enum *fse)
1124 struct ov7670_info *info = to_state(sd);
1127 __u32 index = fse->index;
1128 unsigned int n_win_sizes = info->devtype->n_win_sizes;
1134 * If a minimum width/height was requested, filter out the capture
1135 * windows that fall outside that.
1137 for (i = 0; i < n_win_sizes; i++) {
1138 struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1139 if (info->min_width && win->width < info->min_width)
1141 if (info->min_height && win->height < info->min_height)
1143 if (index == ++num_valid) {
1144 fse->min_width = fse->max_width = win->width;
1145 fse->min_height = fse->max_height = win->height;
1154 * Code for dealing with controls.
1157 static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
1158 int matrix[CMATRIX_LEN])
1161 unsigned char signbits = 0;
1164 * Weird crap seems to exist in the upper part of
1165 * the sign bits register, so let's preserve it.
1167 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
1170 for (i = 0; i < CMATRIX_LEN; i++) {
1173 if (matrix[i] < 0) {
1174 signbits |= (1 << i);
1175 if (matrix[i] < -255)
1178 raw = (-1 * matrix[i]) & 0xff;
1181 if (matrix[i] > 255)
1184 raw = matrix[i] & 0xff;
1186 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
1188 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
1194 * Hue also requires messing with the color matrix. It also requires
1195 * trig functions, which tend not to be well supported in the kernel.
1196 * So here is a simple table of sine values, 0-90 degrees, in steps
1197 * of five degrees. Values are multiplied by 1000.
1199 * The following naive approximate trig functions require an argument
1200 * carefully limited to -180 <= theta <= 180.
1203 static const int ov7670_sin_table[] = {
1204 0, 87, 173, 258, 342, 422,
1205 499, 573, 642, 707, 766, 819,
1206 866, 906, 939, 965, 984, 996,
1210 static int ov7670_sine(int theta)
1220 sine = ov7670_sin_table[theta/SIN_STEP];
1223 sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
1228 static int ov7670_cosine(int theta)
1233 else if (theta < -180)
1235 return ov7670_sine(theta);
1241 static void ov7670_calc_cmatrix(struct ov7670_info *info,
1242 int matrix[CMATRIX_LEN], int sat, int hue)
1246 * Apply the current saturation setting first.
1248 for (i = 0; i < CMATRIX_LEN; i++)
1249 matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7;
1251 * Then, if need be, rotate the hue value.
1254 int sinth, costh, tmpmatrix[CMATRIX_LEN];
1256 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
1257 sinth = ov7670_sine(hue);
1258 costh = ov7670_cosine(hue);
1260 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
1261 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
1262 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
1263 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
1264 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
1265 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
1271 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue)
1273 struct ov7670_info *info = to_state(sd);
1274 int matrix[CMATRIX_LEN];
1277 ov7670_calc_cmatrix(info, matrix, sat, hue);
1278 ret = ov7670_store_cmatrix(sd, matrix);
1284 * Some weird registers seem to store values in a sign/magnitude format!
1287 static unsigned char ov7670_abs_to_sm(unsigned char v)
1291 return (128 - v) | 0x80;
1294 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
1296 unsigned char com8 = 0, v;
1299 ov7670_read(sd, REG_COM8, &com8);
1301 ov7670_write(sd, REG_COM8, com8);
1302 v = ov7670_abs_to_sm(value);
1303 ret = ov7670_write(sd, REG_BRIGHT, v);
1307 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
1309 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
1312 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
1314 unsigned char v = 0;
1317 ret = ov7670_read(sd, REG_MVFP, &v);
1322 msleep(10); /* FIXME */
1323 ret += ov7670_write(sd, REG_MVFP, v);
1327 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
1329 unsigned char v = 0;
1332 ret = ov7670_read(sd, REG_MVFP, &v);
1337 msleep(10); /* FIXME */
1338 ret += ov7670_write(sd, REG_MVFP, v);
1343 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes
1344 * the data sheet, the VREF parts should be the most significant, but
1345 * experience shows otherwise. There seems to be little value in
1346 * messing with the VREF bits, so we leave them alone.
1348 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value)
1353 ret = ov7670_read(sd, REG_GAIN, &gain);
1358 static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
1363 ret = ov7670_write(sd, REG_GAIN, value & 0xff);
1364 /* Have to turn off AGC as well */
1366 ret = ov7670_read(sd, REG_COM8, &com8);
1367 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
1375 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value)
1380 ret = ov7670_read(sd, REG_COM8, &com8);
1386 ret = ov7670_write(sd, REG_COM8, com8);
1391 static int ov7670_s_exp(struct v4l2_subdev *sd, int value)
1394 unsigned char com1, com8, aech, aechh;
1396 ret = ov7670_read(sd, REG_COM1, &com1) +
1397 ov7670_read(sd, REG_COM8, &com8) +
1398 ov7670_read(sd, REG_AECHH, &aechh);
1402 com1 = (com1 & 0xfc) | (value & 0x03);
1403 aech = (value >> 2) & 0xff;
1404 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f);
1405 ret = ov7670_write(sd, REG_COM1, com1) +
1406 ov7670_write(sd, REG_AECH, aech) +
1407 ov7670_write(sd, REG_AECHH, aechh);
1408 /* Have to turn off AEC as well */
1410 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC);
1415 * Tweak autoexposure.
1417 static int ov7670_s_autoexp(struct v4l2_subdev *sd,
1418 enum v4l2_exposure_auto_type value)
1423 ret = ov7670_read(sd, REG_COM8, &com8);
1425 if (value == V4L2_EXPOSURE_AUTO)
1429 ret = ov7670_write(sd, REG_COM8, com8);
1435 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1437 struct v4l2_subdev *sd = to_sd(ctrl);
1438 struct ov7670_info *info = to_state(sd);
1441 case V4L2_CID_AUTOGAIN:
1442 return ov7670_g_gain(sd, &info->gain->val);
1447 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl)
1449 struct v4l2_subdev *sd = to_sd(ctrl);
1450 struct ov7670_info *info = to_state(sd);
1453 case V4L2_CID_BRIGHTNESS:
1454 return ov7670_s_brightness(sd, ctrl->val);
1455 case V4L2_CID_CONTRAST:
1456 return ov7670_s_contrast(sd, ctrl->val);
1457 case V4L2_CID_SATURATION:
1458 return ov7670_s_sat_hue(sd,
1459 info->saturation->val, info->hue->val);
1460 case V4L2_CID_VFLIP:
1461 return ov7670_s_vflip(sd, ctrl->val);
1462 case V4L2_CID_HFLIP:
1463 return ov7670_s_hflip(sd, ctrl->val);
1464 case V4L2_CID_AUTOGAIN:
1465 /* Only set manual gain if auto gain is not explicitly
1468 /* ov7670_s_gain turns off auto gain */
1469 return ov7670_s_gain(sd, info->gain->val);
1471 return ov7670_s_autogain(sd, ctrl->val);
1472 case V4L2_CID_EXPOSURE_AUTO:
1473 /* Only set manual exposure if auto exposure is not explicitly
1475 if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
1476 /* ov7670_s_exp turns off auto exposure */
1477 return ov7670_s_exp(sd, info->exposure->val);
1479 return ov7670_s_autoexp(sd, ctrl->val);
1484 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = {
1485 .s_ctrl = ov7670_s_ctrl,
1486 .g_volatile_ctrl = ov7670_g_volatile_ctrl,
1489 #ifdef CONFIG_VIDEO_ADV_DEBUG
1490 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1492 unsigned char val = 0;
1495 ret = ov7670_read(sd, reg->reg & 0xff, &val);
1501 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1503 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
1508 /* ----------------------------------------------------------------------- */
1510 static const struct v4l2_subdev_core_ops ov7670_core_ops = {
1511 .reset = ov7670_reset,
1512 .init = ov7670_init,
1513 #ifdef CONFIG_VIDEO_ADV_DEBUG
1514 .g_register = ov7670_g_register,
1515 .s_register = ov7670_s_register,
1519 static const struct v4l2_subdev_video_ops ov7670_video_ops = {
1520 .s_parm = ov7670_s_parm,
1521 .g_parm = ov7670_g_parm,
1524 static const struct v4l2_subdev_pad_ops ov7670_pad_ops = {
1525 .enum_frame_interval = ov7670_enum_frame_interval,
1526 .enum_frame_size = ov7670_enum_frame_size,
1527 .enum_mbus_code = ov7670_enum_mbus_code,
1528 .set_fmt = ov7670_set_fmt,
1531 static const struct v4l2_subdev_ops ov7670_ops = {
1532 .core = &ov7670_core_ops,
1533 .video = &ov7670_video_ops,
1534 .pad = &ov7670_pad_ops,
1537 /* ----------------------------------------------------------------------- */
1539 static const struct ov7670_devtype ov7670_devdata[] = {
1541 .win_sizes = ov7670_win_sizes,
1542 .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes),
1543 .set_framerate = ov7670_set_framerate_legacy,
1544 .get_framerate = ov7670_get_framerate_legacy,
1547 .win_sizes = ov7675_win_sizes,
1548 .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes),
1549 .set_framerate = ov7675_set_framerate,
1550 .get_framerate = ov7675_get_framerate,
1554 static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info)
1556 info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
1558 if (IS_ERR(info->pwdn_gpio)) {
1559 dev_info(&client->dev, "can't get %s GPIO\n", "powerdown");
1560 return PTR_ERR(info->pwdn_gpio);
1563 info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1565 if (IS_ERR(info->resetb_gpio)) {
1566 dev_info(&client->dev, "can't get %s GPIO\n", "reset");
1567 return PTR_ERR(info->resetb_gpio);
1570 usleep_range(3000, 5000);
1575 static int ov7670_probe(struct i2c_client *client,
1576 const struct i2c_device_id *id)
1578 struct v4l2_fract tpf;
1579 struct v4l2_subdev *sd;
1580 struct ov7670_info *info;
1583 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
1587 v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
1589 info->clock_speed = 30; /* default: a guess */
1590 if (client->dev.platform_data) {
1591 struct ov7670_config *config = client->dev.platform_data;
1594 * Must apply configuration before initializing device, because it
1595 * selects I/O method.
1597 info->min_width = config->min_width;
1598 info->min_height = config->min_height;
1599 info->use_smbus = config->use_smbus;
1601 if (config->clock_speed)
1602 info->clock_speed = config->clock_speed;
1604 if (config->pll_bypass)
1605 info->pll_bypass = true;
1607 if (config->pclk_hb_disable)
1608 info->pclk_hb_disable = true;
1611 info->clk = devm_clk_get(&client->dev, "xclk"); /* optional */
1612 if (IS_ERR(info->clk)) {
1613 ret = PTR_ERR(info->clk);
1620 ret = clk_prepare_enable(info->clk);
1623 info->clock_speed = clk_get_rate(info->clk) / 1000000;
1624 if (info->clock_speed < 10 || info->clock_speed > 48) {
1630 ret = ov7670_init_gpio(client, info);
1634 /* Make sure it's an ov7670 */
1635 ret = ov7670_detect(sd);
1637 v4l_dbg(1, debug, client,
1638 "chip found @ 0x%x (%s) is not an ov7670 chip.\n",
1639 client->addr << 1, client->adapter->name);
1642 v4l_info(client, "chip found @ 0x%02x (%s)\n",
1643 client->addr << 1, client->adapter->name);
1645 info->devtype = &ov7670_devdata[id->driver_data];
1646 info->fmt = &ov7670_formats[0];
1649 /* Set default frame rate to 30 fps */
1651 tpf.denominator = 30;
1652 info->devtype->set_framerate(sd, &tpf);
1654 if (info->pclk_hb_disable)
1655 ov7670_write(sd, REG_COM10, COM10_PCLK_HB);
1657 v4l2_ctrl_handler_init(&info->hdl, 10);
1658 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1659 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1660 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1661 V4L2_CID_CONTRAST, 0, 127, 1, 64);
1662 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1663 V4L2_CID_VFLIP, 0, 1, 1, 0);
1664 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1665 V4L2_CID_HFLIP, 0, 1, 1, 0);
1666 info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1667 V4L2_CID_SATURATION, 0, 256, 1, 128);
1668 info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1669 V4L2_CID_HUE, -180, 180, 5, 0);
1670 info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1671 V4L2_CID_GAIN, 0, 255, 1, 128);
1672 info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1673 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1674 info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1675 V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
1676 info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops,
1677 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1678 V4L2_EXPOSURE_AUTO);
1679 sd->ctrl_handler = &info->hdl;
1680 if (info->hdl.error) {
1681 ret = info->hdl.error;
1686 * We have checked empirically that hw allows to read back the gain
1687 * value chosen by auto gain but that's not the case for auto exposure.
1689 v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true);
1690 v4l2_ctrl_auto_cluster(2, &info->auto_exposure,
1691 V4L2_EXPOSURE_MANUAL, false);
1692 v4l2_ctrl_cluster(2, &info->saturation);
1693 v4l2_ctrl_handler_setup(&info->hdl);
1695 ret = v4l2_async_register_subdev(&info->sd);
1702 v4l2_ctrl_handler_free(&info->hdl);
1704 clk_disable_unprepare(info->clk);
1709 static int ov7670_remove(struct i2c_client *client)
1711 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1712 struct ov7670_info *info = to_state(sd);
1714 v4l2_device_unregister_subdev(sd);
1715 v4l2_ctrl_handler_free(&info->hdl);
1716 clk_disable_unprepare(info->clk);
1720 static const struct i2c_device_id ov7670_id[] = {
1721 { "ov7670", MODEL_OV7670 },
1722 { "ov7675", MODEL_OV7675 },
1725 MODULE_DEVICE_TABLE(i2c, ov7670_id);
1727 #if IS_ENABLED(CONFIG_OF)
1728 static const struct of_device_id ov7670_of_match[] = {
1729 { .compatible = "ovti,ov7670", },
1732 MODULE_DEVICE_TABLE(of, ov7670_of_match);
1735 static struct i2c_driver ov7670_driver = {
1738 .of_match_table = of_match_ptr(ov7670_of_match),
1740 .probe = ov7670_probe,
1741 .remove = ov7670_remove,
1742 .id_table = ov7670_id,
1745 module_i2c_driver(ov7670_driver);