2 * V4L2 subdevice driver for OmniVision OV6650 Camera Sensor
4 * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
6 * Based on OmniVision OV96xx Camera Driver
7 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
9 * Based on ov772x camera driver:
10 * Copyright (C) 2008 Renesas Solutions Corp.
11 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
13 * Based on ov7670 and soc_camera_platform driver,
14 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
15 * Copyright (C) 2008 Magnus Damm
16 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
18 * Hardware specific bits initialy based on former work by Matt Callow
19 * drivers/media/video/omap/sensor_ov6650.c
20 * Copyright (C) 2006 Matt Callow
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
27 #include <linux/bitops.h>
28 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/v4l2-mediabus.h>
32 #include <linux/module.h>
34 #include <media/v4l2-clk.h>
35 #include <media/v4l2-ctrls.h>
36 #include <media/v4l2-device.h>
38 /* Register definitions */
39 #define REG_GAIN 0x00 /* range 00 - 3F */
42 #define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */
43 #define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */
51 #define REG_CLKRC 0x11 /* Data Format and Internal Clock */
52 /* [7:6] Input system clock (MHz)*/
53 /* 00=8, 01=12, 10=16, 11=24 */
54 /* [5:0]: Internal Clock Pre-Scaler */
55 #define REG_COMA 0x12 /* [7] Reset */
60 #define REG_HSTRT 0x17
61 #define REG_HSTOP 0x18
62 #define REG_VSTRT 0x19
63 #define REG_VSTOP 0x1a
64 #define REG_PSHFT 0x1b
67 #define REG_HSYNS 0x1e
68 #define REG_HSYNE 0x1f
80 #define REG_FRARL 0x2b
87 #define REG_FRAJH 0x32
88 #define REG_FRAJL 0x33
90 #define REG_L1AEC 0x35
101 #define REG_SPCE 0x68
102 #define REG_ADCL 0x69
104 #define REG_RMCO 0x6c
105 #define REG_GMCO 0x6d
106 #define REG_BMCO 0x6e
109 /* Register bits, values, etc. */
110 #define OV6650_PIDH 0x66 /* high byte of product ID number */
111 #define OV6650_PIDL 0x50 /* low byte of product ID number */
112 #define OV6650_MIDH 0x7F /* high byte of mfg ID */
113 #define OV6650_MIDL 0xA2 /* low byte of mfg ID */
115 #define DEF_GAIN 0x00
116 #define DEF_BLUE 0x80
120 #define SAT_MASK (0xf << SAT_SHIFT)
121 #define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK)
123 #define HUE_EN BIT(5)
124 #define HUE_MASK 0x1f
126 #define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK))
128 #define DEF_AECH 0x4D
130 #define CLKRC_6MHz 0x00
131 #define CLKRC_12MHz 0x40
132 #define CLKRC_16MHz 0x80
133 #define CLKRC_24MHz 0xc0
134 #define CLKRC_DIV_MASK 0x3f
135 #define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1)
137 #define COMA_RESET BIT(7)
138 #define COMA_QCIF BIT(5)
139 #define COMA_RAW_RGB BIT(4)
140 #define COMA_RGB BIT(3)
141 #define COMA_BW BIT(2)
142 #define COMA_WORD_SWAP BIT(1)
143 #define COMA_BYTE_SWAP BIT(0)
144 #define DEF_COMA 0x00
146 #define COMB_FLIP_V BIT(7)
147 #define COMB_FLIP_H BIT(5)
148 #define COMB_BAND_FILTER BIT(4)
149 #define COMB_AWB BIT(2)
150 #define COMB_AGC BIT(1)
151 #define COMB_AEC BIT(0)
152 #define DEF_COMB 0x5f
154 #define COML_ONE_CHANNEL BIT(7)
156 #define DEF_HSTRT 0x24
157 #define DEF_HSTOP 0xd4
158 #define DEF_VSTRT 0x04
159 #define DEF_VSTOP 0x94
161 #define COMF_HREF_LOW BIT(4)
163 #define COMJ_PCLK_RISING BIT(4)
164 #define COMJ_VSYNC_HIGH BIT(0)
166 /* supported resolutions */
167 #define W_QCIF (DEF_HSTOP - DEF_HSTRT)
168 #define W_CIF (W_QCIF << 1)
169 #define H_QCIF (DEF_VSTOP - DEF_VSTRT)
170 #define H_CIF (H_QCIF << 1)
172 #define FRAME_RATE_MAX 30
181 struct v4l2_subdev subdev;
182 struct v4l2_ctrl_handler hdl;
184 /* exposure/autoexposure cluster */
185 struct v4l2_ctrl *autoexposure;
186 struct v4l2_ctrl *exposure;
189 /* gain/autogain cluster */
190 struct v4l2_ctrl *autogain;
191 struct v4l2_ctrl *gain;
194 /* blue/red/autowhitebalance cluster */
195 struct v4l2_ctrl *autowb;
196 struct v4l2_ctrl *blue;
197 struct v4l2_ctrl *red;
199 struct v4l2_clk *clk;
200 bool half_scale; /* scale down output by 2 */
201 struct v4l2_rect rect; /* sensor cropping window */
202 unsigned long pclk_limit; /* from host */
203 unsigned long pclk_max; /* from resolution and format */
204 struct v4l2_fract tpf; /* as requested with s_parm */
209 static u32 ov6650_codes[] = {
210 MEDIA_BUS_FMT_YUYV8_2X8,
211 MEDIA_BUS_FMT_UYVY8_2X8,
212 MEDIA_BUS_FMT_YVYU8_2X8,
213 MEDIA_BUS_FMT_VYUY8_2X8,
214 MEDIA_BUS_FMT_SBGGR8_1X8,
215 MEDIA_BUS_FMT_Y8_1X8,
218 static const struct v4l2_mbus_framefmt ov6650_def_fmt = {
221 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
222 .colorspace = V4L2_COLORSPACE_SRGB,
223 .field = V4L2_FIELD_NONE,
224 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,
225 .quantization = V4L2_QUANTIZATION_DEFAULT,
226 .xfer_func = V4L2_XFER_FUNC_DEFAULT,
229 /* read a register */
230 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
234 struct i2c_msg msg = {
235 .addr = client->addr,
241 ret = i2c_transfer(client->adapter, &msg, 1);
245 msg.flags = I2C_M_RD;
246 ret = i2c_transfer(client->adapter, &msg, 1);
254 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
258 /* write a register */
259 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
262 unsigned char data[2] = { reg, val };
263 struct i2c_msg msg = {
264 .addr = client->addr,
270 ret = i2c_transfer(client->adapter, &msg, 1);
274 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
281 /* Read a register, alter its bits, write it back */
282 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
287 ret = ov6650_reg_read(client, reg, &val);
289 dev_err(&client->dev,
290 "[Read]-Modify-Write of register 0x%02x failed!\n",
298 ret = ov6650_reg_write(client, reg, val);
300 dev_err(&client->dev,
301 "Read-Modify-[Write] of register 0x%02x failed!\n",
307 static struct ov6650 *to_ov6650(const struct i2c_client *client)
309 return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
312 /* Start/Stop streaming from the device */
313 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
318 /* Get status of additional camera capabilities */
319 static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
321 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
322 struct v4l2_subdev *sd = &priv->subdev;
323 struct i2c_client *client = v4l2_get_subdevdata(sd);
328 case V4L2_CID_AUTOGAIN:
329 ret = ov6650_reg_read(client, REG_GAIN, ®);
331 priv->gain->val = reg;
333 case V4L2_CID_AUTO_WHITE_BALANCE:
334 ret = ov6650_reg_read(client, REG_BLUE, ®);
336 ret = ov6650_reg_read(client, REG_RED, ®2);
338 priv->blue->val = reg;
339 priv->red->val = reg2;
342 case V4L2_CID_EXPOSURE_AUTO:
343 ret = ov6650_reg_read(client, REG_AECH, ®);
345 priv->exposure->val = reg;
351 /* Set status of additional camera capabilities */
352 static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
354 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
355 struct v4l2_subdev *sd = &priv->subdev;
356 struct i2c_client *client = v4l2_get_subdevdata(sd);
360 case V4L2_CID_AUTOGAIN:
361 ret = ov6650_reg_rmw(client, REG_COMB,
362 ctrl->val ? COMB_AGC : 0, COMB_AGC);
363 if (!ret && !ctrl->val)
364 ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
366 case V4L2_CID_AUTO_WHITE_BALANCE:
367 ret = ov6650_reg_rmw(client, REG_COMB,
368 ctrl->val ? COMB_AWB : 0, COMB_AWB);
369 if (!ret && !ctrl->val) {
370 ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
372 ret = ov6650_reg_write(client, REG_RED,
376 case V4L2_CID_SATURATION:
377 return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
380 return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
382 case V4L2_CID_BRIGHTNESS:
383 return ov6650_reg_write(client, REG_BRT, ctrl->val);
384 case V4L2_CID_EXPOSURE_AUTO:
385 ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
386 V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
387 if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
388 ret = ov6650_reg_write(client, REG_AECH,
389 priv->exposure->val);
392 return ov6650_reg_write(client, REG_GAM1, ctrl->val);
394 return ov6650_reg_rmw(client, REG_COMB,
395 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
397 return ov6650_reg_rmw(client, REG_COMB,
398 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
404 #ifdef CONFIG_VIDEO_ADV_DEBUG
405 static int ov6650_get_register(struct v4l2_subdev *sd,
406 struct v4l2_dbg_register *reg)
408 struct i2c_client *client = v4l2_get_subdevdata(sd);
412 if (reg->reg & ~0xff)
417 ret = ov6650_reg_read(client, reg->reg, &val);
419 reg->val = (__u64)val;
424 static int ov6650_set_register(struct v4l2_subdev *sd,
425 const struct v4l2_dbg_register *reg)
427 struct i2c_client *client = v4l2_get_subdevdata(sd);
429 if (reg->reg & ~0xff || reg->val & ~0xff)
432 return ov6650_reg_write(client, reg->reg, reg->val);
436 static int ov6650_s_power(struct v4l2_subdev *sd, int on)
438 struct i2c_client *client = v4l2_get_subdevdata(sd);
439 struct ov6650 *priv = to_ov6650(client);
443 ret = v4l2_clk_enable(priv->clk);
445 v4l2_clk_disable(priv->clk);
450 static int ov6650_get_selection(struct v4l2_subdev *sd,
451 struct v4l2_subdev_pad_config *cfg,
452 struct v4l2_subdev_selection *sel)
454 struct i2c_client *client = v4l2_get_subdevdata(sd);
455 struct ov6650 *priv = to_ov6650(client);
457 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
460 switch (sel->target) {
461 case V4L2_SEL_TGT_CROP_BOUNDS:
462 case V4L2_SEL_TGT_CROP_DEFAULT:
463 sel->r.left = DEF_HSTRT << 1;
464 sel->r.top = DEF_VSTRT << 1;
465 sel->r.width = W_CIF;
466 sel->r.height = H_CIF;
468 case V4L2_SEL_TGT_CROP:
476 static int ov6650_set_selection(struct v4l2_subdev *sd,
477 struct v4l2_subdev_pad_config *cfg,
478 struct v4l2_subdev_selection *sel)
480 struct i2c_client *client = v4l2_get_subdevdata(sd);
481 struct ov6650 *priv = to_ov6650(client);
484 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
485 sel->target != V4L2_SEL_TGT_CROP)
488 v4l_bound_align_image(&sel->r.width, 2, W_CIF, 1,
489 &sel->r.height, 2, H_CIF, 1, 0);
490 v4l_bound_align_image(&sel->r.left, DEF_HSTRT << 1,
491 (DEF_HSTRT << 1) + W_CIF - (__s32)sel->r.width, 1,
492 &sel->r.top, DEF_VSTRT << 1,
493 (DEF_VSTRT << 1) + H_CIF - (__s32)sel->r.height,
496 ret = ov6650_reg_write(client, REG_HSTRT, sel->r.left >> 1);
498 priv->rect.width += priv->rect.left - sel->r.left;
499 priv->rect.left = sel->r.left;
500 ret = ov6650_reg_write(client, REG_HSTOP,
501 (sel->r.left + sel->r.width) >> 1);
504 priv->rect.width = sel->r.width;
505 ret = ov6650_reg_write(client, REG_VSTRT, sel->r.top >> 1);
508 priv->rect.height += priv->rect.top - sel->r.top;
509 priv->rect.top = sel->r.top;
510 ret = ov6650_reg_write(client, REG_VSTOP,
511 (sel->r.top + sel->r.height) >> 1);
514 priv->rect.height = sel->r.height;
519 static int ov6650_get_fmt(struct v4l2_subdev *sd,
520 struct v4l2_subdev_pad_config *cfg,
521 struct v4l2_subdev_format *format)
523 struct v4l2_mbus_framefmt *mf = &format->format;
524 struct i2c_client *client = v4l2_get_subdevdata(sd);
525 struct ov6650 *priv = to_ov6650(client);
530 /* initialize response with default media bus frame format */
531 *mf = ov6650_def_fmt;
533 /* update media bus format code and frame size */
534 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
535 mf->width = cfg->try_fmt.width;
536 mf->height = cfg->try_fmt.height;
537 mf->code = cfg->try_fmt.code;
540 mf->width = priv->rect.width >> priv->half_scale;
541 mf->height = priv->rect.height >> priv->half_scale;
542 mf->code = priv->code;
547 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
549 return width > rect->width >> 1 || height > rect->height >> 1;
552 static u8 to_clkrc(struct v4l2_fract *timeperframe,
553 unsigned long pclk_limit, unsigned long pclk_max)
557 if (timeperframe->numerator && timeperframe->denominator)
558 pclk = pclk_max * timeperframe->denominator /
559 (FRAME_RATE_MAX * timeperframe->numerator);
563 if (pclk_limit && pclk_limit < pclk)
566 return (pclk_max - 1) / pclk;
569 /* set the format we will capture in */
570 static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
572 struct i2c_client *client = v4l2_get_subdevdata(sd);
573 struct ov6650 *priv = to_ov6650(client);
574 bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
575 struct v4l2_subdev_selection sel = {
576 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
577 .target = V4L2_SEL_TGT_CROP,
578 .r.left = priv->rect.left + (priv->rect.width >> 1) -
579 (mf->width >> (1 - half_scale)),
580 .r.top = priv->rect.top + (priv->rect.height >> 1) -
581 (mf->height >> (1 - half_scale)),
582 .r.width = mf->width << half_scale,
583 .r.height = mf->height << half_scale,
586 unsigned long mclk, pclk;
587 u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc;
590 /* select color matrix configuration for given color encoding */
592 case MEDIA_BUS_FMT_Y8_1X8:
593 dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
594 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
597 case MEDIA_BUS_FMT_YUYV8_2X8:
598 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
599 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
600 coma_set |= COMA_WORD_SWAP;
602 case MEDIA_BUS_FMT_YVYU8_2X8:
603 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
604 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
607 case MEDIA_BUS_FMT_UYVY8_2X8:
608 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
610 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
611 coma_set |= COMA_BYTE_SWAP;
613 coma_mask |= COMA_RGB | COMA_BW;
614 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
617 case MEDIA_BUS_FMT_VYUY8_2X8:
618 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
620 coma_mask |= COMA_RGB | COMA_BW;
621 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
623 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
624 coma_set |= COMA_BYTE_SWAP;
627 case MEDIA_BUS_FMT_SBGGR8_1X8:
628 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
629 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
630 coma_set |= COMA_RAW_RGB | COMA_RGB;
633 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
637 if (code == MEDIA_BUS_FMT_Y8_1X8 ||
638 code == MEDIA_BUS_FMT_SBGGR8_1X8) {
639 coml_mask = COML_ONE_CHANNEL;
641 priv->pclk_max = 4000000;
644 coml_set = COML_ONE_CHANNEL;
645 priv->pclk_max = 8000000;
649 dev_dbg(&client->dev, "max resolution: QCIF\n");
650 coma_set |= COMA_QCIF;
653 dev_dbg(&client->dev, "max resolution: CIF\n");
654 coma_mask |= COMA_QCIF;
659 priv->pclk_limit = 1334000;
660 dev_dbg(&client->dev, "using 12MHz input clock\n");
662 clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
664 pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc);
665 dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n",
666 mclk / pclk, 10 * mclk % pclk / pclk);
668 ret = ov6650_set_selection(sd, NULL, &sel);
670 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
672 ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
674 priv->half_scale = half_scale;
676 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
684 static int ov6650_set_fmt(struct v4l2_subdev *sd,
685 struct v4l2_subdev_pad_config *cfg,
686 struct v4l2_subdev_format *format)
688 struct v4l2_mbus_framefmt *mf = &format->format;
689 struct i2c_client *client = v4l2_get_subdevdata(sd);
690 struct ov6650 *priv = to_ov6650(client);
695 if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
696 v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
697 &mf->height, 2, H_CIF, 1, 0);
700 case MEDIA_BUS_FMT_Y10_1X10:
701 mf->code = MEDIA_BUS_FMT_Y8_1X8;
703 case MEDIA_BUS_FMT_Y8_1X8:
704 case MEDIA_BUS_FMT_YVYU8_2X8:
705 case MEDIA_BUS_FMT_YUYV8_2X8:
706 case MEDIA_BUS_FMT_VYUY8_2X8:
707 case MEDIA_BUS_FMT_UYVY8_2X8:
710 mf->code = MEDIA_BUS_FMT_SBGGR8_1X8;
712 case MEDIA_BUS_FMT_SBGGR8_1X8:
716 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
717 /* store media bus format code and frame size in pad config */
718 cfg->try_fmt.width = mf->width;
719 cfg->try_fmt.height = mf->height;
720 cfg->try_fmt.code = mf->code;
722 /* return default mbus frame format updated with pad config */
723 *mf = ov6650_def_fmt;
724 mf->width = cfg->try_fmt.width;
725 mf->height = cfg->try_fmt.height;
726 mf->code = cfg->try_fmt.code;
729 /* apply new media bus format code and frame size */
730 int ret = ov6650_s_fmt(sd, mf);
735 /* return default format updated with active size and code */
736 *mf = ov6650_def_fmt;
737 mf->width = priv->rect.width >> priv->half_scale;
738 mf->height = priv->rect.height >> priv->half_scale;
739 mf->code = priv->code;
744 static int ov6650_enum_mbus_code(struct v4l2_subdev *sd,
745 struct v4l2_subdev_pad_config *cfg,
746 struct v4l2_subdev_mbus_code_enum *code)
748 if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes))
751 code->code = ov6650_codes[code->index];
755 static int ov6650_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
757 struct i2c_client *client = v4l2_get_subdevdata(sd);
758 struct ov6650 *priv = to_ov6650(client);
759 struct v4l2_captureparm *cp = &parms->parm.capture;
761 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
764 memset(cp, 0, sizeof(*cp));
765 cp->capability = V4L2_CAP_TIMEPERFRAME;
766 cp->timeperframe.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf,
767 priv->pclk_limit, priv->pclk_max));
768 cp->timeperframe.denominator = FRAME_RATE_MAX;
770 dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
771 cp->timeperframe.numerator, cp->timeperframe.denominator);
776 static int ov6650_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
778 struct i2c_client *client = v4l2_get_subdevdata(sd);
779 struct ov6650 *priv = to_ov6650(client);
780 struct v4l2_captureparm *cp = &parms->parm.capture;
781 struct v4l2_fract *tpf = &cp->timeperframe;
785 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
788 if (cp->extendedmode != 0)
791 if (tpf->numerator == 0 || tpf->denominator == 0)
792 div = 1; /* Reset to full rate */
794 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
798 else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
799 div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
802 * Keep result to be used as tpf limit
803 * for subseqent clock divider calculations
805 priv->tpf.numerator = div;
806 priv->tpf.denominator = FRAME_RATE_MAX;
808 clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
810 ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK);
812 tpf->numerator = GET_CLKRC_DIV(clkrc);
813 tpf->denominator = FRAME_RATE_MAX;
819 /* Soft reset the camera. This has nothing to do with the RESET pin! */
820 static int ov6650_reset(struct i2c_client *client)
824 dev_dbg(&client->dev, "reset\n");
826 ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
828 dev_err(&client->dev,
829 "An error occurred while entering soft reset!\n");
834 /* program default register values */
835 static int ov6650_prog_dflt(struct i2c_client *client)
839 dev_dbg(&client->dev, "initializing\n");
841 ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */
843 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
848 static int ov6650_video_probe(struct i2c_client *client)
850 struct ov6650 *priv = to_ov6650(client);
851 u8 pidh, pidl, midh, midl;
854 priv->clk = v4l2_clk_get(&client->dev, NULL);
855 if (IS_ERR(priv->clk)) {
856 ret = PTR_ERR(priv->clk);
857 dev_err(&client->dev, "v4l2_clk request err: %d\n", ret);
861 ret = ov6650_s_power(&priv->subdev, 1);
868 * check and show product ID and manufacturer ID
870 ret = ov6650_reg_read(client, REG_PIDH, &pidh);
872 ret = ov6650_reg_read(client, REG_PIDL, &pidl);
874 ret = ov6650_reg_read(client, REG_MIDH, &midh);
876 ret = ov6650_reg_read(client, REG_MIDL, &midl);
881 if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
882 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
888 dev_info(&client->dev,
889 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
890 pidh, pidl, midh, midl);
892 ret = ov6650_reset(client);
894 ret = ov6650_prog_dflt(client);
896 ret = v4l2_ctrl_handler_setup(&priv->hdl);
899 ov6650_s_power(&priv->subdev, 0);
903 v4l2_clk_put(priv->clk);
908 static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
909 .g_volatile_ctrl = ov6550_g_volatile_ctrl,
910 .s_ctrl = ov6550_s_ctrl,
913 static const struct v4l2_subdev_core_ops ov6650_core_ops = {
914 #ifdef CONFIG_VIDEO_ADV_DEBUG
915 .g_register = ov6650_get_register,
916 .s_register = ov6650_set_register,
918 .s_power = ov6650_s_power,
921 /* Request bus settings on camera side */
922 static int ov6650_g_mbus_config(struct v4l2_subdev *sd,
923 struct v4l2_mbus_config *cfg)
926 cfg->flags = V4L2_MBUS_MASTER |
927 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
928 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
929 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
930 V4L2_MBUS_DATA_ACTIVE_HIGH;
931 cfg->type = V4L2_MBUS_PARALLEL;
936 /* Alter bus settings on camera side */
937 static int ov6650_s_mbus_config(struct v4l2_subdev *sd,
938 const struct v4l2_mbus_config *cfg)
940 struct i2c_client *client = v4l2_get_subdevdata(sd);
943 if (cfg->flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
944 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
946 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
950 if (cfg->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
951 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
953 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
957 if (cfg->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
958 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
960 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
965 static const struct v4l2_subdev_video_ops ov6650_video_ops = {
966 .s_stream = ov6650_s_stream,
967 .g_parm = ov6650_g_parm,
968 .s_parm = ov6650_s_parm,
969 .g_mbus_config = ov6650_g_mbus_config,
970 .s_mbus_config = ov6650_s_mbus_config,
973 static const struct v4l2_subdev_pad_ops ov6650_pad_ops = {
974 .enum_mbus_code = ov6650_enum_mbus_code,
975 .get_selection = ov6650_get_selection,
976 .set_selection = ov6650_set_selection,
977 .get_fmt = ov6650_get_fmt,
978 .set_fmt = ov6650_set_fmt,
981 static const struct v4l2_subdev_ops ov6650_subdev_ops = {
982 .core = &ov6650_core_ops,
983 .video = &ov6650_video_ops,
984 .pad = &ov6650_pad_ops,
988 * i2c_driver function
990 static int ov6650_probe(struct i2c_client *client,
991 const struct i2c_device_id *did)
996 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
998 dev_err(&client->dev,
999 "Failed to allocate memory for private data!\n");
1003 v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
1004 v4l2_ctrl_handler_init(&priv->hdl, 13);
1005 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1006 V4L2_CID_VFLIP, 0, 1, 1, 0);
1007 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1008 V4L2_CID_HFLIP, 0, 1, 1, 0);
1009 priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1010 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1011 priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1012 V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
1013 priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1014 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1015 priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1016 V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
1017 priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1018 V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
1019 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1020 V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
1021 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1022 V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
1023 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1024 V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
1025 priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
1026 &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
1027 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
1028 priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1029 V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
1030 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
1031 V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
1033 priv->subdev.ctrl_handler = &priv->hdl;
1034 if (priv->hdl.error)
1035 return priv->hdl.error;
1037 v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
1038 v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1039 v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1040 V4L2_EXPOSURE_MANUAL, true);
1042 priv->rect.left = DEF_HSTRT << 1;
1043 priv->rect.top = DEF_VSTRT << 1;
1044 priv->rect.width = W_CIF;
1045 priv->rect.height = H_CIF;
1046 priv->half_scale = false;
1047 priv->code = MEDIA_BUS_FMT_YUYV8_2X8;
1049 ret = ov6650_video_probe(client);
1051 v4l2_ctrl_handler_free(&priv->hdl);
1056 static int ov6650_remove(struct i2c_client *client)
1058 struct ov6650 *priv = to_ov6650(client);
1060 v4l2_clk_put(priv->clk);
1061 v4l2_device_unregister_subdev(&priv->subdev);
1062 v4l2_ctrl_handler_free(&priv->hdl);
1066 static const struct i2c_device_id ov6650_id[] = {
1070 MODULE_DEVICE_TABLE(i2c, ov6650_id);
1072 static struct i2c_driver ov6650_i2c_driver = {
1076 .probe = ov6650_probe,
1077 .remove = ov6650_remove,
1078 .id_table = ov6650_id,
1081 module_i2c_driver(ov6650_i2c_driver);
1083 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650");
1084 MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>");
1085 MODULE_LICENSE("GPL v2");