1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2020 Intel Corporation.
4 #include <asm/unaligned.h>
5 #include <linux/acpi.h>
6 #include <linux/delay.h>
8 #include <linux/module.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/nvmem-provider.h>
11 #include <linux/regmap.h>
12 #include <media/v4l2-ctrls.h>
13 #include <media/v4l2-device.h>
14 #include <media/v4l2-fwnode.h>
16 #define OV2740_LINK_FREQ_360MHZ 360000000ULL
17 #define OV2740_SCLK 72000000LL
18 #define OV2740_MCLK 19200000
19 #define OV2740_DATA_LANES 2
20 #define OV2740_RGB_DEPTH 10
22 #define OV2740_REG_CHIP_ID 0x300a
23 #define OV2740_CHIP_ID 0x2740
25 #define OV2740_REG_MODE_SELECT 0x0100
26 #define OV2740_MODE_STANDBY 0x00
27 #define OV2740_MODE_STREAMING 0x01
29 /* vertical-timings from sensor */
30 #define OV2740_REG_VTS 0x380e
31 #define OV2740_VTS_DEF 0x088a
32 #define OV2740_VTS_MIN 0x0460
33 #define OV2740_VTS_MAX 0x7fff
35 /* horizontal-timings from sensor */
36 #define OV2740_REG_HTS 0x380c
38 /* Exposure controls from sensor */
39 #define OV2740_REG_EXPOSURE 0x3500
40 #define OV2740_EXPOSURE_MIN 8
41 #define OV2740_EXPOSURE_MAX_MARGIN 8
42 #define OV2740_EXPOSURE_STEP 1
44 /* Analog gain controls from sensor */
45 #define OV2740_REG_ANALOG_GAIN 0x3508
46 #define OV2740_ANAL_GAIN_MIN 128
47 #define OV2740_ANAL_GAIN_MAX 1983
48 #define OV2740_ANAL_GAIN_STEP 1
50 /* Digital gain controls from sensor */
51 #define OV2740_REG_MWB_R_GAIN 0x500a
52 #define OV2740_REG_MWB_G_GAIN 0x500c
53 #define OV2740_REG_MWB_B_GAIN 0x500e
54 #define OV2740_DGTL_GAIN_MIN 0
55 #define OV2740_DGTL_GAIN_MAX 4095
56 #define OV2740_DGTL_GAIN_STEP 1
57 #define OV2740_DGTL_GAIN_DEFAULT 1024
59 /* Test Pattern Control */
60 #define OV2740_REG_TEST_PATTERN 0x5040
61 #define OV2740_TEST_PATTERN_ENABLE BIT(7)
62 #define OV2740_TEST_PATTERN_BAR_SHIFT 2
65 #define OV2740_REG_ISP_CTRL00 0x5000
67 #define OV2740_REG_ISP_CTRL01 0x5001
68 /* Customer Addresses: 0x7010 - 0x710F */
69 #define CUSTOMER_USE_OTP_SIZE 0x100
70 /* OTP registers from sensor */
71 #define OV2740_REG_OTP_CUSTOMER 0x7010
75 struct nvmem_device *nvmem;
76 struct regmap *regmap;
80 OV2740_LINK_FREQ_360MHZ_INDEX,
88 struct ov2740_reg_list {
90 const struct ov2740_reg *regs;
93 struct ov2740_link_freq_config {
94 const struct ov2740_reg_list reg_list;
98 /* Frame width in pixels */
101 /* Frame height in pixels */
104 /* Horizontal timining size */
107 /* Default vertical timining size */
110 /* Min vertical timining size */
113 /* Link frequency needed for this resolution */
116 /* Sensor register settings for this resolution */
117 const struct ov2740_reg_list reg_list;
120 static const struct ov2740_reg mipi_data_rate_720mbps[] = {
129 static const struct ov2740_reg mode_1932x1092_regs[] = {
282 static const char * const ov2740_test_pattern_menu[] = {
285 "Top-Bottom Darker Color Bar",
286 "Right-Left Darker Color Bar",
287 "Bottom-Top Darker Color Bar",
290 static const s64 link_freq_menu_items[] = {
291 OV2740_LINK_FREQ_360MHZ,
294 static const struct ov2740_link_freq_config link_freq_configs[] = {
295 [OV2740_LINK_FREQ_360MHZ_INDEX] = {
297 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
298 .regs = mipi_data_rate_720mbps,
303 static const struct ov2740_mode supported_modes[] = {
308 .vts_def = OV2740_VTS_DEF,
309 .vts_min = OV2740_VTS_MIN,
311 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs),
312 .regs = mode_1932x1092_regs,
314 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX,
319 struct v4l2_subdev sd;
320 struct media_pad pad;
321 struct v4l2_ctrl_handler ctrl_handler;
324 struct v4l2_ctrl *link_freq;
325 struct v4l2_ctrl *pixel_rate;
326 struct v4l2_ctrl *vblank;
327 struct v4l2_ctrl *hblank;
328 struct v4l2_ctrl *exposure;
331 const struct ov2740_mode *cur_mode;
333 /* To serialize asynchronus callbacks */
336 /* Streaming on/off */
340 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev)
342 return container_of(subdev, struct ov2740, sd);
345 static u64 to_pixel_rate(u32 f_index)
347 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES;
349 do_div(pixel_rate, OV2740_RGB_DEPTH);
354 static u64 to_pixels_per_line(u32 hts, u32 f_index)
356 u64 ppl = hts * to_pixel_rate(f_index);
358 do_div(ppl, OV2740_SCLK);
363 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val)
365 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
366 struct i2c_msg msgs[2];
368 u8 data_buf[4] = {0};
371 if (len > sizeof(data_buf))
374 put_unaligned_be16(reg, addr_buf);
375 msgs[0].addr = client->addr;
377 msgs[0].len = sizeof(addr_buf);
378 msgs[0].buf = addr_buf;
379 msgs[1].addr = client->addr;
380 msgs[1].flags = I2C_M_RD;
382 msgs[1].buf = &data_buf[sizeof(data_buf) - len];
384 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
385 if (ret != ARRAY_SIZE(msgs))
386 return ret < 0 ? ret : -EIO;
388 *val = get_unaligned_be32(data_buf);
393 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)
395 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
402 put_unaligned_be16(reg, buf);
403 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
405 ret = i2c_master_send(client, buf, len + 2);
407 return ret < 0 ? ret : -EIO;
412 static int ov2740_write_reg_list(struct ov2740 *ov2740,
413 const struct ov2740_reg_list *r_list)
415 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
419 for (i = 0; i < r_list->num_of_regs; i++) {
420 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,
421 r_list->regs[i].val);
423 dev_err_ratelimited(&client->dev,
424 "write reg 0x%4.4x return err = %d",
425 r_list->regs[i].address, ret);
433 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain)
437 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);
441 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);
445 return ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);
448 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern)
451 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT |
452 OV2740_TEST_PATTERN_ENABLE;
454 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);
457 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl)
459 struct ov2740 *ov2740 = container_of(ctrl->handler,
460 struct ov2740, ctrl_handler);
461 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
465 /* Propagate change of current control to all related controls */
466 if (ctrl->id == V4L2_CID_VBLANK) {
467 /* Update max exposure while meeting expected vblanking */
468 exposure_max = ov2740->cur_mode->height + ctrl->val -
469 OV2740_EXPOSURE_MAX_MARGIN;
470 __v4l2_ctrl_modify_range(ov2740->exposure,
471 ov2740->exposure->minimum,
472 exposure_max, ov2740->exposure->step,
476 /* V4L2 controls values will be applied only when power is already up */
477 if (!pm_runtime_get_if_in_use(&client->dev))
481 case V4L2_CID_ANALOGUE_GAIN:
482 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,
486 case V4L2_CID_DIGITAL_GAIN:
487 ret = ov2740_update_digital_gain(ov2740, ctrl->val);
490 case V4L2_CID_EXPOSURE:
491 /* 4 least significant bits of expsoure are fractional part */
492 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,
496 case V4L2_CID_VBLANK:
497 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,
498 ov2740->cur_mode->height + ctrl->val);
501 case V4L2_CID_TEST_PATTERN:
502 ret = ov2740_test_pattern(ov2740, ctrl->val);
510 pm_runtime_put(&client->dev);
515 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = {
516 .s_ctrl = ov2740_set_ctrl,
519 static int ov2740_init_controls(struct ov2740 *ov2740)
521 struct v4l2_ctrl_handler *ctrl_hdlr;
522 const struct ov2740_mode *cur_mode;
523 s64 exposure_max, h_blank, pixel_rate;
524 u32 vblank_min, vblank_max, vblank_default;
528 ctrl_hdlr = &ov2740->ctrl_handler;
529 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
533 ctrl_hdlr->lock = &ov2740->mutex;
534 cur_mode = ov2740->cur_mode;
535 size = ARRAY_SIZE(link_freq_menu_items);
537 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops,
540 link_freq_menu_items);
541 if (ov2740->link_freq)
542 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
544 pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX);
545 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
546 V4L2_CID_PIXEL_RATE, 0,
547 pixel_rate, 1, pixel_rate);
549 vblank_min = cur_mode->vts_min - cur_mode->height;
550 vblank_max = OV2740_VTS_MAX - cur_mode->height;
551 vblank_default = cur_mode->vts_def - cur_mode->height;
552 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
553 V4L2_CID_VBLANK, vblank_min,
554 vblank_max, 1, vblank_default);
556 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index);
557 h_blank -= cur_mode->width;
558 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
559 V4L2_CID_HBLANK, h_blank, h_blank, 1,
562 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
564 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
565 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX,
566 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN);
567 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
568 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX,
569 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT);
570 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN;
571 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
573 OV2740_EXPOSURE_MIN, exposure_max,
574 OV2740_EXPOSURE_STEP,
576 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops,
577 V4L2_CID_TEST_PATTERN,
578 ARRAY_SIZE(ov2740_test_pattern_menu) - 1,
579 0, 0, ov2740_test_pattern_menu);
580 if (ctrl_hdlr->error)
581 return ctrl_hdlr->error;
583 ov2740->sd.ctrl_handler = ctrl_hdlr;
588 static void ov2740_update_pad_format(const struct ov2740_mode *mode,
589 struct v4l2_mbus_framefmt *fmt)
591 fmt->width = mode->width;
592 fmt->height = mode->height;
593 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
594 fmt->field = V4L2_FIELD_NONE;
597 static int ov2740_start_streaming(struct ov2740 *ov2740)
599 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
600 const struct ov2740_reg_list *reg_list;
604 link_freq_index = ov2740->cur_mode->link_freq_index;
605 reg_list = &link_freq_configs[link_freq_index].reg_list;
606 ret = ov2740_write_reg_list(ov2740, reg_list);
608 dev_err(&client->dev, "failed to set plls");
612 reg_list = &ov2740->cur_mode->reg_list;
613 ret = ov2740_write_reg_list(ov2740, reg_list);
615 dev_err(&client->dev, "failed to set mode");
619 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler);
623 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
624 OV2740_MODE_STREAMING);
626 dev_err(&client->dev, "failed to start streaming");
631 static void ov2740_stop_streaming(struct ov2740 *ov2740)
633 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
635 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
636 OV2740_MODE_STANDBY))
637 dev_err(&client->dev, "failed to stop streaming");
640 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable)
642 struct ov2740 *ov2740 = to_ov2740(sd);
643 struct i2c_client *client = v4l2_get_subdevdata(sd);
646 if (ov2740->streaming == enable)
649 mutex_lock(&ov2740->mutex);
651 ret = pm_runtime_get_sync(&client->dev);
653 pm_runtime_put_noidle(&client->dev);
654 mutex_unlock(&ov2740->mutex);
658 ret = ov2740_start_streaming(ov2740);
661 ov2740_stop_streaming(ov2740);
662 pm_runtime_put(&client->dev);
665 ov2740_stop_streaming(ov2740);
666 pm_runtime_put(&client->dev);
669 ov2740->streaming = enable;
670 mutex_unlock(&ov2740->mutex);
675 static int __maybe_unused ov2740_suspend(struct device *dev)
677 struct i2c_client *client = to_i2c_client(dev);
678 struct v4l2_subdev *sd = i2c_get_clientdata(client);
679 struct ov2740 *ov2740 = to_ov2740(sd);
681 mutex_lock(&ov2740->mutex);
682 if (ov2740->streaming)
683 ov2740_stop_streaming(ov2740);
685 mutex_unlock(&ov2740->mutex);
690 static int __maybe_unused ov2740_resume(struct device *dev)
692 struct i2c_client *client = to_i2c_client(dev);
693 struct v4l2_subdev *sd = i2c_get_clientdata(client);
694 struct ov2740 *ov2740 = to_ov2740(sd);
697 mutex_lock(&ov2740->mutex);
698 if (!ov2740->streaming)
701 ret = ov2740_start_streaming(ov2740);
703 ov2740->streaming = false;
704 ov2740_stop_streaming(ov2740);
708 mutex_unlock(&ov2740->mutex);
712 static int ov2740_set_format(struct v4l2_subdev *sd,
713 struct v4l2_subdev_pad_config *cfg,
714 struct v4l2_subdev_format *fmt)
716 struct ov2740 *ov2740 = to_ov2740(sd);
717 const struct ov2740_mode *mode;
718 s32 vblank_def, h_blank;
720 mode = v4l2_find_nearest_size(supported_modes,
721 ARRAY_SIZE(supported_modes), width,
722 height, fmt->format.width,
725 mutex_lock(&ov2740->mutex);
726 ov2740_update_pad_format(mode, &fmt->format);
727 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
728 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
730 ov2740->cur_mode = mode;
731 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index);
732 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate,
733 to_pixel_rate(mode->link_freq_index));
735 /* Update limits and set FPS to default */
736 vblank_def = mode->vts_def - mode->height;
737 __v4l2_ctrl_modify_range(ov2740->vblank,
738 mode->vts_min - mode->height,
739 OV2740_VTS_MAX - mode->height, 1,
741 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def);
742 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
744 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1,
747 mutex_unlock(&ov2740->mutex);
752 static int ov2740_get_format(struct v4l2_subdev *sd,
753 struct v4l2_subdev_pad_config *cfg,
754 struct v4l2_subdev_format *fmt)
756 struct ov2740 *ov2740 = to_ov2740(sd);
758 mutex_lock(&ov2740->mutex);
759 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
760 fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd, cfg,
763 ov2740_update_pad_format(ov2740->cur_mode, &fmt->format);
765 mutex_unlock(&ov2740->mutex);
770 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd,
771 struct v4l2_subdev_pad_config *cfg,
772 struct v4l2_subdev_mbus_code_enum *code)
777 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
782 static int ov2740_enum_frame_size(struct v4l2_subdev *sd,
783 struct v4l2_subdev_pad_config *cfg,
784 struct v4l2_subdev_frame_size_enum *fse)
786 if (fse->index >= ARRAY_SIZE(supported_modes))
789 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
792 fse->min_width = supported_modes[fse->index].width;
793 fse->max_width = fse->min_width;
794 fse->min_height = supported_modes[fse->index].height;
795 fse->max_height = fse->min_height;
800 static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
802 struct ov2740 *ov2740 = to_ov2740(sd);
804 mutex_lock(&ov2740->mutex);
805 ov2740_update_pad_format(&supported_modes[0],
806 v4l2_subdev_get_try_format(sd, fh->pad, 0));
807 mutex_unlock(&ov2740->mutex);
812 static const struct v4l2_subdev_video_ops ov2740_video_ops = {
813 .s_stream = ov2740_set_stream,
816 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = {
817 .set_fmt = ov2740_set_format,
818 .get_fmt = ov2740_get_format,
819 .enum_mbus_code = ov2740_enum_mbus_code,
820 .enum_frame_size = ov2740_enum_frame_size,
823 static const struct v4l2_subdev_ops ov2740_subdev_ops = {
824 .video = &ov2740_video_ops,
825 .pad = &ov2740_pad_ops,
828 static const struct media_entity_operations ov2740_subdev_entity_ops = {
829 .link_validate = v4l2_subdev_link_validate,
832 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = {
836 static int ov2740_identify_module(struct ov2740 *ov2740)
838 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
842 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val);
846 if (val != OV2740_CHIP_ID) {
847 dev_err(&client->dev, "chip id mismatch: %x!=%x",
848 OV2740_CHIP_ID, val);
855 static int ov2740_check_hwcfg(struct device *dev)
857 struct fwnode_handle *ep;
858 struct fwnode_handle *fwnode = dev_fwnode(dev);
859 struct v4l2_fwnode_endpoint bus_cfg = {
860 .bus_type = V4L2_MBUS_CSI2_DPHY
869 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
873 if (mclk != OV2740_MCLK) {
874 dev_err(dev, "external clock %d is not supported", mclk);
878 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
882 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
883 fwnode_handle_put(ep);
887 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) {
888 dev_err(dev, "number of CSI2 data lanes %d is not supported",
889 bus_cfg.bus.mipi_csi2.num_data_lanes);
891 goto check_hwcfg_error;
894 if (!bus_cfg.nr_of_link_frequencies) {
895 dev_err(dev, "no link frequencies defined");
897 goto check_hwcfg_error;
900 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
901 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
902 if (link_freq_menu_items[i] ==
903 bus_cfg.link_frequencies[j])
907 if (j == bus_cfg.nr_of_link_frequencies) {
908 dev_err(dev, "no link frequency %lld supported",
909 link_freq_menu_items[i]);
911 goto check_hwcfg_error;
916 v4l2_fwnode_endpoint_free(&bus_cfg);
921 static int ov2740_remove(struct i2c_client *client)
923 struct v4l2_subdev *sd = i2c_get_clientdata(client);
924 struct ov2740 *ov2740 = to_ov2740(sd);
926 v4l2_async_unregister_subdev(sd);
927 media_entity_cleanup(&sd->entity);
928 v4l2_ctrl_handler_free(sd->ctrl_handler);
929 pm_runtime_disable(&client->dev);
930 mutex_destroy(&ov2740->mutex);
935 static int ov2740_load_otp_data(struct i2c_client *client, struct nvm_data *nvm)
937 struct ov2740 *ov2740 = to_ov2740(i2c_get_clientdata(client));
942 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
944 dev_err(&client->dev, "failed to read ISP CTRL00\n");
947 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
949 dev_err(&client->dev, "failed to read ISP CTRL01\n");
953 /* Clear bit 5 of ISP CTRL00 */
954 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
955 isp_ctrl00 & ~BIT(5));
957 dev_err(&client->dev, "failed to write ISP CTRL00\n");
961 /* Clear bit 7 of ISP CTRL01 */
962 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
963 isp_ctrl01 & ~BIT(7));
965 dev_err(&client->dev, "failed to write ISP CTRL01\n");
969 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
970 OV2740_MODE_STREAMING);
972 dev_err(&client->dev, "failed to start streaming\n");
977 * Users are not allowed to access OTP-related registers and memory
978 * during the 20 ms period after streaming starts (0x100 = 0x01).
982 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER,
983 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE);
985 dev_err(&client->dev, "failed to read OTP data, ret %d\n", ret);
989 ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
990 OV2740_MODE_STANDBY);
991 ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
992 ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
998 static int ov2740_nvmem_read(void *priv, unsigned int off, void *val,
1001 struct nvm_data *nvm = priv;
1003 memcpy(val, nvm->nvm_buffer + off, count);
1008 static int ov2740_register_nvmem(struct i2c_client *client)
1010 struct nvm_data *nvm;
1011 struct regmap_config regmap_config = { };
1012 struct nvmem_config nvmem_config = { };
1013 struct regmap *regmap;
1014 struct device *dev = &client->dev;
1017 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL);
1021 nvm->nvm_buffer = devm_kzalloc(dev, CUSTOMER_USE_OTP_SIZE, GFP_KERNEL);
1022 if (!nvm->nvm_buffer)
1025 regmap_config.val_bits = 8;
1026 regmap_config.reg_bits = 16;
1027 regmap_config.disable_locking = true;
1028 regmap = devm_regmap_init_i2c(client, ®map_config);
1030 return PTR_ERR(regmap);
1032 nvm->regmap = regmap;
1034 ret = ov2740_load_otp_data(client, nvm);
1036 dev_err(dev, "failed to load OTP data, ret %d\n", ret);
1040 nvmem_config.name = dev_name(dev);
1041 nvmem_config.dev = dev;
1042 nvmem_config.read_only = true;
1043 nvmem_config.root_only = true;
1044 nvmem_config.owner = THIS_MODULE;
1045 nvmem_config.compat = true;
1046 nvmem_config.base_dev = dev;
1047 nvmem_config.reg_read = ov2740_nvmem_read;
1048 nvmem_config.reg_write = NULL;
1049 nvmem_config.priv = nvm;
1050 nvmem_config.stride = 1;
1051 nvmem_config.word_size = 1;
1052 nvmem_config.size = CUSTOMER_USE_OTP_SIZE;
1054 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config);
1056 return PTR_ERR_OR_ZERO(nvm->nvmem);
1059 static int ov2740_probe(struct i2c_client *client)
1061 struct ov2740 *ov2740;
1064 ret = ov2740_check_hwcfg(&client->dev);
1066 dev_err(&client->dev, "failed to check HW configuration: %d",
1071 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL);
1075 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops);
1076 ret = ov2740_identify_module(ov2740);
1078 dev_err(&client->dev, "failed to find sensor: %d", ret);
1082 mutex_init(&ov2740->mutex);
1083 ov2740->cur_mode = &supported_modes[0];
1084 ret = ov2740_init_controls(ov2740);
1086 dev_err(&client->dev, "failed to init controls: %d", ret);
1087 goto probe_error_v4l2_ctrl_handler_free;
1090 ov2740->sd.internal_ops = &ov2740_internal_ops;
1091 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1092 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops;
1093 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1094 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE;
1095 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad);
1097 dev_err(&client->dev, "failed to init entity pads: %d", ret);
1098 goto probe_error_v4l2_ctrl_handler_free;
1101 ret = v4l2_async_register_subdev_sensor_common(&ov2740->sd);
1103 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
1105 goto probe_error_media_entity_cleanup;
1108 ret = ov2740_register_nvmem(client);
1110 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret);
1113 * Device is already turned on by i2c-core with ACPI domain PM.
1114 * Enable runtime PM and turn off the device.
1116 pm_runtime_set_active(&client->dev);
1117 pm_runtime_enable(&client->dev);
1118 pm_runtime_idle(&client->dev);
1122 probe_error_media_entity_cleanup:
1123 media_entity_cleanup(&ov2740->sd.entity);
1125 probe_error_v4l2_ctrl_handler_free:
1126 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler);
1127 mutex_destroy(&ov2740->mutex);
1132 static const struct dev_pm_ops ov2740_pm_ops = {
1133 SET_SYSTEM_SLEEP_PM_OPS(ov2740_suspend, ov2740_resume)
1136 static const struct acpi_device_id ov2740_acpi_ids[] = {
1141 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids);
1143 static struct i2c_driver ov2740_i2c_driver = {
1146 .pm = &ov2740_pm_ops,
1147 .acpi_match_table = ov2740_acpi_ids,
1149 .probe_new = ov2740_probe,
1150 .remove = ov2740_remove,
1153 module_i2c_driver(ov2740_i2c_driver);
1155 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
1156 MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
1157 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1158 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver");
1159 MODULE_LICENSE("GPL v2");