drivers/media/i2c/ov13b10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2021 Intel Corporation.
   3
   4 #include <linux/acpi.h>
   5 #include <linux/i2c.h>
   6 #include <linux/module.h>
   7 #include <linux/pm_runtime.h>
   8 #include <media/v4l2-ctrls.h>
   9 #include <media/v4l2-device.h>
  10 #include <media/v4l2-fwnode.h>
  11
  12 #define OV13B10_REG_VALUE_08BIT         1
  13 #define OV13B10_REG_VALUE_16BIT         2
  14 #define OV13B10_REG_VALUE_24BIT         3
  15
  16 #define OV13B10_REG_MODE_SELECT         0x0100
  17 #define OV13B10_MODE_STANDBY            0x00
  18 #define OV13B10_MODE_STREAMING          0x01
  19
  20 #define OV13B10_REG_SOFTWARE_RST        0x0103
  21 #define OV13B10_SOFTWARE_RST            0x01
  22
  23 /* Chip ID */
  24 #define OV13B10_REG_CHIP_ID             0x300a
  25 #define OV13B10_CHIP_ID                 0x560d42
  26
  27 /* V_TIMING internal */
  28 #define OV13B10_REG_VTS                 0x380e
  29 #define OV13B10_VTS_30FPS               0x0c7c
  30 #define OV13B10_VTS_60FPS               0x063e
  31 #define OV13B10_VTS_MAX                 0x7fff
  32
  33 /* HBLANK control - read only */
  34 #define OV13B10_PPL_560MHZ              4704
  35
  36 /* Exposure control */
  37 #define OV13B10_REG_EXPOSURE            0x3500
  38 #define OV13B10_EXPOSURE_MIN            4
  39 #define OV13B10_EXPOSURE_STEP           1
  40 #define OV13B10_EXPOSURE_DEFAULT        0x40
  41
  42 /* Analog gain control */
  43 #define OV13B10_REG_ANALOG_GAIN         0x3508
  44 #define OV13B10_ANA_GAIN_MIN            0x80
  45 #define OV13B10_ANA_GAIN_MAX            0x07c0
  46 #define OV13B10_ANA_GAIN_STEP           1
  47 #define OV13B10_ANA_GAIN_DEFAULT        0x80
  48
  49 /* Digital gain control */
  50 #define OV13B10_REG_DGTL_GAIN_H         0x350a
  51 #define OV13B10_REG_DGTL_GAIN_M         0x350b
  52 #define OV13B10_REG_DGTL_GAIN_L         0x350c
  53
  54 #define OV13B10_DGTL_GAIN_MIN           1024         /* Min = 1 X */
  55 #define OV13B10_DGTL_GAIN_MAX           (4096 - 1)   /* Max = 4 X */
  56 #define OV13B10_DGTL_GAIN_DEFAULT       2560         /* Default gain = 2.5 X */
  57 #define OV13B10_DGTL_GAIN_STEP          1            /* Each step = 1/1024 */
  58
  59 #define OV13B10_DGTL_GAIN_L_SHIFT       6
  60 #define OV13B10_DGTL_GAIN_L_MASK        0x3
  61 #define OV13B10_DGTL_GAIN_M_SHIFT       2
  62 #define OV13B10_DGTL_GAIN_M_MASK        0xff
  63 #define OV13B10_DGTL_GAIN_H_SHIFT       10
  64 #define OV13B10_DGTL_GAIN_H_MASK        0x3
  65
  66 /* Test Pattern Control */
  67 #define OV13B10_REG_TEST_PATTERN        0x5080
  68 #define OV13B10_TEST_PATTERN_ENABLE     BIT(7)
  69 #define OV13B10_TEST_PATTERN_MASK       0xf3
  70 #define OV13B10_TEST_PATTERN_BAR_SHIFT  2
  71
  72 /* Flip Control */
  73 #define OV13B10_REG_FORMAT1             0x3820
  74 #define OV13B10_REG_FORMAT2             0x3821
  75
  76 /* Horizontal Window Offset */
  77 #define OV13B10_REG_H_WIN_OFFSET        0x3811
  78
  79 /* Vertical Window Offset */
  80 #define OV13B10_REG_V_WIN_OFFSET        0x3813
  81
  82 struct ov13b10_reg {
  83         u16 address;
  84         u8 val;
  85 };
  86
  87 struct ov13b10_reg_list {
  88         u32 num_of_regs;
  89         const struct ov13b10_reg *regs;
  90 };
  91
  92 /* Link frequency config */
  93 struct ov13b10_link_freq_config {
  94         u32 pixels_per_line;
  95
  96         /* registers for this link frequency */
  97         struct ov13b10_reg_list reg_list;
  98 };
  99
 100 /* Mode : resolution and related config&values */
 101 struct ov13b10_mode {
 102         /* Frame width */
 103         u32 width;
 104         /* Frame height */
 105         u32 height;
 106
 107         /* V-timing */
 108         u32 vts_def;
 109         u32 vts_min;
 110
 111         /* Index of Link frequency config to be used */
 112         u32 link_freq_index;
 113         /* Default register values */
 114         struct ov13b10_reg_list reg_list;
 115 };
 116
 117 /* 4208x3120 needs 1120Mbps/lane, 4 lanes */
 118 static const struct ov13b10_reg mipi_data_rate_1120mbps[] = {
 119         {0x0103, 0x01},
 120         {0x0303, 0x04},
 121         {0x0305, 0xaf},
 122         {0x0321, 0x00},
 123         {0x0323, 0x04},
 124         {0x0324, 0x01},
 125         {0x0325, 0xa4},
 126         {0x0326, 0x81},
 127         {0x0327, 0x04},
 128         {0x3012, 0x07},
 129         {0x3013, 0x32},
 130         {0x3107, 0x23},
 131         {0x3501, 0x0c},
 132         {0x3502, 0x10},
 133         {0x3504, 0x08},
 134         {0x3508, 0x07},
 135         {0x3509, 0xc0},
 136         {0x3600, 0x16},
 137         {0x3601, 0x54},
 138         {0x3612, 0x4e},
 139         {0x3620, 0x00},
 140         {0x3621, 0x68},
 141         {0x3622, 0x66},
 142         {0x3623, 0x03},
 143         {0x3662, 0x92},
 144         {0x3666, 0xbb},
 145         {0x3667, 0x44},
 146         {0x366e, 0xff},
 147         {0x366f, 0xf3},
 148         {0x3675, 0x44},
 149         {0x3676, 0x00},
 150         {0x367f, 0xe9},
 151         {0x3681, 0x32},
 152         {0x3682, 0x1f},
 153         {0x3683, 0x0b},
 154         {0x3684, 0x0b},
 155         {0x3704, 0x0f},
 156         {0x3706, 0x40},
 157         {0x3708, 0x3b},
 158         {0x3709, 0x72},
 159         {0x370b, 0xa2},
 160         {0x3714, 0x24},
 161         {0x371a, 0x3e},
 162         {0x3725, 0x42},
 163         {0x3739, 0x12},
 164         {0x3767, 0x00},
 165         {0x377a, 0x0d},
 166         {0x3789, 0x18},
 167         {0x3790, 0x40},
 168         {0x3791, 0xa2},
 169         {0x37c2, 0x04},
 170         {0x37c3, 0xf1},
 171         {0x37d9, 0x0c},
 172         {0x37da, 0x02},
 173         {0x37dc, 0x02},
 174         {0x37e1, 0x04},
 175         {0x37e2, 0x0a},
 176         {0x3800, 0x00},
 177         {0x3801, 0x00},
 178         {0x3802, 0x00},
 179         {0x3803, 0x08},
 180         {0x3804, 0x10},
 181         {0x3805, 0x8f},
 182         {0x3806, 0x0c},
 183         {0x3807, 0x47},
 184         {0x3808, 0x10},
 185         {0x3809, 0x70},
 186         {0x380a, 0x0c},
 187         {0x380b, 0x30},
 188         {0x380c, 0x04},
 189         {0x380d, 0x98},
 190         {0x380e, 0x0c},
 191         {0x380f, 0x7c},
 192         {0x3811, 0x0f},
 193         {0x3813, 0x09},
 194         {0x3814, 0x01},
 195         {0x3815, 0x01},
 196         {0x3816, 0x01},
 197         {0x3817, 0x01},
 198         {0x381f, 0x08},
 199         {0x3820, 0x88},
 200         {0x3821, 0x00},
 201         {0x3822, 0x14},
 202         {0x382e, 0xe6},
 203         {0x3c80, 0x00},
 204         {0x3c87, 0x01},
 205         {0x3c8c, 0x19},
 206         {0x3c8d, 0x1c},
 207         {0x3ca0, 0x00},
 208         {0x3ca1, 0x00},
 209         {0x3ca2, 0x00},
 210         {0x3ca3, 0x00},
 211         {0x3ca4, 0x50},
 212         {0x3ca5, 0x11},
 213         {0x3ca6, 0x01},
 214         {0x3ca7, 0x00},
 215         {0x3ca8, 0x00},
 216         {0x4008, 0x02},
 217         {0x4009, 0x0f},
 218         {0x400a, 0x01},
 219         {0x400b, 0x19},
 220         {0x4011, 0x21},
 221         {0x4017, 0x08},
 222         {0x4019, 0x04},
 223         {0x401a, 0x58},
 224         {0x4032, 0x1e},
 225         {0x4050, 0x02},
 226         {0x4051, 0x09},
 227         {0x405e, 0x00},
 228         {0x4066, 0x02},
 229         {0x4501, 0x00},
 230         {0x4502, 0x10},
 231         {0x4505, 0x00},
 232         {0x4800, 0x64},
 233         {0x481b, 0x3e},
 234         {0x481f, 0x30},
 235         {0x4825, 0x34},
 236         {0x4837, 0x0e},
 237         {0x484b, 0x01},
 238         {0x4883, 0x02},
 239         {0x5000, 0xff},
 240         {0x5001, 0x0f},
 241         {0x5045, 0x20},
 242         {0x5046, 0x20},
 243         {0x5047, 0xa4},
 244         {0x5048, 0x20},
 245         {0x5049, 0xa4},
 246         {0x0100, 0x01},
 247 };
 248
 249 static const struct ov13b10_reg mode_4208x3120_regs[] = {
 250         {0x0305, 0xaf},
 251         {0x3501, 0x0c},
 252         {0x3662, 0x92},
 253         {0x3714, 0x24},
 254         {0x3739, 0x12},
 255         {0x37c2, 0x04},
 256         {0x37d9, 0x0c},
 257         {0x37e2, 0x0a},
 258         {0x3800, 0x00},
 259         {0x3801, 0x00},
 260         {0x3802, 0x00},
 261         {0x3803, 0x08},
 262         {0x3804, 0x10},
 263         {0x3805, 0x8f},
 264         {0x3806, 0x0c},
 265         {0x3807, 0x47},
 266         {0x3808, 0x10},
 267         {0x3809, 0x70},
 268         {0x380a, 0x0c},
 269         {0x380b, 0x30},
 270         {0x380c, 0x04},
 271         {0x380d, 0x98},
 272         {0x380e, 0x0c},
 273         {0x380f, 0x7c},
 274         {0x3810, 0x00},
 275         {0x3811, 0x0f},
 276         {0x3812, 0x00},
 277         {0x3813, 0x09},
 278         {0x3814, 0x01},
 279         {0x3816, 0x01},
 280         {0x3820, 0x88},
 281         {0x3c8c, 0x19},
 282         {0x4008, 0x02},
 283         {0x4009, 0x0f},
 284         {0x4050, 0x02},
 285         {0x4051, 0x09},
 286         {0x4501, 0x00},
 287         {0x4505, 0x00},
 288         {0x4837, 0x0e},
 289         {0x5000, 0xff},
 290         {0x5001, 0x0f},
 291 };
 292
 293 static const struct ov13b10_reg mode_4160x3120_regs[] = {
 294         {0x0305, 0xaf},
 295         {0x3501, 0x0c},
 296         {0x3662, 0x92},
 297         {0x3714, 0x24},
 298         {0x3739, 0x12},
 299         {0x37c2, 0x04},
 300         {0x37d9, 0x0c},
 301         {0x37e2, 0x0a},
 302         {0x3800, 0x00},
 303         {0x3801, 0x00},
 304         {0x3802, 0x00},
 305         {0x3803, 0x08},
 306         {0x3804, 0x10},
 307         {0x3805, 0x8f},
 308         {0x3806, 0x0c},
 309         {0x3807, 0x47},
 310         {0x3808, 0x10},
 311         {0x3809, 0x40},
 312         {0x380a, 0x0c},
 313         {0x380b, 0x30},
 314         {0x380c, 0x04},
 315         {0x380d, 0x98},
 316         {0x380e, 0x0c},
 317         {0x380f, 0x7c},
 318         {0x3810, 0x00},
 319         {0x3811, 0x27},
 320         {0x3812, 0x00},
 321         {0x3813, 0x09},
 322         {0x3814, 0x01},
 323         {0x3816, 0x01},
 324         {0x3820, 0x88},
 325         {0x3c8c, 0x19},
 326         {0x4008, 0x02},
 327         {0x4009, 0x0f},
 328         {0x4050, 0x02},
 329         {0x4051, 0x09},
 330         {0x4501, 0x00},
 331         {0x4505, 0x00},
 332         {0x4837, 0x0e},
 333         {0x5000, 0xff},
 334         {0x5001, 0x0f},
 335 };
 336
 337 static const struct ov13b10_reg mode_4160x2340_regs[] = {
 338         {0x0305, 0xaf},
 339         {0x3501, 0x0c},
 340         {0x3662, 0x92},
 341         {0x3714, 0x24},
 342         {0x3739, 0x12},
 343         {0x37c2, 0x04},
 344         {0x37d9, 0x0c},
 345         {0x37e2, 0x0a},
 346         {0x3800, 0x00},
 347         {0x3801, 0x00},
 348         {0x3802, 0x00},
 349         {0x3803, 0x08},
 350         {0x3804, 0x10},
 351         {0x3805, 0x8f},
 352         {0x3806, 0x0c},
 353         {0x3807, 0x47},
 354         {0x3808, 0x10},
 355         {0x3809, 0x40},
 356         {0x380a, 0x09},
 357         {0x380b, 0x24},
 358         {0x380c, 0x04},
 359         {0x380d, 0x98},
 360         {0x380e, 0x0c},
 361         {0x380f, 0x7c},
 362         {0x3810, 0x00},
 363         {0x3811, 0x27},
 364         {0x3812, 0x01},
 365         {0x3813, 0x8f},
 366         {0x3814, 0x01},
 367         {0x3816, 0x01},
 368         {0x3820, 0x88},
 369         {0x3c8c, 0x19},
 370         {0x4008, 0x02},
 371         {0x4009, 0x0f},
 372         {0x4050, 0x02},
 373         {0x4051, 0x09},
 374         {0x4501, 0x00},
 375         {0x4505, 0x00},
 376         {0x4837, 0x0e},
 377         {0x5000, 0xff},
 378         {0x5001, 0x0f},
 379 };
 380
 381 static const struct ov13b10_reg mode_2104x1560_regs[] = {
 382         {0x0305, 0xaf},
 383         {0x3501, 0x06},
 384         {0x3662, 0x88},
 385         {0x3714, 0x28},
 386         {0x3739, 0x10},
 387         {0x37c2, 0x14},
 388         {0x37d9, 0x06},
 389         {0x37e2, 0x0c},
 390         {0x3800, 0x00},
 391         {0x3801, 0x00},
 392         {0x3802, 0x00},
 393         {0x3803, 0x08},
 394         {0x3804, 0x10},
 395         {0x3805, 0x8f},
 396         {0x3806, 0x0c},
 397         {0x3807, 0x47},
 398         {0x3808, 0x08},
 399         {0x3809, 0x38},
 400         {0x380a, 0x06},
 401         {0x380b, 0x18},
 402         {0x380c, 0x04},
 403         {0x380d, 0x98},
 404         {0x380e, 0x06},
 405         {0x380f, 0x3e},
 406         {0x3810, 0x00},
 407         {0x3811, 0x07},
 408         {0x3812, 0x00},
 409         {0x3813, 0x05},
 410         {0x3814, 0x03},
 411         {0x3816, 0x03},
 412         {0x3820, 0x8b},
 413         {0x3c8c, 0x18},
 414         {0x4008, 0x00},
 415         {0x4009, 0x05},
 416         {0x4050, 0x00},
 417         {0x4051, 0x05},
 418         {0x4501, 0x08},
 419         {0x4505, 0x00},
 420         {0x4837, 0x0e},
 421         {0x5000, 0xfd},
 422         {0x5001, 0x0d},
 423 };
 424
 425 static const struct ov13b10_reg mode_2080x1170_regs[] = {
 426         {0x0305, 0xaf},
 427         {0x3501, 0x06},
 428         {0x3662, 0x88},
 429         {0x3714, 0x28},
 430         {0x3739, 0x10},
 431         {0x37c2, 0x14},
 432         {0x37d9, 0x06},
 433         {0x37e2, 0x0c},
 434         {0x3800, 0x00},
 435         {0x3801, 0x00},
 436         {0x3802, 0x00},
 437         {0x3803, 0x08},
 438         {0x3804, 0x10},
 439         {0x3805, 0x8f},
 440         {0x3806, 0x0c},
 441         {0x3807, 0x47},
 442         {0x3808, 0x08},
 443         {0x3809, 0x20},
 444         {0x380a, 0x04},
 445         {0x380b, 0x92},
 446         {0x380c, 0x04},
 447         {0x380d, 0x98},
 448         {0x380e, 0x06},
 449         {0x380f, 0x3e},
 450         {0x3810, 0x00},
 451         {0x3811, 0x13},
 452         {0x3812, 0x00},
 453         {0x3813, 0xc9},
 454         {0x3814, 0x03},
 455         {0x3816, 0x03},
 456         {0x3820, 0x8b},
 457         {0x3c8c, 0x18},
 458         {0x4008, 0x00},
 459         {0x4009, 0x05},
 460         {0x4050, 0x00},
 461         {0x4051, 0x05},
 462         {0x4501, 0x08},
 463         {0x4505, 0x00},
 464         {0x4837, 0x0e},
 465         {0x5000, 0xfd},
 466         {0x5001, 0x0d},
 467 };
 468
 469 static const char * const ov13b10_test_pattern_menu[] = {
 470         "Disabled",
 471         "Vertical Color Bar Type 1",
 472         "Vertical Color Bar Type 2",
 473         "Vertical Color Bar Type 3",
 474         "Vertical Color Bar Type 4"
 475 };
 476
 477 /* Configurations for supported link frequencies */
 478 #define OV13B10_LINK_FREQ_560MHZ        560000000ULL
 479 #define OV13B10_LINK_FREQ_INDEX_0       0
 480
 481 #define OV13B10_EXT_CLK                 19200000
 482 #define OV13B10_DATA_LANES              4
 483
 484 /*
 485  * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
 486  * data rate => double data rate; number of lanes => 4; bits per pixel => 10
 487  */
 488 static u64 link_freq_to_pixel_rate(u64 f)
 489 {
 490         f *= 2 * OV13B10_DATA_LANES;
 491         do_div(f, 10);
 492
 493         return f;
 494 }
 495
 496 /* Menu items for LINK_FREQ V4L2 control */
 497 static const s64 link_freq_menu_items[] = {
 498         OV13B10_LINK_FREQ_560MHZ
 499 };
 500
 501 /* Link frequency configs */
 502 static const struct ov13b10_link_freq_config
 503                         link_freq_configs[] = {
 504         {
 505                 .pixels_per_line = OV13B10_PPL_560MHZ,
 506                 .reg_list = {
 507                         .num_of_regs = ARRAY_SIZE(mipi_data_rate_1120mbps),
 508                         .regs = mipi_data_rate_1120mbps,
 509                 }
 510         }
 511 };
 512
 513 /* Mode configs */
 514 static const struct ov13b10_mode supported_modes[] = {
 515         {
 516                 .width = 4208,
 517                 .height = 3120,
 518                 .vts_def = OV13B10_VTS_30FPS,
 519                 .vts_min = OV13B10_VTS_30FPS,
 520                 .reg_list = {
 521                         .num_of_regs = ARRAY_SIZE(mode_4208x3120_regs),
 522                         .regs = mode_4208x3120_regs,
 523                 },
 524                 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
 525         },
 526         {
 527                 .width = 4160,
 528                 .height = 3120,
 529                 .vts_def = OV13B10_VTS_30FPS,
 530                 .vts_min = OV13B10_VTS_30FPS,
 531                 .reg_list = {
 532                         .num_of_regs = ARRAY_SIZE(mode_4160x3120_regs),
 533                         .regs = mode_4160x3120_regs,
 534                 },
 535                 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
 536         },
 537         {
 538                 .width = 4160,
 539                 .height = 2340,
 540                 .vts_def = OV13B10_VTS_30FPS,
 541                 .vts_min = OV13B10_VTS_30FPS,
 542                 .reg_list = {
 543                         .num_of_regs = ARRAY_SIZE(mode_4160x2340_regs),
 544                         .regs = mode_4160x2340_regs,
 545                 },
 546                 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
 547         },
 548         {
 549                 .width = 2104,
 550                 .height = 1560,
 551                 .vts_def = OV13B10_VTS_60FPS,
 552                 .vts_min = OV13B10_VTS_60FPS,
 553                 .reg_list = {
 554                         .num_of_regs = ARRAY_SIZE(mode_2104x1560_regs),
 555                         .regs = mode_2104x1560_regs,
 556                 },
 557                 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
 558         },
 559         {
 560                 .width = 2080,
 561                 .height = 1170,
 562                 .vts_def = OV13B10_VTS_60FPS,
 563                 .vts_min = OV13B10_VTS_60FPS,
 564                 .reg_list = {
 565                         .num_of_regs = ARRAY_SIZE(mode_2080x1170_regs),
 566                         .regs = mode_2080x1170_regs,
 567                 },
 568                 .link_freq_index = OV13B10_LINK_FREQ_INDEX_0,
 569         }
 570 };
 571
 572 struct ov13b10 {
 573         struct v4l2_subdev sd;
 574         struct media_pad pad;
 575
 576         struct v4l2_ctrl_handler ctrl_handler;
 577         /* V4L2 Controls */
 578         struct v4l2_ctrl *link_freq;
 579         struct v4l2_ctrl *pixel_rate;
 580         struct v4l2_ctrl *vblank;
 581         struct v4l2_ctrl *hblank;
 582         struct v4l2_ctrl *exposure;
 583
 584         /* Current mode */
 585         const struct ov13b10_mode *cur_mode;
 586
 587         /* Mutex for serialized access */
 588         struct mutex mutex;
 589
 590         /* Streaming on/off */
 591         bool streaming;
 592
 593         /* True if the device has been identified */
 594         bool identified;
 595 };
 596
 597 #define to_ov13b10(_sd) container_of(_sd, struct ov13b10, sd)
 598
 599 /* Read registers up to 4 at a time */
 600 static int ov13b10_read_reg(struct ov13b10 *ov13b,
 601                             u16 reg, u32 len, u32 *val)
 602 {
 603         struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
 604         struct i2c_msg msgs[2];
 605         u8 *data_be_p;
 606         int ret;
 607         __be32 data_be = 0;
 608         __be16 reg_addr_be = cpu_to_be16(reg);
 609
 610         if (len > 4)
 611                 return -EINVAL;
 612
 613         data_be_p = (u8 *)&data_be;
 614         /* Write register address */
 615         msgs[0].addr = client->addr;
 616         msgs[0].flags = 0;
 617         msgs[0].len = 2;
 618         msgs[0].buf = (u8 *)&reg_addr_be;
 619
 620         /* Read data from register */
 621         msgs[1].addr = client->addr;
 622         msgs[1].flags = I2C_M_RD;
 623         msgs[1].len = len;
 624         msgs[1].buf = &data_be_p[4 - len];
 625
 626         ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
 627         if (ret != ARRAY_SIZE(msgs))
 628                 return -EIO;
 629
 630         *val = be32_to_cpu(data_be);
 631
 632         return 0;
 633 }
 634
 635 /* Write registers up to 4 at a time */
 636 static int ov13b10_write_reg(struct ov13b10 *ov13b,
 637                              u16 reg, u32 len, u32 __val)
 638 {
 639         struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
 640         int buf_i, val_i;
 641         u8 buf[6], *val_p;
 642         __be32 val;
 643
 644         if (len > 4)
 645                 return -EINVAL;
 646
 647         buf[0] = reg >> 8;
 648         buf[1] = reg & 0xff;
 649
 650         val = cpu_to_be32(__val);
 651         val_p = (u8 *)&val;
 652         buf_i = 2;
 653         val_i = 4 - len;
 654
 655         while (val_i < 4)
 656                 buf[buf_i++] = val_p[val_i++];
 657
 658         if (i2c_master_send(client, buf, len + 2) != len + 2)
 659                 return -EIO;
 660
 661         return 0;
 662 }
 663
 664 /* Write a list of registers */
 665 static int ov13b10_write_regs(struct ov13b10 *ov13b,
 666                               const struct ov13b10_reg *regs, u32 len)
 667 {
 668         struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
 669         int ret;
 670         u32 i;
 671
 672         for (i = 0; i < len; i++) {
 673                 ret = ov13b10_write_reg(ov13b, regs[i].address, 1,
 674                                         regs[i].val);
 675                 if (ret) {
 676                         dev_err_ratelimited(&client->dev,
 677                                             "Failed to write reg 0x%4.4x. error = %d\n",
 678                                             regs[i].address, ret);
 679
 680                         return ret;
 681                 }
 682         }
 683
 684         return 0;
 685 }
 686
 687 static int ov13b10_write_reg_list(struct ov13b10 *ov13b,
 688                                   const struct ov13b10_reg_list *r_list)
 689 {
 690         return ov13b10_write_regs(ov13b, r_list->regs, r_list->num_of_regs);
 691 }
 692
 693 /* Open sub-device */
 694 static int ov13b10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
 695 {
 696         const struct ov13b10_mode *default_mode = &supported_modes[0];
 697         struct ov13b10 *ov13b = to_ov13b10(sd);
 698         struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,
 699                                                                         fh->state,
 700                                                                         0);
 701
 702         mutex_lock(&ov13b->mutex);
 703
 704         /* Initialize try_fmt */
 705         try_fmt->width = default_mode->width;
 706         try_fmt->height = default_mode->height;
 707         try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
 708         try_fmt->field = V4L2_FIELD_NONE;
 709
 710         /* No crop or compose */
 711         mutex_unlock(&ov13b->mutex);
 712
 713         return 0;
 714 }
 715
 716 static int ov13b10_update_digital_gain(struct ov13b10 *ov13b, u32 d_gain)
 717 {
 718         int ret;
 719         u32 val;
 720
 721         /*
 722          * 0x350C[7:6], 0x350B[7:0], 0x350A[1:0]
 723          */
 724
 725         val = (d_gain & OV13B10_DGTL_GAIN_L_MASK) << OV13B10_DGTL_GAIN_L_SHIFT;
 726         ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_L,
 727                                 OV13B10_REG_VALUE_08BIT, val);
 728         if (ret)
 729                 return ret;
 730
 731         val = (d_gain >> OV13B10_DGTL_GAIN_M_SHIFT) & OV13B10_DGTL_GAIN_M_MASK;
 732         ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_M,
 733                                 OV13B10_REG_VALUE_08BIT, val);
 734         if (ret)
 735                 return ret;
 736
 737         val = (d_gain >> OV13B10_DGTL_GAIN_H_SHIFT) & OV13B10_DGTL_GAIN_H_MASK;
 738         ret = ov13b10_write_reg(ov13b, OV13B10_REG_DGTL_GAIN_H,
 739                                 OV13B10_REG_VALUE_08BIT, val);
 740
 741         return ret;
 742 }
 743
 744 static int ov13b10_enable_test_pattern(struct ov13b10 *ov13b, u32 pattern)
 745 {
 746         int ret;
 747         u32 val;
 748
 749         ret = ov13b10_read_reg(ov13b, OV13B10_REG_TEST_PATTERN,
 750                                OV13B10_REG_VALUE_08BIT, &val);
 751         if (ret)
 752                 return ret;
 753
 754         if (pattern) {
 755                 val &= OV13B10_TEST_PATTERN_MASK;
 756                 val |= ((pattern - 1) << OV13B10_TEST_PATTERN_BAR_SHIFT) |
 757                      OV13B10_TEST_PATTERN_ENABLE;
 758         } else {
 759                 val &= ~OV13B10_TEST_PATTERN_ENABLE;
 760         }
 761
 762         return ov13b10_write_reg(ov13b, OV13B10_REG_TEST_PATTERN,
 763                                  OV13B10_REG_VALUE_08BIT, val);
 764 }
 765
 766 static int ov13b10_set_ctrl_hflip(struct ov13b10 *ov13b, u32 ctrl_val)
 767 {
 768         int ret;
 769         u32 val;
 770
 771         ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1,
 772                                OV13B10_REG_VALUE_08BIT, &val);
 773         if (ret)
 774                 return ret;
 775
 776         ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1,
 777                                 OV13B10_REG_VALUE_08BIT,
 778                                 ctrl_val ? val & ~BIT(3) : val);
 779
 780         if (ret)
 781                 return ret;
 782
 783         ret = ov13b10_read_reg(ov13b, OV13B10_REG_H_WIN_OFFSET,
 784                                OV13B10_REG_VALUE_08BIT, &val);
 785         if (ret)
 786                 return ret;
 787
 788         /*
 789          * Applying cropping offset to reverse the change of Bayer order
 790          * after mirroring image
 791          */
 792         return ov13b10_write_reg(ov13b, OV13B10_REG_H_WIN_OFFSET,
 793                                  OV13B10_REG_VALUE_08BIT,
 794                                  ctrl_val ? ++val : val);
 795 }
 796
 797 static int ov13b10_set_ctrl_vflip(struct ov13b10 *ov13b, u32 ctrl_val)
 798 {
 799         int ret;
 800         u32 val;
 801
 802         ret = ov13b10_read_reg(ov13b, OV13B10_REG_FORMAT1,
 803                                OV13B10_REG_VALUE_08BIT, &val);
 804         if (ret)
 805                 return ret;
 806
 807         ret = ov13b10_write_reg(ov13b, OV13B10_REG_FORMAT1,
 808                                 OV13B10_REG_VALUE_08BIT,
 809                                 ctrl_val ? val | BIT(4) | BIT(5)  : val);
 810
 811         if (ret)
 812                 return ret;
 813
 814         ret = ov13b10_read_reg(ov13b, OV13B10_REG_V_WIN_OFFSET,
 815                                OV13B10_REG_VALUE_08BIT, &val);
 816         if (ret)
 817                 return ret;
 818
 819         /*
 820          * Applying cropping offset to reverse the change of Bayer order
 821          * after flipping image
 822          */
 823         return ov13b10_write_reg(ov13b, OV13B10_REG_V_WIN_OFFSET,
 824                                  OV13B10_REG_VALUE_08BIT,
 825                                  ctrl_val ? --val : val);
 826 }
 827
 828 static int ov13b10_set_ctrl(struct v4l2_ctrl *ctrl)
 829 {
 830         struct ov13b10 *ov13b = container_of(ctrl->handler,
 831                                              struct ov13b10, ctrl_handler);
 832         struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
 833         s64 max;
 834         int ret;
 835
 836         /* Propagate change of current control to all related controls */
 837         switch (ctrl->id) {
 838         case V4L2_CID_VBLANK:
 839                 /* Update max exposure while meeting expected vblanking */
 840                 max = ov13b->cur_mode->height + ctrl->val - 8;
 841                 __v4l2_ctrl_modify_range(ov13b->exposure,
 842                                          ov13b->exposure->minimum,
 843                                          max, ov13b->exposure->step, max);
 844                 break;
 845         }
 846
 847         /*
 848          * Applying V4L2 control value only happens
 849          * when power is up for streaming
 850          */
 851         if (!pm_runtime_get_if_in_use(&client->dev))
 852                 return 0;
 853
 854         ret = 0;
 855         switch (ctrl->id) {
 856         case V4L2_CID_ANALOGUE_GAIN:
 857                 ret = ov13b10_write_reg(ov13b, OV13B10_REG_ANALOG_GAIN,
 858                                         OV13B10_REG_VALUE_16BIT,
 859                                         ctrl->val << 1);
 860                 break;
 861         case V4L2_CID_DIGITAL_GAIN:
 862                 ret = ov13b10_update_digital_gain(ov13b, ctrl->val);
 863                 break;
 864         case V4L2_CID_EXPOSURE:
 865                 ret = ov13b10_write_reg(ov13b, OV13B10_REG_EXPOSURE,
 866                                         OV13B10_REG_VALUE_24BIT,
 867                                         ctrl->val);
 868                 break;
 869         case V4L2_CID_VBLANK:
 870                 ret = ov13b10_write_reg(ov13b, OV13B10_REG_VTS,
 871                                         OV13B10_REG_VALUE_16BIT,
 872                                         ov13b->cur_mode->height
 873                                         + ctrl->val);
 874                 break;
 875         case V4L2_CID_TEST_PATTERN:
 876                 ret = ov13b10_enable_test_pattern(ov13b, ctrl->val);
 877                 break;
 878         case V4L2_CID_HFLIP:
 879                 ov13b10_set_ctrl_hflip(ov13b, ctrl->val);
 880                 break;
 881         case V4L2_CID_VFLIP:
 882                 ov13b10_set_ctrl_vflip(ov13b, ctrl->val);
 883                 break;
 884         default:
 885                 dev_info(&client->dev,
 886                          "ctrl(id:0x%x,val:0x%x) is not handled\n",
 887                          ctrl->id, ctrl->val);
 888                 break;
 889         }
 890
 891         pm_runtime_put(&client->dev);
 892
 893         return ret;
 894 }
 895
 896 static const struct v4l2_ctrl_ops ov13b10_ctrl_ops = {
 897         .s_ctrl = ov13b10_set_ctrl,
 898 };
 899
 900 static int ov13b10_enum_mbus_code(struct v4l2_subdev *sd,
 901                                   struct v4l2_subdev_state *sd_state,
 902                                   struct v4l2_subdev_mbus_code_enum *code)
 903 {
 904         /* Only one bayer order(GRBG) is supported */
 905         if (code->index > 0)
 906                 return -EINVAL;
 907
 908         code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
 909
 910         return 0;
 911 }
 912
 913 static int ov13b10_enum_frame_size(struct v4l2_subdev *sd,
 914                                    struct v4l2_subdev_state *sd_state,
 915                                    struct v4l2_subdev_frame_size_enum *fse)
 916 {
 917         if (fse->index >= ARRAY_SIZE(supported_modes))
 918                 return -EINVAL;
 919
 920         if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
 921                 return -EINVAL;
 922
 923         fse->min_width = supported_modes[fse->index].width;
 924         fse->max_width = fse->min_width;
 925         fse->min_height = supported_modes[fse->index].height;
 926         fse->max_height = fse->min_height;
 927
 928         return 0;
 929 }
 930
 931 static void ov13b10_update_pad_format(const struct ov13b10_mode *mode,
 932                                       struct v4l2_subdev_format *fmt)
 933 {
 934         fmt->format.width = mode->width;
 935         fmt->format.height = mode->height;
 936         fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
 937         fmt->format.field = V4L2_FIELD_NONE;
 938 }
 939
 940 static int ov13b10_do_get_pad_format(struct ov13b10 *ov13b,
 941                                      struct v4l2_subdev_state *sd_state,
 942                                      struct v4l2_subdev_format *fmt)
 943 {
 944         struct v4l2_mbus_framefmt *framefmt;
 945         struct v4l2_subdev *sd = &ov13b->sd;
 946
 947         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
 948                 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
 949                 fmt->format = *framefmt;
 950         } else {
 951                 ov13b10_update_pad_format(ov13b->cur_mode, fmt);
 952         }
 953
 954         return 0;
 955 }
 956
 957 static int ov13b10_get_pad_format(struct v4l2_subdev *sd,
 958                                   struct v4l2_subdev_state *sd_state,
 959                                   struct v4l2_subdev_format *fmt)
 960 {
 961         struct ov13b10 *ov13b = to_ov13b10(sd);
 962         int ret;
 963
 964         mutex_lock(&ov13b->mutex);
 965         ret = ov13b10_do_get_pad_format(ov13b, sd_state, fmt);
 966         mutex_unlock(&ov13b->mutex);
 967
 968         return ret;
 969 }
 970
 971 static int
 972 ov13b10_set_pad_format(struct v4l2_subdev *sd,
 973                        struct v4l2_subdev_state *sd_state,
 974                        struct v4l2_subdev_format *fmt)
 975 {
 976         struct ov13b10 *ov13b = to_ov13b10(sd);
 977         const struct ov13b10_mode *mode;
 978         struct v4l2_mbus_framefmt *framefmt;
 979         s32 vblank_def;
 980         s32 vblank_min;
 981         s64 h_blank;
 982         s64 pixel_rate;
 983         s64 link_freq;
 984
 985         mutex_lock(&ov13b->mutex);
 986
 987         /* Only one raw bayer(GRBG) order is supported */
 988         if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
 989                 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
 990
 991         mode = v4l2_find_nearest_size(supported_modes,
 992                                       ARRAY_SIZE(supported_modes),
 993                                       width, height,
 994                                       fmt->format.width, fmt->format.height);
 995         ov13b10_update_pad_format(mode, fmt);
 996         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
 997                 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
 998                 *framefmt = fmt->format;
 999         } else {
1000                 ov13b->cur_mode = mode;
1001                 __v4l2_ctrl_s_ctrl(ov13b->link_freq, mode->link_freq_index);
1002                 link_freq = link_freq_menu_items[mode->link_freq_index];
1003                 pixel_rate = link_freq_to_pixel_rate(link_freq);
1004                 __v4l2_ctrl_s_ctrl_int64(ov13b->pixel_rate, pixel_rate);
1005
1006                 /* Update limits and set FPS to default */
1007                 vblank_def = ov13b->cur_mode->vts_def -
1008                              ov13b->cur_mode->height;
1009                 vblank_min = ov13b->cur_mode->vts_min -
1010                              ov13b->cur_mode->height;
1011                 __v4l2_ctrl_modify_range(ov13b->vblank, vblank_min,
1012                                          OV13B10_VTS_MAX
1013                                          - ov13b->cur_mode->height,
1014                                          1,
1015                                          vblank_def);
1016                 __v4l2_ctrl_s_ctrl(ov13b->vblank, vblank_def);
1017                 h_blank =
1018                         link_freq_configs[mode->link_freq_index].pixels_per_line
1019                          - ov13b->cur_mode->width;
1020                 __v4l2_ctrl_modify_range(ov13b->hblank, h_blank,
1021                                          h_blank, 1, h_blank);
1022         }
1023
1024         mutex_unlock(&ov13b->mutex);
1025
1026         return 0;
1027 }
1028
1029 /* Verify chip ID */
1030 static int ov13b10_identify_module(struct ov13b10 *ov13b)
1031 {
1032         struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1033         int ret;
1034         u32 val;
1035
1036         if (ov13b->identified)
1037                 return 0;
1038
1039         ret = ov13b10_read_reg(ov13b, OV13B10_REG_CHIP_ID,
1040                                OV13B10_REG_VALUE_24BIT, &val);
1041         if (ret)
1042                 return ret;
1043
1044         if (val != OV13B10_CHIP_ID) {
1045                 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1046                         OV13B10_CHIP_ID, val);
1047                 return -EIO;
1048         }
1049
1050         ov13b->identified = true;
1051
1052         return 0;
1053 }
1054
1055 static int ov13b10_start_streaming(struct ov13b10 *ov13b)
1056 {
1057         struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1058         const struct ov13b10_reg_list *reg_list;
1059         int ret, link_freq_index;
1060
1061         ret = ov13b10_identify_module(ov13b);
1062         if (ret)
1063                 return ret;
1064
1065         /* Get out of from software reset */
1066         ret = ov13b10_write_reg(ov13b, OV13B10_REG_SOFTWARE_RST,
1067                                 OV13B10_REG_VALUE_08BIT, OV13B10_SOFTWARE_RST);
1068         if (ret) {
1069                 dev_err(&client->dev, "%s failed to set powerup registers\n",
1070                         __func__);
1071                 return ret;
1072         }
1073
1074         link_freq_index = ov13b->cur_mode->link_freq_index;
1075         reg_list = &link_freq_configs[link_freq_index].reg_list;
1076         ret = ov13b10_write_reg_list(ov13b, reg_list);
1077         if (ret) {
1078                 dev_err(&client->dev, "%s failed to set plls\n", __func__);
1079                 return ret;
1080         }
1081
1082         /* Apply default values of current mode */
1083         reg_list = &ov13b->cur_mode->reg_list;
1084         ret = ov13b10_write_reg_list(ov13b, reg_list);
1085         if (ret) {
1086                 dev_err(&client->dev, "%s failed to set mode\n", __func__);
1087                 return ret;
1088         }
1089
1090         /* Apply customized values from user */
1091         ret =  __v4l2_ctrl_handler_setup(ov13b->sd.ctrl_handler);
1092         if (ret)
1093                 return ret;
1094
1095         return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT,
1096                                  OV13B10_REG_VALUE_08BIT,
1097                                  OV13B10_MODE_STREAMING);
1098 }
1099
1100 /* Stop streaming */
1101 static int ov13b10_stop_streaming(struct ov13b10 *ov13b)
1102 {
1103         return ov13b10_write_reg(ov13b, OV13B10_REG_MODE_SELECT,
1104                                  OV13B10_REG_VALUE_08BIT, OV13B10_MODE_STANDBY);
1105 }
1106
1107 static int ov13b10_set_stream(struct v4l2_subdev *sd, int enable)
1108 {
1109         struct ov13b10 *ov13b = to_ov13b10(sd);
1110         struct i2c_client *client = v4l2_get_subdevdata(sd);
1111         int ret = 0;
1112
1113         mutex_lock(&ov13b->mutex);
1114         if (ov13b->streaming == enable) {
1115                 mutex_unlock(&ov13b->mutex);
1116                 return 0;
1117         }
1118
1119         if (enable) {
1120                 ret = pm_runtime_resume_and_get(&client->dev);
1121                 if (ret < 0)
1122                         goto err_unlock;
1123
1124                 /*
1125                  * Apply default & customized values
1126                  * and then start streaming.
1127                  */
1128                 ret = ov13b10_start_streaming(ov13b);
1129                 if (ret)
1130                         goto err_rpm_put;
1131         } else {
1132                 ov13b10_stop_streaming(ov13b);
1133                 pm_runtime_put(&client->dev);
1134         }
1135
1136         ov13b->streaming = enable;
1137         mutex_unlock(&ov13b->mutex);
1138
1139         return ret;
1140
1141 err_rpm_put:
1142         pm_runtime_put(&client->dev);
1143 err_unlock:
1144         mutex_unlock(&ov13b->mutex);
1145
1146         return ret;
1147 }
1148
1149 static int __maybe_unused ov13b10_suspend(struct device *dev)
1150 {
1151         struct v4l2_subdev *sd = dev_get_drvdata(dev);
1152         struct ov13b10 *ov13b = to_ov13b10(sd);
1153
1154         if (ov13b->streaming)
1155                 ov13b10_stop_streaming(ov13b);
1156
1157         return 0;
1158 }
1159
1160 static int __maybe_unused ov13b10_resume(struct device *dev)
1161 {
1162         struct v4l2_subdev *sd = dev_get_drvdata(dev);
1163         struct ov13b10 *ov13b = to_ov13b10(sd);
1164         int ret;
1165
1166         if (ov13b->streaming) {
1167                 ret = ov13b10_start_streaming(ov13b);
1168                 if (ret)
1169                         goto error;
1170         }
1171
1172         return 0;
1173
1174 error:
1175         ov13b10_stop_streaming(ov13b);
1176         ov13b->streaming = false;
1177         return ret;
1178 }
1179
1180 static const struct v4l2_subdev_video_ops ov13b10_video_ops = {
1181         .s_stream = ov13b10_set_stream,
1182 };
1183
1184 static const struct v4l2_subdev_pad_ops ov13b10_pad_ops = {
1185         .enum_mbus_code = ov13b10_enum_mbus_code,
1186         .get_fmt = ov13b10_get_pad_format,
1187         .set_fmt = ov13b10_set_pad_format,
1188         .enum_frame_size = ov13b10_enum_frame_size,
1189 };
1190
1191 static const struct v4l2_subdev_ops ov13b10_subdev_ops = {
1192         .video = &ov13b10_video_ops,
1193         .pad = &ov13b10_pad_ops,
1194 };
1195
1196 static const struct media_entity_operations ov13b10_subdev_entity_ops = {
1197         .link_validate = v4l2_subdev_link_validate,
1198 };
1199
1200 static const struct v4l2_subdev_internal_ops ov13b10_internal_ops = {
1201         .open = ov13b10_open,
1202 };
1203
1204 /* Initialize control handlers */
1205 static int ov13b10_init_controls(struct ov13b10 *ov13b)
1206 {
1207         struct i2c_client *client = v4l2_get_subdevdata(&ov13b->sd);
1208         struct v4l2_fwnode_device_properties props;
1209         struct v4l2_ctrl_handler *ctrl_hdlr;
1210         s64 exposure_max;
1211         s64 vblank_def;
1212         s64 vblank_min;
1213         s64 hblank;
1214         s64 pixel_rate_min;
1215         s64 pixel_rate_max;
1216         const struct ov13b10_mode *mode;
1217         u32 max;
1218         int ret;
1219
1220         ctrl_hdlr = &ov13b->ctrl_handler;
1221         ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
1222         if (ret)
1223                 return ret;
1224
1225         mutex_init(&ov13b->mutex);
1226         ctrl_hdlr->lock = &ov13b->mutex;
1227         max = ARRAY_SIZE(link_freq_menu_items) - 1;
1228         ov13b->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1229                                                   &ov13b10_ctrl_ops,
1230                                                   V4L2_CID_LINK_FREQ,
1231                                                   max,
1232                                                   0,
1233                                                   link_freq_menu_items);
1234         if (ov13b->link_freq)
1235                 ov13b->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1236
1237         pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1238         pixel_rate_min = 0;
1239         /* By default, PIXEL_RATE is read only */
1240         ov13b->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1241                                               V4L2_CID_PIXEL_RATE,
1242                                               pixel_rate_min, pixel_rate_max,
1243                                               1, pixel_rate_max);
1244
1245         mode = ov13b->cur_mode;
1246         vblank_def = mode->vts_def - mode->height;
1247         vblank_min = mode->vts_min - mode->height;
1248         ov13b->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1249                                           V4L2_CID_VBLANK,
1250                                           vblank_min,
1251                                           OV13B10_VTS_MAX - mode->height, 1,
1252                                           vblank_def);
1253
1254         hblank = link_freq_configs[mode->link_freq_index].pixels_per_line -
1255                  mode->width;
1256         ov13b->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1257                                           V4L2_CID_HBLANK,
1258                                           hblank, hblank, 1, hblank);
1259         if (ov13b->hblank)
1260                 ov13b->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1261
1262         exposure_max = mode->vts_def - 8;
1263         ov13b->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1264                                             V4L2_CID_EXPOSURE,
1265                                             OV13B10_EXPOSURE_MIN,
1266                                             exposure_max, OV13B10_EXPOSURE_STEP,
1267                                             exposure_max);
1268
1269         v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1270                           OV13B10_ANA_GAIN_MIN, OV13B10_ANA_GAIN_MAX,
1271                           OV13B10_ANA_GAIN_STEP, OV13B10_ANA_GAIN_DEFAULT);
1272
1273         /* Digital gain */
1274         v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1275                           OV13B10_DGTL_GAIN_MIN, OV13B10_DGTL_GAIN_MAX,
1276                           OV13B10_DGTL_GAIN_STEP, OV13B10_DGTL_GAIN_DEFAULT);
1277
1278         v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13b10_ctrl_ops,
1279                                      V4L2_CID_TEST_PATTERN,
1280                                      ARRAY_SIZE(ov13b10_test_pattern_menu) - 1,
1281                                      0, 0, ov13b10_test_pattern_menu);
1282
1283         v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1284                           V4L2_CID_HFLIP, 0, 1, 1, 0);
1285         v4l2_ctrl_new_std(ctrl_hdlr, &ov13b10_ctrl_ops,
1286                           V4L2_CID_VFLIP, 0, 1, 1, 0);
1287
1288         if (ctrl_hdlr->error) {
1289                 ret = ctrl_hdlr->error;
1290                 dev_err(&client->dev, "%s control init failed (%d)\n",
1291                         __func__, ret);
1292                 goto error;
1293         }
1294
1295         ret = v4l2_fwnode_device_parse(&client->dev, &props);
1296         if (ret)
1297                 goto error;
1298
1299         ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov13b10_ctrl_ops,
1300                                               &props);
1301         if (ret)
1302                 goto error;
1303
1304         ov13b->sd.ctrl_handler = ctrl_hdlr;
1305
1306         return 0;
1307
1308 error:
1309         v4l2_ctrl_handler_free(ctrl_hdlr);
1310         mutex_destroy(&ov13b->mutex);
1311
1312         return ret;
1313 }
1314
1315 static void ov13b10_free_controls(struct ov13b10 *ov13b)
1316 {
1317         v4l2_ctrl_handler_free(ov13b->sd.ctrl_handler);
1318         mutex_destroy(&ov13b->mutex);
1319 }
1320
1321 static int ov13b10_check_hwcfg(struct device *dev)
1322 {
1323         struct v4l2_fwnode_endpoint bus_cfg = {
1324                 .bus_type = V4L2_MBUS_CSI2_DPHY
1325         };
1326         struct fwnode_handle *ep;
1327         struct fwnode_handle *fwnode = dev_fwnode(dev);
1328         unsigned int i, j;
1329         int ret;
1330         u32 ext_clk;
1331
1332         if (!fwnode)
1333                 return -ENXIO;
1334
1335         ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
1336                                        &ext_clk);
1337         if (ret) {
1338                 dev_err(dev, "can't get clock frequency");
1339                 return ret;
1340         }
1341
1342         if (ext_clk != OV13B10_EXT_CLK) {
1343                 dev_err(dev, "external clock %d is not supported",
1344                         ext_clk);
1345                 return -EINVAL;
1346         }
1347
1348         ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1349         if (!ep)
1350                 return -ENXIO;
1351
1352         ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1353         fwnode_handle_put(ep);
1354         if (ret)
1355                 return ret;
1356
1357         if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV13B10_DATA_LANES) {
1358                 dev_err(dev, "number of CSI2 data lanes %d is not supported",
1359                         bus_cfg.bus.mipi_csi2.num_data_lanes);
1360                 ret = -EINVAL;
1361                 goto out_err;
1362         }
1363
1364         if (!bus_cfg.nr_of_link_frequencies) {
1365                 dev_err(dev, "no link frequencies defined");
1366                 ret = -EINVAL;
1367                 goto out_err;
1368         }
1369
1370         for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1371                 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1372                         if (link_freq_menu_items[i] ==
1373                                 bus_cfg.link_frequencies[j])
1374                                 break;
1375                 }
1376
1377                 if (j == bus_cfg.nr_of_link_frequencies) {
1378                         dev_err(dev, "no link frequency %lld supported",
1379                                 link_freq_menu_items[i]);
1380                         ret = -EINVAL;
1381                         goto out_err;
1382                 }
1383         }
1384
1385 out_err:
1386         v4l2_fwnode_endpoint_free(&bus_cfg);
1387
1388         return ret;
1389 }
1390
1391 static int ov13b10_probe(struct i2c_client *client)
1392 {
1393         struct ov13b10 *ov13b;
1394         bool full_power;
1395         int ret;
1396
1397         /* Check HW config */
1398         ret = ov13b10_check_hwcfg(&client->dev);
1399         if (ret) {
1400                 dev_err(&client->dev, "failed to check hwcfg: %d", ret);
1401                 return ret;
1402         }
1403
1404         ov13b = devm_kzalloc(&client->dev, sizeof(*ov13b), GFP_KERNEL);
1405         if (!ov13b)
1406                 return -ENOMEM;
1407
1408         /* Initialize subdev */
1409         v4l2_i2c_subdev_init(&ov13b->sd, client, &ov13b10_subdev_ops);
1410
1411         full_power = acpi_dev_state_d0(&client->dev);
1412         if (full_power) {
1413                 /* Check module identity */
1414                 ret = ov13b10_identify_module(ov13b);
1415                 if (ret) {
1416                         dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1417                         return ret;
1418                 }
1419         }
1420
1421         /* Set default mode to max resolution */
1422         ov13b->cur_mode = &supported_modes[0];
1423
1424         ret = ov13b10_init_controls(ov13b);
1425         if (ret)
1426                 return ret;
1427
1428         /* Initialize subdev */
1429         ov13b->sd.internal_ops = &ov13b10_internal_ops;
1430         ov13b->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1431         ov13b->sd.entity.ops = &ov13b10_subdev_entity_ops;
1432         ov13b->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1433
1434         /* Initialize source pad */
1435         ov13b->pad.flags = MEDIA_PAD_FL_SOURCE;
1436         ret = media_entity_pads_init(&ov13b->sd.entity, 1, &ov13b->pad);
1437         if (ret) {
1438                 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1439                 goto error_handler_free;
1440         }
1441
1442
1443         /*
1444          * Device is already turned on by i2c-core with ACPI domain PM.
1445          * Enable runtime PM and turn off the device.
1446          */
1447         /* Set the device's state to active if it's in D0 state. */
1448         if (full_power)
1449                 pm_runtime_set_active(&client->dev);
1450         pm_runtime_enable(&client->dev);
1451         pm_runtime_idle(&client->dev);
1452
1453         ret = v4l2_async_register_subdev_sensor(&ov13b->sd);
1454         if (ret < 0)
1455                 goto error_media_entity_runtime_pm;
1456
1457         return 0;
1458
1459 error_media_entity_runtime_pm:
1460         pm_runtime_disable(&client->dev);
1461         if (full_power)
1462                 pm_runtime_set_suspended(&client->dev);
1463         media_entity_cleanup(&ov13b->sd.entity);
1464
1465 error_handler_free:
1466         ov13b10_free_controls(ov13b);
1467         dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1468
1469         return ret;
1470 }
1471
1472 static void ov13b10_remove(struct i2c_client *client)
1473 {
1474         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1475         struct ov13b10 *ov13b = to_ov13b10(sd);
1476
1477         v4l2_async_unregister_subdev(sd);
1478         media_entity_cleanup(&sd->entity);
1479         ov13b10_free_controls(ov13b);
1480
1481         pm_runtime_disable(&client->dev);
1482         pm_runtime_set_suspended(&client->dev);
1483 }
1484
1485 static const struct dev_pm_ops ov13b10_pm_ops = {
1486         SET_SYSTEM_SLEEP_PM_OPS(ov13b10_suspend, ov13b10_resume)
1487 };
1488
1489 #ifdef CONFIG_ACPI
1490 static const struct acpi_device_id ov13b10_acpi_ids[] = {
1491         {"OVTIDB10"},
1492         { /* sentinel */ }
1493 };
1494
1495 MODULE_DEVICE_TABLE(acpi, ov13b10_acpi_ids);
1496 #endif
1497
1498 static struct i2c_driver ov13b10_i2c_driver = {
1499         .driver = {
1500                 .name = "ov13b10",
1501                 .pm = &ov13b10_pm_ops,
1502                 .acpi_match_table = ACPI_PTR(ov13b10_acpi_ids),
1503         },
1504         .probe_new = ov13b10_probe,
1505         .remove = ov13b10_remove,
1506         .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE,
1507 };
1508
1509 module_i2c_driver(ov13b10_i2c_driver);
1510
1511 MODULE_AUTHOR("Kao, Arec <arec.kao@intel.com>");
1512 MODULE_DESCRIPTION("Omnivision ov13b10 sensor driver");
1513 MODULE_LICENSE("GPL v2");