2 * Copyright (c) 2017 Intel Corporation.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License version
6 * 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
15 #include <linux/acpi.h>
16 #include <linux/i2c.h>
17 #include <linux/module.h>
18 #include <linux/pm_runtime.h>
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
22 #define OV13858_REG_VALUE_08BIT 1
23 #define OV13858_REG_VALUE_16BIT 2
24 #define OV13858_REG_VALUE_24BIT 3
26 #define OV13858_REG_MODE_SELECT 0x0100
27 #define OV13858_MODE_STANDBY 0x00
28 #define OV13858_MODE_STREAMING 0x01
30 #define OV13858_REG_SOFTWARE_RST 0x0103
31 #define OV13858_SOFTWARE_RST 0x01
33 /* PLL1 generates PCLK and MIPI_PHY_CLK */
34 #define OV13858_REG_PLL1_CTRL_0 0x0300
35 #define OV13858_REG_PLL1_CTRL_1 0x0301
36 #define OV13858_REG_PLL1_CTRL_2 0x0302
37 #define OV13858_REG_PLL1_CTRL_3 0x0303
38 #define OV13858_REG_PLL1_CTRL_4 0x0304
39 #define OV13858_REG_PLL1_CTRL_5 0x0305
41 /* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */
42 #define OV13858_REG_PLL2_CTRL_B 0x030b
43 #define OV13858_REG_PLL2_CTRL_C 0x030c
44 #define OV13858_REG_PLL2_CTRL_D 0x030d
45 #define OV13858_REG_PLL2_CTRL_E 0x030e
46 #define OV13858_REG_PLL2_CTRL_F 0x030f
47 #define OV13858_REG_PLL2_CTRL_12 0x0312
48 #define OV13858_REG_MIPI_SC_CTRL0 0x3016
49 #define OV13858_REG_MIPI_SC_CTRL1 0x3022
52 #define OV13858_REG_CHIP_ID 0x300a
53 #define OV13858_CHIP_ID 0x00d855
55 /* V_TIMING internal */
56 #define OV13858_REG_VTS 0x380e
57 #define OV13858_VTS_30FPS 0x0c8e /* 30 fps */
58 #define OV13858_VTS_60FPS 0x0648 /* 60 fps */
59 #define OV13858_VTS_MAX 0x7fff
61 /* HBLANK control - read only */
62 #define OV13858_PPL_270MHZ 2244
63 #define OV13858_PPL_540MHZ 4488
65 /* Exposure control */
66 #define OV13858_REG_EXPOSURE 0x3500
67 #define OV13858_EXPOSURE_MIN 4
68 #define OV13858_EXPOSURE_STEP 1
69 #define OV13858_EXPOSURE_DEFAULT 0x640
71 /* Analog gain control */
72 #define OV13858_REG_ANALOG_GAIN 0x3508
73 #define OV13858_ANA_GAIN_MIN 0
74 #define OV13858_ANA_GAIN_MAX 0x1fff
75 #define OV13858_ANA_GAIN_STEP 1
76 #define OV13858_ANA_GAIN_DEFAULT 0x80
78 /* Digital gain control */
79 #define OV13858_REG_B_MWB_GAIN 0x5100
80 #define OV13858_REG_G_MWB_GAIN 0x5102
81 #define OV13858_REG_R_MWB_GAIN 0x5104
82 #define OV13858_DGTL_GAIN_MIN 0
83 #define OV13858_DGTL_GAIN_MAX 16384 /* Max = 16 X */
84 #define OV13858_DGTL_GAIN_DEFAULT 1024 /* Default gain = 1 X */
85 #define OV13858_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */
87 /* Test Pattern Control */
88 #define OV13858_REG_TEST_PATTERN 0x4503
89 #define OV13858_TEST_PATTERN_ENABLE BIT(7)
90 #define OV13858_TEST_PATTERN_MASK 0xfc
92 /* Number of frames to skip */
93 #define OV13858_NUM_OF_SKIP_FRAMES 2
100 struct ov13858_reg_list {
102 const struct ov13858_reg *regs;
105 /* Link frequency config */
106 struct ov13858_link_freq_config {
110 /* PLL registers for this link frequency */
111 struct ov13858_reg_list reg_list;
114 /* Mode : resolution and related config&values */
115 struct ov13858_mode {
125 /* Index of Link frequency config to be used */
127 /* Default register values */
128 struct ov13858_reg_list reg_list;
131 /* 4224x3136 needs 1080Mbps/lane, 4 lanes */
132 static const struct ov13858_reg mipi_data_rate_1080mbps[] = {
134 {OV13858_REG_PLL1_CTRL_0, 0x07},
135 {OV13858_REG_PLL1_CTRL_1, 0x01},
136 {OV13858_REG_PLL1_CTRL_2, 0xc2},
137 {OV13858_REG_PLL1_CTRL_3, 0x00},
138 {OV13858_REG_PLL1_CTRL_4, 0x00},
139 {OV13858_REG_PLL1_CTRL_5, 0x01},
142 {OV13858_REG_PLL2_CTRL_B, 0x05},
143 {OV13858_REG_PLL2_CTRL_C, 0x01},
144 {OV13858_REG_PLL2_CTRL_D, 0x0e},
145 {OV13858_REG_PLL2_CTRL_E, 0x05},
146 {OV13858_REG_PLL2_CTRL_F, 0x01},
147 {OV13858_REG_PLL2_CTRL_12, 0x01},
148 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
149 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
153 * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane,
156 static const struct ov13858_reg mipi_data_rate_540mbps[] = {
158 {OV13858_REG_PLL1_CTRL_0, 0x07},
159 {OV13858_REG_PLL1_CTRL_1, 0x01},
160 {OV13858_REG_PLL1_CTRL_2, 0xc2},
161 {OV13858_REG_PLL1_CTRL_3, 0x01},
162 {OV13858_REG_PLL1_CTRL_4, 0x00},
163 {OV13858_REG_PLL1_CTRL_5, 0x01},
166 {OV13858_REG_PLL2_CTRL_B, 0x05},
167 {OV13858_REG_PLL2_CTRL_C, 0x01},
168 {OV13858_REG_PLL2_CTRL_D, 0x0e},
169 {OV13858_REG_PLL2_CTRL_E, 0x05},
170 {OV13858_REG_PLL2_CTRL_F, 0x01},
171 {OV13858_REG_PLL2_CTRL_12, 0x01},
172 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
173 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
176 static const struct ov13858_reg mode_4224x3136_regs[] = {
366 static const struct ov13858_reg mode_2112x1568_regs[] = {
556 static const struct ov13858_reg mode_2112x1188_regs[] = {
746 static const struct ov13858_reg mode_1056x784_regs[] = {
936 static const char * const ov13858_test_pattern_menu[] = {
938 "Vertical Color Bar Type 1",
939 "Vertical Color Bar Type 2",
940 "Vertical Color Bar Type 3",
941 "Vertical Color Bar Type 4"
944 /* Configurations for supported link frequencies */
945 #define OV13858_NUM_OF_LINK_FREQS 2
946 #define OV13858_LINK_FREQ_540MHZ 540000000ULL
947 #define OV13858_LINK_FREQ_270MHZ 270000000ULL
948 #define OV13858_LINK_FREQ_INDEX_0 0
949 #define OV13858_LINK_FREQ_INDEX_1 1
951 /* Menu items for LINK_FREQ V4L2 control */
952 static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = {
953 OV13858_LINK_FREQ_540MHZ,
954 OV13858_LINK_FREQ_270MHZ
957 /* Link frequency configs */
958 static const struct ov13858_link_freq_config
959 link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = {
961 /* pixel_rate = link_freq * 2 * nr_of_lanes / bits_per_sample */
962 .pixel_rate = (OV13858_LINK_FREQ_540MHZ * 2 * 4) / 10,
963 .pixels_per_line = OV13858_PPL_540MHZ,
965 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps),
966 .regs = mipi_data_rate_1080mbps,
970 /* pixel_rate = link_freq * 2 * nr_of_lanes / bits_per_sample */
971 .pixel_rate = (OV13858_LINK_FREQ_270MHZ * 2 * 4) / 10,
972 .pixels_per_line = OV13858_PPL_270MHZ,
974 .num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps),
975 .regs = mipi_data_rate_540mbps,
981 static const struct ov13858_mode supported_modes[] = {
985 .vts_def = OV13858_VTS_30FPS,
986 .vts_min = OV13858_VTS_30FPS,
988 .num_of_regs = ARRAY_SIZE(mode_4224x3136_regs),
989 .regs = mode_4224x3136_regs,
991 .link_freq_index = OV13858_LINK_FREQ_INDEX_0,
996 .vts_def = OV13858_VTS_30FPS,
999 .num_of_regs = ARRAY_SIZE(mode_2112x1568_regs),
1000 .regs = mode_2112x1568_regs,
1002 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1007 .vts_def = OV13858_VTS_30FPS,
1010 .num_of_regs = ARRAY_SIZE(mode_2112x1188_regs),
1011 .regs = mode_2112x1188_regs,
1013 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1018 .vts_def = OV13858_VTS_30FPS,
1021 .num_of_regs = ARRAY_SIZE(mode_1056x784_regs),
1022 .regs = mode_1056x784_regs,
1024 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1029 struct v4l2_subdev sd;
1030 struct media_pad pad;
1032 struct v4l2_ctrl_handler ctrl_handler;
1034 struct v4l2_ctrl *link_freq;
1035 struct v4l2_ctrl *pixel_rate;
1036 struct v4l2_ctrl *vblank;
1037 struct v4l2_ctrl *hblank;
1038 struct v4l2_ctrl *exposure;
1041 const struct ov13858_mode *cur_mode;
1043 /* Mutex for serialized access */
1046 /* Streaming on/off */
1050 #define to_ov13858(_sd) container_of(_sd, struct ov13858, sd)
1052 /* Read registers up to 4 at a time */
1053 static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 *val)
1055 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1056 struct i2c_msg msgs[2];
1060 u16 reg_addr_be = cpu_to_be16(reg);
1065 data_be_p = (u8 *)&data_be;
1066 /* Write register address */
1067 msgs[0].addr = client->addr;
1070 msgs[0].buf = (u8 *)®_addr_be;
1072 /* Read data from register */
1073 msgs[1].addr = client->addr;
1074 msgs[1].flags = I2C_M_RD;
1076 msgs[1].buf = &data_be_p[4 - len];
1078 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1079 if (ret != ARRAY_SIZE(msgs))
1082 *val = be32_to_cpu(data_be);
1087 /* Write registers up to 4 at a time */
1088 static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len, u32 val)
1090 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1098 buf[1] = reg & 0xff;
1100 val = cpu_to_be32(val);
1106 buf[buf_i++] = val_p[val_i++];
1108 if (i2c_master_send(client, buf, len + 2) != len + 2)
1114 /* Write a list of registers */
1115 static int ov13858_write_regs(struct ov13858 *ov13858,
1116 const struct ov13858_reg *regs, u32 len)
1118 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1122 for (i = 0; i < len; i++) {
1123 ret = ov13858_write_reg(ov13858, regs[i].address, 1,
1126 dev_err_ratelimited(
1128 "Failed to write reg 0x%4.4x. error = %d\n",
1129 regs[i].address, ret);
1138 static int ov13858_write_reg_list(struct ov13858 *ov13858,
1139 const struct ov13858_reg_list *r_list)
1141 return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs);
1144 /* Open sub-device */
1145 static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1147 struct ov13858 *ov13858 = to_ov13858(sd);
1148 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,
1152 mutex_lock(&ov13858->mutex);
1154 /* Initialize try_fmt */
1155 try_fmt->width = ov13858->cur_mode->width;
1156 try_fmt->height = ov13858->cur_mode->height;
1157 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1158 try_fmt->field = V4L2_FIELD_NONE;
1160 /* No crop or compose */
1161 mutex_unlock(&ov13858->mutex);
1166 static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain)
1170 ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN,
1171 OV13858_REG_VALUE_16BIT, d_gain);
1175 ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN,
1176 OV13858_REG_VALUE_16BIT, d_gain);
1180 ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN,
1181 OV13858_REG_VALUE_16BIT, d_gain);
1186 static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern)
1191 ret = ov13858_read_reg(ov13858, OV13858_REG_TEST_PATTERN,
1192 OV13858_REG_VALUE_08BIT, &val);
1197 val &= OV13858_TEST_PATTERN_MASK;
1198 val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE;
1200 val &= ~OV13858_TEST_PATTERN_ENABLE;
1203 return ov13858_write_reg(ov13858, OV13858_REG_TEST_PATTERN,
1204 OV13858_REG_VALUE_08BIT, val);
1207 static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl)
1209 struct ov13858 *ov13858 = container_of(ctrl->handler,
1210 struct ov13858, ctrl_handler);
1211 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1215 /* Propagate change of current control to all related controls */
1217 case V4L2_CID_VBLANK:
1218 /* Update max exposure while meeting expected vblanking */
1219 max = ov13858->cur_mode->height + ctrl->val - 8;
1220 __v4l2_ctrl_modify_range(ov13858->exposure,
1221 ov13858->exposure->minimum,
1222 max, ov13858->exposure->step, max);
1227 * Applying V4L2 control value only happens
1228 * when power is up for streaming
1230 if (pm_runtime_get_if_in_use(&client->dev) <= 0)
1235 case V4L2_CID_ANALOGUE_GAIN:
1236 ret = ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN,
1237 OV13858_REG_VALUE_16BIT, ctrl->val);
1239 case V4L2_CID_DIGITAL_GAIN:
1240 ret = ov13858_update_digital_gain(ov13858, ctrl->val);
1242 case V4L2_CID_EXPOSURE:
1243 ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE,
1244 OV13858_REG_VALUE_24BIT,
1247 case V4L2_CID_VBLANK:
1248 /* Update VTS that meets expected vertical blanking */
1249 ret = ov13858_write_reg(ov13858, OV13858_REG_VTS,
1250 OV13858_REG_VALUE_16BIT,
1251 ov13858->cur_mode->height
1254 case V4L2_CID_TEST_PATTERN:
1255 ret = ov13858_enable_test_pattern(ov13858, ctrl->val);
1258 dev_info(&client->dev,
1259 "ctrl(id:0x%x,val:0x%x) is not handled\n",
1260 ctrl->id, ctrl->val);
1264 pm_runtime_put(&client->dev);
1269 static const struct v4l2_ctrl_ops ov13858_ctrl_ops = {
1270 .s_ctrl = ov13858_set_ctrl,
1273 static int ov13858_enum_mbus_code(struct v4l2_subdev *sd,
1274 struct v4l2_subdev_pad_config *cfg,
1275 struct v4l2_subdev_mbus_code_enum *code)
1277 /* Only one bayer order(GRBG) is supported */
1278 if (code->index > 0)
1281 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1286 static int ov13858_enum_frame_size(struct v4l2_subdev *sd,
1287 struct v4l2_subdev_pad_config *cfg,
1288 struct v4l2_subdev_frame_size_enum *fse)
1290 if (fse->index >= ARRAY_SIZE(supported_modes))
1293 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1296 fse->min_width = supported_modes[fse->index].width;
1297 fse->max_width = fse->min_width;
1298 fse->min_height = supported_modes[fse->index].height;
1299 fse->max_height = fse->min_height;
1304 static void ov13858_update_pad_format(const struct ov13858_mode *mode,
1305 struct v4l2_subdev_format *fmt)
1307 fmt->format.width = mode->width;
1308 fmt->format.height = mode->height;
1309 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1310 fmt->format.field = V4L2_FIELD_NONE;
1313 static int ov13858_do_get_pad_format(struct ov13858 *ov13858,
1314 struct v4l2_subdev_pad_config *cfg,
1315 struct v4l2_subdev_format *fmt)
1317 struct v4l2_mbus_framefmt *framefmt;
1318 struct v4l2_subdev *sd = &ov13858->sd;
1320 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1321 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1322 fmt->format = *framefmt;
1324 ov13858_update_pad_format(ov13858->cur_mode, fmt);
1330 static int ov13858_get_pad_format(struct v4l2_subdev *sd,
1331 struct v4l2_subdev_pad_config *cfg,
1332 struct v4l2_subdev_format *fmt)
1334 struct ov13858 *ov13858 = to_ov13858(sd);
1337 mutex_lock(&ov13858->mutex);
1338 ret = ov13858_do_get_pad_format(ov13858, cfg, fmt);
1339 mutex_unlock(&ov13858->mutex);
1345 * Calculate resolution distance
1348 ov13858_get_resolution_dist(const struct ov13858_mode *mode,
1349 struct v4l2_mbus_framefmt *framefmt)
1351 return abs(mode->width - framefmt->width) +
1352 abs(mode->height - framefmt->height);
1356 * Find the closest supported resolution to the requested resolution
1358 static const struct ov13858_mode *
1359 ov13858_find_best_fit(struct ov13858 *ov13858,
1360 struct v4l2_subdev_format *fmt)
1362 int i, dist, cur_best_fit = 0, cur_best_fit_dist = -1;
1363 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1365 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1366 dist = ov13858_get_resolution_dist(&supported_modes[i],
1368 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1369 cur_best_fit_dist = dist;
1374 return &supported_modes[cur_best_fit];
1378 ov13858_set_pad_format(struct v4l2_subdev *sd,
1379 struct v4l2_subdev_pad_config *cfg,
1380 struct v4l2_subdev_format *fmt)
1382 struct ov13858 *ov13858 = to_ov13858(sd);
1383 const struct ov13858_mode *mode;
1384 struct v4l2_mbus_framefmt *framefmt;
1389 mutex_lock(&ov13858->mutex);
1391 /* Only one raw bayer(GRBG) order is supported */
1392 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
1393 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1395 mode = ov13858_find_best_fit(ov13858, fmt);
1396 ov13858_update_pad_format(mode, fmt);
1397 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1398 framefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1399 *framefmt = fmt->format;
1401 ov13858->cur_mode = mode;
1402 __v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index);
1403 __v4l2_ctrl_s_ctrl_int64(
1404 ov13858->pixel_rate,
1405 link_freq_configs[mode->link_freq_index].pixel_rate);
1406 /* Update limits and set FPS to default */
1407 vblank_def = ov13858->cur_mode->vts_def -
1408 ov13858->cur_mode->height;
1409 vblank_min = ov13858->cur_mode->vts_min -
1410 ov13858->cur_mode->height;
1411 __v4l2_ctrl_modify_range(
1412 ov13858->vblank, vblank_min,
1413 OV13858_VTS_MAX - ov13858->cur_mode->height, 1,
1415 __v4l2_ctrl_s_ctrl(ov13858->vblank, vblank_def);
1417 link_freq_configs[mode->link_freq_index].pixels_per_line
1418 - ov13858->cur_mode->width;
1419 __v4l2_ctrl_modify_range(ov13858->hblank, h_blank,
1420 h_blank, 1, h_blank);
1423 mutex_unlock(&ov13858->mutex);
1428 static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
1430 *frames = OV13858_NUM_OF_SKIP_FRAMES;
1435 /* Start streaming */
1436 static int ov13858_start_streaming(struct ov13858 *ov13858)
1438 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1439 const struct ov13858_reg_list *reg_list;
1440 int ret, link_freq_index;
1442 /* Get out of from software reset */
1443 ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST,
1444 OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST);
1446 dev_err(&client->dev, "%s failed to set powerup registers\n",
1452 link_freq_index = ov13858->cur_mode->link_freq_index;
1453 reg_list = &link_freq_configs[link_freq_index].reg_list;
1454 ret = ov13858_write_reg_list(ov13858, reg_list);
1456 dev_err(&client->dev, "%s failed to set plls\n", __func__);
1460 /* Apply default values of current mode */
1461 reg_list = &ov13858->cur_mode->reg_list;
1462 ret = ov13858_write_reg_list(ov13858, reg_list);
1464 dev_err(&client->dev, "%s failed to set mode\n", __func__);
1468 /* Apply customized values from user */
1469 ret = __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler);
1473 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1474 OV13858_REG_VALUE_08BIT,
1475 OV13858_MODE_STREAMING);
1478 /* Stop streaming */
1479 static int ov13858_stop_streaming(struct ov13858 *ov13858)
1481 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1482 OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY);
1485 static int ov13858_set_stream(struct v4l2_subdev *sd, int enable)
1487 struct ov13858 *ov13858 = to_ov13858(sd);
1488 struct i2c_client *client = v4l2_get_subdevdata(sd);
1491 mutex_lock(&ov13858->mutex);
1492 if (ov13858->streaming == enable) {
1493 mutex_unlock(&ov13858->mutex);
1498 ret = pm_runtime_get_sync(&client->dev);
1500 pm_runtime_put_noidle(&client->dev);
1505 * Apply default & customized values
1506 * and then start streaming.
1508 ret = ov13858_start_streaming(ov13858);
1512 ov13858_stop_streaming(ov13858);
1513 pm_runtime_put(&client->dev);
1516 ov13858->streaming = enable;
1517 mutex_unlock(&ov13858->mutex);
1522 pm_runtime_put(&client->dev);
1524 mutex_unlock(&ov13858->mutex);
1529 static int __maybe_unused ov13858_suspend(struct device *dev)
1531 struct i2c_client *client = to_i2c_client(dev);
1532 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1533 struct ov13858 *ov13858 = to_ov13858(sd);
1535 if (ov13858->streaming)
1536 ov13858_stop_streaming(ov13858);
1541 static int __maybe_unused ov13858_resume(struct device *dev)
1543 struct i2c_client *client = to_i2c_client(dev);
1544 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1545 struct ov13858 *ov13858 = to_ov13858(sd);
1548 if (ov13858->streaming) {
1549 ret = ov13858_start_streaming(ov13858);
1557 ov13858_stop_streaming(ov13858);
1558 ov13858->streaming = 0;
1562 /* Verify chip ID */
1563 static int ov13858_identify_module(struct ov13858 *ov13858)
1565 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1569 ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID,
1570 OV13858_REG_VALUE_24BIT, &val);
1574 if (val != OV13858_CHIP_ID) {
1575 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1576 OV13858_CHIP_ID, val);
1583 static const struct v4l2_subdev_video_ops ov13858_video_ops = {
1584 .s_stream = ov13858_set_stream,
1587 static const struct v4l2_subdev_pad_ops ov13858_pad_ops = {
1588 .enum_mbus_code = ov13858_enum_mbus_code,
1589 .get_fmt = ov13858_get_pad_format,
1590 .set_fmt = ov13858_set_pad_format,
1591 .enum_frame_size = ov13858_enum_frame_size,
1594 static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = {
1595 .g_skip_frames = ov13858_get_skip_frames,
1598 static const struct v4l2_subdev_ops ov13858_subdev_ops = {
1599 .video = &ov13858_video_ops,
1600 .pad = &ov13858_pad_ops,
1601 .sensor = &ov13858_sensor_ops,
1604 static const struct media_entity_operations ov13858_subdev_entity_ops = {
1605 .link_validate = v4l2_subdev_link_validate,
1608 static const struct v4l2_subdev_internal_ops ov13858_internal_ops = {
1609 .open = ov13858_open,
1612 /* Initialize control handlers */
1613 static int ov13858_init_controls(struct ov13858 *ov13858)
1615 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1616 struct v4l2_ctrl_handler *ctrl_hdlr;
1622 ctrl_hdlr = &ov13858->ctrl_handler;
1623 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
1627 mutex_init(&ov13858->mutex);
1628 ctrl_hdlr->lock = &ov13858->mutex;
1629 ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1632 OV13858_NUM_OF_LINK_FREQS - 1,
1634 link_freq_menu_items);
1635 ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1637 /* By default, PIXEL_RATE is read only */
1638 ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops,
1639 V4L2_CID_PIXEL_RATE, 0,
1640 link_freq_configs[0].pixel_rate, 1,
1641 link_freq_configs[0].pixel_rate);
1643 vblank_def = ov13858->cur_mode->vts_def - ov13858->cur_mode->height;
1644 vblank_min = ov13858->cur_mode->vts_min - ov13858->cur_mode->height;
1645 ov13858->vblank = v4l2_ctrl_new_std(
1646 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_VBLANK,
1648 OV13858_VTS_MAX - ov13858->cur_mode->height, 1,
1651 ov13858->hblank = v4l2_ctrl_new_std(
1652 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK,
1653 OV13858_PPL_540MHZ - ov13858->cur_mode->width,
1654 OV13858_PPL_540MHZ - ov13858->cur_mode->width,
1656 OV13858_PPL_540MHZ - ov13858->cur_mode->width);
1657 ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1659 exposure_max = ov13858->cur_mode->vts_def - 8;
1660 ov13858->exposure = v4l2_ctrl_new_std(
1661 ctrl_hdlr, &ov13858_ctrl_ops,
1662 V4L2_CID_EXPOSURE, OV13858_EXPOSURE_MIN,
1663 exposure_max, OV13858_EXPOSURE_STEP,
1664 OV13858_EXPOSURE_DEFAULT);
1666 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1667 OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX,
1668 OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT);
1671 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1672 OV13858_DGTL_GAIN_MIN, OV13858_DGTL_GAIN_MAX,
1673 OV13858_DGTL_GAIN_STEP, OV13858_DGTL_GAIN_DEFAULT);
1675 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13858_ctrl_ops,
1676 V4L2_CID_TEST_PATTERN,
1677 ARRAY_SIZE(ov13858_test_pattern_menu) - 1,
1678 0, 0, ov13858_test_pattern_menu);
1679 if (ctrl_hdlr->error) {
1680 ret = ctrl_hdlr->error;
1681 dev_err(&client->dev, "%s control init failed (%d)\n",
1686 ov13858->sd.ctrl_handler = ctrl_hdlr;
1691 v4l2_ctrl_handler_free(ctrl_hdlr);
1692 mutex_destroy(&ov13858->mutex);
1697 static void ov13858_free_controls(struct ov13858 *ov13858)
1699 v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler);
1700 mutex_destroy(&ov13858->mutex);
1703 static int ov13858_probe(struct i2c_client *client,
1704 const struct i2c_device_id *devid)
1706 struct ov13858 *ov13858;
1710 device_property_read_u32(&client->dev, "clock-frequency", &val);
1711 if (val != 19200000)
1714 ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL);
1718 /* Initialize subdev */
1719 v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops);
1721 /* Check module identity */
1722 ret = ov13858_identify_module(ov13858);
1724 dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1728 /* Set default mode to max resolution */
1729 ov13858->cur_mode = &supported_modes[0];
1731 ret = ov13858_init_controls(ov13858);
1735 /* Initialize subdev */
1736 ov13858->sd.internal_ops = &ov13858_internal_ops;
1737 ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1738 ov13858->sd.entity.ops = &ov13858_subdev_entity_ops;
1739 ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1741 /* Initialize source pad */
1742 ov13858->pad.flags = MEDIA_PAD_FL_SOURCE;
1743 ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad);
1745 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1746 goto error_handler_free;
1749 ret = v4l2_async_register_subdev(&ov13858->sd);
1751 goto error_media_entity;
1754 * Device is already turned on by i2c-core with ACPI domain PM.
1755 * Enable runtime PM and turn off the device.
1757 pm_runtime_get_noresume(&client->dev);
1758 pm_runtime_set_active(&client->dev);
1759 pm_runtime_enable(&client->dev);
1760 pm_runtime_put(&client->dev);
1765 media_entity_cleanup(&ov13858->sd.entity);
1768 ov13858_free_controls(ov13858);
1769 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1774 static int ov13858_remove(struct i2c_client *client)
1776 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1777 struct ov13858 *ov13858 = to_ov13858(sd);
1779 v4l2_async_unregister_subdev(sd);
1780 media_entity_cleanup(&sd->entity);
1781 ov13858_free_controls(ov13858);
1784 * Disable runtime PM but keep the device turned on.
1785 * i2c-core with ACPI domain PM will turn off the device.
1787 pm_runtime_get_sync(&client->dev);
1788 pm_runtime_disable(&client->dev);
1789 pm_runtime_set_suspended(&client->dev);
1790 pm_runtime_put_noidle(&client->dev);
1795 static const struct i2c_device_id ov13858_id_table[] = {
1800 MODULE_DEVICE_TABLE(i2c, ov13858_id_table);
1802 static const struct dev_pm_ops ov13858_pm_ops = {
1803 SET_SYSTEM_SLEEP_PM_OPS(ov13858_suspend, ov13858_resume)
1807 static const struct acpi_device_id ov13858_acpi_ids[] = {
1812 MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids);
1815 static struct i2c_driver ov13858_i2c_driver = {
1818 .owner = THIS_MODULE,
1819 .pm = &ov13858_pm_ops,
1820 .acpi_match_table = ACPI_PTR(ov13858_acpi_ids),
1822 .probe = ov13858_probe,
1823 .remove = ov13858_remove,
1824 .id_table = ov13858_id_table,
1827 module_i2c_driver(ov13858_i2c_driver);
1829 MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>");
1830 MODULE_AUTHOR("Rapolu, Chiranjeevi <chiranjeevi.rapolu@intel.com>");
1831 MODULE_AUTHOR("Yang, Hyungwoo <hyungwoo.yang@intel.com>");
1832 MODULE_DESCRIPTION("Omnivision ov13858 sensor driver");
1833 MODULE_LICENSE("GPL v2");