1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017 Intel Corporation.
4 #include <linux/acpi.h>
6 #include <linux/module.h>
7 #include <linux/pm_runtime.h>
8 #include <media/v4l2-ctrls.h>
9 #include <media/v4l2-device.h>
10 #include <media/v4l2-event.h>
11 #include <media/v4l2-fwnode.h>
13 #define OV13858_REG_VALUE_08BIT 1
14 #define OV13858_REG_VALUE_16BIT 2
15 #define OV13858_REG_VALUE_24BIT 3
17 #define OV13858_REG_MODE_SELECT 0x0100
18 #define OV13858_MODE_STANDBY 0x00
19 #define OV13858_MODE_STREAMING 0x01
21 #define OV13858_REG_SOFTWARE_RST 0x0103
22 #define OV13858_SOFTWARE_RST 0x01
24 /* PLL1 generates PCLK and MIPI_PHY_CLK */
25 #define OV13858_REG_PLL1_CTRL_0 0x0300
26 #define OV13858_REG_PLL1_CTRL_1 0x0301
27 #define OV13858_REG_PLL1_CTRL_2 0x0302
28 #define OV13858_REG_PLL1_CTRL_3 0x0303
29 #define OV13858_REG_PLL1_CTRL_4 0x0304
30 #define OV13858_REG_PLL1_CTRL_5 0x0305
32 /* PLL2 generates DAC_CLK, SCLK and SRAM_CLK */
33 #define OV13858_REG_PLL2_CTRL_B 0x030b
34 #define OV13858_REG_PLL2_CTRL_C 0x030c
35 #define OV13858_REG_PLL2_CTRL_D 0x030d
36 #define OV13858_REG_PLL2_CTRL_E 0x030e
37 #define OV13858_REG_PLL2_CTRL_F 0x030f
38 #define OV13858_REG_PLL2_CTRL_12 0x0312
39 #define OV13858_REG_MIPI_SC_CTRL0 0x3016
40 #define OV13858_REG_MIPI_SC_CTRL1 0x3022
43 #define OV13858_REG_CHIP_ID 0x300a
44 #define OV13858_CHIP_ID 0x00d855
46 /* V_TIMING internal */
47 #define OV13858_REG_VTS 0x380e
48 #define OV13858_VTS_30FPS 0x0c8e /* 30 fps */
49 #define OV13858_VTS_60FPS 0x0648 /* 60 fps */
50 #define OV13858_VTS_MAX 0x7fff
52 /* HBLANK control - read only */
53 #define OV13858_PPL_270MHZ 2244
54 #define OV13858_PPL_540MHZ 4488
56 /* Exposure control */
57 #define OV13858_REG_EXPOSURE 0x3500
58 #define OV13858_EXPOSURE_MIN 4
59 #define OV13858_EXPOSURE_STEP 1
60 #define OV13858_EXPOSURE_DEFAULT 0x640
62 /* Analog gain control */
63 #define OV13858_REG_ANALOG_GAIN 0x3508
64 #define OV13858_ANA_GAIN_MIN 0
65 #define OV13858_ANA_GAIN_MAX 0x1fff
66 #define OV13858_ANA_GAIN_STEP 1
67 #define OV13858_ANA_GAIN_DEFAULT 0x80
69 /* Digital gain control */
70 #define OV13858_REG_B_MWB_GAIN 0x5100
71 #define OV13858_REG_G_MWB_GAIN 0x5102
72 #define OV13858_REG_R_MWB_GAIN 0x5104
73 #define OV13858_DGTL_GAIN_MIN 0
74 #define OV13858_DGTL_GAIN_MAX 16384 /* Max = 16 X */
75 #define OV13858_DGTL_GAIN_DEFAULT 1024 /* Default gain = 1 X */
76 #define OV13858_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */
78 /* Test Pattern Control */
79 #define OV13858_REG_TEST_PATTERN 0x4503
80 #define OV13858_TEST_PATTERN_ENABLE BIT(7)
81 #define OV13858_TEST_PATTERN_MASK 0xfc
83 /* Number of frames to skip */
84 #define OV13858_NUM_OF_SKIP_FRAMES 2
91 struct ov13858_reg_list {
93 const struct ov13858_reg *regs;
96 /* Link frequency config */
97 struct ov13858_link_freq_config {
100 /* PLL registers for this link frequency */
101 struct ov13858_reg_list reg_list;
104 /* Mode : resolution and related config&values */
105 struct ov13858_mode {
115 /* Index of Link frequency config to be used */
117 /* Default register values */
118 struct ov13858_reg_list reg_list;
121 /* 4224x3136 needs 1080Mbps/lane, 4 lanes */
122 static const struct ov13858_reg mipi_data_rate_1080mbps[] = {
124 {OV13858_REG_PLL1_CTRL_0, 0x07},
125 {OV13858_REG_PLL1_CTRL_1, 0x01},
126 {OV13858_REG_PLL1_CTRL_2, 0xc2},
127 {OV13858_REG_PLL1_CTRL_3, 0x00},
128 {OV13858_REG_PLL1_CTRL_4, 0x00},
129 {OV13858_REG_PLL1_CTRL_5, 0x01},
132 {OV13858_REG_PLL2_CTRL_B, 0x05},
133 {OV13858_REG_PLL2_CTRL_C, 0x01},
134 {OV13858_REG_PLL2_CTRL_D, 0x0e},
135 {OV13858_REG_PLL2_CTRL_E, 0x05},
136 {OV13858_REG_PLL2_CTRL_F, 0x01},
137 {OV13858_REG_PLL2_CTRL_12, 0x01},
138 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
139 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
143 * 2112x1568, 2112x1188, 1056x784 need 540Mbps/lane,
146 static const struct ov13858_reg mipi_data_rate_540mbps[] = {
148 {OV13858_REG_PLL1_CTRL_0, 0x07},
149 {OV13858_REG_PLL1_CTRL_1, 0x01},
150 {OV13858_REG_PLL1_CTRL_2, 0xc2},
151 {OV13858_REG_PLL1_CTRL_3, 0x01},
152 {OV13858_REG_PLL1_CTRL_4, 0x00},
153 {OV13858_REG_PLL1_CTRL_5, 0x01},
156 {OV13858_REG_PLL2_CTRL_B, 0x05},
157 {OV13858_REG_PLL2_CTRL_C, 0x01},
158 {OV13858_REG_PLL2_CTRL_D, 0x0e},
159 {OV13858_REG_PLL2_CTRL_E, 0x05},
160 {OV13858_REG_PLL2_CTRL_F, 0x01},
161 {OV13858_REG_PLL2_CTRL_12, 0x01},
162 {OV13858_REG_MIPI_SC_CTRL0, 0x72},
163 {OV13858_REG_MIPI_SC_CTRL1, 0x01},
166 static const struct ov13858_reg mode_4224x3136_regs[] = {
357 static const struct ov13858_reg mode_2112x1568_regs[] = {
548 static const struct ov13858_reg mode_2112x1188_regs[] = {
739 static const struct ov13858_reg mode_1056x784_regs[] = {
930 static const char * const ov13858_test_pattern_menu[] = {
932 "Vertical Color Bar Type 1",
933 "Vertical Color Bar Type 2",
934 "Vertical Color Bar Type 3",
935 "Vertical Color Bar Type 4"
938 /* Configurations for supported link frequencies */
939 #define OV13858_NUM_OF_LINK_FREQS 2
940 #define OV13858_LINK_FREQ_540MHZ 540000000ULL
941 #define OV13858_LINK_FREQ_270MHZ 270000000ULL
942 #define OV13858_LINK_FREQ_INDEX_0 0
943 #define OV13858_LINK_FREQ_INDEX_1 1
946 * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample
947 * data rate => double data rate; number of lanes => 4; bits per pixel => 10
949 static u64 link_freq_to_pixel_rate(u64 f)
957 /* Menu items for LINK_FREQ V4L2 control */
958 static const s64 link_freq_menu_items[OV13858_NUM_OF_LINK_FREQS] = {
959 OV13858_LINK_FREQ_540MHZ,
960 OV13858_LINK_FREQ_270MHZ
963 /* Link frequency configs */
964 static const struct ov13858_link_freq_config
965 link_freq_configs[OV13858_NUM_OF_LINK_FREQS] = {
967 .pixels_per_line = OV13858_PPL_540MHZ,
969 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1080mbps),
970 .regs = mipi_data_rate_1080mbps,
974 .pixels_per_line = OV13858_PPL_270MHZ,
976 .num_of_regs = ARRAY_SIZE(mipi_data_rate_540mbps),
977 .regs = mipi_data_rate_540mbps,
983 static const struct ov13858_mode supported_modes[] = {
987 .vts_def = OV13858_VTS_30FPS,
988 .vts_min = OV13858_VTS_30FPS,
990 .num_of_regs = ARRAY_SIZE(mode_4224x3136_regs),
991 .regs = mode_4224x3136_regs,
993 .link_freq_index = OV13858_LINK_FREQ_INDEX_0,
998 .vts_def = OV13858_VTS_30FPS,
1001 .num_of_regs = ARRAY_SIZE(mode_2112x1568_regs),
1002 .regs = mode_2112x1568_regs,
1004 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1009 .vts_def = OV13858_VTS_30FPS,
1012 .num_of_regs = ARRAY_SIZE(mode_2112x1188_regs),
1013 .regs = mode_2112x1188_regs,
1015 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1020 .vts_def = OV13858_VTS_30FPS,
1023 .num_of_regs = ARRAY_SIZE(mode_1056x784_regs),
1024 .regs = mode_1056x784_regs,
1026 .link_freq_index = OV13858_LINK_FREQ_INDEX_1,
1031 struct v4l2_subdev sd;
1032 struct media_pad pad;
1034 struct v4l2_ctrl_handler ctrl_handler;
1036 struct v4l2_ctrl *link_freq;
1037 struct v4l2_ctrl *pixel_rate;
1038 struct v4l2_ctrl *vblank;
1039 struct v4l2_ctrl *hblank;
1040 struct v4l2_ctrl *exposure;
1043 const struct ov13858_mode *cur_mode;
1045 /* Mutex for serialized access */
1049 #define to_ov13858(_sd) container_of(_sd, struct ov13858, sd)
1051 /* Read registers up to 4 at a time */
1052 static int ov13858_read_reg(struct ov13858 *ov13858, u16 reg, u32 len,
1055 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1056 struct i2c_msg msgs[2];
1060 __be16 reg_addr_be = cpu_to_be16(reg);
1065 data_be_p = (u8 *)&data_be;
1066 /* Write register address */
1067 msgs[0].addr = client->addr;
1070 msgs[0].buf = (u8 *)®_addr_be;
1072 /* Read data from register */
1073 msgs[1].addr = client->addr;
1074 msgs[1].flags = I2C_M_RD;
1076 msgs[1].buf = &data_be_p[4 - len];
1078 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1079 if (ret != ARRAY_SIZE(msgs))
1082 *val = be32_to_cpu(data_be);
1087 /* Write registers up to 4 at a time */
1088 static int ov13858_write_reg(struct ov13858 *ov13858, u16 reg, u32 len,
1091 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1100 buf[1] = reg & 0xff;
1102 val = cpu_to_be32(__val);
1108 buf[buf_i++] = val_p[val_i++];
1110 if (i2c_master_send(client, buf, len + 2) != len + 2)
1116 /* Write a list of registers */
1117 static int ov13858_write_regs(struct ov13858 *ov13858,
1118 const struct ov13858_reg *regs, u32 len)
1120 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1124 for (i = 0; i < len; i++) {
1125 ret = ov13858_write_reg(ov13858, regs[i].address, 1,
1128 dev_err_ratelimited(
1130 "Failed to write reg 0x%4.4x. error = %d\n",
1131 regs[i].address, ret);
1140 static int ov13858_write_reg_list(struct ov13858 *ov13858,
1141 const struct ov13858_reg_list *r_list)
1143 return ov13858_write_regs(ov13858, r_list->regs, r_list->num_of_regs);
1146 /* Open sub-device */
1147 static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1149 struct ov13858 *ov13858 = to_ov13858(sd);
1150 struct v4l2_mbus_framefmt *try_fmt = v4l2_subdev_get_try_format(sd,
1154 mutex_lock(&ov13858->mutex);
1156 /* Initialize try_fmt */
1157 try_fmt->width = ov13858->cur_mode->width;
1158 try_fmt->height = ov13858->cur_mode->height;
1159 try_fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1160 try_fmt->field = V4L2_FIELD_NONE;
1162 /* No crop or compose */
1163 mutex_unlock(&ov13858->mutex);
1168 static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain)
1172 ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN,
1173 OV13858_REG_VALUE_16BIT, d_gain);
1177 ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN,
1178 OV13858_REG_VALUE_16BIT, d_gain);
1182 ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN,
1183 OV13858_REG_VALUE_16BIT, d_gain);
1188 static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern)
1193 ret = ov13858_read_reg(ov13858, OV13858_REG_TEST_PATTERN,
1194 OV13858_REG_VALUE_08BIT, &val);
1199 val &= OV13858_TEST_PATTERN_MASK;
1200 val |= (pattern - 1) | OV13858_TEST_PATTERN_ENABLE;
1202 val &= ~OV13858_TEST_PATTERN_ENABLE;
1205 return ov13858_write_reg(ov13858, OV13858_REG_TEST_PATTERN,
1206 OV13858_REG_VALUE_08BIT, val);
1209 static int ov13858_set_ctrl(struct v4l2_ctrl *ctrl)
1211 struct ov13858 *ov13858 = container_of(ctrl->handler,
1212 struct ov13858, ctrl_handler);
1213 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1217 /* Propagate change of current control to all related controls */
1219 case V4L2_CID_VBLANK:
1220 /* Update max exposure while meeting expected vblanking */
1221 max = ov13858->cur_mode->height + ctrl->val - 8;
1222 __v4l2_ctrl_modify_range(ov13858->exposure,
1223 ov13858->exposure->minimum,
1224 max, ov13858->exposure->step, max);
1229 * Applying V4L2 control value only happens
1230 * when power is up for streaming
1232 if (!pm_runtime_get_if_in_use(&client->dev))
1237 case V4L2_CID_ANALOGUE_GAIN:
1238 ret = ov13858_write_reg(ov13858, OV13858_REG_ANALOG_GAIN,
1239 OV13858_REG_VALUE_16BIT, ctrl->val);
1241 case V4L2_CID_DIGITAL_GAIN:
1242 ret = ov13858_update_digital_gain(ov13858, ctrl->val);
1244 case V4L2_CID_EXPOSURE:
1245 ret = ov13858_write_reg(ov13858, OV13858_REG_EXPOSURE,
1246 OV13858_REG_VALUE_24BIT,
1249 case V4L2_CID_VBLANK:
1250 /* Update VTS that meets expected vertical blanking */
1251 ret = ov13858_write_reg(ov13858, OV13858_REG_VTS,
1252 OV13858_REG_VALUE_16BIT,
1253 ov13858->cur_mode->height
1256 case V4L2_CID_TEST_PATTERN:
1257 ret = ov13858_enable_test_pattern(ov13858, ctrl->val);
1260 dev_info(&client->dev,
1261 "ctrl(id:0x%x,val:0x%x) is not handled\n",
1262 ctrl->id, ctrl->val);
1266 pm_runtime_put(&client->dev);
1271 static const struct v4l2_ctrl_ops ov13858_ctrl_ops = {
1272 .s_ctrl = ov13858_set_ctrl,
1275 static int ov13858_enum_mbus_code(struct v4l2_subdev *sd,
1276 struct v4l2_subdev_state *sd_state,
1277 struct v4l2_subdev_mbus_code_enum *code)
1279 /* Only one bayer order(GRBG) is supported */
1280 if (code->index > 0)
1283 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1288 static int ov13858_enum_frame_size(struct v4l2_subdev *sd,
1289 struct v4l2_subdev_state *sd_state,
1290 struct v4l2_subdev_frame_size_enum *fse)
1292 if (fse->index >= ARRAY_SIZE(supported_modes))
1295 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1298 fse->min_width = supported_modes[fse->index].width;
1299 fse->max_width = fse->min_width;
1300 fse->min_height = supported_modes[fse->index].height;
1301 fse->max_height = fse->min_height;
1306 static void ov13858_update_pad_format(const struct ov13858_mode *mode,
1307 struct v4l2_subdev_format *fmt)
1309 fmt->format.width = mode->width;
1310 fmt->format.height = mode->height;
1311 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1312 fmt->format.field = V4L2_FIELD_NONE;
1315 static int ov13858_do_get_pad_format(struct ov13858 *ov13858,
1316 struct v4l2_subdev_state *sd_state,
1317 struct v4l2_subdev_format *fmt)
1319 struct v4l2_mbus_framefmt *framefmt;
1320 struct v4l2_subdev *sd = &ov13858->sd;
1322 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1323 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
1324 fmt->format = *framefmt;
1326 ov13858_update_pad_format(ov13858->cur_mode, fmt);
1332 static int ov13858_get_pad_format(struct v4l2_subdev *sd,
1333 struct v4l2_subdev_state *sd_state,
1334 struct v4l2_subdev_format *fmt)
1336 struct ov13858 *ov13858 = to_ov13858(sd);
1339 mutex_lock(&ov13858->mutex);
1340 ret = ov13858_do_get_pad_format(ov13858, sd_state, fmt);
1341 mutex_unlock(&ov13858->mutex);
1347 ov13858_set_pad_format(struct v4l2_subdev *sd,
1348 struct v4l2_subdev_state *sd_state,
1349 struct v4l2_subdev_format *fmt)
1351 struct ov13858 *ov13858 = to_ov13858(sd);
1352 const struct ov13858_mode *mode;
1353 struct v4l2_mbus_framefmt *framefmt;
1360 mutex_lock(&ov13858->mutex);
1362 /* Only one raw bayer(GRBG) order is supported */
1363 if (fmt->format.code != MEDIA_BUS_FMT_SGRBG10_1X10)
1364 fmt->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1366 mode = v4l2_find_nearest_size(supported_modes,
1367 ARRAY_SIZE(supported_modes),
1369 fmt->format.width, fmt->format.height);
1370 ov13858_update_pad_format(mode, fmt);
1371 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1372 framefmt = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
1373 *framefmt = fmt->format;
1375 ov13858->cur_mode = mode;
1376 __v4l2_ctrl_s_ctrl(ov13858->link_freq, mode->link_freq_index);
1377 link_freq = link_freq_menu_items[mode->link_freq_index];
1378 pixel_rate = link_freq_to_pixel_rate(link_freq);
1379 __v4l2_ctrl_s_ctrl_int64(ov13858->pixel_rate, pixel_rate);
1381 /* Update limits and set FPS to default */
1382 vblank_def = ov13858->cur_mode->vts_def -
1383 ov13858->cur_mode->height;
1384 vblank_min = ov13858->cur_mode->vts_min -
1385 ov13858->cur_mode->height;
1386 __v4l2_ctrl_modify_range(
1387 ov13858->vblank, vblank_min,
1388 OV13858_VTS_MAX - ov13858->cur_mode->height, 1,
1390 __v4l2_ctrl_s_ctrl(ov13858->vblank, vblank_def);
1392 link_freq_configs[mode->link_freq_index].pixels_per_line
1393 - ov13858->cur_mode->width;
1394 __v4l2_ctrl_modify_range(ov13858->hblank, h_blank,
1395 h_blank, 1, h_blank);
1398 mutex_unlock(&ov13858->mutex);
1403 static int ov13858_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
1405 *frames = OV13858_NUM_OF_SKIP_FRAMES;
1410 /* Start streaming */
1411 static int ov13858_start_streaming(struct ov13858 *ov13858)
1413 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1414 const struct ov13858_reg_list *reg_list;
1415 int ret, link_freq_index;
1417 /* Get out of from software reset */
1418 ret = ov13858_write_reg(ov13858, OV13858_REG_SOFTWARE_RST,
1419 OV13858_REG_VALUE_08BIT, OV13858_SOFTWARE_RST);
1421 dev_err(&client->dev, "%s failed to set powerup registers\n",
1427 link_freq_index = ov13858->cur_mode->link_freq_index;
1428 reg_list = &link_freq_configs[link_freq_index].reg_list;
1429 ret = ov13858_write_reg_list(ov13858, reg_list);
1431 dev_err(&client->dev, "%s failed to set plls\n", __func__);
1435 /* Apply default values of current mode */
1436 reg_list = &ov13858->cur_mode->reg_list;
1437 ret = ov13858_write_reg_list(ov13858, reg_list);
1439 dev_err(&client->dev, "%s failed to set mode\n", __func__);
1443 /* Apply customized values from user */
1444 ret = __v4l2_ctrl_handler_setup(ov13858->sd.ctrl_handler);
1448 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1449 OV13858_REG_VALUE_08BIT,
1450 OV13858_MODE_STREAMING);
1453 /* Stop streaming */
1454 static int ov13858_stop_streaming(struct ov13858 *ov13858)
1456 return ov13858_write_reg(ov13858, OV13858_REG_MODE_SELECT,
1457 OV13858_REG_VALUE_08BIT, OV13858_MODE_STANDBY);
1460 static int ov13858_set_stream(struct v4l2_subdev *sd, int enable)
1462 struct ov13858 *ov13858 = to_ov13858(sd);
1463 struct i2c_client *client = v4l2_get_subdevdata(sd);
1466 mutex_lock(&ov13858->mutex);
1469 ret = pm_runtime_resume_and_get(&client->dev);
1474 * Apply default & customized values
1475 * and then start streaming.
1477 ret = ov13858_start_streaming(ov13858);
1481 ov13858_stop_streaming(ov13858);
1482 pm_runtime_put(&client->dev);
1485 mutex_unlock(&ov13858->mutex);
1490 pm_runtime_put(&client->dev);
1492 mutex_unlock(&ov13858->mutex);
1497 /* Verify chip ID */
1498 static int ov13858_identify_module(struct ov13858 *ov13858)
1500 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1504 ret = ov13858_read_reg(ov13858, OV13858_REG_CHIP_ID,
1505 OV13858_REG_VALUE_24BIT, &val);
1509 if (val != OV13858_CHIP_ID) {
1510 dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
1511 OV13858_CHIP_ID, val);
1518 static const struct v4l2_subdev_core_ops ov13858_core_ops = {
1519 .log_status = v4l2_ctrl_subdev_log_status,
1520 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1521 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1524 static const struct v4l2_subdev_video_ops ov13858_video_ops = {
1525 .s_stream = ov13858_set_stream,
1528 static const struct v4l2_subdev_pad_ops ov13858_pad_ops = {
1529 .enum_mbus_code = ov13858_enum_mbus_code,
1530 .get_fmt = ov13858_get_pad_format,
1531 .set_fmt = ov13858_set_pad_format,
1532 .enum_frame_size = ov13858_enum_frame_size,
1535 static const struct v4l2_subdev_sensor_ops ov13858_sensor_ops = {
1536 .g_skip_frames = ov13858_get_skip_frames,
1539 static const struct v4l2_subdev_ops ov13858_subdev_ops = {
1540 .core = &ov13858_core_ops,
1541 .video = &ov13858_video_ops,
1542 .pad = &ov13858_pad_ops,
1543 .sensor = &ov13858_sensor_ops,
1546 static const struct media_entity_operations ov13858_subdev_entity_ops = {
1547 .link_validate = v4l2_subdev_link_validate,
1550 static const struct v4l2_subdev_internal_ops ov13858_internal_ops = {
1551 .open = ov13858_open,
1554 /* Initialize control handlers */
1555 static int ov13858_init_controls(struct ov13858 *ov13858)
1557 struct i2c_client *client = v4l2_get_subdevdata(&ov13858->sd);
1558 struct v4l2_fwnode_device_properties props;
1559 struct v4l2_ctrl_handler *ctrl_hdlr;
1566 const struct ov13858_mode *mode;
1569 ctrl_hdlr = &ov13858->ctrl_handler;
1570 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
1574 mutex_init(&ov13858->mutex);
1575 ctrl_hdlr->lock = &ov13858->mutex;
1576 ov13858->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
1579 OV13858_NUM_OF_LINK_FREQS - 1,
1581 link_freq_menu_items);
1582 if (ov13858->link_freq)
1583 ov13858->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1585 pixel_rate_max = link_freq_to_pixel_rate(link_freq_menu_items[0]);
1586 pixel_rate_min = link_freq_to_pixel_rate(link_freq_menu_items[1]);
1587 /* By default, PIXEL_RATE is read only */
1588 ov13858->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops,
1589 V4L2_CID_PIXEL_RATE,
1590 pixel_rate_min, pixel_rate_max,
1593 mode = ov13858->cur_mode;
1594 vblank_def = mode->vts_def - mode->height;
1595 vblank_min = mode->vts_min - mode->height;
1596 ov13858->vblank = v4l2_ctrl_new_std(
1597 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_VBLANK,
1598 vblank_min, OV13858_VTS_MAX - mode->height, 1,
1601 hblank = link_freq_configs[mode->link_freq_index].pixels_per_line -
1603 ov13858->hblank = v4l2_ctrl_new_std(
1604 ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_HBLANK,
1605 hblank, hblank, 1, hblank);
1606 if (ov13858->hblank)
1607 ov13858->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1609 exposure_max = mode->vts_def - 8;
1610 ov13858->exposure = v4l2_ctrl_new_std(
1611 ctrl_hdlr, &ov13858_ctrl_ops,
1612 V4L2_CID_EXPOSURE, OV13858_EXPOSURE_MIN,
1613 exposure_max, OV13858_EXPOSURE_STEP,
1614 OV13858_EXPOSURE_DEFAULT);
1616 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1617 OV13858_ANA_GAIN_MIN, OV13858_ANA_GAIN_MAX,
1618 OV13858_ANA_GAIN_STEP, OV13858_ANA_GAIN_DEFAULT);
1621 v4l2_ctrl_new_std(ctrl_hdlr, &ov13858_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1622 OV13858_DGTL_GAIN_MIN, OV13858_DGTL_GAIN_MAX,
1623 OV13858_DGTL_GAIN_STEP, OV13858_DGTL_GAIN_DEFAULT);
1625 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov13858_ctrl_ops,
1626 V4L2_CID_TEST_PATTERN,
1627 ARRAY_SIZE(ov13858_test_pattern_menu) - 1,
1628 0, 0, ov13858_test_pattern_menu);
1629 if (ctrl_hdlr->error) {
1630 ret = ctrl_hdlr->error;
1631 dev_err(&client->dev, "%s control init failed (%d)\n",
1636 ret = v4l2_fwnode_device_parse(&client->dev, &props);
1640 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov13858_ctrl_ops,
1645 ov13858->sd.ctrl_handler = ctrl_hdlr;
1650 v4l2_ctrl_handler_free(ctrl_hdlr);
1651 mutex_destroy(&ov13858->mutex);
1656 static void ov13858_free_controls(struct ov13858 *ov13858)
1658 v4l2_ctrl_handler_free(ov13858->sd.ctrl_handler);
1659 mutex_destroy(&ov13858->mutex);
1662 static int ov13858_probe(struct i2c_client *client)
1664 struct ov13858 *ov13858;
1668 device_property_read_u32(&client->dev, "clock-frequency", &val);
1669 if (val != 19200000)
1672 ov13858 = devm_kzalloc(&client->dev, sizeof(*ov13858), GFP_KERNEL);
1676 /* Initialize subdev */
1677 v4l2_i2c_subdev_init(&ov13858->sd, client, &ov13858_subdev_ops);
1679 /* Check module identity */
1680 ret = ov13858_identify_module(ov13858);
1682 dev_err(&client->dev, "failed to find sensor: %d\n", ret);
1686 /* Set default mode to max resolution */
1687 ov13858->cur_mode = &supported_modes[0];
1689 ret = ov13858_init_controls(ov13858);
1693 /* Initialize subdev */
1694 ov13858->sd.internal_ops = &ov13858_internal_ops;
1695 ov13858->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1696 V4L2_SUBDEV_FL_HAS_EVENTS;
1697 ov13858->sd.entity.ops = &ov13858_subdev_entity_ops;
1698 ov13858->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1700 /* Initialize source pad */
1701 ov13858->pad.flags = MEDIA_PAD_FL_SOURCE;
1702 ret = media_entity_pads_init(&ov13858->sd.entity, 1, &ov13858->pad);
1704 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1705 goto error_handler_free;
1708 ret = v4l2_async_register_subdev_sensor(&ov13858->sd);
1710 goto error_media_entity;
1713 * Device is already turned on by i2c-core with ACPI domain PM.
1714 * Enable runtime PM and turn off the device.
1716 pm_runtime_set_active(&client->dev);
1717 pm_runtime_enable(&client->dev);
1718 pm_runtime_idle(&client->dev);
1723 media_entity_cleanup(&ov13858->sd.entity);
1726 ov13858_free_controls(ov13858);
1727 dev_err(&client->dev, "%s failed:%d\n", __func__, ret);
1732 static void ov13858_remove(struct i2c_client *client)
1734 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1735 struct ov13858 *ov13858 = to_ov13858(sd);
1737 v4l2_async_unregister_subdev(sd);
1738 media_entity_cleanup(&sd->entity);
1739 ov13858_free_controls(ov13858);
1741 pm_runtime_disable(&client->dev);
1744 static const struct i2c_device_id ov13858_id_table[] = {
1749 MODULE_DEVICE_TABLE(i2c, ov13858_id_table);
1752 static const struct acpi_device_id ov13858_acpi_ids[] = {
1757 MODULE_DEVICE_TABLE(acpi, ov13858_acpi_ids);
1760 static struct i2c_driver ov13858_i2c_driver = {
1763 .acpi_match_table = ACPI_PTR(ov13858_acpi_ids),
1765 .probe = ov13858_probe,
1766 .remove = ov13858_remove,
1767 .id_table = ov13858_id_table,
1770 module_i2c_driver(ov13858_i2c_driver);
1772 MODULE_AUTHOR("Kan, Chris <chris.kan@intel.com>");
1773 MODULE_AUTHOR("Rapolu, Chiranjeevi");
1774 MODULE_AUTHOR("Yang, Hyungwoo");
1775 MODULE_DESCRIPTION("Omnivision ov13858 sensor driver");
1776 MODULE_LICENSE("GPL v2");