2 * Driver for MT9V022, MT9V024, MT9V032, and MT9V034 CMOS Image Sensors
4 * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6 * Based on the MT9M001 driver,
8 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/log2.h>
19 #include <linux/mutex.h>
21 #include <linux/of_gpio.h>
22 #include <linux/regmap.h>
23 #include <linux/slab.h>
24 #include <linux/videodev2.h>
25 #include <linux/v4l2-mediabus.h>
26 #include <linux/module.h>
28 #include <media/mt9v032.h>
29 #include <media/v4l2-ctrls.h>
30 #include <media/v4l2-device.h>
31 #include <media/v4l2-of.h>
32 #include <media/v4l2-subdev.h>
34 /* The first four rows are black rows. The active area spans 753x481 pixels. */
35 #define MT9V032_PIXEL_ARRAY_HEIGHT 485
36 #define MT9V032_PIXEL_ARRAY_WIDTH 753
38 #define MT9V032_SYSCLK_FREQ_DEF 26600000
40 #define MT9V032_CHIP_VERSION 0x00
41 #define MT9V032_CHIP_ID_REV1 0x1311
42 #define MT9V032_CHIP_ID_REV3 0x1313
43 #define MT9V034_CHIP_ID_REV1 0X1324
44 #define MT9V032_COLUMN_START 0x01
45 #define MT9V032_COLUMN_START_MIN 1
46 #define MT9V032_COLUMN_START_DEF 1
47 #define MT9V032_COLUMN_START_MAX 752
48 #define MT9V032_ROW_START 0x02
49 #define MT9V032_ROW_START_MIN 4
50 #define MT9V032_ROW_START_DEF 5
51 #define MT9V032_ROW_START_MAX 482
52 #define MT9V032_WINDOW_HEIGHT 0x03
53 #define MT9V032_WINDOW_HEIGHT_MIN 1
54 #define MT9V032_WINDOW_HEIGHT_DEF 480
55 #define MT9V032_WINDOW_HEIGHT_MAX 480
56 #define MT9V032_WINDOW_WIDTH 0x04
57 #define MT9V032_WINDOW_WIDTH_MIN 1
58 #define MT9V032_WINDOW_WIDTH_DEF 752
59 #define MT9V032_WINDOW_WIDTH_MAX 752
60 #define MT9V032_HORIZONTAL_BLANKING 0x05
61 #define MT9V032_HORIZONTAL_BLANKING_MIN 43
62 #define MT9V034_HORIZONTAL_BLANKING_MIN 61
63 #define MT9V032_HORIZONTAL_BLANKING_DEF 94
64 #define MT9V032_HORIZONTAL_BLANKING_MAX 1023
65 #define MT9V032_VERTICAL_BLANKING 0x06
66 #define MT9V032_VERTICAL_BLANKING_MIN 4
67 #define MT9V034_VERTICAL_BLANKING_MIN 2
68 #define MT9V032_VERTICAL_BLANKING_DEF 45
69 #define MT9V032_VERTICAL_BLANKING_MAX 3000
70 #define MT9V034_VERTICAL_BLANKING_MAX 32288
71 #define MT9V032_CHIP_CONTROL 0x07
72 #define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3)
73 #define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7)
74 #define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8)
75 #define MT9V032_SHUTTER_WIDTH1 0x08
76 #define MT9V032_SHUTTER_WIDTH2 0x09
77 #define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a
78 #define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b
79 #define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1
80 #define MT9V034_TOTAL_SHUTTER_WIDTH_MIN 0
81 #define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480
82 #define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767
83 #define MT9V034_TOTAL_SHUTTER_WIDTH_MAX 32765
84 #define MT9V032_RESET 0x0c
85 #define MT9V032_READ_MODE 0x0d
86 #define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0)
87 #define MT9V032_READ_MODE_ROW_BIN_SHIFT 0
88 #define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2)
89 #define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2
90 #define MT9V032_READ_MODE_ROW_FLIP (1 << 4)
91 #define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5)
92 #define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6)
93 #define MT9V032_READ_MODE_DARK_ROWS (1 << 7)
94 #define MT9V032_READ_MODE_RESERVED 0x0300
95 #define MT9V032_PIXEL_OPERATION_MODE 0x0f
96 #define MT9V034_PIXEL_OPERATION_MODE_HDR (1 << 0)
97 #define MT9V034_PIXEL_OPERATION_MODE_COLOR (1 << 1)
98 #define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2)
99 #define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6)
100 #define MT9V032_ANALOG_GAIN 0x35
101 #define MT9V032_ANALOG_GAIN_MIN 16
102 #define MT9V032_ANALOG_GAIN_DEF 16
103 #define MT9V032_ANALOG_GAIN_MAX 64
104 #define MT9V032_MAX_ANALOG_GAIN 0x36
105 #define MT9V032_MAX_ANALOG_GAIN_MAX 127
106 #define MT9V032_FRAME_DARK_AVERAGE 0x42
107 #define MT9V032_DARK_AVG_THRESH 0x46
108 #define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0)
109 #define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0
110 #define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8)
111 #define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8
112 #define MT9V032_ROW_NOISE_CORR_CONTROL 0x70
113 #define MT9V034_ROW_NOISE_CORR_ENABLE (1 << 0)
114 #define MT9V034_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1)
115 #define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5)
116 #define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7)
117 #define MT9V032_PIXEL_CLOCK 0x74
118 #define MT9V034_PIXEL_CLOCK 0x72
119 #define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0)
120 #define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1)
121 #define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2)
122 #define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3)
123 #define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4)
124 #define MT9V032_TEST_PATTERN 0x7f
125 #define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0)
126 #define MT9V032_TEST_PATTERN_DATA_SHIFT 0
127 #define MT9V032_TEST_PATTERN_USE_DATA (1 << 10)
128 #define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11)
129 #define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11)
130 #define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11)
131 #define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11)
132 #define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11)
133 #define MT9V032_TEST_PATTERN_ENABLE (1 << 13)
134 #define MT9V032_TEST_PATTERN_FLIP (1 << 14)
135 #define MT9V032_AEC_AGC_ENABLE 0xaf
136 #define MT9V032_AEC_ENABLE (1 << 0)
137 #define MT9V032_AGC_ENABLE (1 << 1)
138 #define MT9V032_THERMAL_INFO 0xc1
141 MT9V032_MODEL_V022_COLOR, /* MT9V022IX7ATC */
142 MT9V032_MODEL_V022_MONO, /* MT9V022IX7ATM */
143 MT9V032_MODEL_V024_COLOR, /* MT9V024IA7XTC */
144 MT9V032_MODEL_V024_MONO, /* MT9V024IA7XTM */
145 MT9V032_MODEL_V032_COLOR, /* MT9V032C12STM */
146 MT9V032_MODEL_V032_MONO, /* MT9V032C12STC */
147 MT9V032_MODEL_V034_COLOR,
148 MT9V032_MODEL_V034_MONO,
151 struct mt9v032_model_version {
152 unsigned int version;
156 struct mt9v032_model_data {
157 unsigned int min_row_time;
158 unsigned int min_hblank;
159 unsigned int min_vblank;
160 unsigned int max_vblank;
161 unsigned int min_shutter;
162 unsigned int max_shutter;
163 unsigned int pclk_reg;
166 struct mt9v032_model_info {
167 const struct mt9v032_model_data *data;
171 static const struct mt9v032_model_version mt9v032_versions[] = {
172 { MT9V032_CHIP_ID_REV1, "MT9V022/MT9V032 rev1/2" },
173 { MT9V032_CHIP_ID_REV3, "MT9V022/MT9V032 rev3" },
174 { MT9V034_CHIP_ID_REV1, "MT9V024/MT9V034 rev1" },
177 static const struct mt9v032_model_data mt9v032_model_data[] = {
179 /* MT9V022, MT9V032 revisions 1/2/3 */
181 .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN,
182 .min_vblank = MT9V032_VERTICAL_BLANKING_MIN,
183 .max_vblank = MT9V032_VERTICAL_BLANKING_MAX,
184 .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN,
185 .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX,
186 .pclk_reg = MT9V032_PIXEL_CLOCK,
188 /* MT9V024, MT9V034 */
190 .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN,
191 .min_vblank = MT9V034_VERTICAL_BLANKING_MIN,
192 .max_vblank = MT9V034_VERTICAL_BLANKING_MAX,
193 .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN,
194 .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX,
195 .pclk_reg = MT9V034_PIXEL_CLOCK,
199 static const struct mt9v032_model_info mt9v032_models[] = {
200 [MT9V032_MODEL_V022_COLOR] = {
201 .data = &mt9v032_model_data[0],
204 [MT9V032_MODEL_V022_MONO] = {
205 .data = &mt9v032_model_data[0],
208 [MT9V032_MODEL_V024_COLOR] = {
209 .data = &mt9v032_model_data[1],
212 [MT9V032_MODEL_V024_MONO] = {
213 .data = &mt9v032_model_data[1],
216 [MT9V032_MODEL_V032_COLOR] = {
217 .data = &mt9v032_model_data[0],
220 [MT9V032_MODEL_V032_MONO] = {
221 .data = &mt9v032_model_data[0],
224 [MT9V032_MODEL_V034_COLOR] = {
225 .data = &mt9v032_model_data[1],
228 [MT9V032_MODEL_V034_MONO] = {
229 .data = &mt9v032_model_data[1],
235 struct v4l2_subdev subdev;
236 struct media_pad pad;
238 struct v4l2_mbus_framefmt format;
239 struct v4l2_rect crop;
243 struct v4l2_ctrl_handler ctrls;
245 struct v4l2_ctrl *link_freq;
246 struct v4l2_ctrl *pixel_rate;
249 struct mutex power_lock;
252 struct regmap *regmap;
255 struct mt9v032_platform_data *pdata;
256 const struct mt9v032_model_info *model;
257 const struct mt9v032_model_version *version;
263 struct v4l2_ctrl *test_pattern;
264 struct v4l2_ctrl *test_pattern_color;
268 static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
270 return container_of(sd, struct mt9v032, subdev);
274 mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable)
276 struct regmap *map = mt9v032->regmap;
277 u16 value = mt9v032->aec_agc;
285 ret = regmap_write(map, MT9V032_AEC_AGC_ENABLE, value);
289 mt9v032->aec_agc = value;
294 mt9v032_update_hblank(struct mt9v032 *mt9v032)
296 struct v4l2_rect *crop = &mt9v032->crop;
297 unsigned int min_hblank = mt9v032->model->data->min_hblank;
300 if (mt9v032->version->version == MT9V034_CHIP_ID_REV1)
301 min_hblank += (mt9v032->hratio - 1) * 10;
302 min_hblank = max_t(int, mt9v032->model->data->min_row_time - crop->width,
304 hblank = max_t(unsigned int, mt9v032->hblank, min_hblank);
306 return regmap_write(mt9v032->regmap, MT9V032_HORIZONTAL_BLANKING,
310 static int mt9v032_power_on(struct mt9v032 *mt9v032)
312 struct regmap *map = mt9v032->regmap;
315 ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk);
319 ret = clk_prepare_enable(mt9v032->clk);
325 /* Reset the chip and stop data read out */
326 ret = regmap_write(map, MT9V032_RESET, 1);
330 ret = regmap_write(map, MT9V032_RESET, 0);
334 return regmap_write(map, MT9V032_CHIP_CONTROL, 0);
337 static void mt9v032_power_off(struct mt9v032 *mt9v032)
339 clk_disable_unprepare(mt9v032->clk);
342 static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on)
344 struct regmap *map = mt9v032->regmap;
348 mt9v032_power_off(mt9v032);
352 ret = mt9v032_power_on(mt9v032);
356 /* Configure the pixel clock polarity */
357 if (mt9v032->pdata && mt9v032->pdata->clk_pol) {
358 ret = regmap_write(map, mt9v032->model->data->pclk_reg,
359 MT9V032_PIXEL_CLOCK_INV_PXL_CLK);
364 /* Disable the noise correction algorithm and restore the controls. */
365 ret = regmap_write(map, MT9V032_ROW_NOISE_CORR_CONTROL, 0);
369 return v4l2_ctrl_handler_setup(&mt9v032->ctrls);
372 /* -----------------------------------------------------------------------------
373 * V4L2 subdev video operations
376 static struct v4l2_mbus_framefmt *
377 __mt9v032_get_pad_format(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg,
378 unsigned int pad, enum v4l2_subdev_format_whence which)
381 case V4L2_SUBDEV_FORMAT_TRY:
382 return v4l2_subdev_get_try_format(&mt9v032->subdev, cfg, pad);
383 case V4L2_SUBDEV_FORMAT_ACTIVE:
384 return &mt9v032->format;
390 static struct v4l2_rect *
391 __mt9v032_get_pad_crop(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg,
392 unsigned int pad, enum v4l2_subdev_format_whence which)
395 case V4L2_SUBDEV_FORMAT_TRY:
396 return v4l2_subdev_get_try_crop(&mt9v032->subdev, cfg, pad);
397 case V4L2_SUBDEV_FORMAT_ACTIVE:
398 return &mt9v032->crop;
404 static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable)
406 const u16 mode = MT9V032_CHIP_CONTROL_MASTER_MODE
407 | MT9V032_CHIP_CONTROL_DOUT_ENABLE
408 | MT9V032_CHIP_CONTROL_SEQUENTIAL;
409 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
410 struct v4l2_rect *crop = &mt9v032->crop;
411 struct regmap *map = mt9v032->regmap;
417 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, 0);
419 /* Configure the window size and row/column bin */
420 hbin = fls(mt9v032->hratio) - 1;
421 vbin = fls(mt9v032->vratio) - 1;
422 ret = regmap_update_bits(map, MT9V032_READ_MODE,
423 ~MT9V032_READ_MODE_RESERVED,
424 hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT |
425 vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT);
429 ret = regmap_write(map, MT9V032_COLUMN_START, crop->left);
433 ret = regmap_write(map, MT9V032_ROW_START, crop->top);
437 ret = regmap_write(map, MT9V032_WINDOW_WIDTH, crop->width);
441 ret = regmap_write(map, MT9V032_WINDOW_HEIGHT, crop->height);
445 ret = mt9v032_update_hblank(mt9v032);
449 /* Switch to master "normal" mode */
450 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, mode);
453 static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev,
454 struct v4l2_subdev_pad_config *cfg,
455 struct v4l2_subdev_mbus_code_enum *code)
457 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
462 code->code = mt9v032->format.code;
466 static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev,
467 struct v4l2_subdev_pad_config *cfg,
468 struct v4l2_subdev_frame_size_enum *fse)
470 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
474 if (mt9v032->format.code != fse->code)
477 fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index);
478 fse->max_width = fse->min_width;
479 fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index);
480 fse->max_height = fse->min_height;
485 static int mt9v032_get_format(struct v4l2_subdev *subdev,
486 struct v4l2_subdev_pad_config *cfg,
487 struct v4l2_subdev_format *format)
489 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
491 format->format = *__mt9v032_get_pad_format(mt9v032, cfg, format->pad,
496 static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032)
498 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
501 ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate,
502 mt9v032->sysclk / mt9v032->hratio);
504 dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret);
507 static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output)
509 /* Compute the power-of-two binning factor closest to the input size to
510 * output size ratio. Given that the output size is bounded by input/4
511 * and input, a generic implementation would be an ineffective luxury.
513 if (output * 3 > input * 2)
515 if (output * 3 > input)
520 static int mt9v032_set_format(struct v4l2_subdev *subdev,
521 struct v4l2_subdev_pad_config *cfg,
522 struct v4l2_subdev_format *format)
524 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
525 struct v4l2_mbus_framefmt *__format;
526 struct v4l2_rect *__crop;
532 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, format->pad,
535 /* Clamp the width and height to avoid dividing by zero. */
536 width = clamp(ALIGN(format->format.width, 2),
537 max_t(unsigned int, __crop->width / 4,
538 MT9V032_WINDOW_WIDTH_MIN),
540 height = clamp(ALIGN(format->format.height, 2),
541 max_t(unsigned int, __crop->height / 4,
542 MT9V032_WINDOW_HEIGHT_MIN),
545 hratio = mt9v032_calc_ratio(__crop->width, width);
546 vratio = mt9v032_calc_ratio(__crop->height, height);
548 __format = __mt9v032_get_pad_format(mt9v032, cfg, format->pad,
550 __format->width = __crop->width / hratio;
551 __format->height = __crop->height / vratio;
553 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
554 mt9v032->hratio = hratio;
555 mt9v032->vratio = vratio;
556 mt9v032_configure_pixel_rate(mt9v032);
559 format->format = *__format;
564 static int mt9v032_get_selection(struct v4l2_subdev *subdev,
565 struct v4l2_subdev_pad_config *cfg,
566 struct v4l2_subdev_selection *sel)
568 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
570 if (sel->target != V4L2_SEL_TGT_CROP)
573 sel->r = *__mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which);
577 static int mt9v032_set_selection(struct v4l2_subdev *subdev,
578 struct v4l2_subdev_pad_config *cfg,
579 struct v4l2_subdev_selection *sel)
581 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
582 struct v4l2_mbus_framefmt *__format;
583 struct v4l2_rect *__crop;
584 struct v4l2_rect rect;
586 if (sel->target != V4L2_SEL_TGT_CROP)
589 /* Clamp the crop rectangle boundaries and align them to a non multiple
590 * of 2 pixels to ensure a GRBG Bayer pattern.
592 rect.left = clamp(ALIGN(sel->r.left + 1, 2) - 1,
593 MT9V032_COLUMN_START_MIN,
594 MT9V032_COLUMN_START_MAX);
595 rect.top = clamp(ALIGN(sel->r.top + 1, 2) - 1,
596 MT9V032_ROW_START_MIN,
597 MT9V032_ROW_START_MAX);
598 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2),
599 MT9V032_WINDOW_WIDTH_MIN,
600 MT9V032_WINDOW_WIDTH_MAX);
601 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2),
602 MT9V032_WINDOW_HEIGHT_MIN,
603 MT9V032_WINDOW_HEIGHT_MAX);
605 rect.width = min_t(unsigned int,
606 rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left);
607 rect.height = min_t(unsigned int,
608 rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top);
610 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which);
612 if (rect.width != __crop->width || rect.height != __crop->height) {
613 /* Reset the output image size if the crop rectangle size has
616 __format = __mt9v032_get_pad_format(mt9v032, cfg, sel->pad,
618 __format->width = rect.width;
619 __format->height = rect.height;
620 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
623 mt9v032_configure_pixel_rate(mt9v032);
633 /* -----------------------------------------------------------------------------
634 * V4L2 subdev control operations
637 #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
639 static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
641 struct mt9v032 *mt9v032 =
642 container_of(ctrl->handler, struct mt9v032, ctrls);
643 struct regmap *map = mt9v032->regmap;
648 case V4L2_CID_AUTOGAIN:
649 return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE,
653 return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val);
655 case V4L2_CID_EXPOSURE_AUTO:
656 return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE,
659 case V4L2_CID_EXPOSURE:
660 return regmap_write(map, MT9V032_TOTAL_SHUTTER_WIDTH,
663 case V4L2_CID_HBLANK:
664 mt9v032->hblank = ctrl->val;
665 return mt9v032_update_hblank(mt9v032);
667 case V4L2_CID_VBLANK:
668 return regmap_write(map, MT9V032_VERTICAL_BLANKING,
671 case V4L2_CID_PIXEL_RATE:
672 case V4L2_CID_LINK_FREQ:
673 if (mt9v032->link_freq == NULL)
676 freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val];
677 *mt9v032->pixel_rate->p_new.p_s64 = freq;
678 mt9v032->sysclk = freq;
681 case V4L2_CID_TEST_PATTERN:
682 switch (mt9v032->test_pattern->val) {
687 data = MT9V032_TEST_PATTERN_GRAY_VERTICAL
688 | MT9V032_TEST_PATTERN_ENABLE;
691 data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL
692 | MT9V032_TEST_PATTERN_ENABLE;
695 data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL
696 | MT9V032_TEST_PATTERN_ENABLE;
699 data = (mt9v032->test_pattern_color->val <<
700 MT9V032_TEST_PATTERN_DATA_SHIFT)
701 | MT9V032_TEST_PATTERN_USE_DATA
702 | MT9V032_TEST_PATTERN_ENABLE
703 | MT9V032_TEST_PATTERN_FLIP;
706 return regmap_write(map, MT9V032_TEST_PATTERN, data);
712 static struct v4l2_ctrl_ops mt9v032_ctrl_ops = {
713 .s_ctrl = mt9v032_s_ctrl,
716 static const char * const mt9v032_test_pattern_menu[] = {
718 "Gray Vertical Shade",
719 "Gray Horizontal Shade",
720 "Gray Diagonal Shade",
724 static const struct v4l2_ctrl_config mt9v032_test_pattern_color = {
725 .ops = &mt9v032_ctrl_ops,
726 .id = V4L2_CID_TEST_PATTERN_COLOR,
727 .type = V4L2_CTRL_TYPE_INTEGER,
728 .name = "Test Pattern Color",
736 /* -----------------------------------------------------------------------------
737 * V4L2 subdev core operations
740 static int mt9v032_set_power(struct v4l2_subdev *subdev, int on)
742 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
745 mutex_lock(&mt9v032->power_lock);
747 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
748 * update the power state.
750 if (mt9v032->power_count == !on) {
751 ret = __mt9v032_set_power(mt9v032, !!on);
756 /* Update the power count. */
757 mt9v032->power_count += on ? 1 : -1;
758 WARN_ON(mt9v032->power_count < 0);
761 mutex_unlock(&mt9v032->power_lock);
765 /* -----------------------------------------------------------------------------
766 * V4L2 subdev internal operations
769 static int mt9v032_registered(struct v4l2_subdev *subdev)
771 struct i2c_client *client = v4l2_get_subdevdata(subdev);
772 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
777 dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n",
780 ret = mt9v032_power_on(mt9v032);
782 dev_err(&client->dev, "MT9V032 power up failed\n");
786 /* Read and check the sensor version */
787 ret = regmap_read(mt9v032->regmap, MT9V032_CHIP_VERSION, &version);
789 dev_err(&client->dev, "Failed reading chip version\n");
793 for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) {
794 if (mt9v032_versions[i].version == version) {
795 mt9v032->version = &mt9v032_versions[i];
800 if (mt9v032->version == NULL) {
801 dev_err(&client->dev, "Unsupported chip version 0x%04x\n",
806 mt9v032_power_off(mt9v032);
808 dev_info(&client->dev, "%s detected at address 0x%02x\n",
809 mt9v032->version->name, client->addr);
811 mt9v032_configure_pixel_rate(mt9v032);
816 static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
818 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
819 struct v4l2_mbus_framefmt *format;
820 struct v4l2_rect *crop;
822 crop = v4l2_subdev_get_try_crop(subdev, fh->pad, 0);
823 crop->left = MT9V032_COLUMN_START_DEF;
824 crop->top = MT9V032_ROW_START_DEF;
825 crop->width = MT9V032_WINDOW_WIDTH_DEF;
826 crop->height = MT9V032_WINDOW_HEIGHT_DEF;
828 format = v4l2_subdev_get_try_format(subdev, fh->pad, 0);
830 if (mt9v032->model->color)
831 format->code = MEDIA_BUS_FMT_SGRBG10_1X10;
833 format->code = MEDIA_BUS_FMT_Y10_1X10;
835 format->width = MT9V032_WINDOW_WIDTH_DEF;
836 format->height = MT9V032_WINDOW_HEIGHT_DEF;
837 format->field = V4L2_FIELD_NONE;
838 format->colorspace = V4L2_COLORSPACE_SRGB;
840 return mt9v032_set_power(subdev, 1);
843 static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
845 return mt9v032_set_power(subdev, 0);
848 static struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = {
849 .s_power = mt9v032_set_power,
852 static struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = {
853 .s_stream = mt9v032_s_stream,
856 static struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = {
857 .enum_mbus_code = mt9v032_enum_mbus_code,
858 .enum_frame_size = mt9v032_enum_frame_size,
859 .get_fmt = mt9v032_get_format,
860 .set_fmt = mt9v032_set_format,
861 .get_selection = mt9v032_get_selection,
862 .set_selection = mt9v032_set_selection,
865 static struct v4l2_subdev_ops mt9v032_subdev_ops = {
866 .core = &mt9v032_subdev_core_ops,
867 .video = &mt9v032_subdev_video_ops,
868 .pad = &mt9v032_subdev_pad_ops,
871 static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = {
872 .registered = mt9v032_registered,
873 .open = mt9v032_open,
874 .close = mt9v032_close,
877 static const struct regmap_config mt9v032_regmap_config = {
880 .max_register = 0xff,
881 .cache_type = REGCACHE_RBTREE,
884 /* -----------------------------------------------------------------------------
885 * Driver initialization and probing
888 static struct mt9v032_platform_data *
889 mt9v032_get_pdata(struct i2c_client *client)
891 struct mt9v032_platform_data *pdata = NULL;
892 struct v4l2_of_endpoint endpoint;
893 struct device_node *np;
894 struct property *prop;
896 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
897 return client->dev.platform_data;
899 np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
903 if (v4l2_of_parse_endpoint(np, &endpoint) < 0)
906 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
910 prop = of_find_property(np, "link-frequencies", NULL);
913 size_t size = prop->length / sizeof(*link_freqs);
915 link_freqs = devm_kcalloc(&client->dev, size,
916 sizeof(*link_freqs), GFP_KERNEL);
920 if (of_property_read_u64_array(np, "link-frequencies",
921 link_freqs, size) < 0)
924 pdata->link_freqs = link_freqs;
925 pdata->link_def_freq = link_freqs[0];
928 pdata->clk_pol = !!(endpoint.bus.parallel.flags &
929 V4L2_MBUS_PCLK_SAMPLE_RISING);
936 static int mt9v032_probe(struct i2c_client *client,
937 const struct i2c_device_id *did)
939 struct mt9v032_platform_data *pdata = mt9v032_get_pdata(client);
940 struct mt9v032 *mt9v032;
944 if (!i2c_check_functionality(client->adapter,
945 I2C_FUNC_SMBUS_WORD_DATA)) {
946 dev_warn(&client->adapter->dev,
947 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
951 mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL);
955 mt9v032->regmap = devm_regmap_init_i2c(client, &mt9v032_regmap_config);
956 if (IS_ERR(mt9v032->regmap))
957 return PTR_ERR(mt9v032->regmap);
959 mt9v032->clk = devm_clk_get(&client->dev, NULL);
960 if (IS_ERR(mt9v032->clk))
961 return PTR_ERR(mt9v032->clk);
963 mutex_init(&mt9v032->power_lock);
964 mt9v032->pdata = pdata;
965 mt9v032->model = (const void *)did->driver_data;
967 v4l2_ctrl_handler_init(&mt9v032->ctrls, 10);
969 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
970 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
971 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
972 V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN,
973 MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF);
974 v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops,
975 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
977 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
978 V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter,
979 mt9v032->model->data->max_shutter, 1,
980 MT9V032_TOTAL_SHUTTER_WIDTH_DEF);
981 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
982 V4L2_CID_HBLANK, mt9v032->model->data->min_hblank,
983 MT9V032_HORIZONTAL_BLANKING_MAX, 1,
984 MT9V032_HORIZONTAL_BLANKING_DEF);
985 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
986 V4L2_CID_VBLANK, mt9v032->model->data->min_vblank,
987 mt9v032->model->data->max_vblank, 1,
988 MT9V032_VERTICAL_BLANKING_DEF);
989 mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls,
990 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN,
991 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0,
992 mt9v032_test_pattern_menu);
993 mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls,
994 &mt9v032_test_pattern_color, NULL);
996 v4l2_ctrl_cluster(2, &mt9v032->test_pattern);
998 mt9v032->pixel_rate =
999 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1000 V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
1002 if (pdata && pdata->link_freqs) {
1003 unsigned int def = 0;
1005 for (i = 0; pdata->link_freqs[i]; ++i) {
1006 if (pdata->link_freqs[i] == pdata->link_def_freq)
1010 mt9v032->link_freq =
1011 v4l2_ctrl_new_int_menu(&mt9v032->ctrls,
1013 V4L2_CID_LINK_FREQ, i - 1, def,
1015 v4l2_ctrl_cluster(2, &mt9v032->link_freq);
1019 mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
1021 if (mt9v032->ctrls.error) {
1022 dev_err(&client->dev, "control initialization error %d\n",
1023 mt9v032->ctrls.error);
1024 ret = mt9v032->ctrls.error;
1028 mt9v032->crop.left = MT9V032_COLUMN_START_DEF;
1029 mt9v032->crop.top = MT9V032_ROW_START_DEF;
1030 mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF;
1031 mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF;
1033 if (mt9v032->model->color)
1034 mt9v032->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1036 mt9v032->format.code = MEDIA_BUS_FMT_Y10_1X10;
1038 mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF;
1039 mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF;
1040 mt9v032->format.field = V4L2_FIELD_NONE;
1041 mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB;
1043 mt9v032->hratio = 1;
1044 mt9v032->vratio = 1;
1046 mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE;
1047 mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF;
1048 mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF;
1050 v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops);
1051 mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops;
1052 mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1054 mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE;
1055 ret = media_entity_init(&mt9v032->subdev.entity, 1, &mt9v032->pad, 0);
1059 mt9v032->subdev.dev = &client->dev;
1060 ret = v4l2_async_register_subdev(&mt9v032->subdev);
1067 media_entity_cleanup(&mt9v032->subdev.entity);
1068 v4l2_ctrl_handler_free(&mt9v032->ctrls);
1072 static int mt9v032_remove(struct i2c_client *client)
1074 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1075 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
1077 v4l2_async_unregister_subdev(subdev);
1078 v4l2_ctrl_handler_free(&mt9v032->ctrls);
1079 media_entity_cleanup(&subdev->entity);
1084 static const struct i2c_device_id mt9v032_id[] = {
1085 { "mt9v022", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_COLOR] },
1086 { "mt9v022m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_MONO] },
1087 { "mt9v024", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_COLOR] },
1088 { "mt9v024m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_MONO] },
1089 { "mt9v032", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_COLOR] },
1090 { "mt9v032m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_MONO] },
1091 { "mt9v034", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_COLOR] },
1092 { "mt9v034m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_MONO] },
1095 MODULE_DEVICE_TABLE(i2c, mt9v032_id);
1097 #if IS_ENABLED(CONFIG_OF)
1098 static const struct of_device_id mt9v032_of_match[] = {
1099 { .compatible = "aptina,mt9v022" },
1100 { .compatible = "aptina,mt9v022m" },
1101 { .compatible = "aptina,mt9v024" },
1102 { .compatible = "aptina,mt9v024m" },
1103 { .compatible = "aptina,mt9v032" },
1104 { .compatible = "aptina,mt9v032m" },
1105 { .compatible = "aptina,mt9v034" },
1106 { .compatible = "aptina,mt9v034m" },
1109 MODULE_DEVICE_TABLE(of, mt9v032_of_match);
1112 static struct i2c_driver mt9v032_driver = {
1115 .of_match_table = of_match_ptr(mt9v032_of_match),
1117 .probe = mt9v032_probe,
1118 .remove = mt9v032_remove,
1119 .id_table = mt9v032_id,
1122 module_i2c_driver(mt9v032_driver);
1124 MODULE_DESCRIPTION("Aptina MT9V032 Camera driver");
1125 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1126 MODULE_LICENSE("GPL");