2 * Driver for MT9V022, MT9V024, MT9V032, and MT9V034 CMOS Image Sensors
4 * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
6 * Based on the MT9M001 driver,
8 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/i2c.h>
19 #include <linux/log2.h>
20 #include <linux/mutex.h>
22 #include <linux/of_graph.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
25 #include <linux/videodev2.h>
26 #include <linux/v4l2-mediabus.h>
27 #include <linux/module.h>
29 #include <media/i2c/mt9v032.h>
30 #include <media/v4l2-ctrls.h>
31 #include <media/v4l2-device.h>
32 #include <media/v4l2-fwnode.h>
33 #include <media/v4l2-subdev.h>
35 /* The first four rows are black rows. The active area spans 753x481 pixels. */
36 #define MT9V032_PIXEL_ARRAY_HEIGHT 485
37 #define MT9V032_PIXEL_ARRAY_WIDTH 753
39 #define MT9V032_SYSCLK_FREQ_DEF 26600000
41 #define MT9V032_CHIP_VERSION 0x00
42 #define MT9V032_CHIP_ID_REV1 0x1311
43 #define MT9V032_CHIP_ID_REV3 0x1313
44 #define MT9V034_CHIP_ID_REV1 0X1324
45 #define MT9V032_COLUMN_START 0x01
46 #define MT9V032_COLUMN_START_MIN 1
47 #define MT9V032_COLUMN_START_DEF 1
48 #define MT9V032_COLUMN_START_MAX 752
49 #define MT9V032_ROW_START 0x02
50 #define MT9V032_ROW_START_MIN 4
51 #define MT9V032_ROW_START_DEF 5
52 #define MT9V032_ROW_START_MAX 482
53 #define MT9V032_WINDOW_HEIGHT 0x03
54 #define MT9V032_WINDOW_HEIGHT_MIN 1
55 #define MT9V032_WINDOW_HEIGHT_DEF 480
56 #define MT9V032_WINDOW_HEIGHT_MAX 480
57 #define MT9V032_WINDOW_WIDTH 0x04
58 #define MT9V032_WINDOW_WIDTH_MIN 1
59 #define MT9V032_WINDOW_WIDTH_DEF 752
60 #define MT9V032_WINDOW_WIDTH_MAX 752
61 #define MT9V032_HORIZONTAL_BLANKING 0x05
62 #define MT9V032_HORIZONTAL_BLANKING_MIN 43
63 #define MT9V034_HORIZONTAL_BLANKING_MIN 61
64 #define MT9V032_HORIZONTAL_BLANKING_DEF 94
65 #define MT9V032_HORIZONTAL_BLANKING_MAX 1023
66 #define MT9V032_VERTICAL_BLANKING 0x06
67 #define MT9V032_VERTICAL_BLANKING_MIN 4
68 #define MT9V034_VERTICAL_BLANKING_MIN 2
69 #define MT9V032_VERTICAL_BLANKING_DEF 45
70 #define MT9V032_VERTICAL_BLANKING_MAX 3000
71 #define MT9V034_VERTICAL_BLANKING_MAX 32288
72 #define MT9V032_CHIP_CONTROL 0x07
73 #define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3)
74 #define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7)
75 #define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8)
76 #define MT9V032_SHUTTER_WIDTH1 0x08
77 #define MT9V032_SHUTTER_WIDTH2 0x09
78 #define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a
79 #define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b
80 #define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1
81 #define MT9V034_TOTAL_SHUTTER_WIDTH_MIN 0
82 #define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480
83 #define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767
84 #define MT9V034_TOTAL_SHUTTER_WIDTH_MAX 32765
85 #define MT9V032_RESET 0x0c
86 #define MT9V032_READ_MODE 0x0d
87 #define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0)
88 #define MT9V032_READ_MODE_ROW_BIN_SHIFT 0
89 #define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2)
90 #define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2
91 #define MT9V032_READ_MODE_ROW_FLIP (1 << 4)
92 #define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5)
93 #define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6)
94 #define MT9V032_READ_MODE_DARK_ROWS (1 << 7)
95 #define MT9V032_READ_MODE_RESERVED 0x0300
96 #define MT9V032_PIXEL_OPERATION_MODE 0x0f
97 #define MT9V034_PIXEL_OPERATION_MODE_HDR (1 << 0)
98 #define MT9V034_PIXEL_OPERATION_MODE_COLOR (1 << 1)
99 #define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2)
100 #define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6)
101 #define MT9V032_ANALOG_GAIN 0x35
102 #define MT9V032_ANALOG_GAIN_MIN 16
103 #define MT9V032_ANALOG_GAIN_DEF 16
104 #define MT9V032_ANALOG_GAIN_MAX 64
105 #define MT9V032_MAX_ANALOG_GAIN 0x36
106 #define MT9V032_MAX_ANALOG_GAIN_MAX 127
107 #define MT9V032_FRAME_DARK_AVERAGE 0x42
108 #define MT9V032_DARK_AVG_THRESH 0x46
109 #define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0)
110 #define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0
111 #define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8)
112 #define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8
113 #define MT9V032_ROW_NOISE_CORR_CONTROL 0x70
114 #define MT9V034_ROW_NOISE_CORR_ENABLE (1 << 0)
115 #define MT9V034_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1)
116 #define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5)
117 #define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7)
118 #define MT9V032_PIXEL_CLOCK 0x74
119 #define MT9V034_PIXEL_CLOCK 0x72
120 #define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0)
121 #define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1)
122 #define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2)
123 #define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3)
124 #define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4)
125 #define MT9V032_TEST_PATTERN 0x7f
126 #define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0)
127 #define MT9V032_TEST_PATTERN_DATA_SHIFT 0
128 #define MT9V032_TEST_PATTERN_USE_DATA (1 << 10)
129 #define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11)
130 #define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11)
131 #define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11)
132 #define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11)
133 #define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11)
134 #define MT9V032_TEST_PATTERN_ENABLE (1 << 13)
135 #define MT9V032_TEST_PATTERN_FLIP (1 << 14)
136 #define MT9V032_AEGC_DESIRED_BIN 0xa5
137 #define MT9V032_AEC_UPDATE_FREQUENCY 0xa6
138 #define MT9V032_AEC_LPF 0xa8
139 #define MT9V032_AGC_UPDATE_FREQUENCY 0xa9
140 #define MT9V032_AGC_LPF 0xaa
141 #define MT9V032_AEC_AGC_ENABLE 0xaf
142 #define MT9V032_AEC_ENABLE (1 << 0)
143 #define MT9V032_AGC_ENABLE (1 << 1)
144 #define MT9V034_AEC_MAX_SHUTTER_WIDTH 0xad
145 #define MT9V032_AEC_MAX_SHUTTER_WIDTH 0xbd
146 #define MT9V032_THERMAL_INFO 0xc1
149 MT9V032_MODEL_V022_COLOR, /* MT9V022IX7ATC */
150 MT9V032_MODEL_V022_MONO, /* MT9V022IX7ATM */
151 MT9V032_MODEL_V024_COLOR, /* MT9V024IA7XTC */
152 MT9V032_MODEL_V024_MONO, /* MT9V024IA7XTM */
153 MT9V032_MODEL_V032_COLOR, /* MT9V032C12STM */
154 MT9V032_MODEL_V032_MONO, /* MT9V032C12STC */
155 MT9V032_MODEL_V034_COLOR,
156 MT9V032_MODEL_V034_MONO,
159 struct mt9v032_model_version {
160 unsigned int version;
164 struct mt9v032_model_data {
165 unsigned int min_row_time;
166 unsigned int min_hblank;
167 unsigned int min_vblank;
168 unsigned int max_vblank;
169 unsigned int min_shutter;
170 unsigned int max_shutter;
171 unsigned int pclk_reg;
172 unsigned int aec_max_shutter_reg;
173 const struct v4l2_ctrl_config * const aec_max_shutter_v4l2_ctrl;
176 struct mt9v032_model_info {
177 const struct mt9v032_model_data *data;
181 static const struct mt9v032_model_version mt9v032_versions[] = {
182 { MT9V032_CHIP_ID_REV1, "MT9V022/MT9V032 rev1/2" },
183 { MT9V032_CHIP_ID_REV3, "MT9V022/MT9V032 rev3" },
184 { MT9V034_CHIP_ID_REV1, "MT9V024/MT9V034 rev1" },
188 struct v4l2_subdev subdev;
189 struct media_pad pad;
191 struct v4l2_mbus_framefmt format;
192 struct v4l2_rect crop;
196 struct v4l2_ctrl_handler ctrls;
198 struct v4l2_ctrl *link_freq;
199 struct v4l2_ctrl *pixel_rate;
202 struct mutex power_lock;
205 struct regmap *regmap;
207 struct gpio_desc *reset_gpio;
208 struct gpio_desc *standby_gpio;
210 struct mt9v032_platform_data *pdata;
211 const struct mt9v032_model_info *model;
212 const struct mt9v032_model_version *version;
218 struct v4l2_ctrl *test_pattern;
219 struct v4l2_ctrl *test_pattern_color;
223 static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
225 return container_of(sd, struct mt9v032, subdev);
229 mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable)
231 struct regmap *map = mt9v032->regmap;
232 u16 value = mt9v032->aec_agc;
240 ret = regmap_write(map, MT9V032_AEC_AGC_ENABLE, value);
244 mt9v032->aec_agc = value;
249 mt9v032_update_hblank(struct mt9v032 *mt9v032)
251 struct v4l2_rect *crop = &mt9v032->crop;
252 unsigned int min_hblank = mt9v032->model->data->min_hblank;
255 if (mt9v032->version->version == MT9V034_CHIP_ID_REV1)
256 min_hblank += (mt9v032->hratio - 1) * 10;
257 min_hblank = max_t(int, mt9v032->model->data->min_row_time - crop->width,
259 hblank = max_t(unsigned int, mt9v032->hblank, min_hblank);
261 return regmap_write(mt9v032->regmap, MT9V032_HORIZONTAL_BLANKING,
265 static int mt9v032_power_on(struct mt9v032 *mt9v032)
267 struct regmap *map = mt9v032->regmap;
270 gpiod_set_value_cansleep(mt9v032->reset_gpio, 1);
272 ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk);
276 /* System clock has to be enabled before releasing the reset */
277 ret = clk_prepare_enable(mt9v032->clk);
283 if (mt9v032->reset_gpio) {
284 gpiod_set_value_cansleep(mt9v032->reset_gpio, 0);
286 /* After releasing reset we need to wait 10 clock cycles
287 * before accessing the sensor over I2C. As the minimum SYSCLK
288 * frequency is 13MHz, waiting 1µs will be enough in the worst
294 /* Reset the chip and stop data read out */
295 ret = regmap_write(map, MT9V032_RESET, 1);
299 ret = regmap_write(map, MT9V032_RESET, 0);
303 return regmap_write(map, MT9V032_CHIP_CONTROL,
304 MT9V032_CHIP_CONTROL_MASTER_MODE);
307 static void mt9v032_power_off(struct mt9v032 *mt9v032)
309 clk_disable_unprepare(mt9v032->clk);
312 static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on)
314 struct regmap *map = mt9v032->regmap;
318 mt9v032_power_off(mt9v032);
322 ret = mt9v032_power_on(mt9v032);
326 /* Configure the pixel clock polarity */
327 if (mt9v032->pdata && mt9v032->pdata->clk_pol) {
328 ret = regmap_write(map, mt9v032->model->data->pclk_reg,
329 MT9V032_PIXEL_CLOCK_INV_PXL_CLK);
334 /* Disable the noise correction algorithm and restore the controls. */
335 ret = regmap_write(map, MT9V032_ROW_NOISE_CORR_CONTROL, 0);
339 return v4l2_ctrl_handler_setup(&mt9v032->ctrls);
342 /* -----------------------------------------------------------------------------
343 * V4L2 subdev video operations
346 static struct v4l2_mbus_framefmt *
347 __mt9v032_get_pad_format(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg,
348 unsigned int pad, enum v4l2_subdev_format_whence which)
351 case V4L2_SUBDEV_FORMAT_TRY:
352 return v4l2_subdev_get_try_format(&mt9v032->subdev, cfg, pad);
353 case V4L2_SUBDEV_FORMAT_ACTIVE:
354 return &mt9v032->format;
360 static struct v4l2_rect *
361 __mt9v032_get_pad_crop(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg,
362 unsigned int pad, enum v4l2_subdev_format_whence which)
365 case V4L2_SUBDEV_FORMAT_TRY:
366 return v4l2_subdev_get_try_crop(&mt9v032->subdev, cfg, pad);
367 case V4L2_SUBDEV_FORMAT_ACTIVE:
368 return &mt9v032->crop;
374 static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable)
376 const u16 mode = MT9V032_CHIP_CONTROL_DOUT_ENABLE
377 | MT9V032_CHIP_CONTROL_SEQUENTIAL;
378 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
379 struct v4l2_rect *crop = &mt9v032->crop;
380 struct regmap *map = mt9v032->regmap;
386 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, 0);
388 /* Configure the window size and row/column bin */
389 hbin = fls(mt9v032->hratio) - 1;
390 vbin = fls(mt9v032->vratio) - 1;
391 ret = regmap_update_bits(map, MT9V032_READ_MODE,
392 ~MT9V032_READ_MODE_RESERVED,
393 hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT |
394 vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT);
398 ret = regmap_write(map, MT9V032_COLUMN_START, crop->left);
402 ret = regmap_write(map, MT9V032_ROW_START, crop->top);
406 ret = regmap_write(map, MT9V032_WINDOW_WIDTH, crop->width);
410 ret = regmap_write(map, MT9V032_WINDOW_HEIGHT, crop->height);
414 ret = mt9v032_update_hblank(mt9v032);
418 /* Switch to master "normal" mode */
419 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, mode);
422 static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev,
423 struct v4l2_subdev_pad_config *cfg,
424 struct v4l2_subdev_mbus_code_enum *code)
426 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
431 code->code = mt9v032->format.code;
435 static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev,
436 struct v4l2_subdev_pad_config *cfg,
437 struct v4l2_subdev_frame_size_enum *fse)
439 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
443 if (mt9v032->format.code != fse->code)
446 fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index);
447 fse->max_width = fse->min_width;
448 fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index);
449 fse->max_height = fse->min_height;
454 static int mt9v032_get_format(struct v4l2_subdev *subdev,
455 struct v4l2_subdev_pad_config *cfg,
456 struct v4l2_subdev_format *format)
458 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
460 format->format = *__mt9v032_get_pad_format(mt9v032, cfg, format->pad,
465 static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032)
467 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
470 ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate,
471 mt9v032->sysclk / mt9v032->hratio);
473 dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret);
476 static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output)
478 /* Compute the power-of-two binning factor closest to the input size to
479 * output size ratio. Given that the output size is bounded by input/4
480 * and input, a generic implementation would be an ineffective luxury.
482 if (output * 3 > input * 2)
484 if (output * 3 > input)
489 static int mt9v032_set_format(struct v4l2_subdev *subdev,
490 struct v4l2_subdev_pad_config *cfg,
491 struct v4l2_subdev_format *format)
493 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
494 struct v4l2_mbus_framefmt *__format;
495 struct v4l2_rect *__crop;
501 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, format->pad,
504 /* Clamp the width and height to avoid dividing by zero. */
505 width = clamp(ALIGN(format->format.width, 2),
506 max_t(unsigned int, __crop->width / 4,
507 MT9V032_WINDOW_WIDTH_MIN),
509 height = clamp(ALIGN(format->format.height, 2),
510 max_t(unsigned int, __crop->height / 4,
511 MT9V032_WINDOW_HEIGHT_MIN),
514 hratio = mt9v032_calc_ratio(__crop->width, width);
515 vratio = mt9v032_calc_ratio(__crop->height, height);
517 __format = __mt9v032_get_pad_format(mt9v032, cfg, format->pad,
519 __format->width = __crop->width / hratio;
520 __format->height = __crop->height / vratio;
522 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
523 mt9v032->hratio = hratio;
524 mt9v032->vratio = vratio;
525 mt9v032_configure_pixel_rate(mt9v032);
528 format->format = *__format;
533 static int mt9v032_get_selection(struct v4l2_subdev *subdev,
534 struct v4l2_subdev_pad_config *cfg,
535 struct v4l2_subdev_selection *sel)
537 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
539 if (sel->target != V4L2_SEL_TGT_CROP)
542 sel->r = *__mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which);
546 static int mt9v032_set_selection(struct v4l2_subdev *subdev,
547 struct v4l2_subdev_pad_config *cfg,
548 struct v4l2_subdev_selection *sel)
550 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
551 struct v4l2_mbus_framefmt *__format;
552 struct v4l2_rect *__crop;
553 struct v4l2_rect rect;
555 if (sel->target != V4L2_SEL_TGT_CROP)
558 /* Clamp the crop rectangle boundaries and align them to a non multiple
559 * of 2 pixels to ensure a GRBG Bayer pattern.
561 rect.left = clamp(ALIGN(sel->r.left + 1, 2) - 1,
562 MT9V032_COLUMN_START_MIN,
563 MT9V032_COLUMN_START_MAX);
564 rect.top = clamp(ALIGN(sel->r.top + 1, 2) - 1,
565 MT9V032_ROW_START_MIN,
566 MT9V032_ROW_START_MAX);
567 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2),
568 MT9V032_WINDOW_WIDTH_MIN,
569 MT9V032_WINDOW_WIDTH_MAX);
570 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2),
571 MT9V032_WINDOW_HEIGHT_MIN,
572 MT9V032_WINDOW_HEIGHT_MAX);
574 rect.width = min_t(unsigned int,
575 rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left);
576 rect.height = min_t(unsigned int,
577 rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top);
579 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which);
581 if (rect.width != __crop->width || rect.height != __crop->height) {
582 /* Reset the output image size if the crop rectangle size has
585 __format = __mt9v032_get_pad_format(mt9v032, cfg, sel->pad,
587 __format->width = rect.width;
588 __format->height = rect.height;
589 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
592 mt9v032_configure_pixel_rate(mt9v032);
602 /* -----------------------------------------------------------------------------
603 * V4L2 subdev control operations
606 #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
608 * Value between 1 and 64 to set the desired bin. This is effectively a measure
609 * of how bright the image is supposed to be. Both AGC and AEC try to reach
612 #define V4L2_CID_AEGC_DESIRED_BIN (V4L2_CID_USER_BASE | 0x1002)
614 * LPF is the low pass filter capability of the chip. Both AEC and AGC have
615 * this setting. This limits the speed in which AGC/AEC adjust their settings.
616 * Possible values are 0-2. 0 means no LPF. For 1 and 2 this equation is used:
618 * if |(calculated new exp - current exp)| > (current exp / 4)
619 * next exp = calculated new exp
621 * next exp = current exp + ((calculated new exp - current exp) / 2^LPF)
623 #define V4L2_CID_AEC_LPF (V4L2_CID_USER_BASE | 0x1003)
624 #define V4L2_CID_AGC_LPF (V4L2_CID_USER_BASE | 0x1004)
626 * Value between 0 and 15. This is the number of frames being skipped before
627 * updating the auto exposure/gain.
629 #define V4L2_CID_AEC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1005)
630 #define V4L2_CID_AGC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1006)
632 * Maximum shutter width used for AEC.
634 #define V4L2_CID_AEC_MAX_SHUTTER_WIDTH (V4L2_CID_USER_BASE | 0x1007)
636 static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
638 struct mt9v032 *mt9v032 =
639 container_of(ctrl->handler, struct mt9v032, ctrls);
640 struct regmap *map = mt9v032->regmap;
645 case V4L2_CID_AUTOGAIN:
646 return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE,
650 return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val);
652 case V4L2_CID_EXPOSURE_AUTO:
653 return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE,
656 case V4L2_CID_EXPOSURE:
657 return regmap_write(map, MT9V032_TOTAL_SHUTTER_WIDTH,
660 case V4L2_CID_HBLANK:
661 mt9v032->hblank = ctrl->val;
662 return mt9v032_update_hblank(mt9v032);
664 case V4L2_CID_VBLANK:
665 return regmap_write(map, MT9V032_VERTICAL_BLANKING,
668 case V4L2_CID_PIXEL_RATE:
669 case V4L2_CID_LINK_FREQ:
670 if (mt9v032->link_freq == NULL)
673 freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val];
674 *mt9v032->pixel_rate->p_new.p_s64 = freq;
675 mt9v032->sysclk = freq;
678 case V4L2_CID_TEST_PATTERN:
679 switch (mt9v032->test_pattern->val) {
684 data = MT9V032_TEST_PATTERN_GRAY_VERTICAL
685 | MT9V032_TEST_PATTERN_ENABLE;
688 data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL
689 | MT9V032_TEST_PATTERN_ENABLE;
692 data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL
693 | MT9V032_TEST_PATTERN_ENABLE;
696 data = (mt9v032->test_pattern_color->val <<
697 MT9V032_TEST_PATTERN_DATA_SHIFT)
698 | MT9V032_TEST_PATTERN_USE_DATA
699 | MT9V032_TEST_PATTERN_ENABLE
700 | MT9V032_TEST_PATTERN_FLIP;
703 return regmap_write(map, MT9V032_TEST_PATTERN, data);
705 case V4L2_CID_AEGC_DESIRED_BIN:
706 return regmap_write(map, MT9V032_AEGC_DESIRED_BIN, ctrl->val);
708 case V4L2_CID_AEC_LPF:
709 return regmap_write(map, MT9V032_AEC_LPF, ctrl->val);
711 case V4L2_CID_AGC_LPF:
712 return regmap_write(map, MT9V032_AGC_LPF, ctrl->val);
714 case V4L2_CID_AEC_UPDATE_INTERVAL:
715 return regmap_write(map, MT9V032_AEC_UPDATE_FREQUENCY,
718 case V4L2_CID_AGC_UPDATE_INTERVAL:
719 return regmap_write(map, MT9V032_AGC_UPDATE_FREQUENCY,
722 case V4L2_CID_AEC_MAX_SHUTTER_WIDTH:
723 return regmap_write(map,
724 mt9v032->model->data->aec_max_shutter_reg,
731 static const struct v4l2_ctrl_ops mt9v032_ctrl_ops = {
732 .s_ctrl = mt9v032_s_ctrl,
735 static const char * const mt9v032_test_pattern_menu[] = {
737 "Gray Vertical Shade",
738 "Gray Horizontal Shade",
739 "Gray Diagonal Shade",
743 static const struct v4l2_ctrl_config mt9v032_test_pattern_color = {
744 .ops = &mt9v032_ctrl_ops,
745 .id = V4L2_CID_TEST_PATTERN_COLOR,
746 .type = V4L2_CTRL_TYPE_INTEGER,
747 .name = "Test Pattern Color",
755 static const struct v4l2_ctrl_config mt9v032_aegc_controls[] = {
757 .ops = &mt9v032_ctrl_ops,
758 .id = V4L2_CID_AEGC_DESIRED_BIN,
759 .type = V4L2_CTRL_TYPE_INTEGER,
760 .name = "AEC/AGC Desired Bin",
767 .ops = &mt9v032_ctrl_ops,
768 .id = V4L2_CID_AEC_LPF,
769 .type = V4L2_CTRL_TYPE_INTEGER,
770 .name = "AEC Low Pass Filter",
777 .ops = &mt9v032_ctrl_ops,
778 .id = V4L2_CID_AGC_LPF,
779 .type = V4L2_CTRL_TYPE_INTEGER,
780 .name = "AGC Low Pass Filter",
787 .ops = &mt9v032_ctrl_ops,
788 .id = V4L2_CID_AEC_UPDATE_INTERVAL,
789 .type = V4L2_CTRL_TYPE_INTEGER,
790 .name = "AEC Update Interval",
797 .ops = &mt9v032_ctrl_ops,
798 .id = V4L2_CID_AGC_UPDATE_INTERVAL,
799 .type = V4L2_CTRL_TYPE_INTEGER,
800 .name = "AGC Update Interval",
809 static const struct v4l2_ctrl_config mt9v032_aec_max_shutter_width = {
810 .ops = &mt9v032_ctrl_ops,
811 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
812 .type = V4L2_CTRL_TYPE_INTEGER,
813 .name = "AEC Max Shutter Width",
821 static const struct v4l2_ctrl_config mt9v034_aec_max_shutter_width = {
822 .ops = &mt9v032_ctrl_ops,
823 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
824 .type = V4L2_CTRL_TYPE_INTEGER,
825 .name = "AEC Max Shutter Width",
833 /* -----------------------------------------------------------------------------
834 * V4L2 subdev core operations
837 static int mt9v032_set_power(struct v4l2_subdev *subdev, int on)
839 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
842 mutex_lock(&mt9v032->power_lock);
844 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
845 * update the power state.
847 if (mt9v032->power_count == !on) {
848 ret = __mt9v032_set_power(mt9v032, !!on);
853 /* Update the power count. */
854 mt9v032->power_count += on ? 1 : -1;
855 WARN_ON(mt9v032->power_count < 0);
858 mutex_unlock(&mt9v032->power_lock);
862 /* -----------------------------------------------------------------------------
863 * V4L2 subdev internal operations
866 static int mt9v032_registered(struct v4l2_subdev *subdev)
868 struct i2c_client *client = v4l2_get_subdevdata(subdev);
869 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
874 dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n",
877 ret = mt9v032_power_on(mt9v032);
879 dev_err(&client->dev, "MT9V032 power up failed\n");
883 /* Read and check the sensor version */
884 ret = regmap_read(mt9v032->regmap, MT9V032_CHIP_VERSION, &version);
886 dev_err(&client->dev, "Failed reading chip version\n");
890 for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) {
891 if (mt9v032_versions[i].version == version) {
892 mt9v032->version = &mt9v032_versions[i];
897 if (mt9v032->version == NULL) {
898 dev_err(&client->dev, "Unsupported chip version 0x%04x\n",
903 mt9v032_power_off(mt9v032);
905 dev_info(&client->dev, "%s detected at address 0x%02x\n",
906 mt9v032->version->name, client->addr);
908 mt9v032_configure_pixel_rate(mt9v032);
913 static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
915 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
916 struct v4l2_mbus_framefmt *format;
917 struct v4l2_rect *crop;
919 crop = v4l2_subdev_get_try_crop(subdev, fh->pad, 0);
920 crop->left = MT9V032_COLUMN_START_DEF;
921 crop->top = MT9V032_ROW_START_DEF;
922 crop->width = MT9V032_WINDOW_WIDTH_DEF;
923 crop->height = MT9V032_WINDOW_HEIGHT_DEF;
925 format = v4l2_subdev_get_try_format(subdev, fh->pad, 0);
927 if (mt9v032->model->color)
928 format->code = MEDIA_BUS_FMT_SGRBG10_1X10;
930 format->code = MEDIA_BUS_FMT_Y10_1X10;
932 format->width = MT9V032_WINDOW_WIDTH_DEF;
933 format->height = MT9V032_WINDOW_HEIGHT_DEF;
934 format->field = V4L2_FIELD_NONE;
935 format->colorspace = V4L2_COLORSPACE_SRGB;
937 return mt9v032_set_power(subdev, 1);
940 static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
942 return mt9v032_set_power(subdev, 0);
945 static const struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = {
946 .s_power = mt9v032_set_power,
949 static const struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = {
950 .s_stream = mt9v032_s_stream,
953 static const struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = {
954 .enum_mbus_code = mt9v032_enum_mbus_code,
955 .enum_frame_size = mt9v032_enum_frame_size,
956 .get_fmt = mt9v032_get_format,
957 .set_fmt = mt9v032_set_format,
958 .get_selection = mt9v032_get_selection,
959 .set_selection = mt9v032_set_selection,
962 static const struct v4l2_subdev_ops mt9v032_subdev_ops = {
963 .core = &mt9v032_subdev_core_ops,
964 .video = &mt9v032_subdev_video_ops,
965 .pad = &mt9v032_subdev_pad_ops,
968 static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = {
969 .registered = mt9v032_registered,
970 .open = mt9v032_open,
971 .close = mt9v032_close,
974 static const struct regmap_config mt9v032_regmap_config = {
977 .max_register = 0xff,
978 .cache_type = REGCACHE_RBTREE,
981 /* -----------------------------------------------------------------------------
982 * Driver initialization and probing
985 static struct mt9v032_platform_data *
986 mt9v032_get_pdata(struct i2c_client *client)
988 struct mt9v032_platform_data *pdata = NULL;
989 struct v4l2_fwnode_endpoint endpoint;
990 struct device_node *np;
991 struct property *prop;
993 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
994 return client->dev.platform_data;
996 np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
1000 if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0)
1003 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1007 prop = of_find_property(np, "link-frequencies", NULL);
1010 size_t size = prop->length / sizeof(*link_freqs);
1012 link_freqs = devm_kcalloc(&client->dev, size,
1013 sizeof(*link_freqs), GFP_KERNEL);
1017 if (of_property_read_u64_array(np, "link-frequencies",
1018 link_freqs, size) < 0)
1021 pdata->link_freqs = link_freqs;
1022 pdata->link_def_freq = link_freqs[0];
1025 pdata->clk_pol = !!(endpoint.bus.parallel.flags &
1026 V4L2_MBUS_PCLK_SAMPLE_RISING);
1033 static int mt9v032_probe(struct i2c_client *client,
1034 const struct i2c_device_id *did)
1036 struct mt9v032_platform_data *pdata = mt9v032_get_pdata(client);
1037 struct mt9v032 *mt9v032;
1041 mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL);
1045 mt9v032->regmap = devm_regmap_init_i2c(client, &mt9v032_regmap_config);
1046 if (IS_ERR(mt9v032->regmap))
1047 return PTR_ERR(mt9v032->regmap);
1049 mt9v032->clk = devm_clk_get(&client->dev, NULL);
1050 if (IS_ERR(mt9v032->clk))
1051 return PTR_ERR(mt9v032->clk);
1053 mt9v032->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1055 if (IS_ERR(mt9v032->reset_gpio))
1056 return PTR_ERR(mt9v032->reset_gpio);
1058 mt9v032->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby",
1060 if (IS_ERR(mt9v032->standby_gpio))
1061 return PTR_ERR(mt9v032->standby_gpio);
1063 mutex_init(&mt9v032->power_lock);
1064 mt9v032->pdata = pdata;
1065 mt9v032->model = (const void *)did->driver_data;
1067 v4l2_ctrl_handler_init(&mt9v032->ctrls, 11 +
1068 ARRAY_SIZE(mt9v032_aegc_controls));
1070 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1071 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1072 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1073 V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN,
1074 MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF);
1075 v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1076 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1077 V4L2_EXPOSURE_AUTO);
1078 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1079 V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter,
1080 mt9v032->model->data->max_shutter, 1,
1081 MT9V032_TOTAL_SHUTTER_WIDTH_DEF);
1082 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1083 V4L2_CID_HBLANK, mt9v032->model->data->min_hblank,
1084 MT9V032_HORIZONTAL_BLANKING_MAX, 1,
1085 MT9V032_HORIZONTAL_BLANKING_DEF);
1086 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1087 V4L2_CID_VBLANK, mt9v032->model->data->min_vblank,
1088 mt9v032->model->data->max_vblank, 1,
1089 MT9V032_VERTICAL_BLANKING_DEF);
1090 mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls,
1091 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN,
1092 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0,
1093 mt9v032_test_pattern_menu);
1094 mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls,
1095 &mt9v032_test_pattern_color, NULL);
1097 v4l2_ctrl_new_custom(&mt9v032->ctrls,
1098 mt9v032->model->data->aec_max_shutter_v4l2_ctrl,
1100 for (i = 0; i < ARRAY_SIZE(mt9v032_aegc_controls); ++i)
1101 v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_aegc_controls[i],
1104 v4l2_ctrl_cluster(2, &mt9v032->test_pattern);
1106 mt9v032->pixel_rate =
1107 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1108 V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
1110 if (pdata && pdata->link_freqs) {
1111 unsigned int def = 0;
1113 for (i = 0; pdata->link_freqs[i]; ++i) {
1114 if (pdata->link_freqs[i] == pdata->link_def_freq)
1118 mt9v032->link_freq =
1119 v4l2_ctrl_new_int_menu(&mt9v032->ctrls,
1121 V4L2_CID_LINK_FREQ, i - 1, def,
1123 v4l2_ctrl_cluster(2, &mt9v032->link_freq);
1127 mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
1129 if (mt9v032->ctrls.error) {
1130 dev_err(&client->dev, "control initialization error %d\n",
1131 mt9v032->ctrls.error);
1132 ret = mt9v032->ctrls.error;
1136 mt9v032->crop.left = MT9V032_COLUMN_START_DEF;
1137 mt9v032->crop.top = MT9V032_ROW_START_DEF;
1138 mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF;
1139 mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF;
1141 if (mt9v032->model->color)
1142 mt9v032->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1144 mt9v032->format.code = MEDIA_BUS_FMT_Y10_1X10;
1146 mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF;
1147 mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF;
1148 mt9v032->format.field = V4L2_FIELD_NONE;
1149 mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB;
1151 mt9v032->hratio = 1;
1152 mt9v032->vratio = 1;
1154 mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE;
1155 mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF;
1156 mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF;
1158 v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops);
1159 mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops;
1160 mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1162 mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE;
1163 ret = media_entity_pads_init(&mt9v032->subdev.entity, 1, &mt9v032->pad);
1167 mt9v032->subdev.dev = &client->dev;
1168 ret = v4l2_async_register_subdev(&mt9v032->subdev);
1175 media_entity_cleanup(&mt9v032->subdev.entity);
1176 v4l2_ctrl_handler_free(&mt9v032->ctrls);
1180 static int mt9v032_remove(struct i2c_client *client)
1182 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1183 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
1185 v4l2_async_unregister_subdev(subdev);
1186 v4l2_ctrl_handler_free(&mt9v032->ctrls);
1187 media_entity_cleanup(&subdev->entity);
1192 static const struct mt9v032_model_data mt9v032_model_data[] = {
1194 /* MT9V022, MT9V032 revisions 1/2/3 */
1195 .min_row_time = 660,
1196 .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN,
1197 .min_vblank = MT9V032_VERTICAL_BLANKING_MIN,
1198 .max_vblank = MT9V032_VERTICAL_BLANKING_MAX,
1199 .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN,
1200 .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX,
1201 .pclk_reg = MT9V032_PIXEL_CLOCK,
1202 .aec_max_shutter_reg = MT9V032_AEC_MAX_SHUTTER_WIDTH,
1203 .aec_max_shutter_v4l2_ctrl = &mt9v032_aec_max_shutter_width,
1205 /* MT9V024, MT9V034 */
1206 .min_row_time = 690,
1207 .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN,
1208 .min_vblank = MT9V034_VERTICAL_BLANKING_MIN,
1209 .max_vblank = MT9V034_VERTICAL_BLANKING_MAX,
1210 .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN,
1211 .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX,
1212 .pclk_reg = MT9V034_PIXEL_CLOCK,
1213 .aec_max_shutter_reg = MT9V034_AEC_MAX_SHUTTER_WIDTH,
1214 .aec_max_shutter_v4l2_ctrl = &mt9v034_aec_max_shutter_width,
1218 static const struct mt9v032_model_info mt9v032_models[] = {
1219 [MT9V032_MODEL_V022_COLOR] = {
1220 .data = &mt9v032_model_data[0],
1223 [MT9V032_MODEL_V022_MONO] = {
1224 .data = &mt9v032_model_data[0],
1227 [MT9V032_MODEL_V024_COLOR] = {
1228 .data = &mt9v032_model_data[1],
1231 [MT9V032_MODEL_V024_MONO] = {
1232 .data = &mt9v032_model_data[1],
1235 [MT9V032_MODEL_V032_COLOR] = {
1236 .data = &mt9v032_model_data[0],
1239 [MT9V032_MODEL_V032_MONO] = {
1240 .data = &mt9v032_model_data[0],
1243 [MT9V032_MODEL_V034_COLOR] = {
1244 .data = &mt9v032_model_data[1],
1247 [MT9V032_MODEL_V034_MONO] = {
1248 .data = &mt9v032_model_data[1],
1253 static const struct i2c_device_id mt9v032_id[] = {
1254 { "mt9v022", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_COLOR] },
1255 { "mt9v022m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_MONO] },
1256 { "mt9v024", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_COLOR] },
1257 { "mt9v024m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_MONO] },
1258 { "mt9v032", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_COLOR] },
1259 { "mt9v032m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_MONO] },
1260 { "mt9v034", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_COLOR] },
1261 { "mt9v034m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_MONO] },
1264 MODULE_DEVICE_TABLE(i2c, mt9v032_id);
1266 #if IS_ENABLED(CONFIG_OF)
1267 static const struct of_device_id mt9v032_of_match[] = {
1268 { .compatible = "aptina,mt9v022" },
1269 { .compatible = "aptina,mt9v022m" },
1270 { .compatible = "aptina,mt9v024" },
1271 { .compatible = "aptina,mt9v024m" },
1272 { .compatible = "aptina,mt9v032" },
1273 { .compatible = "aptina,mt9v032m" },
1274 { .compatible = "aptina,mt9v034" },
1275 { .compatible = "aptina,mt9v034m" },
1278 MODULE_DEVICE_TABLE(of, mt9v032_of_match);
1281 static struct i2c_driver mt9v032_driver = {
1284 .of_match_table = of_match_ptr(mt9v032_of_match),
1286 .probe = mt9v032_probe,
1287 .remove = mt9v032_remove,
1288 .id_table = mt9v032_id,
1291 module_i2c_driver(mt9v032_driver);
1293 MODULE_DESCRIPTION("Aptina MT9V032 Camera driver");
1294 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1295 MODULE_LICENSE("GPL");