1 // SPDX-License-Identifier: GPL-2.0+
3 * Maxim MAX9286 GMSL Deserializer Driver
5 * Copyright (C) 2017-2019 Jacopo Mondi
6 * Copyright (C) 2017-2019 Kieran Bingham
7 * Copyright (C) 2017-2019 Laurent Pinchart
8 * Copyright (C) 2017-2019 Niklas Söderlund
9 * Copyright (C) 2016 Renesas Electronics Corporation
10 * Copyright (C) 2015 Cogent Embedded, Inc.
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/fwnode.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/gpio/machine.h>
19 #include <linux/i2c.h>
20 #include <linux/i2c-mux.h>
21 #include <linux/module.h>
22 #include <linux/mutex.h>
23 #include <linux/of_graph.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/slab.h>
27 #include <media/v4l2-async.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-fwnode.h>
31 #include <media/v4l2-subdev.h>
34 #define MAX9286_MSTLINKSEL_AUTO (7 << 5)
35 #define MAX9286_MSTLINKSEL(n) ((n) << 5)
36 #define MAX9286_EN_VS_GEN BIT(4)
37 #define MAX9286_LINKEN(n) (1 << (n))
39 #define MAX9286_FSYNCMODE_ECU (3 << 6)
40 #define MAX9286_FSYNCMODE_EXT (2 << 6)
41 #define MAX9286_FSYNCMODE_INT_OUT (1 << 6)
42 #define MAX9286_FSYNCMODE_INT_HIZ (0 << 6)
43 #define MAX9286_GPIEN BIT(5)
44 #define MAX9286_ENLMO_RSTFSYNC BIT(2)
45 #define MAX9286_FSYNCMETH_AUTO (2 << 0)
46 #define MAX9286_FSYNCMETH_SEMI_AUTO (1 << 0)
47 #define MAX9286_FSYNCMETH_MANUAL (0 << 0)
48 #define MAX9286_REG_FSYNC_PERIOD_L 0x06
49 #define MAX9286_REG_FSYNC_PERIOD_M 0x07
50 #define MAX9286_REG_FSYNC_PERIOD_H 0x08
52 #define MAX9286_FWDCCEN(n) (1 << ((n) + 4))
53 #define MAX9286_REVCCEN(n) (1 << (n))
55 #define MAX9286_HVEN BIT(7)
56 #define MAX9286_EDC_6BIT_HAMMING (2 << 5)
57 #define MAX9286_EDC_6BIT_CRC (1 << 5)
58 #define MAX9286_EDC_1BIT_PARITY (0 << 5)
59 #define MAX9286_DESEL BIT(4)
60 #define MAX9286_INVVS BIT(3)
61 #define MAX9286_INVHS BIT(2)
62 #define MAX9286_HVSRC_D0 (2 << 0)
63 #define MAX9286_HVSRC_D14 (1 << 0)
64 #define MAX9286_HVSRC_D18 (0 << 0)
66 #define MAX9286_0X0F_RESERVED BIT(3)
68 #define MAX9286_CSILANECNT(n) (((n) - 1) << 6)
69 #define MAX9286_CSIDBL BIT(5)
70 #define MAX9286_DBL BIT(4)
71 #define MAX9286_DATATYPE_USER_8BIT (11 << 0)
72 #define MAX9286_DATATYPE_USER_YUV_12BIT (10 << 0)
73 #define MAX9286_DATATYPE_USER_24BIT (9 << 0)
74 #define MAX9286_DATATYPE_RAW14 (8 << 0)
75 #define MAX9286_DATATYPE_RAW12 (7 << 0)
76 #define MAX9286_DATATYPE_RAW10 (6 << 0)
77 #define MAX9286_DATATYPE_RAW8 (5 << 0)
78 #define MAX9286_DATATYPE_YUV422_10BIT (4 << 0)
79 #define MAX9286_DATATYPE_YUV422_8BIT (3 << 0)
80 #define MAX9286_DATATYPE_RGB555 (2 << 0)
81 #define MAX9286_DATATYPE_RGB565 (1 << 0)
82 #define MAX9286_DATATYPE_RGB888 (0 << 0)
84 #define MAX9286_CSI_IMAGE_TYP BIT(7)
85 #define MAX9286_VC(n) ((n) << 5)
86 #define MAX9286_VCTYPE BIT(4)
87 #define MAX9286_CSIOUTEN BIT(3)
88 #define MAX9286_SWP_ENDIAN BIT(2)
89 #define MAX9286_EN_CCBSYB_CLK_STR BIT(1)
90 #define MAX9286_EN_GPI_CCBSYB BIT(0)
92 #define MAX9286_SWITCHIN(n) (1 << ((n) + 4))
93 #define MAX9286_ENEQ(n) (1 << (n))
95 #define MAX9286_HIGHIMM(n) BIT((n) + 4)
96 #define MAX9286_I2CSEL BIT(2)
97 #define MAX9286_HIBW BIT(1)
98 #define MAX9286_BWS BIT(0)
100 #define MAX9286_LOCKED BIT(7)
102 #define MAX9286_FSYNC_LOCKED BIT(6)
104 #define MAX9286_I2CLOCACK BIT(7)
105 #define MAX9286_I2CSLVSH_1046NS_469NS (3 << 5)
106 #define MAX9286_I2CSLVSH_938NS_352NS (2 << 5)
107 #define MAX9286_I2CSLVSH_469NS_234NS (1 << 5)
108 #define MAX9286_I2CSLVSH_352NS_117NS (0 << 5)
109 #define MAX9286_I2CMSTBT_837KBPS (7 << 2)
110 #define MAX9286_I2CMSTBT_533KBPS (6 << 2)
111 #define MAX9286_I2CMSTBT_339KBPS (5 << 2)
112 #define MAX9286_I2CMSTBT_173KBPS (4 << 2)
113 #define MAX9286_I2CMSTBT_105KBPS (3 << 2)
114 #define MAX9286_I2CMSTBT_84KBPS (2 << 2)
115 #define MAX9286_I2CMSTBT_28KBPS (1 << 2)
116 #define MAX9286_I2CMSTBT_8KBPS (0 << 2)
117 #define MAX9286_I2CSLVTO_NONE (3 << 0)
118 #define MAX9286_I2CSLVTO_1024US (2 << 0)
119 #define MAX9286_I2CSLVTO_256US (1 << 0)
120 #define MAX9286_I2CSLVTO_64US (0 << 0)
122 #define MAX9286_REV_TRF(n) ((n) << 4)
123 #define MAX9286_REV_AMP(n) ((((n) - 30) / 10) << 1) /* in mV */
124 #define MAX9286_REV_AMP_X BIT(0)
125 #define MAX9286_REV_AMP_HIGH 170
127 #define MAX9286_EN_REV_CFG BIT(6)
128 #define MAX9286_REV_FLEN(n) ((n) - 20)
130 #define MAX9286_VIDEO_DETECT_MASK 0x0f
132 #define MAX9286_LFLTBMONMASKED BIT(7)
133 #define MAX9286_LOCKMONMASKED BIT(6)
134 #define MAX9286_AUTOCOMBACKEN BIT(5)
135 #define MAX9286_AUTOMASKEN BIT(4)
136 #define MAX9286_MASKLINK(n) ((n) << 0)
139 * The sink and source pads are created to match the OF graph port numbers so
140 * that their indexes can be used interchangeably.
142 #define MAX9286_NUM_GMSL 4
143 #define MAX9286_N_SINKS 4
144 #define MAX9286_N_PADS 5
145 #define MAX9286_SRC_PAD 4
147 struct max9286_format_info {
152 struct max9286_i2c_speed {
157 struct max9286_source {
158 struct v4l2_subdev *sd;
159 struct fwnode_handle *fwnode;
160 struct regulator *regulator;
164 struct v4l2_async_connection base;
165 struct max9286_source *source;
168 static inline struct max9286_asd *
169 to_max9286_asd(struct v4l2_async_connection *asd)
171 return container_of(asd, struct max9286_asd, base);
174 struct max9286_priv {
175 struct i2c_client *client;
176 struct gpio_desc *gpiod_pwdn;
177 struct v4l2_subdev sd;
178 struct media_pad pads[MAX9286_N_PADS];
179 struct regulator *regulator;
181 struct gpio_chip gpio;
184 struct i2c_mux_core *mux;
185 unsigned int mux_channel;
188 /* The initial reverse control channel amplitude. */
189 u32 init_rev_chan_mv;
197 struct v4l2_ctrl_handler ctrls;
198 struct v4l2_ctrl *pixelrate_ctrl;
199 unsigned int pixelrate;
201 struct v4l2_mbus_framefmt fmt[MAX9286_N_SINKS];
202 struct v4l2_fract interval;
204 /* Protects controls and fmt structures */
207 unsigned int nsources;
208 unsigned int source_mask;
209 unsigned int route_mask;
210 unsigned int bound_sources;
211 unsigned int csi2_data_lanes;
212 struct max9286_source sources[MAX9286_NUM_GMSL];
213 struct v4l2_async_notifier notifier;
216 static struct max9286_source *next_source(struct max9286_priv *priv,
217 struct max9286_source *source)
220 source = &priv->sources[0];
224 for (; source < &priv->sources[MAX9286_NUM_GMSL]; source++) {
232 #define for_each_source(priv, source) \
233 for ((source) = NULL; ((source) = next_source((priv), (source))); )
235 #define to_index(priv, source) ((source) - &(priv)->sources[0])
237 static inline struct max9286_priv *sd_to_max9286(struct v4l2_subdev *sd)
239 return container_of(sd, struct max9286_priv, sd);
242 static const struct max9286_format_info max9286_formats[] = {
244 .code = MEDIA_BUS_FMT_UYVY8_1X16,
245 .datatype = MAX9286_DATATYPE_YUV422_8BIT,
247 .code = MEDIA_BUS_FMT_VYUY8_1X16,
248 .datatype = MAX9286_DATATYPE_YUV422_8BIT,
250 .code = MEDIA_BUS_FMT_YUYV8_1X16,
251 .datatype = MAX9286_DATATYPE_YUV422_8BIT,
253 .code = MEDIA_BUS_FMT_YVYU8_1X16,
254 .datatype = MAX9286_DATATYPE_YUV422_8BIT,
256 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
257 .datatype = MAX9286_DATATYPE_RAW12,
259 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
260 .datatype = MAX9286_DATATYPE_RAW12,
262 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
263 .datatype = MAX9286_DATATYPE_RAW12,
265 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
266 .datatype = MAX9286_DATATYPE_RAW12,
270 static const struct max9286_i2c_speed max9286_i2c_speeds[] = {
271 { .rate = 8470, .mstbt = MAX9286_I2CMSTBT_8KBPS },
272 { .rate = 28300, .mstbt = MAX9286_I2CMSTBT_28KBPS },
273 { .rate = 84700, .mstbt = MAX9286_I2CMSTBT_84KBPS },
274 { .rate = 105000, .mstbt = MAX9286_I2CMSTBT_105KBPS },
275 { .rate = 173000, .mstbt = MAX9286_I2CMSTBT_173KBPS },
276 { .rate = 339000, .mstbt = MAX9286_I2CMSTBT_339KBPS },
277 { .rate = 533000, .mstbt = MAX9286_I2CMSTBT_533KBPS },
278 { .rate = 837000, .mstbt = MAX9286_I2CMSTBT_837KBPS },
281 /* -----------------------------------------------------------------------------
285 static int max9286_read(struct max9286_priv *priv, u8 reg)
289 ret = i2c_smbus_read_byte_data(priv->client, reg);
291 dev_err(&priv->client->dev,
292 "%s: register 0x%02x read failed (%d)\n",
298 static int max9286_write(struct max9286_priv *priv, u8 reg, u8 val)
302 ret = i2c_smbus_write_byte_data(priv->client, reg, val);
304 dev_err(&priv->client->dev,
305 "%s: register 0x%02x write failed (%d)\n",
311 /* -----------------------------------------------------------------------------
315 static void max9286_i2c_mux_configure(struct max9286_priv *priv, u8 conf)
317 max9286_write(priv, 0x0a, conf);
320 * We must sleep after any change to the forward or reverse channel
323 usleep_range(3000, 5000);
326 static void max9286_i2c_mux_open(struct max9286_priv *priv)
328 /* Open all channels on the MAX9286 */
329 max9286_i2c_mux_configure(priv, 0xff);
331 priv->mux_open = true;
334 static void max9286_i2c_mux_close(struct max9286_priv *priv)
337 * Ensure that both the forward and reverse channel are disabled on the
338 * mux, and that the channel ID is invalidated to ensure we reconfigure
339 * on the next max9286_i2c_mux_select() call.
341 max9286_i2c_mux_configure(priv, 0x00);
343 priv->mux_open = false;
344 priv->mux_channel = -1;
347 static int max9286_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan)
349 struct max9286_priv *priv = i2c_mux_priv(muxc);
351 /* Channel select is disabled when configured in the opened state. */
355 if (priv->mux_channel == chan)
358 priv->mux_channel = chan;
360 max9286_i2c_mux_configure(priv, MAX9286_FWDCCEN(chan) |
361 MAX9286_REVCCEN(chan));
366 static int max9286_i2c_mux_init(struct max9286_priv *priv)
368 struct max9286_source *source;
371 if (!i2c_check_functionality(priv->client->adapter,
372 I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
375 priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev,
376 priv->nsources, 0, I2C_MUX_LOCKED,
377 max9286_i2c_mux_select, NULL);
381 priv->mux->priv = priv;
383 for_each_source(priv, source) {
384 unsigned int index = to_index(priv, source);
386 ret = i2c_mux_add_adapter(priv->mux, 0, index, 0);
394 i2c_mux_del_adapters(priv->mux);
398 static void max9286_configure_i2c(struct max9286_priv *priv, bool localack)
400 u8 config = MAX9286_I2CSLVSH_469NS_234NS | MAX9286_I2CSLVTO_1024US |
404 config |= MAX9286_I2CLOCACK;
406 max9286_write(priv, 0x34, config);
407 usleep_range(3000, 5000);
410 static void max9286_reverse_channel_setup(struct max9286_priv *priv,
411 unsigned int chan_amplitude)
415 if (priv->rev_chan_mv == chan_amplitude)
418 priv->rev_chan_mv = chan_amplitude;
420 /* Reverse channel transmission time: default to 1. */
421 chan_config = MAX9286_REV_TRF(1);
424 * Reverse channel setup.
426 * - Enable custom reverse channel configuration (through register 0x3f)
427 * and set the first pulse length to 35 clock cycles.
428 * - Adjust reverse channel amplitude: values > 130 are programmed
429 * using the additional +100mV REV_AMP_X boost flag
431 max9286_write(priv, 0x3f, MAX9286_EN_REV_CFG | MAX9286_REV_FLEN(35));
433 if (chan_amplitude > 100) {
434 /* It is not possible to express values (100 < x < 130) */
435 chan_amplitude = max(30U, chan_amplitude - 100);
436 chan_config |= MAX9286_REV_AMP_X;
438 max9286_write(priv, 0x3b, chan_config | MAX9286_REV_AMP(chan_amplitude));
439 usleep_range(2000, 2500);
443 * max9286_check_video_links() - Make sure video links are detected and locked
445 * Performs safety checks on video link status. Make sure they are detected
446 * and all enabled links are locked.
448 * Returns 0 for success, -EIO for errors.
450 static int max9286_check_video_links(struct max9286_priv *priv)
456 * Make sure valid video links are detected.
457 * The delay is not characterized in de-serializer manual, wait up
460 for (i = 0; i < 10; i++) {
461 ret = max9286_read(priv, 0x49);
465 if ((ret & MAX9286_VIDEO_DETECT_MASK) == priv->source_mask)
468 usleep_range(350, 500);
472 dev_err(&priv->client->dev,
473 "Unable to detect video links: 0x%02x\n", ret);
477 /* Make sure all enabled links are locked (4ms max). */
478 for (i = 0; i < 10; i++) {
479 ret = max9286_read(priv, 0x27);
483 if (ret & MAX9286_LOCKED)
486 usleep_range(350, 450);
490 dev_err(&priv->client->dev, "Not all enabled links locked\n");
498 * max9286_check_config_link() - Detect and wait for configuration links
500 * Determine if the configuration channel is up and settled for a link.
502 * Returns 0 for success, -EIO for errors.
504 static int max9286_check_config_link(struct max9286_priv *priv,
505 unsigned int source_mask)
507 unsigned int conflink_mask = (source_mask & 0x0f) << 4;
512 * Make sure requested configuration links are detected.
513 * The delay is not characterized in the chip manual: wait up
516 for (i = 0; i < 10; i++) {
517 ret = max9286_read(priv, 0x49);
522 if (ret == conflink_mask)
525 usleep_range(350, 500);
528 if (ret != conflink_mask) {
529 dev_err(&priv->client->dev,
530 "Unable to detect configuration links: 0x%02x expected 0x%02x\n",
535 dev_info(&priv->client->dev,
536 "Successfully detected configuration links after %u loops: 0x%02x\n",
542 static void max9286_set_video_format(struct max9286_priv *priv,
543 const struct v4l2_mbus_framefmt *format)
545 const struct max9286_format_info *info = NULL;
548 for (i = 0; i < ARRAY_SIZE(max9286_formats); ++i) {
549 if (max9286_formats[i].code == format->code) {
550 info = &max9286_formats[i];
559 * Video format setup: disable CSI output, set VC according to Link
560 * number, enable I2C clock stretching when CCBSY is low, enable CCBSY
561 * in external GPI-to-GPO mode.
563 max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_EN_CCBSYB_CLK_STR |
564 MAX9286_EN_GPI_CCBSYB);
566 /* Enable CSI-2 Lane D0-D3 only, DBL mode. */
567 max9286_write(priv, 0x12, MAX9286_CSIDBL | MAX9286_DBL |
568 MAX9286_CSILANECNT(priv->csi2_data_lanes) |
572 * Enable HS/VS encoding, use HS as line valid source, use D14/15 for
575 max9286_write(priv, 0x0c, MAX9286_HVEN | MAX9286_DESEL |
576 MAX9286_INVVS | MAX9286_HVSRC_D14);
579 static void max9286_set_fsync_period(struct max9286_priv *priv)
583 if (!priv->interval.numerator || !priv->interval.denominator) {
585 * Special case, a null interval enables automatic FRAMESYNC
586 * mode. FRAMESYNC is taken from the slowest link.
588 max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_HIZ |
589 MAX9286_FSYNCMETH_AUTO);
596 * The FRAMESYNC generator is configured with a period expressed as a
597 * number of PCLK periods.
599 fsync = div_u64((u64)priv->pixelrate * priv->interval.numerator,
600 priv->interval.denominator);
602 dev_dbg(&priv->client->dev, "fsync period %u (pclk %u)\n", fsync,
605 max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_OUT |
606 MAX9286_FSYNCMETH_MANUAL);
608 max9286_write(priv, 0x06, (fsync >> 0) & 0xff);
609 max9286_write(priv, 0x07, (fsync >> 8) & 0xff);
610 max9286_write(priv, 0x08, (fsync >> 16) & 0xff);
613 /* -----------------------------------------------------------------------------
617 static int max9286_set_pixelrate(struct max9286_priv *priv)
619 struct max9286_source *source = NULL;
622 for_each_source(priv, source) {
623 struct v4l2_ctrl *ctrl;
626 /* Pixel rate is mandatory to be reported by sources. */
627 ctrl = v4l2_ctrl_find(source->sd->ctrl_handler,
628 V4L2_CID_PIXEL_RATE);
634 /* All source must report the same pixel rate. */
635 source_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
637 pixelrate = source_rate;
638 } else if (pixelrate != source_rate) {
639 dev_err(&priv->client->dev,
640 "Unable to calculate pixel rate\n");
646 dev_err(&priv->client->dev,
647 "No pixel rate control available in sources\n");
651 priv->pixelrate = pixelrate;
654 * The CSI-2 transmitter pixel rate is the single source rate multiplied
655 * by the number of available sources.
657 return v4l2_ctrl_s_ctrl_int64(priv->pixelrate_ctrl,
658 pixelrate * priv->nsources);
661 static int max9286_notify_bound(struct v4l2_async_notifier *notifier,
662 struct v4l2_subdev *subdev,
663 struct v4l2_async_connection *asd)
665 struct max9286_priv *priv = sd_to_max9286(notifier->sd);
666 struct max9286_source *source = to_max9286_asd(asd)->source;
667 unsigned int index = to_index(priv, source);
668 unsigned int src_pad;
671 ret = media_entity_get_fwnode_pad(&subdev->entity,
673 MEDIA_PAD_FL_SOURCE);
675 dev_err(&priv->client->dev,
676 "Failed to find pad for %s\n", subdev->name);
680 priv->bound_sources |= BIT(index);
684 ret = media_create_pad_link(&source->sd->entity, src_pad,
685 &priv->sd.entity, index,
686 MEDIA_LNK_FL_ENABLED |
687 MEDIA_LNK_FL_IMMUTABLE);
689 dev_err(&priv->client->dev,
690 "Unable to link %s:%u -> %s:%u\n",
691 source->sd->name, src_pad, priv->sd.name, index);
695 dev_dbg(&priv->client->dev, "Bound %s pad: %u on index %u\n",
696 subdev->name, src_pad, index);
699 * As we register a subdev notifiers we won't get a .complete() callback
700 * here, so we have to use bound_sources to identify when all remote
701 * serializers have probed.
703 if (priv->bound_sources != priv->source_mask)
707 * All enabled sources have probed and enabled their reverse control
710 * - Increase the reverse channel amplitude to compensate for the
711 * remote ends high threshold
712 * - Verify all configuration links are properly detected
713 * - Disable auto-ack as communication on the control channel are now
716 max9286_reverse_channel_setup(priv, MAX9286_REV_AMP_HIGH);
717 max9286_check_config_link(priv, priv->source_mask);
718 max9286_configure_i2c(priv, false);
720 return max9286_set_pixelrate(priv);
723 static void max9286_notify_unbind(struct v4l2_async_notifier *notifier,
724 struct v4l2_subdev *subdev,
725 struct v4l2_async_connection *asd)
727 struct max9286_priv *priv = sd_to_max9286(notifier->sd);
728 struct max9286_source *source = to_max9286_asd(asd)->source;
729 unsigned int index = to_index(priv, source);
732 priv->bound_sources &= ~BIT(index);
735 static const struct v4l2_async_notifier_operations max9286_notify_ops = {
736 .bound = max9286_notify_bound,
737 .unbind = max9286_notify_unbind,
740 static int max9286_v4l2_notifier_register(struct max9286_priv *priv)
742 struct device *dev = &priv->client->dev;
743 struct max9286_source *source = NULL;
749 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd);
751 for_each_source(priv, source) {
752 unsigned int i = to_index(priv, source);
753 struct max9286_asd *mas;
755 mas = v4l2_async_nf_add_fwnode(&priv->notifier, source->fwnode,
758 dev_err(dev, "Failed to add subdev for source %u: %ld",
760 v4l2_async_nf_cleanup(&priv->notifier);
764 mas->source = source;
767 priv->notifier.ops = &max9286_notify_ops;
769 ret = v4l2_async_nf_register(&priv->notifier);
771 dev_err(dev, "Failed to register subdev_notifier");
772 v4l2_async_nf_cleanup(&priv->notifier);
779 static void max9286_v4l2_notifier_unregister(struct max9286_priv *priv)
784 v4l2_async_nf_unregister(&priv->notifier);
785 v4l2_async_nf_cleanup(&priv->notifier);
788 static int max9286_s_stream(struct v4l2_subdev *sd, int enable)
790 struct max9286_priv *priv = sd_to_max9286(sd);
791 struct max9286_source *source;
797 const struct v4l2_mbus_framefmt *format;
800 * Get the format from the first used sink pad, as all sink
801 * formats must be identical.
803 format = &priv->fmt[__ffs(priv->bound_sources)];
805 max9286_set_video_format(priv, format);
806 max9286_set_fsync_period(priv);
809 * The frame sync between cameras is transmitted across the
810 * reverse channel as GPIO. We must open all channels while
811 * streaming to allow this synchronisation signal to be shared.
813 max9286_i2c_mux_open(priv);
815 /* Start all cameras. */
816 for_each_source(priv, source) {
817 ret = v4l2_subdev_call(source->sd, video, s_stream, 1);
822 ret = max9286_check_video_links(priv);
827 * Wait until frame synchronization is locked.
829 * Manual says frame sync locking should take ~6 VTS.
830 * From practical experience at least 8 are required. Give
831 * 12 complete frames time (~400ms at 30 fps) to achieve frame
832 * locking before returning error.
834 for (i = 0; i < 40; i++) {
835 if (max9286_read(priv, 0x31) & MAX9286_FSYNC_LOCKED) {
839 usleep_range(9000, 11000);
843 dev_err(&priv->client->dev,
844 "Failed to get frame synchronization\n");
845 return -EXDEV; /* Invalid cross-device link */
849 * Configure the CSI-2 output to line interleaved mode (W x (N
850 * x H), as opposed to the (N x W) x H mode that outputs the
851 * images stitched side-by-side) and enable it.
853 max9286_write(priv, 0x15, MAX9286_CSI_IMAGE_TYP | MAX9286_VCTYPE |
854 MAX9286_CSIOUTEN | MAX9286_EN_CCBSYB_CLK_STR |
855 MAX9286_EN_GPI_CCBSYB);
857 max9286_write(priv, 0x15, MAX9286_VCTYPE |
858 MAX9286_EN_CCBSYB_CLK_STR |
859 MAX9286_EN_GPI_CCBSYB);
861 /* Stop all cameras. */
862 for_each_source(priv, source)
863 v4l2_subdev_call(source->sd, video, s_stream, 0);
865 max9286_i2c_mux_close(priv);
871 static int max9286_g_frame_interval(struct v4l2_subdev *sd,
872 struct v4l2_subdev_frame_interval *interval)
874 struct max9286_priv *priv = sd_to_max9286(sd);
876 if (interval->pad != MAX9286_SRC_PAD)
879 interval->interval = priv->interval;
884 static int max9286_s_frame_interval(struct v4l2_subdev *sd,
885 struct v4l2_subdev_frame_interval *interval)
887 struct max9286_priv *priv = sd_to_max9286(sd);
889 if (interval->pad != MAX9286_SRC_PAD)
892 priv->interval = interval->interval;
897 static int max9286_enum_mbus_code(struct v4l2_subdev *sd,
898 struct v4l2_subdev_state *sd_state,
899 struct v4l2_subdev_mbus_code_enum *code)
901 if (code->pad || code->index > 0)
904 code->code = MEDIA_BUS_FMT_UYVY8_1X16;
909 static struct v4l2_mbus_framefmt *
910 max9286_get_pad_format(struct max9286_priv *priv,
911 struct v4l2_subdev_state *sd_state,
912 unsigned int pad, u32 which)
915 case V4L2_SUBDEV_FORMAT_TRY:
916 return v4l2_subdev_get_try_format(&priv->sd, sd_state, pad);
917 case V4L2_SUBDEV_FORMAT_ACTIVE:
918 return &priv->fmt[pad];
924 static int max9286_set_fmt(struct v4l2_subdev *sd,
925 struct v4l2_subdev_state *sd_state,
926 struct v4l2_subdev_format *format)
928 struct max9286_priv *priv = sd_to_max9286(sd);
929 struct v4l2_mbus_framefmt *cfg_fmt;
932 if (format->pad == MAX9286_SRC_PAD)
935 /* Validate the format. */
936 for (i = 0; i < ARRAY_SIZE(max9286_formats); ++i) {
937 if (max9286_formats[i].code == format->format.code)
941 if (i == ARRAY_SIZE(max9286_formats))
942 format->format.code = max9286_formats[0].code;
944 cfg_fmt = max9286_get_pad_format(priv, sd_state, format->pad,
949 mutex_lock(&priv->mutex);
950 *cfg_fmt = format->format;
951 mutex_unlock(&priv->mutex);
956 static int max9286_get_fmt(struct v4l2_subdev *sd,
957 struct v4l2_subdev_state *sd_state,
958 struct v4l2_subdev_format *format)
960 struct max9286_priv *priv = sd_to_max9286(sd);
961 struct v4l2_mbus_framefmt *cfg_fmt;
962 unsigned int pad = format->pad;
965 * Multiplexed Stream Support: Support link validation by returning the
966 * format of the first bound link. All links must have the same format,
967 * as we do not support mixing and matching of cameras connected to the
970 if (pad == MAX9286_SRC_PAD)
971 pad = __ffs(priv->bound_sources);
973 cfg_fmt = max9286_get_pad_format(priv, sd_state, pad, format->which);
977 mutex_lock(&priv->mutex);
978 format->format = *cfg_fmt;
979 mutex_unlock(&priv->mutex);
984 static const struct v4l2_subdev_video_ops max9286_video_ops = {
985 .s_stream = max9286_s_stream,
986 .g_frame_interval = max9286_g_frame_interval,
987 .s_frame_interval = max9286_s_frame_interval,
990 static const struct v4l2_subdev_pad_ops max9286_pad_ops = {
991 .enum_mbus_code = max9286_enum_mbus_code,
992 .get_fmt = max9286_get_fmt,
993 .set_fmt = max9286_set_fmt,
996 static const struct v4l2_subdev_ops max9286_subdev_ops = {
997 .video = &max9286_video_ops,
998 .pad = &max9286_pad_ops,
1001 static const struct v4l2_mbus_framefmt max9286_default_format = {
1004 .code = MEDIA_BUS_FMT_UYVY8_1X16,
1005 .colorspace = V4L2_COLORSPACE_SRGB,
1006 .field = V4L2_FIELD_NONE,
1007 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,
1008 .quantization = V4L2_QUANTIZATION_DEFAULT,
1009 .xfer_func = V4L2_XFER_FUNC_DEFAULT,
1012 static void max9286_init_format(struct v4l2_mbus_framefmt *fmt)
1014 *fmt = max9286_default_format;
1017 static int max9286_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
1019 struct v4l2_mbus_framefmt *format;
1022 for (i = 0; i < MAX9286_N_SINKS; i++) {
1023 format = v4l2_subdev_get_try_format(subdev, fh->state, i);
1024 max9286_init_format(format);
1030 static const struct v4l2_subdev_internal_ops max9286_subdev_internal_ops = {
1031 .open = max9286_open,
1034 static const struct media_entity_operations max9286_media_ops = {
1035 .link_validate = v4l2_subdev_link_validate
1038 static int max9286_s_ctrl(struct v4l2_ctrl *ctrl)
1041 case V4L2_CID_PIXEL_RATE:
1048 static const struct v4l2_ctrl_ops max9286_ctrl_ops = {
1049 .s_ctrl = max9286_s_ctrl,
1052 static int max9286_v4l2_register(struct max9286_priv *priv)
1054 struct device *dev = &priv->client->dev;
1058 /* Register v4l2 async notifiers for connected Camera subdevices */
1059 ret = max9286_v4l2_notifier_register(priv);
1061 dev_err(dev, "Unable to register V4L2 async notifiers\n");
1065 /* Configure V4L2 for the MAX9286 itself */
1067 for (i = 0; i < MAX9286_N_SINKS; i++)
1068 max9286_init_format(&priv->fmt[i]);
1070 v4l2_i2c_subdev_init(&priv->sd, priv->client, &max9286_subdev_ops);
1071 priv->sd.internal_ops = &max9286_subdev_internal_ops;
1072 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1074 v4l2_ctrl_handler_init(&priv->ctrls, 1);
1075 priv->pixelrate_ctrl = v4l2_ctrl_new_std(&priv->ctrls,
1077 V4L2_CID_PIXEL_RATE,
1078 1, INT_MAX, 1, 50000000);
1080 priv->sd.ctrl_handler = &priv->ctrls;
1081 ret = priv->ctrls.error;
1085 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1086 priv->sd.entity.ops = &max9286_media_ops;
1088 priv->pads[MAX9286_SRC_PAD].flags = MEDIA_PAD_FL_SOURCE;
1089 for (i = 0; i < MAX9286_SRC_PAD; i++)
1090 priv->pads[i].flags = MEDIA_PAD_FL_SINK;
1091 ret = media_entity_pads_init(&priv->sd.entity, MAX9286_N_PADS,
1096 ret = v4l2_async_register_subdev(&priv->sd);
1098 dev_err(dev, "Unable to register subdevice\n");
1105 v4l2_ctrl_handler_free(&priv->ctrls);
1106 max9286_v4l2_notifier_unregister(priv);
1111 static void max9286_v4l2_unregister(struct max9286_priv *priv)
1113 v4l2_ctrl_handler_free(&priv->ctrls);
1114 v4l2_async_unregister_subdev(&priv->sd);
1115 max9286_v4l2_notifier_unregister(priv);
1118 /* -----------------------------------------------------------------------------
1122 static int max9286_setup(struct max9286_priv *priv)
1125 * Link ordering values for all enabled links combinations. Orders must
1126 * be assigned sequentially from 0 to the number of enabled links
1127 * without leaving any hole for disabled links. We thus assign orders to
1128 * enabled links first, and use the remaining order values for disabled
1129 * links are all links must have a different order value;
1131 static const u8 link_order[] = {
1132 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxxx */
1133 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxx0 */
1134 (3 << 6) | (2 << 4) | (0 << 2) | (1 << 0), /* xx0x */
1135 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xx10 */
1136 (3 << 6) | (0 << 4) | (2 << 2) | (1 << 0), /* x0xx */
1137 (3 << 6) | (1 << 4) | (2 << 2) | (0 << 0), /* x1x0 */
1138 (3 << 6) | (1 << 4) | (0 << 2) | (2 << 0), /* x10x */
1139 (3 << 6) | (1 << 4) | (1 << 2) | (0 << 0), /* x210 */
1140 (0 << 6) | (3 << 4) | (2 << 2) | (1 << 0), /* 0xxx */
1141 (1 << 6) | (3 << 4) | (2 << 2) | (0 << 0), /* 1xx0 */
1142 (1 << 6) | (3 << 4) | (0 << 2) | (2 << 0), /* 1x0x */
1143 (2 << 6) | (3 << 4) | (1 << 2) | (0 << 0), /* 2x10 */
1144 (1 << 6) | (0 << 4) | (3 << 2) | (2 << 0), /* 10xx */
1145 (2 << 6) | (1 << 4) | (3 << 2) | (0 << 0), /* 21x0 */
1146 (2 << 6) | (1 << 4) | (0 << 2) | (3 << 0), /* 210x */
1147 (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* 3210 */
1152 * Set the I2C bus speed.
1154 * Enable I2C Local Acknowledge during the probe sequences of the camera
1155 * only. This should be disabled after the mux is initialised.
1157 max9286_configure_i2c(priv, true);
1158 max9286_reverse_channel_setup(priv, priv->init_rev_chan_mv);
1161 * Enable GMSL links, mask unused ones and autodetect link
1162 * used as CSI clock source.
1164 max9286_write(priv, 0x00, MAX9286_MSTLINKSEL_AUTO | priv->route_mask);
1165 max9286_write(priv, 0x0b, link_order[priv->route_mask]);
1166 max9286_write(priv, 0x69, (0xf & ~priv->route_mask));
1168 max9286_set_video_format(priv, &max9286_default_format);
1169 max9286_set_fsync_period(priv);
1171 cfg = max9286_read(priv, 0x1c);
1175 dev_dbg(&priv->client->dev, "power-up config: %s immunity, %u-bit bus\n",
1176 cfg & MAX9286_HIGHIMM(0) ? "high" : "legacy",
1177 cfg & MAX9286_BWS ? 32 : cfg & MAX9286_HIBW ? 27 : 24);
1179 if (priv->bus_width) {
1180 cfg &= ~(MAX9286_HIBW | MAX9286_BWS);
1182 if (priv->bus_width == 27)
1183 cfg |= MAX9286_HIBW;
1184 else if (priv->bus_width == 32)
1187 max9286_write(priv, 0x1c, cfg);
1191 * The overlap window seems to provide additional validation by tracking
1192 * the delay between vsync and frame sync, generating an error if the
1193 * delay is bigger than the programmed window, though it's not yet clear
1194 * what value should be set.
1196 * As it's an optional value and can be disabled, we do so by setting
1197 * a 0 overlap value.
1199 max9286_write(priv, 0x63, 0);
1200 max9286_write(priv, 0x64, 0);
1203 * Wait for 2ms to allow the link to resynchronize after the
1204 * configuration change.
1206 usleep_range(2000, 5000);
1211 static int max9286_gpio_set(struct max9286_priv *priv, unsigned int offset,
1215 priv->gpio_state |= BIT(offset);
1217 priv->gpio_state &= ~BIT(offset);
1219 return max9286_write(priv, 0x0f,
1220 MAX9286_0X0F_RESERVED | priv->gpio_state);
1223 static void max9286_gpiochip_set(struct gpio_chip *chip,
1224 unsigned int offset, int value)
1226 struct max9286_priv *priv = gpiochip_get_data(chip);
1228 max9286_gpio_set(priv, offset, value);
1231 static int max9286_gpiochip_get(struct gpio_chip *chip, unsigned int offset)
1233 struct max9286_priv *priv = gpiochip_get_data(chip);
1235 return priv->gpio_state & BIT(offset);
1238 static int max9286_register_gpio(struct max9286_priv *priv)
1240 struct device *dev = &priv->client->dev;
1241 struct gpio_chip *gpio = &priv->gpio;
1244 /* Configure the GPIO */
1245 gpio->label = dev_name(dev);
1247 gpio->owner = THIS_MODULE;
1250 gpio->set = max9286_gpiochip_set;
1251 gpio->get = max9286_gpiochip_get;
1252 gpio->can_sleep = true;
1254 ret = devm_gpiochip_add_data(dev, gpio, priv);
1256 dev_err(dev, "Unable to create gpio_chip\n");
1261 static int max9286_parse_gpios(struct max9286_priv *priv)
1263 struct device *dev = &priv->client->dev;
1267 * Parse the "gpio-poc" vendor property. If the property is not
1268 * specified the camera power is controlled by a regulator.
1270 ret = of_property_read_u32_array(dev->of_node, "maxim,gpio-poc",
1272 if (ret == -EINVAL) {
1274 * If gpio lines are not used for the camera power, register
1275 * a gpio controller for consumers.
1277 return max9286_register_gpio(priv);
1280 /* If the property is specified make sure it is well formed. */
1281 if (ret || priv->gpio_poc[0] > 1 ||
1282 (priv->gpio_poc[1] != GPIO_ACTIVE_HIGH &&
1283 priv->gpio_poc[1] != GPIO_ACTIVE_LOW)) {
1284 dev_err(dev, "Invalid 'gpio-poc' property\n");
1288 priv->use_gpio_poc = true;
1292 static int max9286_poc_power_on(struct max9286_priv *priv)
1294 struct max9286_source *source;
1295 unsigned int enabled = 0;
1298 /* Enable the global regulator if available. */
1299 if (priv->regulator)
1300 return regulator_enable(priv->regulator);
1302 if (priv->use_gpio_poc)
1303 return max9286_gpio_set(priv, priv->gpio_poc[0],
1304 !priv->gpio_poc[1]);
1306 /* Otherwise use the per-port regulators. */
1307 for_each_source(priv, source) {
1308 ret = regulator_enable(source->regulator);
1312 enabled |= BIT(to_index(priv, source));
1318 for_each_source(priv, source) {
1319 if (enabled & BIT(to_index(priv, source)))
1320 regulator_disable(source->regulator);
1326 static int max9286_poc_power_off(struct max9286_priv *priv)
1328 struct max9286_source *source;
1331 if (priv->regulator)
1332 return regulator_disable(priv->regulator);
1334 if (priv->use_gpio_poc)
1335 return max9286_gpio_set(priv, priv->gpio_poc[0],
1338 for_each_source(priv, source) {
1341 err = regulator_disable(source->regulator);
1349 static int max9286_poc_enable(struct max9286_priv *priv, bool enable)
1354 ret = max9286_poc_power_on(priv);
1356 ret = max9286_poc_power_off(priv);
1359 dev_err(&priv->client->dev, "Unable to turn power %s\n",
1360 enable ? "on" : "off");
1365 static int max9286_init(struct max9286_priv *priv)
1367 struct i2c_client *client = priv->client;
1370 ret = max9286_poc_enable(priv, true);
1374 ret = max9286_setup(priv);
1376 dev_err(&client->dev, "Unable to setup max9286\n");
1377 goto err_poc_disable;
1381 * Register all V4L2 interactions for the MAX9286 and notifiers for
1382 * any subdevices connected.
1384 ret = max9286_v4l2_register(priv);
1386 dev_err(&client->dev, "Failed to register with V4L2\n");
1387 goto err_poc_disable;
1390 ret = max9286_i2c_mux_init(priv);
1392 dev_err(&client->dev, "Unable to initialize I2C multiplexer\n");
1393 goto err_v4l2_register;
1396 /* Leave the mux channels disabled until they are selected. */
1397 max9286_i2c_mux_close(priv);
1402 max9286_v4l2_unregister(priv);
1404 max9286_poc_enable(priv, false);
1409 static void max9286_cleanup_dt(struct max9286_priv *priv)
1411 struct max9286_source *source;
1413 for_each_source(priv, source) {
1414 fwnode_handle_put(source->fwnode);
1415 source->fwnode = NULL;
1419 static int max9286_parse_dt(struct max9286_priv *priv)
1421 struct device *dev = &priv->client->dev;
1422 struct device_node *i2c_mux;
1423 struct device_node *node = NULL;
1424 unsigned int i2c_mux_mask = 0;
1425 u32 reverse_channel_microvolt;
1426 u32 i2c_clk_freq = 105000;
1429 /* Balance the of_node_put() performed by of_find_node_by_name(). */
1430 of_node_get(dev->of_node);
1431 i2c_mux = of_find_node_by_name(dev->of_node, "i2c-mux");
1433 dev_err(dev, "Failed to find i2c-mux node\n");
1437 /* Identify which i2c-mux channels are enabled */
1438 for_each_child_of_node(i2c_mux, node) {
1441 of_property_read_u32(node, "reg", &id);
1442 if (id >= MAX9286_NUM_GMSL)
1445 if (!of_device_is_available(node)) {
1446 dev_dbg(dev, "Skipping disabled I2C bus port %u\n", id);
1450 i2c_mux_mask |= BIT(id);
1452 of_node_put(i2c_mux);
1454 /* Parse the endpoints */
1455 for_each_endpoint_of_node(dev->of_node, node) {
1456 struct max9286_source *source;
1457 struct of_endpoint ep;
1459 of_graph_parse_endpoint(node, &ep);
1460 dev_dbg(dev, "Endpoint %pOF on port %d",
1461 ep.local_node, ep.port);
1463 if (ep.port > MAX9286_NUM_GMSL) {
1464 dev_err(dev, "Invalid endpoint %s on port %d",
1465 of_node_full_name(ep.local_node), ep.port);
1469 /* For the source endpoint just parse the bus configuration. */
1470 if (ep.port == MAX9286_SRC_PAD) {
1471 struct v4l2_fwnode_endpoint vep = {
1472 .bus_type = V4L2_MBUS_CSI2_DPHY
1476 ret = v4l2_fwnode_endpoint_parse(
1477 of_fwnode_handle(node), &vep);
1483 priv->csi2_data_lanes =
1484 vep.bus.mipi_csi2.num_data_lanes;
1489 /* Skip if the corresponding GMSL link is unavailable. */
1490 if (!(i2c_mux_mask & BIT(ep.port)))
1493 if (priv->sources[ep.port].fwnode) {
1495 "Multiple port endpoints are not supported: %d",
1501 source = &priv->sources[ep.port];
1502 source->fwnode = fwnode_graph_get_remote_endpoint(
1503 of_fwnode_handle(node));
1504 if (!source->fwnode) {
1506 "Endpoint %pOF has no remote endpoint connection\n",
1512 priv->source_mask |= BIT(ep.port);
1516 of_property_read_u32(dev->of_node, "maxim,bus-width", &priv->bus_width);
1517 switch (priv->bus_width) {
1520 * The property isn't specified in the device tree, the driver
1521 * will keep the default value selected by the BWS pin.
1528 dev_err(dev, "Invalid %s value %u\n", "maxim,bus-width",
1533 of_property_read_u32(dev->of_node, "maxim,i2c-remote-bus-hz",
1535 for (i = 0; i < ARRAY_SIZE(max9286_i2c_speeds); ++i) {
1536 const struct max9286_i2c_speed *speed = &max9286_i2c_speeds[i];
1538 if (speed->rate == i2c_clk_freq) {
1539 priv->i2c_mstbt = speed->mstbt;
1544 if (i == ARRAY_SIZE(max9286_i2c_speeds)) {
1545 dev_err(dev, "Invalid %s value %u\n", "maxim,i2c-remote-bus-hz",
1551 * Parse the initial value of the reverse channel amplitude from
1552 * the firmware interface and convert it to millivolts.
1554 * Default it to 170mV for backward compatibility with DTBs that do not
1555 * provide the property.
1557 if (of_property_read_u32(dev->of_node,
1558 "maxim,reverse-channel-microvolt",
1559 &reverse_channel_microvolt))
1560 priv->init_rev_chan_mv = 170;
1562 priv->init_rev_chan_mv = reverse_channel_microvolt / 1000U;
1564 priv->route_mask = priv->source_mask;
1569 static int max9286_get_poc_supplies(struct max9286_priv *priv)
1571 struct device *dev = &priv->client->dev;
1572 struct max9286_source *source;
1575 /* Start by getting the global regulator. */
1576 priv->regulator = devm_regulator_get_optional(dev, "poc");
1577 if (!IS_ERR(priv->regulator))
1580 if (PTR_ERR(priv->regulator) != -ENODEV)
1581 return dev_err_probe(dev, PTR_ERR(priv->regulator),
1582 "Unable to get PoC regulator\n");
1584 /* If there's no global regulator, get per-port regulators. */
1586 "No global PoC regulator, looking for per-port regulators\n");
1587 priv->regulator = NULL;
1589 for_each_source(priv, source) {
1590 unsigned int index = to_index(priv, source);
1593 snprintf(name, sizeof(name), "port%u-poc", index);
1594 source->regulator = devm_regulator_get(dev, name);
1595 if (IS_ERR(source->regulator)) {
1596 ret = PTR_ERR(source->regulator);
1597 dev_err_probe(dev, ret,
1598 "Unable to get port %u PoC regulator\n",
1607 static int max9286_probe(struct i2c_client *client)
1609 struct max9286_priv *priv;
1612 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1616 mutex_init(&priv->mutex);
1618 priv->client = client;
1620 /* GPIO values default to high */
1621 priv->gpio_state = BIT(0) | BIT(1);
1623 ret = max9286_parse_dt(priv);
1625 goto err_cleanup_dt;
1627 priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable",
1629 if (IS_ERR(priv->gpiod_pwdn)) {
1630 ret = PTR_ERR(priv->gpiod_pwdn);
1631 goto err_cleanup_dt;
1634 gpiod_set_consumer_name(priv->gpiod_pwdn, "max9286-pwdn");
1635 gpiod_set_value_cansleep(priv->gpiod_pwdn, 1);
1637 /* Wait at least 4ms before the I2C lines latch to the address */
1638 if (priv->gpiod_pwdn)
1639 usleep_range(4000, 5000);
1642 * The MAX9286 starts by default with all ports enabled, we disable all
1643 * ports early to ensure that all channels are disabled if we error out
1644 * and keep the bus consistent.
1646 max9286_i2c_mux_close(priv);
1649 * The MAX9286 initialises with auto-acknowledge enabled by default.
1650 * This can be invasive to other transactions on the same bus, so
1651 * disable it early. It will be enabled only as and when needed.
1653 max9286_configure_i2c(priv, false);
1655 ret = max9286_parse_gpios(priv);
1659 if (!priv->use_gpio_poc) {
1660 ret = max9286_get_poc_supplies(priv);
1662 goto err_cleanup_dt;
1665 ret = max9286_init(priv);
1667 goto err_cleanup_dt;
1672 gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
1674 max9286_cleanup_dt(priv);
1679 static void max9286_remove(struct i2c_client *client)
1681 struct max9286_priv *priv = sd_to_max9286(i2c_get_clientdata(client));
1683 i2c_mux_del_adapters(priv->mux);
1685 max9286_v4l2_unregister(priv);
1687 max9286_poc_enable(priv, false);
1689 gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
1691 max9286_cleanup_dt(priv);
1694 static const struct of_device_id max9286_dt_ids[] = {
1695 { .compatible = "maxim,max9286" },
1698 MODULE_DEVICE_TABLE(of, max9286_dt_ids);
1700 static struct i2c_driver max9286_i2c_driver = {
1703 .of_match_table = max9286_dt_ids,
1705 .probe = max9286_probe,
1706 .remove = max9286_remove,
1709 module_i2c_driver(max9286_i2c_driver);
1711 MODULE_DESCRIPTION("Maxim MAX9286 GMSL Deserializer Driver");
1712 MODULE_AUTHOR("Jacopo Mondi, Kieran Bingham, Laurent Pinchart, Niklas Söderlund, Vladimir Barinov");
1713 MODULE_LICENSE("GPL");