1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2022 Intel Corporation.
4 #include <asm/unaligned.h>
5 #include <linux/acpi.h>
6 #include <linux/delay.h>
8 #include <linux/module.h>
9 #include <linux/pm_runtime.h>
10 #include <media/v4l2-ctrls.h>
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-fwnode.h>
14 #define HI847_REG_VALUE_08BIT 1
15 #define HI847_REG_VALUE_16BIT 2
16 #define HI847_REG_VALUE_24BIT 3
18 #define HI847_LINK_FREQ_400MHZ 400000000ULL
19 #define HI847_LINK_FREQ_200MHZ 200000000ULL
20 #define HI847_SCLK 72000000ULL
21 #define HI847_MCLK 19200000
22 #define HI847_DATA_LANES 4
23 #define HI847_RGB_DEPTH 10
25 #define HI847_REG_CHIP_ID 0x0716
26 #define HI847_CHIP_ID 0x0847
28 #define HI847_REG_MODE_SELECT 0x0B00
29 #define HI847_MODE_STANDBY 0x0000
30 #define HI847_MODE_STREAMING 0x0100
32 #define HI847_REG_MODE_TG 0x027E
33 #define HI847_REG_MODE_TG_ENABLE 0x0100
34 #define HI847_REG_MODE_TG_DISABLE 0x0000
36 /* vertical-timings from sensor */
37 #define HI847_REG_FLL 0x020E
38 #define HI847_FLL_30FPS 0x0B51
39 #define HI847_FLL_30FPS_MIN 0x0B51
40 #define HI847_FLL_60FPS 0x05A9
41 #define HI847_FLL_60FPS_MIN 0x05A9
42 #define HI847_FLL_MAX 0x7fff
44 /* horizontal-timings from sensor */
45 #define HI847_REG_LLP 0x0206
47 /* Exposure controls from sensor */
48 #define HI847_REG_EXPOSURE 0x020A
49 #define HI847_EXPOSURE_MIN 4
50 #define HI847_EXPOSURE_MAX_MARGIN 4
51 #define HI847_EXPOSURE_STEP 1
53 /* Analog gain controls from sensor */
54 #define HI847_REG_ANALOG_GAIN 0x0212
55 #define HI847_ANAL_GAIN_MIN 0
56 #define HI847_ANAL_GAIN_MAX 240
57 #define HI847_ANAL_GAIN_STEP 1
59 /* Digital gain controls from sensor */
60 #define HI847_REG_MWB_GR_GAIN 0x0214
61 #define HI847_REG_MWB_GB_GAIN 0x0216
62 #define HI847_REG_MWB_R_GAIN 0x0218
63 #define HI847_REG_MWB_B_GAIN 0x021A
64 #define HI847_DGTL_GAIN_MIN 1
65 #define HI847_DGTL_GAIN_MAX 8191
66 #define HI847_DGTL_GAIN_STEP 1
67 #define HI847_DGTL_GAIN_DEFAULT 512
69 /* Test Pattern Control */
70 #define HI847_REG_ISP 0X0B04
71 #define HI847_REG_ISP_TPG_EN 0x0001
72 #define HI847_REG_TEST_PATTERN 0x0C0A
74 /* Flip Mirror Controls from sensor */
75 #define HI847_REG_MIRROR_FLIP 0x0202
77 #define HI847_REG_FORMAT_X 0x0F04
78 #define HI847_REG_FORMAT_Y 0x0F06
81 HI847_LINK_FREQ_400MHZ_INDEX,
82 HI847_LINK_FREQ_200MHZ_INDEX,
90 struct hi847_reg_list {
92 const struct hi847_reg *regs;
95 struct hi847_link_freq_config {
96 const struct hi847_reg_list reg_list;
100 /* Frame width in pixels */
103 /* Frame height in pixels */
106 /* Horizontal timining size */
109 /* Default vertical timining size */
112 /* Min vertical timining size */
115 /* Link frequency needed for this resolution */
118 /* Sensor register settings for this resolution */
119 const struct hi847_reg_list reg_list;
122 #define to_hi847(_sd) container_of(_sd, struct hi847, sd)
124 //SENSOR_INITIALIZATION
125 static const struct hi847_reg mipi_data_rate_lane_4[] = {
1917 static const struct hi847_reg mode_3264x2448_regs[] = {
2013 static const struct hi847_reg mode_1632x1224_regs[] = {
2109 static const char * const hi847_test_pattern_menu[] = {
2113 "Fade To Grey Colour Bars",
2115 "Horizontal Gradient Pattern",
2116 "Vertical Gradient Pattern",
2121 static const s64 link_freq_menu_items[] = {
2122 HI847_LINK_FREQ_400MHZ,
2123 HI847_LINK_FREQ_200MHZ,
2126 static const struct hi847_link_freq_config link_freq_configs[] = {
2127 [HI847_LINK_FREQ_400MHZ_INDEX] = {
2129 .num_of_regs = ARRAY_SIZE(mipi_data_rate_lane_4),
2130 .regs = mipi_data_rate_lane_4,
2133 [HI847_LINK_FREQ_200MHZ_INDEX] = {
2135 .num_of_regs = ARRAY_SIZE(mipi_data_rate_lane_4),
2136 .regs = mipi_data_rate_lane_4,
2141 static const struct hi847_mode supported_modes[] = {
2145 .fll_def = HI847_FLL_30FPS,
2146 .fll_min = HI847_FLL_30FPS_MIN,
2149 .num_of_regs = ARRAY_SIZE(mode_3264x2448_regs),
2150 .regs = mode_3264x2448_regs,
2152 .link_freq_index = HI847_LINK_FREQ_400MHZ_INDEX,
2157 .fll_def = HI847_FLL_60FPS,
2158 .fll_min = HI847_FLL_60FPS_MIN,
2161 .num_of_regs = ARRAY_SIZE(mode_1632x1224_regs),
2162 .regs = mode_1632x1224_regs,
2164 .link_freq_index = HI847_LINK_FREQ_200MHZ_INDEX,
2169 struct v4l2_subdev sd;
2170 struct media_pad pad;
2171 struct v4l2_ctrl_handler ctrl_handler;
2174 struct v4l2_ctrl *link_freq;
2175 struct v4l2_ctrl *pixel_rate;
2176 struct v4l2_ctrl *vblank;
2177 struct v4l2_ctrl *hblank;
2178 struct v4l2_ctrl *exposure;
2179 struct v4l2_ctrl *vflip;
2180 struct v4l2_ctrl *hflip;
2183 const struct hi847_mode *cur_mode;
2185 /* To serialize asynchronus callbacks */
2188 /* Streaming on/off */
2192 static u64 to_pixel_rate(u32 f_index)
2194 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * HI847_DATA_LANES;
2196 do_div(pixel_rate, HI847_RGB_DEPTH);
2201 static int hi847_read_reg(struct hi847 *hi847, u16 reg, u16 len, u32 *val)
2203 struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd);
2204 struct i2c_msg msgs[2];
2206 u8 data_buf[4] = {0};
2212 put_unaligned_be16(reg, addr_buf);
2213 msgs[0].addr = client->addr;
2215 msgs[0].len = sizeof(addr_buf);
2216 msgs[0].buf = addr_buf;
2217 msgs[1].addr = client->addr;
2218 msgs[1].flags = I2C_M_RD;
2220 msgs[1].buf = &data_buf[4 - len];
2222 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
2223 if (ret != ARRAY_SIZE(msgs))
2226 *val = get_unaligned_be32(data_buf);
2231 static int hi847_write_reg(struct hi847 *hi847, u16 reg, u16 len, u32 val)
2233 struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd);
2239 put_unaligned_be16(reg, buf);
2240 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
2241 if (i2c_master_send(client, buf, len + 2) != len + 2)
2247 static int hi847_write_reg_list(struct hi847 *hi847,
2248 const struct hi847_reg_list *r_list)
2250 struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd);
2254 for (i = 0; i < r_list->num_of_regs; i++) {
2255 ret = hi847_write_reg(hi847, r_list->regs[i].address,
2256 HI847_REG_VALUE_16BIT,
2257 r_list->regs[i].val);
2259 dev_err_ratelimited(&client->dev,
2260 "failed to write reg 0x%4.4x. error = %d",
2261 r_list->regs[i].address, ret);
2269 static int hi847_update_digital_gain(struct hi847 *hi847, u32 d_gain)
2273 ret = hi847_write_reg(hi847, HI847_REG_MWB_GR_GAIN,
2274 HI847_REG_VALUE_16BIT, d_gain);
2278 ret = hi847_write_reg(hi847, HI847_REG_MWB_GB_GAIN,
2279 HI847_REG_VALUE_16BIT, d_gain);
2283 ret = hi847_write_reg(hi847, HI847_REG_MWB_R_GAIN,
2284 HI847_REG_VALUE_16BIT, d_gain);
2288 return hi847_write_reg(hi847, HI847_REG_MWB_B_GAIN,
2289 HI847_REG_VALUE_16BIT, d_gain);
2292 static int hi847_test_pattern(struct hi847 *hi847, u32 pattern)
2298 ret = hi847_read_reg(hi847, HI847_REG_ISP,
2299 HI847_REG_VALUE_16BIT, &val);
2303 ret = hi847_write_reg(hi847, HI847_REG_ISP,
2304 HI847_REG_VALUE_16BIT,
2305 val | HI847_REG_ISP_TPG_EN);
2310 ret = hi847_read_reg(hi847, HI847_REG_TEST_PATTERN,
2311 HI847_REG_VALUE_16BIT, &val);
2315 return hi847_write_reg(hi847, HI847_REG_TEST_PATTERN,
2316 HI847_REG_VALUE_16BIT, val | pattern << 8);
2319 static int hi847_grbg_shift(struct hi847 *hi847)
2324 /* regs shift for full size */
2325 static const u32 FORMAT_X_SHIFT_1[2][2] = {
2326 { 0x0008, 0x0007, },
2327 { 0x0008, 0x0007, },
2330 static const u32 FORMAT_Y_SHIFT_1[2][2] = {
2331 { 0x0002, 0x0002, },
2332 { 0x0001, 0x0001, },
2335 /* regs shift for binning size */
2336 static const u32 FORMAT_X_SHIFT_2[2][2] = {
2337 { 0x0004, 0x0003, },
2338 { 0x0004, 0x0003, },
2341 static const u32 FORMAT_Y_SHIFT_2[2][2] = {
2342 { 0x0002, 0x0002, },
2343 { 0x0001, 0x0001, },
2346 hflip = hi847->hflip->val;
2347 vflip = hi847->vflip->val;
2349 if (hi847->cur_mode->width == 3264) {
2350 ret = hi847_write_reg(hi847, HI847_REG_FORMAT_X,
2351 HI847_REG_VALUE_16BIT,
2352 FORMAT_X_SHIFT_1[vflip][hflip]);
2356 return hi847_write_reg(hi847, HI847_REG_FORMAT_Y,
2357 HI847_REG_VALUE_16BIT,
2358 FORMAT_Y_SHIFT_1[vflip][hflip]);
2360 ret = hi847_write_reg(hi847, HI847_REG_FORMAT_X,
2361 HI847_REG_VALUE_16BIT,
2362 FORMAT_X_SHIFT_2[vflip][hflip]);
2366 return hi847_write_reg(hi847, HI847_REG_FORMAT_Y,
2367 HI847_REG_VALUE_16BIT,
2368 FORMAT_Y_SHIFT_2[vflip][hflip]);
2372 static int hi847_set_ctrl_hflip(struct hi847 *hi847, u32 ctrl_val)
2377 ret = hi847_read_reg(hi847, HI847_REG_MIRROR_FLIP,
2378 HI847_REG_VALUE_16BIT, &val);
2382 ret = hi847_grbg_shift(hi847);
2386 return hi847_write_reg(hi847, HI847_REG_MIRROR_FLIP,
2387 HI847_REG_VALUE_16BIT,
2388 ctrl_val ? val | BIT(8) : val & ~BIT(8));
2391 static int hi847_set_ctrl_vflip(struct hi847 *hi847, u8 ctrl_val)
2396 ret = hi847_read_reg(hi847, HI847_REG_MIRROR_FLIP,
2397 HI847_REG_VALUE_16BIT, &val);
2401 ret = hi847_grbg_shift(hi847);
2405 return hi847_write_reg(hi847, HI847_REG_MIRROR_FLIP,
2406 HI847_REG_VALUE_16BIT,
2407 ctrl_val ? val | BIT(9) : val & ~BIT(9));
2410 static int hi847_set_ctrl(struct v4l2_ctrl *ctrl)
2412 struct hi847 *hi847 = container_of(ctrl->handler,
2413 struct hi847, ctrl_handler);
2414 struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd);
2418 /* Propagate change of current control to all related controls */
2419 if (ctrl->id == V4L2_CID_VBLANK) {
2420 /* Update max exposure while meeting expected vblanking */
2421 exposure_max = hi847->cur_mode->height + ctrl->val -
2422 HI847_EXPOSURE_MAX_MARGIN;
2423 __v4l2_ctrl_modify_range(hi847->exposure,
2424 hi847->exposure->minimum,
2425 exposure_max, hi847->exposure->step,
2429 /* V4L2 controls values will be applied only when power is already up */
2430 if (!pm_runtime_get_if_in_use(&client->dev))
2434 case V4L2_CID_ANALOGUE_GAIN:
2435 ret = hi847_write_reg(hi847, HI847_REG_ANALOG_GAIN,
2436 HI847_REG_VALUE_16BIT, ctrl->val);
2439 case V4L2_CID_DIGITAL_GAIN:
2440 ret = hi847_update_digital_gain(hi847, ctrl->val);
2443 case V4L2_CID_EXPOSURE:
2444 ret = hi847_write_reg(hi847, HI847_REG_EXPOSURE,
2445 HI847_REG_VALUE_16BIT, ctrl->val);
2448 case V4L2_CID_VBLANK:
2449 /* Update FLL that meets expected vertical blanking */
2450 ret = hi847_write_reg(hi847, HI847_REG_FLL,
2451 HI847_REG_VALUE_16BIT,
2452 hi847->cur_mode->height + ctrl->val);
2455 case V4L2_CID_TEST_PATTERN:
2456 ret = hi847_test_pattern(hi847, ctrl->val);
2459 case V4L2_CID_HFLIP:
2460 hi847_set_ctrl_hflip(hi847, ctrl->val);
2463 case V4L2_CID_VFLIP:
2464 hi847_set_ctrl_vflip(hi847, ctrl->val);
2472 pm_runtime_put(&client->dev);
2477 static const struct v4l2_ctrl_ops hi847_ctrl_ops = {
2478 .s_ctrl = hi847_set_ctrl,
2481 static int hi847_init_controls(struct hi847 *hi847)
2483 struct v4l2_ctrl_handler *ctrl_hdlr;
2484 s64 exposure_max, h_blank;
2487 ctrl_hdlr = &hi847->ctrl_handler;
2488 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
2492 ctrl_hdlr->lock = &hi847->mutex;
2493 hi847->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &hi847_ctrl_ops,
2495 ARRAY_SIZE(link_freq_menu_items) - 1,
2496 0, link_freq_menu_items);
2497 if (hi847->link_freq)
2498 hi847->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2500 hi847->pixel_rate = v4l2_ctrl_new_std
2501 (ctrl_hdlr, &hi847_ctrl_ops,
2502 V4L2_CID_PIXEL_RATE, 0,
2503 to_pixel_rate(HI847_LINK_FREQ_400MHZ_INDEX),
2505 to_pixel_rate(HI847_LINK_FREQ_400MHZ_INDEX));
2506 hi847->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops,
2508 hi847->cur_mode->fll_min -
2509 hi847->cur_mode->height,
2511 hi847->cur_mode->height, 1,
2512 hi847->cur_mode->fll_def -
2513 hi847->cur_mode->height);
2515 h_blank = hi847->cur_mode->llp - hi847->cur_mode->width;
2517 hi847->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops,
2518 V4L2_CID_HBLANK, h_blank, h_blank, 1,
2521 hi847->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2523 v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
2524 HI847_ANAL_GAIN_MIN, HI847_ANAL_GAIN_MAX,
2525 HI847_ANAL_GAIN_STEP, HI847_ANAL_GAIN_MIN);
2526 v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
2527 HI847_DGTL_GAIN_MIN, HI847_DGTL_GAIN_MAX,
2528 HI847_DGTL_GAIN_STEP, HI847_DGTL_GAIN_DEFAULT);
2529 exposure_max = hi847->cur_mode->fll_def - HI847_EXPOSURE_MAX_MARGIN;
2530 hi847->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops,
2532 HI847_EXPOSURE_MIN, exposure_max,
2533 HI847_EXPOSURE_STEP,
2535 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &hi847_ctrl_ops,
2536 V4L2_CID_TEST_PATTERN,
2537 ARRAY_SIZE(hi847_test_pattern_menu) - 1,
2538 0, 0, hi847_test_pattern_menu);
2539 hi847->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops,
2540 V4L2_CID_HFLIP, 0, 1, 1, 0);
2541 hi847->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &hi847_ctrl_ops,
2542 V4L2_CID_VFLIP, 0, 1, 1, 0);
2544 if (ctrl_hdlr->error)
2545 return ctrl_hdlr->error;
2547 hi847->sd.ctrl_handler = ctrl_hdlr;
2552 static void hi847_assign_pad_format(const struct hi847_mode *mode,
2553 struct v4l2_mbus_framefmt *fmt)
2555 fmt->width = mode->width;
2556 fmt->height = mode->height;
2557 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
2558 fmt->field = V4L2_FIELD_NONE;
2561 static int hi847_start_streaming(struct hi847 *hi847)
2563 struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd);
2564 const struct hi847_reg_list *reg_list;
2565 int link_freq_index, ret;
2567 link_freq_index = hi847->cur_mode->link_freq_index;
2568 reg_list = &link_freq_configs[link_freq_index].reg_list;
2569 ret = hi847_write_reg_list(hi847, reg_list);
2571 dev_err(&client->dev, "failed to set plls");
2575 reg_list = &hi847->cur_mode->reg_list;
2576 ret = hi847_write_reg_list(hi847, reg_list);
2578 dev_err(&client->dev, "failed to set mode");
2582 ret = __v4l2_ctrl_handler_setup(hi847->sd.ctrl_handler);
2586 ret = hi847_write_reg(hi847, HI847_REG_MODE_TG,
2587 HI847_REG_VALUE_16BIT, HI847_REG_MODE_TG_ENABLE);
2589 ret = hi847_write_reg(hi847, HI847_REG_MODE_SELECT,
2590 HI847_REG_VALUE_16BIT, HI847_MODE_STREAMING);
2593 dev_err(&client->dev, "failed to set stream");
2600 static void hi847_stop_streaming(struct hi847 *hi847)
2602 struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd);
2604 if (hi847_write_reg(hi847, HI847_REG_MODE_TG,
2605 HI847_REG_VALUE_16BIT, HI847_REG_MODE_TG_DISABLE))
2606 dev_err(&client->dev, "failed to set stream 0x%x",
2609 if (hi847_write_reg(hi847, HI847_REG_MODE_SELECT,
2610 HI847_REG_VALUE_16BIT, HI847_MODE_STANDBY))
2611 dev_err(&client->dev, "failed to set stream 0x%x",
2612 HI847_REG_MODE_SELECT);
2615 static int hi847_set_stream(struct v4l2_subdev *sd, int enable)
2617 struct hi847 *hi847 = to_hi847(sd);
2618 struct i2c_client *client = v4l2_get_subdevdata(sd);
2621 if (hi847->streaming == enable)
2624 mutex_lock(&hi847->mutex);
2626 ret = pm_runtime_get_sync(&client->dev);
2628 pm_runtime_put_noidle(&client->dev);
2629 mutex_unlock(&hi847->mutex);
2633 ret = hi847_start_streaming(hi847);
2636 hi847_stop_streaming(hi847);
2637 pm_runtime_put(&client->dev);
2640 hi847_stop_streaming(hi847);
2641 pm_runtime_put(&client->dev);
2644 hi847->streaming = enable;
2645 mutex_unlock(&hi847->mutex);
2650 static int __maybe_unused hi847_suspend(struct device *dev)
2652 struct i2c_client *client = to_i2c_client(dev);
2653 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2654 struct hi847 *hi847 = to_hi847(sd);
2656 mutex_lock(&hi847->mutex);
2657 if (hi847->streaming)
2658 hi847_stop_streaming(hi847);
2660 mutex_unlock(&hi847->mutex);
2665 static int __maybe_unused hi847_resume(struct device *dev)
2667 struct i2c_client *client = to_i2c_client(dev);
2668 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2669 struct hi847 *hi847 = to_hi847(sd);
2672 mutex_lock(&hi847->mutex);
2673 if (hi847->streaming) {
2674 ret = hi847_start_streaming(hi847);
2679 mutex_unlock(&hi847->mutex);
2684 hi847_stop_streaming(hi847);
2685 hi847->streaming = 0;
2686 mutex_unlock(&hi847->mutex);
2690 static int hi847_set_format(struct v4l2_subdev *sd,
2691 struct v4l2_subdev_state *sd_state,
2692 struct v4l2_subdev_format *fmt)
2694 struct hi847 *hi847 = to_hi847(sd);
2695 const struct hi847_mode *mode;
2696 s32 vblank_def, h_blank;
2698 mode = v4l2_find_nearest_size(supported_modes,
2699 ARRAY_SIZE(supported_modes), width,
2700 height, fmt->format.width,
2701 fmt->format.height);
2703 mutex_lock(&hi847->mutex);
2704 hi847_assign_pad_format(mode, &fmt->format);
2705 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
2706 *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) =
2709 hi847->cur_mode = mode;
2710 __v4l2_ctrl_s_ctrl(hi847->link_freq, mode->link_freq_index);
2711 __v4l2_ctrl_s_ctrl_int64(hi847->pixel_rate,
2712 to_pixel_rate(mode->link_freq_index));
2714 /* Update limits and set FPS to default */
2715 vblank_def = mode->fll_def - mode->height;
2716 __v4l2_ctrl_modify_range(hi847->vblank,
2717 mode->fll_min - mode->height,
2718 HI847_FLL_MAX - mode->height, 1,
2720 __v4l2_ctrl_s_ctrl(hi847->vblank, vblank_def);
2722 h_blank = hi847->cur_mode->llp - hi847->cur_mode->width;
2724 __v4l2_ctrl_modify_range(hi847->hblank, h_blank, h_blank, 1,
2728 mutex_unlock(&hi847->mutex);
2733 static int hi847_get_format(struct v4l2_subdev *sd,
2734 struct v4l2_subdev_state *sd_state,
2735 struct v4l2_subdev_format *fmt)
2737 struct hi847 *hi847 = to_hi847(sd);
2739 mutex_lock(&hi847->mutex);
2740 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
2741 fmt->format = *v4l2_subdev_get_try_format(&hi847->sd,
2745 hi847_assign_pad_format(hi847->cur_mode, &fmt->format);
2747 mutex_unlock(&hi847->mutex);
2752 static int hi847_enum_mbus_code(struct v4l2_subdev *sd,
2753 struct v4l2_subdev_state *sd_state,
2754 struct v4l2_subdev_mbus_code_enum *code)
2756 if (code->index > 0)
2759 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
2764 static int hi847_enum_frame_size(struct v4l2_subdev *sd,
2765 struct v4l2_subdev_state *sd_state,
2766 struct v4l2_subdev_frame_size_enum *fse)
2768 if (fse->index >= ARRAY_SIZE(supported_modes))
2771 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
2774 fse->min_width = supported_modes[fse->index].width;
2775 fse->max_width = fse->min_width;
2776 fse->min_height = supported_modes[fse->index].height;
2777 fse->max_height = fse->min_height;
2782 static int hi847_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
2784 struct hi847 *hi847 = to_hi847(sd);
2786 mutex_lock(&hi847->mutex);
2787 hi847_assign_pad_format(&supported_modes[0],
2788 v4l2_subdev_get_try_format(sd, fh->state, 0));
2789 mutex_unlock(&hi847->mutex);
2794 static const struct v4l2_subdev_video_ops hi847_video_ops = {
2795 .s_stream = hi847_set_stream,
2798 static const struct v4l2_subdev_pad_ops hi847_pad_ops = {
2799 .set_fmt = hi847_set_format,
2800 .get_fmt = hi847_get_format,
2801 .enum_mbus_code = hi847_enum_mbus_code,
2802 .enum_frame_size = hi847_enum_frame_size,
2805 static const struct v4l2_subdev_ops hi847_subdev_ops = {
2806 .video = &hi847_video_ops,
2807 .pad = &hi847_pad_ops,
2810 static const struct media_entity_operations hi847_subdev_entity_ops = {
2811 .link_validate = v4l2_subdev_link_validate,
2814 static const struct v4l2_subdev_internal_ops hi847_internal_ops = {
2818 static int hi847_identify_module(struct hi847 *hi847)
2820 struct i2c_client *client = v4l2_get_subdevdata(&hi847->sd);
2824 ret = hi847_read_reg(hi847, HI847_REG_CHIP_ID,
2825 HI847_REG_VALUE_16BIT, &val);
2829 if (val != HI847_CHIP_ID) {
2830 dev_err(&client->dev, "chip id mismatch: %x!=%x",
2831 HI847_CHIP_ID, val);
2838 static int hi847_check_hwcfg(struct device *dev)
2840 struct fwnode_handle *ep;
2841 struct fwnode_handle *fwnode = dev_fwnode(dev);
2842 struct v4l2_fwnode_endpoint bus_cfg = {
2843 .bus_type = V4L2_MBUS_CSI2_DPHY
2852 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
2854 dev_err(dev, "can't get clock frequency");
2858 if (mclk != HI847_MCLK) {
2859 dev_err(dev, "external clock %d is not supported", mclk);
2863 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
2867 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
2868 fwnode_handle_put(ep);
2872 if (bus_cfg.bus.mipi_csi2.num_data_lanes != HI847_DATA_LANES) {
2873 dev_err(dev, "number of CSI2 data lanes %d is not supported",
2874 bus_cfg.bus.mipi_csi2.num_data_lanes);
2876 goto check_hwcfg_error;
2879 if (!bus_cfg.nr_of_link_frequencies) {
2880 dev_err(dev, "no link frequencies defined");
2882 goto check_hwcfg_error;
2885 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
2886 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
2887 if (link_freq_menu_items[i] ==
2888 bus_cfg.link_frequencies[j])
2892 if (j == bus_cfg.nr_of_link_frequencies) {
2893 dev_err(dev, "no link frequency %lld supported",
2894 link_freq_menu_items[i]);
2896 goto check_hwcfg_error;
2901 v4l2_fwnode_endpoint_free(&bus_cfg);
2906 static void hi847_remove(struct i2c_client *client)
2908 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2909 struct hi847 *hi847 = to_hi847(sd);
2911 v4l2_async_unregister_subdev(sd);
2912 media_entity_cleanup(&sd->entity);
2913 v4l2_ctrl_handler_free(sd->ctrl_handler);
2914 pm_runtime_disable(&client->dev);
2915 mutex_destroy(&hi847->mutex);
2918 static int hi847_probe(struct i2c_client *client)
2920 struct hi847 *hi847;
2923 hi847 = devm_kzalloc(&client->dev, sizeof(*hi847), GFP_KERNEL);
2927 ret = hi847_check_hwcfg(&client->dev);
2929 dev_err(&client->dev, "failed to get HW configuration: %d",
2934 v4l2_i2c_subdev_init(&hi847->sd, client, &hi847_subdev_ops);
2935 ret = hi847_identify_module(hi847);
2937 dev_err(&client->dev, "failed to find sensor: %d", ret);
2941 mutex_init(&hi847->mutex);
2942 hi847->cur_mode = &supported_modes[0];
2943 ret = hi847_init_controls(hi847);
2945 dev_err(&client->dev, "failed to init controls: %d", ret);
2946 goto probe_error_v4l2_ctrl_handler_free;
2949 hi847->sd.internal_ops = &hi847_internal_ops;
2950 hi847->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2951 hi847->sd.entity.ops = &hi847_subdev_entity_ops;
2952 hi847->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
2953 hi847->pad.flags = MEDIA_PAD_FL_SOURCE;
2954 ret = media_entity_pads_init(&hi847->sd.entity, 1, &hi847->pad);
2956 dev_err(&client->dev, "failed to init entity pads: %d", ret);
2957 goto probe_error_v4l2_ctrl_handler_free;
2960 ret = v4l2_async_register_subdev_sensor(&hi847->sd);
2962 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
2964 goto probe_error_media_entity_cleanup;
2967 pm_runtime_set_active(&client->dev);
2968 pm_runtime_enable(&client->dev);
2969 pm_runtime_idle(&client->dev);
2973 probe_error_media_entity_cleanup:
2974 media_entity_cleanup(&hi847->sd.entity);
2976 probe_error_v4l2_ctrl_handler_free:
2977 v4l2_ctrl_handler_free(hi847->sd.ctrl_handler);
2978 mutex_destroy(&hi847->mutex);
2983 static const struct dev_pm_ops hi847_pm_ops = {
2984 SET_SYSTEM_SLEEP_PM_OPS(hi847_suspend, hi847_resume)
2988 static const struct acpi_device_id hi847_acpi_ids[] = {
2993 MODULE_DEVICE_TABLE(acpi, hi847_acpi_ids);
2996 static struct i2c_driver hi847_i2c_driver = {
2999 .pm = &hi847_pm_ops,
3000 .acpi_match_table = ACPI_PTR(hi847_acpi_ids),
3002 .probe_new = hi847_probe,
3003 .remove = hi847_remove,
3006 module_i2c_driver(hi847_i2c_driver);
3008 MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
3009 MODULE_DESCRIPTION("Hynix HI847 sensor driver");
3010 MODULE_LICENSE("GPL v2");