1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2020 MediaTek Inc.
4 #include <linux/delay.h>
6 #include <linux/module.h>
7 #include <linux/pm_runtime.h>
8 #include <linux/regulator/consumer.h>
9 #include <media/v4l2-async.h>
10 #include <media/v4l2-ctrls.h>
11 #include <media/v4l2-device.h>
12 #include <media/v4l2-fwnode.h>
13 #include <media/v4l2-subdev.h>
15 #define DW9768_NAME "dw9768"
16 #define DW9768_MAX_FOCUS_POS (1024 - 1)
18 * This sets the minimum granularity for the focus positions.
19 * A value of 1 gives maximum accuracy for a desired focus position
21 #define DW9768_FOCUS_STEPS 1
24 * Ring control and Power control register
27 * 1: AAC mode (ringing control mode)
29 * 0: Normal operation mode
31 * DW9768 requires waiting time of Topr after PD reset takes place.
33 #define DW9768_RING_PD_CONTROL_REG 0x02
34 #define DW9768_PD_MODE_OFF 0x00
35 #define DW9768_PD_MODE_EN BIT(0)
36 #define DW9768_AAC_MODE_EN BIT(1)
39 * DW9768 separates two registers to control the VCM position.
40 * One for MSB value, another is LSB value.
41 * DAC_MSB: D[9:8] (ADD: 0x03)
42 * DAC_LSB: D[7:0] (ADD: 0x04)
43 * D[9:0] DAC data input: positive output current = D[9:0] / 1023 * 100[mA]
45 #define DW9768_MSB_ADDR 0x03
46 #define DW9768_LSB_ADDR 0x04
47 #define DW9768_STATUS_ADDR 0x05
50 * AAC mode control & prescale register
51 * Bit[7:5] Namely AC[2:0], decide the VCM mode and operation time.
52 * 001 AAC2 0.48 x Tvib
53 * 010 AAC3 0.70 x Tvib
54 * 011 AAC4 0.75 x Tvib
55 * 101 AAC8 1.13 x Tvib
56 * Bit[2:0] Namely PRESC[2:0], set the internal clock dividing rate as follow.
64 #define DW9768_AAC_PRESC_REG 0x06
65 #define DW9768_AAC_MODE_SEL_MASK GENMASK(7, 5)
66 #define DW9768_CLOCK_PRE_SCALE_SEL_MASK GENMASK(2, 0)
69 * VCM period of vibration register
70 * Bit[5:0] Defined as VCM rising periodic time (Tvib) together with PRESC[2:0]
71 * Tvib = (6.3ms + AACT[5:0] * 0.1ms) * Dividing Rate
72 * Dividing Rate is the internal clock dividing rate that is defined at
73 * PRESCALE register (ADD: 0x06)
75 #define DW9768_AAC_TIME_REG 0x07
78 * DW9768 requires waiting time (delay time) of t_OPR after power-up,
79 * or in the case of PD reset taking place.
81 #define DW9768_T_OPR_US 1000
82 #define DW9768_TVIB_MS_BASE10 (64 - 1)
83 #define DW9768_AAC_MODE_DEFAULT 2
84 #define DW9768_AAC_TIME_DEFAULT 0x20
85 #define DW9768_CLOCK_PRE_SCALE_DEFAULT 1
88 * This acts as the minimum granularity of lens movement.
89 * Keep this value power of 2, so the control steps can be
90 * uniformly adjusted for gradual lens movement, with desired
91 * number of control steps.
93 #define DW9768_MOVE_STEPS 16
95 static const char * const dw9768_supply_names[] = {
96 "vin", /* Digital I/O power */
97 "vdd", /* Digital core power */
100 /* dw9768 device structure */
102 struct regulator_bulk_data supplies[ARRAY_SIZE(dw9768_supply_names)];
103 struct v4l2_ctrl_handler ctrls;
104 struct v4l2_ctrl *focus;
105 struct v4l2_subdev sd;
113 static inline struct dw9768 *sd_to_dw9768(struct v4l2_subdev *subdev)
115 return container_of(subdev, struct dw9768, sd);
123 struct dw9768_aac_mode_ot_multi {
125 u32 ot_multi_base100;
128 struct dw9768_clk_presc_dividing_rate {
130 u32 dividing_rate_base100;
133 static const struct dw9768_aac_mode_ot_multi aac_mode_ot_multi[] = {
140 static const struct dw9768_clk_presc_dividing_rate presc_dividing_rate[] = {
149 static u32 dw9768_find_ot_multi(u32 aac_mode_param)
151 u32 cur_ot_multi_base100 = 70;
154 for (i = 0; i < ARRAY_SIZE(aac_mode_ot_multi); i++) {
155 if (aac_mode_ot_multi[i].aac_mode_enum == aac_mode_param) {
156 cur_ot_multi_base100 =
157 aac_mode_ot_multi[i].ot_multi_base100;
161 return cur_ot_multi_base100;
164 static u32 dw9768_find_dividing_rate(u32 presc_param)
166 u32 cur_clk_dividing_rate_base100 = 100;
169 for (i = 0; i < ARRAY_SIZE(presc_dividing_rate); i++) {
170 if (presc_dividing_rate[i].clk_presc_enum == presc_param) {
171 cur_clk_dividing_rate_base100 =
172 presc_dividing_rate[i].dividing_rate_base100;
176 return cur_clk_dividing_rate_base100;
180 * DW9768_AAC_PRESC_REG & DW9768_AAC_TIME_REG determine VCM operation time.
181 * For current VCM mode: AAC3, Operation Time would be 0.70 x Tvib.
182 * Tvib = (6.3ms + AACT[5:0] * 0.1MS) * Dividing Rate.
183 * Below is calculation of the operation delay for each step.
185 static inline u32 dw9768_cal_move_delay(u32 aac_mode_param, u32 presc_param,
186 u32 aac_timing_param)
189 u32 ot_multi_base100;
190 u32 clk_dividing_rate_base100;
192 ot_multi_base100 = dw9768_find_ot_multi(aac_mode_param);
194 clk_dividing_rate_base100 = dw9768_find_dividing_rate(presc_param);
196 Tvib_us = (DW9768_TVIB_MS_BASE10 + aac_timing_param) *
197 clk_dividing_rate_base100;
199 return Tvib_us * ot_multi_base100 / 100;
202 static int dw9768_mod_reg(struct dw9768 *dw9768, u8 reg, u8 mask, u8 val)
204 struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
207 ret = i2c_smbus_read_byte_data(client, reg);
211 val = ((unsigned char)ret & ~mask) | (val & mask);
213 return i2c_smbus_write_byte_data(client, reg, val);
216 static int dw9768_set_dac(struct dw9768 *dw9768, u16 val)
218 struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
220 /* Write VCM position to registers */
221 return i2c_smbus_write_word_swapped(client, DW9768_MSB_ADDR, val);
224 static int dw9768_init(struct dw9768 *dw9768)
226 struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
229 /* Reset DW9768_RING_PD_CONTROL_REG to default status 0x00 */
230 ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
236 * DW9769 requires waiting delay time of t_OPR
237 * after PD reset takes place.
239 usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
241 /* Set DW9768_RING_PD_CONTROL_REG to DW9768_AAC_MODE_EN(0x01) */
242 ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
248 ret = dw9768_mod_reg(dw9768, DW9768_AAC_PRESC_REG,
249 DW9768_AAC_MODE_SEL_MASK,
250 dw9768->aac_mode << 5);
254 /* Set clock presc */
255 if (dw9768->clock_presc != DW9768_CLOCK_PRE_SCALE_DEFAULT) {
256 ret = dw9768_mod_reg(dw9768, DW9768_AAC_PRESC_REG,
257 DW9768_CLOCK_PRE_SCALE_SEL_MASK,
258 dw9768->clock_presc);
264 if (dw9768->aac_timing != DW9768_AAC_TIME_DEFAULT) {
265 ret = i2c_smbus_write_byte_data(client, DW9768_AAC_TIME_REG,
271 for (val = dw9768->focus->val % DW9768_MOVE_STEPS;
272 val <= dw9768->focus->val;
273 val += DW9768_MOVE_STEPS) {
274 ret = dw9768_set_dac(dw9768, val);
276 dev_err(&client->dev, "I2C failure: %d", ret);
279 usleep_range(dw9768->move_delay_us,
280 dw9768->move_delay_us + 1000);
286 static int dw9768_release(struct dw9768 *dw9768)
288 struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
291 val = round_down(dw9768->focus->val, DW9768_MOVE_STEPS);
292 for ( ; val >= 0; val -= DW9768_MOVE_STEPS) {
293 ret = dw9768_set_dac(dw9768, val);
295 dev_err(&client->dev, "I2C write fail: %d", ret);
298 usleep_range(dw9768->move_delay_us,
299 dw9768->move_delay_us + 1000);
302 ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
308 * DW9769 requires waiting delay time of t_OPR
309 * after PD reset takes place.
311 usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
316 static int dw9768_runtime_suspend(struct device *dev)
318 struct i2c_client *client = to_i2c_client(dev);
319 struct v4l2_subdev *sd = i2c_get_clientdata(client);
320 struct dw9768 *dw9768 = sd_to_dw9768(sd);
322 dw9768_release(dw9768);
323 regulator_bulk_disable(ARRAY_SIZE(dw9768_supply_names),
329 static int dw9768_runtime_resume(struct device *dev)
331 struct i2c_client *client = to_i2c_client(dev);
332 struct v4l2_subdev *sd = i2c_get_clientdata(client);
333 struct dw9768 *dw9768 = sd_to_dw9768(sd);
336 ret = regulator_bulk_enable(ARRAY_SIZE(dw9768_supply_names),
339 dev_err(dev, "failed to enable regulators\n");
344 * The datasheet refers to t_OPR that needs to be waited before sending
345 * I2C commands after power-up.
347 usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
349 ret = dw9768_init(dw9768);
351 goto disable_regulator;
356 regulator_bulk_disable(ARRAY_SIZE(dw9768_supply_names),
362 static int dw9768_set_ctrl(struct v4l2_ctrl *ctrl)
364 struct dw9768 *dw9768 = container_of(ctrl->handler,
365 struct dw9768, ctrls);
367 if (ctrl->id == V4L2_CID_FOCUS_ABSOLUTE)
368 return dw9768_set_dac(dw9768, ctrl->val);
373 static const struct v4l2_ctrl_ops dw9768_ctrl_ops = {
374 .s_ctrl = dw9768_set_ctrl,
377 static int dw9768_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
381 ret = pm_runtime_get_sync(sd->dev);
383 pm_runtime_put_noidle(sd->dev);
390 static int dw9768_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
392 pm_runtime_put(sd->dev);
397 static const struct v4l2_subdev_internal_ops dw9768_int_ops = {
399 .close = dw9768_close,
402 static const struct v4l2_subdev_ops dw9768_ops = { };
404 static int dw9768_init_controls(struct dw9768 *dw9768)
406 struct v4l2_ctrl_handler *hdl = &dw9768->ctrls;
407 const struct v4l2_ctrl_ops *ops = &dw9768_ctrl_ops;
409 v4l2_ctrl_handler_init(hdl, 1);
411 dw9768->focus = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_ABSOLUTE, 0,
412 DW9768_MAX_FOCUS_POS,
413 DW9768_FOCUS_STEPS, 0);
418 dw9768->sd.ctrl_handler = hdl;
423 static int dw9768_probe(struct i2c_client *client)
425 struct device *dev = &client->dev;
426 struct dw9768 *dw9768;
430 dw9768 = devm_kzalloc(dev, sizeof(*dw9768), GFP_KERNEL);
434 /* Initialize subdev */
435 v4l2_i2c_subdev_init(&dw9768->sd, client, &dw9768_ops);
437 dw9768->aac_mode = DW9768_AAC_MODE_DEFAULT;
438 dw9768->aac_timing = DW9768_AAC_TIME_DEFAULT;
439 dw9768->clock_presc = DW9768_CLOCK_PRE_SCALE_DEFAULT;
441 /* Optional indication of AAC mode select */
442 fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,aac-mode",
445 /* Optional indication of clock pre-scale select */
446 fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,clock-presc",
447 &dw9768->clock_presc);
449 /* Optional indication of AAC Timing */
450 fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,aac-timing",
451 &dw9768->aac_timing);
453 dw9768->move_delay_us = dw9768_cal_move_delay(dw9768->aac_mode,
457 for (i = 0; i < ARRAY_SIZE(dw9768_supply_names); i++)
458 dw9768->supplies[i].supply = dw9768_supply_names[i];
460 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dw9768_supply_names),
463 dev_err(dev, "failed to get regulators\n");
467 /* Initialize controls */
468 ret = dw9768_init_controls(dw9768);
470 goto err_free_handler;
472 /* Initialize subdev */
473 dw9768->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
474 dw9768->sd.internal_ops = &dw9768_int_ops;
476 ret = media_entity_pads_init(&dw9768->sd.entity, 0, NULL);
478 goto err_free_handler;
480 dw9768->sd.entity.function = MEDIA_ENT_F_LENS;
482 pm_runtime_enable(dev);
483 if (!pm_runtime_enabled(dev)) {
484 ret = dw9768_runtime_resume(dev);
486 dev_err(dev, "failed to power on: %d\n", ret);
487 goto err_clean_entity;
491 ret = v4l2_async_register_subdev(&dw9768->sd);
493 dev_err(dev, "failed to register V4L2 subdev: %d", ret);
500 if (pm_runtime_enabled(dev))
501 pm_runtime_disable(dev);
503 dw9768_runtime_suspend(dev);
505 media_entity_cleanup(&dw9768->sd.entity);
507 v4l2_ctrl_handler_free(&dw9768->ctrls);
512 static int dw9768_remove(struct i2c_client *client)
514 struct v4l2_subdev *sd = i2c_get_clientdata(client);
515 struct dw9768 *dw9768 = sd_to_dw9768(sd);
517 v4l2_async_unregister_subdev(&dw9768->sd);
518 v4l2_ctrl_handler_free(&dw9768->ctrls);
519 media_entity_cleanup(&dw9768->sd.entity);
520 pm_runtime_disable(&client->dev);
521 if (!pm_runtime_status_suspended(&client->dev))
522 dw9768_runtime_suspend(&client->dev);
523 pm_runtime_set_suspended(&client->dev);
528 static const struct of_device_id dw9768_of_table[] = {
529 { .compatible = "dongwoon,dw9768" },
530 { .compatible = "giantec,gt9769" },
533 MODULE_DEVICE_TABLE(of, dw9768_of_table);
535 static const struct dev_pm_ops dw9768_pm_ops = {
536 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
537 pm_runtime_force_resume)
538 SET_RUNTIME_PM_OPS(dw9768_runtime_suspend, dw9768_runtime_resume, NULL)
541 static struct i2c_driver dw9768_i2c_driver = {
544 .pm = &dw9768_pm_ops,
545 .of_match_table = dw9768_of_table,
547 .probe_new = dw9768_probe,
548 .remove = dw9768_remove,
550 module_i2c_driver(dw9768_i2c_driver);
552 MODULE_AUTHOR("Dongchun Zhu <dongchun.zhu@mediatek.com>");
553 MODULE_DESCRIPTION("DW9768 VCM driver");
554 MODULE_LICENSE("GPL v2");