1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Texas Instruments DS90UB960-Q1 video deserializer
5 * Copyright (c) 2019 Luca Ceresoli <luca@lucaceresoli.net>
6 * Copyright (c) 2023 Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
12 * - PM for serializer and remote peripherals. We need to manage:
14 * - Power domain? Regulator? Somehow any remote device should be able to
15 * cause the VPOC to be turned on.
16 * - Link between the deserializer and the serializer
17 * - Related to VPOC management. We probably always want to turn on the VPOC
18 * and then enable the link.
19 * - Serializer's services: i2c, gpios, power
20 * - The serializer needs to resume before the remote peripherals can
22 * - How to handle gpios? Reserving a gpio essentially keeps the provider
23 * (serializer) always powered on.
24 * - Do we need a new bus for the FPD-Link? At the moment the serializers
25 * are children of the same i2c-adapter where the deserializer resides.
26 * - i2c-atr could be made embeddable instead of allocatable.
29 #include <linux/bitops.h>
30 #include <linux/clk.h>
31 #include <linux/delay.h>
32 #include <linux/fwnode.h>
33 #include <linux/gpio/consumer.h>
34 #include <linux/i2c-atr.h>
35 #include <linux/i2c.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/kernel.h>
39 #include <linux/kthread.h>
40 #include <linux/module.h>
41 #include <linux/mutex.h>
42 #include <linux/property.h>
43 #include <linux/regmap.h>
44 #include <linux/regulator/consumer.h>
45 #include <linux/slab.h>
46 #include <linux/workqueue.h>
48 #include <media/i2c/ds90ub9xx.h>
49 #include <media/mipi-csi2.h>
50 #include <media/v4l2-ctrls.h>
51 #include <media/v4l2-event.h>
52 #include <media/v4l2-fwnode.h>
53 #include <media/v4l2-subdev.h>
55 #define MHZ(v) ((u32)((v) * 1000000U))
57 #define UB960_POLL_TIME_MS 500
59 #define UB960_MAX_RX_NPORTS 4
60 #define UB960_MAX_TX_NPORTS 2
61 #define UB960_MAX_NPORTS (UB960_MAX_RX_NPORTS + UB960_MAX_TX_NPORTS)
63 #define UB960_MAX_PORT_ALIASES 8
65 #define UB960_NUM_BC_GPIOS 4
70 * 0x00-0x32 Shared (UB960_SR)
71 * 0x33-0x3a CSI-2 TX (per-port paged on DS90UB960, shared on 954) (UB960_TR)
72 * 0x4c Shared (UB960_SR)
73 * 0x4d-0x7f FPD-Link RX, per-port paged (UB960_RR)
74 * 0xb0-0xbf Shared (UB960_SR)
75 * 0xd0-0xdf FPD-Link RX, per-port paged (UB960_RR)
76 * 0xf0-0xf5 Shared (UB960_SR)
77 * 0xf8-0xfb Shared (UB960_SR)
81 * UB960_SR_* = Shared register
82 * UB960_RR_* = FPD-Link RX, per-port paged register
83 * UB960_TR_* = CSI-2 TX, per-port paged register
84 * UB960_XR_* = Reserved register
85 * UB960_IR_* = Indirect register
88 #define UB960_SR_I2C_DEV_ID 0x00
89 #define UB960_SR_RESET 0x01
90 #define UB960_SR_RESET_DIGITAL_RESET1 BIT(1)
91 #define UB960_SR_RESET_DIGITAL_RESET0 BIT(0)
92 #define UB960_SR_RESET_GPIO_LOCK_RELEASE BIT(5)
94 #define UB960_SR_GEN_CONFIG 0x02
95 #define UB960_SR_REV_MASK 0x03
96 #define UB960_SR_DEVICE_STS 0x04
97 #define UB960_SR_PAR_ERR_THOLD_HI 0x05
98 #define UB960_SR_PAR_ERR_THOLD_LO 0x06
99 #define UB960_SR_BCC_WDOG_CTL 0x07
100 #define UB960_SR_I2C_CTL1 0x08
101 #define UB960_SR_I2C_CTL2 0x09
102 #define UB960_SR_SCL_HIGH_TIME 0x0a
103 #define UB960_SR_SCL_LOW_TIME 0x0b
104 #define UB960_SR_RX_PORT_CTL 0x0c
105 #define UB960_SR_IO_CTL 0x0d
106 #define UB960_SR_GPIO_PIN_STS 0x0e
107 #define UB960_SR_GPIO_INPUT_CTL 0x0f
108 #define UB960_SR_GPIO_PIN_CTL(n) (0x10 + (n)) /* n < UB960_NUM_GPIOS */
109 #define UB960_SR_GPIO_PIN_CTL_GPIO_OUT_SEL 5
110 #define UB960_SR_GPIO_PIN_CTL_GPIO_OUT_SRC_SHIFT 2
111 #define UB960_SR_GPIO_PIN_CTL_GPIO_OUT_EN BIT(0)
113 #define UB960_SR_FS_CTL 0x18
114 #define UB960_SR_FS_HIGH_TIME_1 0x19
115 #define UB960_SR_FS_HIGH_TIME_0 0x1a
116 #define UB960_SR_FS_LOW_TIME_1 0x1b
117 #define UB960_SR_FS_LOW_TIME_0 0x1c
118 #define UB960_SR_MAX_FRM_HI 0x1d
119 #define UB960_SR_MAX_FRM_LO 0x1e
120 #define UB960_SR_CSI_PLL_CTL 0x1f
122 #define UB960_SR_FWD_CTL1 0x20
123 #define UB960_SR_FWD_CTL1_PORT_DIS(n) BIT((n) + 4)
125 #define UB960_SR_FWD_CTL2 0x21
126 #define UB960_SR_FWD_STS 0x22
128 #define UB960_SR_INTERRUPT_CTL 0x23
129 #define UB960_SR_INTERRUPT_CTL_INT_EN BIT(7)
130 #define UB960_SR_INTERRUPT_CTL_IE_CSI_TX0 BIT(4)
131 #define UB960_SR_INTERRUPT_CTL_IE_RX(n) BIT((n)) /* rxport[n] IRQ */
133 #define UB960_SR_INTERRUPT_STS 0x24
134 #define UB960_SR_INTERRUPT_STS_INT BIT(7)
135 #define UB960_SR_INTERRUPT_STS_IS_CSI_TX(n) BIT(4 + (n)) /* txport[n] IRQ */
136 #define UB960_SR_INTERRUPT_STS_IS_RX(n) BIT((n)) /* rxport[n] IRQ */
138 #define UB960_SR_TS_CONFIG 0x25
139 #define UB960_SR_TS_CONTROL 0x26
140 #define UB960_SR_TS_LINE_HI 0x27
141 #define UB960_SR_TS_LINE_LO 0x28
142 #define UB960_SR_TS_STATUS 0x29
143 #define UB960_SR_TIMESTAMP_P0_HI 0x2a
144 #define UB960_SR_TIMESTAMP_P0_LO 0x2b
145 #define UB960_SR_TIMESTAMP_P1_HI 0x2c
146 #define UB960_SR_TIMESTAMP_P1_LO 0x2d
148 #define UB960_SR_CSI_PORT_SEL 0x32
150 #define UB960_TR_CSI_CTL 0x33
151 #define UB960_TR_CSI_CTL_CSI_CAL_EN BIT(6)
152 #define UB960_TR_CSI_CTL_CSI_CONTS_CLOCK BIT(1)
153 #define UB960_TR_CSI_CTL_CSI_ENABLE BIT(0)
155 #define UB960_TR_CSI_CTL2 0x34
156 #define UB960_TR_CSI_STS 0x35
157 #define UB960_TR_CSI_TX_ICR 0x36
159 #define UB960_TR_CSI_TX_ISR 0x37
160 #define UB960_TR_CSI_TX_ISR_IS_CSI_SYNC_ERROR BIT(3)
161 #define UB960_TR_CSI_TX_ISR_IS_CSI_PASS_ERROR BIT(1)
163 #define UB960_TR_CSI_TEST_CTL 0x38
164 #define UB960_TR_CSI_TEST_PATT_HI 0x39
165 #define UB960_TR_CSI_TEST_PATT_LO 0x3a
167 #define UB960_XR_SFILTER_CFG 0x41
168 #define UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT 4
169 #define UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT 0
171 #define UB960_XR_AEQ_CTL1 0x42
172 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_FPD_CLK BIT(6)
173 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_ENCODING BIT(5)
174 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_PARITY BIT(4)
175 #define UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_MASK \
176 (UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_FPD_CLK | \
177 UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_ENCODING | \
178 UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_PARITY)
179 #define UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN BIT(0)
181 #define UB960_XR_AEQ_ERR_THOLD 0x43
183 #define UB960_RR_BCC_ERR_CTL 0x46
184 #define UB960_RR_BCC_STATUS 0x47
185 #define UB960_RR_BCC_STATUS_SEQ_ERROR BIT(5)
186 #define UB960_RR_BCC_STATUS_MASTER_ERR BIT(4)
187 #define UB960_RR_BCC_STATUS_MASTER_TO BIT(3)
188 #define UB960_RR_BCC_STATUS_SLAVE_ERR BIT(2)
189 #define UB960_RR_BCC_STATUS_SLAVE_TO BIT(1)
190 #define UB960_RR_BCC_STATUS_RESP_ERR BIT(0)
191 #define UB960_RR_BCC_STATUS_ERROR_MASK \
192 (UB960_RR_BCC_STATUS_SEQ_ERROR | UB960_RR_BCC_STATUS_MASTER_ERR | \
193 UB960_RR_BCC_STATUS_MASTER_TO | UB960_RR_BCC_STATUS_SLAVE_ERR | \
194 UB960_RR_BCC_STATUS_SLAVE_TO | UB960_RR_BCC_STATUS_RESP_ERR)
196 #define UB960_RR_FPD3_CAP 0x4a
197 #define UB960_RR_RAW_EMBED_DTYPE 0x4b
198 #define UB960_RR_RAW_EMBED_DTYPE_LINES_SHIFT 6
200 #define UB960_SR_FPD3_PORT_SEL 0x4c
202 #define UB960_RR_RX_PORT_STS1 0x4d
203 #define UB960_RR_RX_PORT_STS1_BCC_CRC_ERROR BIT(5)
204 #define UB960_RR_RX_PORT_STS1_LOCK_STS_CHG BIT(4)
205 #define UB960_RR_RX_PORT_STS1_BCC_SEQ_ERROR BIT(3)
206 #define UB960_RR_RX_PORT_STS1_PARITY_ERROR BIT(2)
207 #define UB960_RR_RX_PORT_STS1_PORT_PASS BIT(1)
208 #define UB960_RR_RX_PORT_STS1_LOCK_STS BIT(0)
209 #define UB960_RR_RX_PORT_STS1_ERROR_MASK \
210 (UB960_RR_RX_PORT_STS1_BCC_CRC_ERROR | \
211 UB960_RR_RX_PORT_STS1_BCC_SEQ_ERROR | \
212 UB960_RR_RX_PORT_STS1_PARITY_ERROR)
214 #define UB960_RR_RX_PORT_STS2 0x4e
215 #define UB960_RR_RX_PORT_STS2_LINE_LEN_UNSTABLE BIT(7)
216 #define UB960_RR_RX_PORT_STS2_LINE_LEN_CHG BIT(6)
217 #define UB960_RR_RX_PORT_STS2_FPD3_ENCODE_ERROR BIT(5)
218 #define UB960_RR_RX_PORT_STS2_BUFFER_ERROR BIT(4)
219 #define UB960_RR_RX_PORT_STS2_CSI_ERROR BIT(3)
220 #define UB960_RR_RX_PORT_STS2_FREQ_STABLE BIT(2)
221 #define UB960_RR_RX_PORT_STS2_CABLE_FAULT BIT(1)
222 #define UB960_RR_RX_PORT_STS2_LINE_CNT_CHG BIT(0)
223 #define UB960_RR_RX_PORT_STS2_ERROR_MASK \
224 UB960_RR_RX_PORT_STS2_BUFFER_ERROR
226 #define UB960_RR_RX_FREQ_HIGH 0x4f
227 #define UB960_RR_RX_FREQ_LOW 0x50
228 #define UB960_RR_SENSOR_STS_0 0x51
229 #define UB960_RR_SENSOR_STS_1 0x52
230 #define UB960_RR_SENSOR_STS_2 0x53
231 #define UB960_RR_SENSOR_STS_3 0x54
232 #define UB960_RR_RX_PAR_ERR_HI 0x55
233 #define UB960_RR_RX_PAR_ERR_LO 0x56
234 #define UB960_RR_BIST_ERR_COUNT 0x57
236 #define UB960_RR_BCC_CONFIG 0x58
237 #define UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH BIT(6)
238 #define UB960_RR_BCC_CONFIG_BC_FREQ_SEL_MASK GENMASK(2, 0)
240 #define UB960_RR_DATAPATH_CTL1 0x59
241 #define UB960_RR_DATAPATH_CTL2 0x5a
242 #define UB960_RR_SER_ID 0x5b
243 #define UB960_RR_SER_ALIAS_ID 0x5c
245 /* For these two register sets: n < UB960_MAX_PORT_ALIASES */
246 #define UB960_RR_SLAVE_ID(n) (0x5d + (n))
247 #define UB960_RR_SLAVE_ALIAS(n) (0x65 + (n))
249 #define UB960_RR_PORT_CONFIG 0x6d
250 #define UB960_RR_PORT_CONFIG_FPD3_MODE_MASK GENMASK(1, 0)
252 #define UB960_RR_BC_GPIO_CTL(n) (0x6e + (n)) /* n < 2 */
253 #define UB960_RR_RAW10_ID 0x70
254 #define UB960_RR_RAW10_ID_VC_SHIFT 6
255 #define UB960_RR_RAW10_ID_DT_SHIFT 0
257 #define UB960_RR_RAW12_ID 0x71
258 #define UB960_RR_CSI_VC_MAP 0x72
259 #define UB960_RR_CSI_VC_MAP_SHIFT(x) ((x) * 2)
261 #define UB960_RR_LINE_COUNT_HI 0x73
262 #define UB960_RR_LINE_COUNT_LO 0x74
263 #define UB960_RR_LINE_LEN_1 0x75
264 #define UB960_RR_LINE_LEN_0 0x76
265 #define UB960_RR_FREQ_DET_CTL 0x77
266 #define UB960_RR_MAILBOX_1 0x78
267 #define UB960_RR_MAILBOX_2 0x79
269 #define UB960_RR_CSI_RX_STS 0x7a
270 #define UB960_RR_CSI_RX_STS_LENGTH_ERR BIT(3)
271 #define UB960_RR_CSI_RX_STS_CKSUM_ERR BIT(2)
272 #define UB960_RR_CSI_RX_STS_ECC2_ERR BIT(1)
273 #define UB960_RR_CSI_RX_STS_ECC1_ERR BIT(0)
274 #define UB960_RR_CSI_RX_STS_ERROR_MASK \
275 (UB960_RR_CSI_RX_STS_LENGTH_ERR | UB960_RR_CSI_RX_STS_CKSUM_ERR | \
276 UB960_RR_CSI_RX_STS_ECC2_ERR | UB960_RR_CSI_RX_STS_ECC1_ERR)
278 #define UB960_RR_CSI_ERR_COUNTER 0x7b
279 #define UB960_RR_PORT_CONFIG2 0x7c
280 #define UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_MASK GENMASK(7, 6)
281 #define UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_SHIFT 6
283 #define UB960_RR_PORT_CONFIG2_LV_POL_LOW BIT(1)
284 #define UB960_RR_PORT_CONFIG2_FV_POL_LOW BIT(0)
286 #define UB960_RR_PORT_PASS_CTL 0x7d
287 #define UB960_RR_SEN_INT_RISE_CTL 0x7e
288 #define UB960_RR_SEN_INT_FALL_CTL 0x7f
290 #define UB960_SR_CSI_FRAME_COUNT_HI(n) (0x90 + 8 * (n))
291 #define UB960_SR_CSI_FRAME_COUNT_LO(n) (0x91 + 8 * (n))
292 #define UB960_SR_CSI_FRAME_ERR_COUNT_HI(n) (0x92 + 8 * (n))
293 #define UB960_SR_CSI_FRAME_ERR_COUNT_LO(n) (0x93 + 8 * (n))
294 #define UB960_SR_CSI_LINE_COUNT_HI(n) (0x94 + 8 * (n))
295 #define UB960_SR_CSI_LINE_COUNT_LO(n) (0x95 + 8 * (n))
296 #define UB960_SR_CSI_LINE_ERR_COUNT_HI(n) (0x96 + 8 * (n))
297 #define UB960_SR_CSI_LINE_ERR_COUNT_LO(n) (0x97 + 8 * (n))
299 #define UB960_XR_REFCLK_FREQ 0xa5 /* UB960 */
301 #define UB960_RR_VC_ID_MAP(x) (0xa0 + (x)) /* UB9702 */
303 #define UB960_SR_IND_ACC_CTL 0xb0
304 #define UB960_SR_IND_ACC_CTL_IA_AUTO_INC BIT(1)
306 #define UB960_SR_IND_ACC_ADDR 0xb1
307 #define UB960_SR_IND_ACC_DATA 0xb2
308 #define UB960_SR_BIST_CONTROL 0xb3
309 #define UB960_SR_MODE_IDX_STS 0xb8
310 #define UB960_SR_LINK_ERROR_COUNT 0xb9
311 #define UB960_SR_FPD3_ENC_CTL 0xba
312 #define UB960_SR_FV_MIN_TIME 0xbc
313 #define UB960_SR_GPIO_PD_CTL 0xbe
315 #define UB960_SR_FPD_RATE_CFG 0xc2 /* UB9702 */
316 #define UB960_SR_CSI_PLL_DIV 0xc9 /* UB9702 */
318 #define UB960_RR_PORT_DEBUG 0xd0
319 #define UB960_RR_AEQ_CTL2 0xd2
320 #define UB960_RR_AEQ_CTL2_SET_AEQ_FLOOR BIT(2)
322 #define UB960_RR_AEQ_STATUS 0xd3
323 #define UB960_RR_AEQ_STATUS_STATUS_2 GENMASK(5, 3)
324 #define UB960_RR_AEQ_STATUS_STATUS_1 GENMASK(2, 0)
326 #define UB960_RR_AEQ_BYPASS 0xd4
327 #define UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_SHIFT 5
328 #define UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_MASK GENMASK(7, 5)
329 #define UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_SHIFT 1
330 #define UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_MASK GENMASK(3, 1)
331 #define UB960_RR_AEQ_BYPASS_ENABLE BIT(0)
333 #define UB960_RR_AEQ_MIN_MAX 0xd5
334 #define UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT 4
335 #define UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT 0
337 #define UB960_RR_SFILTER_STS_0 0xd6
338 #define UB960_RR_SFILTER_STS_1 0xd7
339 #define UB960_RR_PORT_ICR_HI 0xd8
340 #define UB960_RR_PORT_ICR_LO 0xd9
341 #define UB960_RR_PORT_ISR_HI 0xda
342 #define UB960_RR_PORT_ISR_LO 0xdb
343 #define UB960_RR_FC_GPIO_STS 0xdc
344 #define UB960_RR_FC_GPIO_ICR 0xdd
345 #define UB960_RR_SEN_INT_RISE_STS 0xde
346 #define UB960_RR_SEN_INT_FALL_STS 0xdf
348 #define UB960_RR_CHANNEL_MODE 0xe4 /* UB9702 */
350 #define UB960_SR_FPD3_RX_ID(n) (0xf0 + (n))
351 #define UB960_SR_FPD3_RX_ID_LEN 6
353 #define UB960_SR_I2C_RX_ID(n) (0xf8 + (n)) /* < UB960_FPD_RX_NPORTS */
355 /* Indirect register blocks */
356 #define UB960_IND_TARGET_PAT_GEN 0x00
357 #define UB960_IND_TARGET_RX_ANA(n) (0x01 + (n))
358 #define UB960_IND_TARGET_CSI_CSIPLL_REG_1 0x92 /* UB9702 */
359 #define UB960_IND_TARGET_CSI_ANA 0x07
361 /* UB960_IR_PGEN_*: Indirect Registers for Test Pattern Generator */
363 #define UB960_IR_PGEN_CTL 0x01
364 #define UB960_IR_PGEN_CTL_PGEN_ENABLE BIT(0)
366 #define UB960_IR_PGEN_CFG 0x02
367 #define UB960_IR_PGEN_CSI_DI 0x03
368 #define UB960_IR_PGEN_LINE_SIZE1 0x04
369 #define UB960_IR_PGEN_LINE_SIZE0 0x05
370 #define UB960_IR_PGEN_BAR_SIZE1 0x06
371 #define UB960_IR_PGEN_BAR_SIZE0 0x07
372 #define UB960_IR_PGEN_ACT_LPF1 0x08
373 #define UB960_IR_PGEN_ACT_LPF0 0x09
374 #define UB960_IR_PGEN_TOT_LPF1 0x0a
375 #define UB960_IR_PGEN_TOT_LPF0 0x0b
376 #define UB960_IR_PGEN_LINE_PD1 0x0c
377 #define UB960_IR_PGEN_LINE_PD0 0x0d
378 #define UB960_IR_PGEN_VBP 0x0e
379 #define UB960_IR_PGEN_VFP 0x0f
380 #define UB960_IR_PGEN_COLOR(n) (0x10 + (n)) /* n < 15 */
382 #define UB960_IR_RX_ANA_STROBE_SET_CLK 0x08
383 #define UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY BIT(3)
384 #define UB960_IR_RX_ANA_STROBE_SET_CLK_DELAY_MASK GENMASK(2, 0)
386 #define UB960_IR_RX_ANA_STROBE_SET_DATA 0x09
387 #define UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY BIT(3)
388 #define UB960_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK GENMASK(2, 0)
392 #define UB960_MIN_AEQ_STROBE_POS -7
393 #define UB960_MAX_AEQ_STROBE_POS 7
395 #define UB960_MANUAL_STROBE_EXTRA_DELAY 6
397 #define UB960_MIN_MANUAL_STROBE_POS -(7 + UB960_MANUAL_STROBE_EXTRA_DELAY)
398 #define UB960_MAX_MANUAL_STROBE_POS (7 + UB960_MANUAL_STROBE_EXTRA_DELAY)
399 #define UB960_NUM_MANUAL_STROBE_POS (UB960_MAX_MANUAL_STROBE_POS - UB960_MIN_MANUAL_STROBE_POS + 1)
401 #define UB960_MIN_EQ_LEVEL 0
402 #define UB960_MAX_EQ_LEVEL 14
403 #define UB960_NUM_EQ_LEVELS (UB960_MAX_EQ_LEVEL - UB960_MIN_EQ_LEVEL + 1)
405 struct ub960_hw_data {
413 enum ub960_rxport_mode {
414 RXPORT_MODE_RAW10 = 0,
415 RXPORT_MODE_RAW12_HF = 1,
416 RXPORT_MODE_RAW12_LF = 2,
417 RXPORT_MODE_CSI2_SYNC = 3,
418 RXPORT_MODE_CSI2_NONSYNC = 4,
419 RXPORT_MODE_LAST = RXPORT_MODE_CSI2_NONSYNC,
422 enum ub960_rxport_cdr {
425 RXPORT_CDR_LAST = RXPORT_CDR_FPD4,
428 struct ub960_rxport {
429 struct ub960_data *priv;
430 u8 nport; /* RX port number, and index in priv->rxport[] */
433 struct v4l2_subdev *sd;
435 struct fwnode_handle *ep_fwnode;
440 struct fwnode_handle *fwnode;
441 struct i2c_client *client;
442 unsigned short alias; /* I2C alias (lower 7 bits) */
443 struct ds90ub9xx_platform_data pdata;
446 enum ub960_rxport_mode rx_mode;
447 enum ub960_rxport_cdr cdr_mode;
449 u8 lv_fv_pol; /* LV and FV polarities */
451 struct regulator *vpoc;
471 const struct i2c_client *aliased_clients[UB960_MAX_PORT_ALIASES];
475 struct v4l2_async_connection base;
476 struct ub960_rxport *rxport;
479 static inline struct ub960_asd *to_ub960_asd(struct v4l2_async_connection *asd)
481 return container_of(asd, struct ub960_asd, base);
484 struct ub960_txport {
485 struct ub960_data *priv;
486 u8 nport; /* TX port number, and index in priv->txport[] */
489 bool non_continous_clk;
493 const struct ub960_hw_data *hw_data;
494 struct i2c_client *client; /* for shared local registers */
495 struct regmap *regmap;
497 /* lock for register access */
498 struct mutex reg_lock;
502 struct regulator *vddio;
504 struct gpio_desc *pd_gpio;
505 struct delayed_work poll_work;
506 struct ub960_rxport *rxports[UB960_MAX_RX_NPORTS];
507 struct ub960_txport *txports[UB960_MAX_TX_NPORTS];
509 struct v4l2_subdev sd;
510 struct media_pad pads[UB960_MAX_NPORTS];
512 struct v4l2_ctrl_handler ctrl_handler;
513 struct v4l2_async_notifier notifier;
515 u32 tx_data_rate; /* Nominal data rate (Gb/s) */
530 u64 stream_enable_mask[UB960_MAX_NPORTS];
532 /* These are common to all ports */
541 static inline struct ub960_data *sd_to_ub960(struct v4l2_subdev *sd)
543 return container_of(sd, struct ub960_data, sd);
546 static inline bool ub960_pad_is_sink(struct ub960_data *priv, u32 pad)
548 return pad < priv->hw_data->num_rxports;
551 static inline bool ub960_pad_is_source(struct ub960_data *priv, u32 pad)
553 return pad >= priv->hw_data->num_rxports;
556 static inline unsigned int ub960_pad_to_port(struct ub960_data *priv, u32 pad)
558 if (ub960_pad_is_sink(priv, pad))
561 return pad - priv->hw_data->num_rxports;
564 struct ub960_format_info {
571 static const struct ub960_format_info ub960_formats[] = {
572 { .code = MEDIA_BUS_FMT_YUYV8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
573 { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
574 { .code = MEDIA_BUS_FMT_VYUY8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
575 { .code = MEDIA_BUS_FMT_YVYU8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
577 { .code = MEDIA_BUS_FMT_SBGGR12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
578 { .code = MEDIA_BUS_FMT_SGBRG12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
579 { .code = MEDIA_BUS_FMT_SGRBG12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
580 { .code = MEDIA_BUS_FMT_SRGGB12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
583 static const struct ub960_format_info *ub960_find_format(u32 code)
587 for (i = 0; i < ARRAY_SIZE(ub960_formats); i++) {
588 if (ub960_formats[i].code == code)
589 return &ub960_formats[i];
595 /* -----------------------------------------------------------------------------
596 * Basic device access
599 static int ub960_read(struct ub960_data *priv, u8 reg, u8 *val)
601 struct device *dev = &priv->client->dev;
605 mutex_lock(&priv->reg_lock);
607 ret = regmap_read(priv->regmap, reg, &v);
609 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
617 mutex_unlock(&priv->reg_lock);
622 static int ub960_write(struct ub960_data *priv, u8 reg, u8 val)
624 struct device *dev = &priv->client->dev;
627 mutex_lock(&priv->reg_lock);
629 ret = regmap_write(priv->regmap, reg, val);
631 dev_err(dev, "%s: cannot write register 0x%02x (%d)!\n",
634 mutex_unlock(&priv->reg_lock);
639 static int ub960_update_bits(struct ub960_data *priv, u8 reg, u8 mask, u8 val)
641 struct device *dev = &priv->client->dev;
644 mutex_lock(&priv->reg_lock);
646 ret = regmap_update_bits(priv->regmap, reg, mask, val);
648 dev_err(dev, "%s: cannot update register 0x%02x (%d)!\n",
651 mutex_unlock(&priv->reg_lock);
656 static int ub960_read16(struct ub960_data *priv, u8 reg, u16 *val)
658 struct device *dev = &priv->client->dev;
662 mutex_lock(&priv->reg_lock);
664 ret = regmap_bulk_read(priv->regmap, reg, &__v, sizeof(__v));
666 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
671 *val = be16_to_cpu(__v);
674 mutex_unlock(&priv->reg_lock);
679 static int ub960_rxport_select(struct ub960_data *priv, u8 nport)
681 struct device *dev = &priv->client->dev;
684 lockdep_assert_held(&priv->reg_lock);
686 if (priv->reg_current.rxport == nport)
689 ret = regmap_write(priv->regmap, UB960_SR_FPD3_PORT_SEL,
690 (nport << 4) | BIT(nport));
692 dev_err(dev, "%s: cannot select rxport %d (%d)!\n", __func__,
697 priv->reg_current.rxport = nport;
702 static int ub960_rxport_read(struct ub960_data *priv, u8 nport, u8 reg, u8 *val)
704 struct device *dev = &priv->client->dev;
708 mutex_lock(&priv->reg_lock);
710 ret = ub960_rxport_select(priv, nport);
714 ret = regmap_read(priv->regmap, reg, &v);
716 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
724 mutex_unlock(&priv->reg_lock);
729 static int ub960_rxport_write(struct ub960_data *priv, u8 nport, u8 reg, u8 val)
731 struct device *dev = &priv->client->dev;
734 mutex_lock(&priv->reg_lock);
736 ret = ub960_rxport_select(priv, nport);
740 ret = regmap_write(priv->regmap, reg, val);
742 dev_err(dev, "%s: cannot write register 0x%02x (%d)!\n",
746 mutex_unlock(&priv->reg_lock);
751 static int ub960_rxport_update_bits(struct ub960_data *priv, u8 nport, u8 reg,
754 struct device *dev = &priv->client->dev;
757 mutex_lock(&priv->reg_lock);
759 ret = ub960_rxport_select(priv, nport);
763 ret = regmap_update_bits(priv->regmap, reg, mask, val);
765 dev_err(dev, "%s: cannot update register 0x%02x (%d)!\n",
769 mutex_unlock(&priv->reg_lock);
774 static int ub960_rxport_read16(struct ub960_data *priv, u8 nport, u8 reg,
777 struct device *dev = &priv->client->dev;
781 mutex_lock(&priv->reg_lock);
783 ret = ub960_rxport_select(priv, nport);
787 ret = regmap_bulk_read(priv->regmap, reg, &__v, sizeof(__v));
789 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
794 *val = be16_to_cpu(__v);
797 mutex_unlock(&priv->reg_lock);
802 static int ub960_txport_select(struct ub960_data *priv, u8 nport)
804 struct device *dev = &priv->client->dev;
807 lockdep_assert_held(&priv->reg_lock);
809 if (priv->reg_current.txport == nport)
812 ret = regmap_write(priv->regmap, UB960_SR_CSI_PORT_SEL,
813 (nport << 4) | BIT(nport));
815 dev_err(dev, "%s: cannot select tx port %d (%d)!\n", __func__,
820 priv->reg_current.txport = nport;
825 static int ub960_txport_read(struct ub960_data *priv, u8 nport, u8 reg, u8 *val)
827 struct device *dev = &priv->client->dev;
831 mutex_lock(&priv->reg_lock);
833 ret = ub960_txport_select(priv, nport);
837 ret = regmap_read(priv->regmap, reg, &v);
839 dev_err(dev, "%s: cannot read register 0x%02x (%d)!\n",
847 mutex_unlock(&priv->reg_lock);
852 static int ub960_txport_write(struct ub960_data *priv, u8 nport, u8 reg, u8 val)
854 struct device *dev = &priv->client->dev;
857 mutex_lock(&priv->reg_lock);
859 ret = ub960_txport_select(priv, nport);
863 ret = regmap_write(priv->regmap, reg, val);
865 dev_err(dev, "%s: cannot write register 0x%02x (%d)!\n",
869 mutex_unlock(&priv->reg_lock);
874 static int ub960_txport_update_bits(struct ub960_data *priv, u8 nport, u8 reg,
877 struct device *dev = &priv->client->dev;
880 mutex_lock(&priv->reg_lock);
882 ret = ub960_txport_select(priv, nport);
886 ret = regmap_update_bits(priv->regmap, reg, mask, val);
888 dev_err(dev, "%s: cannot update register 0x%02x (%d)!\n",
892 mutex_unlock(&priv->reg_lock);
897 static int ub960_select_ind_reg_block(struct ub960_data *priv, u8 block)
899 struct device *dev = &priv->client->dev;
902 lockdep_assert_held(&priv->reg_lock);
904 if (priv->reg_current.indirect_target == block)
907 ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_CTL, block << 2);
909 dev_err(dev, "%s: cannot select indirect target %u (%d)!\n",
910 __func__, block, ret);
914 priv->reg_current.indirect_target = block;
919 static int ub960_read_ind(struct ub960_data *priv, u8 block, u8 reg, u8 *val)
921 struct device *dev = &priv->client->dev;
925 mutex_lock(&priv->reg_lock);
927 ret = ub960_select_ind_reg_block(priv, block);
931 ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_ADDR, reg);
934 "Write to IND_ACC_ADDR failed when reading %u:%x02x: %d\n",
939 ret = regmap_read(priv->regmap, UB960_SR_IND_ACC_DATA, &v);
942 "Write to IND_ACC_DATA failed when reading %u:%x02x: %d\n",
950 mutex_unlock(&priv->reg_lock);
955 static int ub960_write_ind(struct ub960_data *priv, u8 block, u8 reg, u8 val)
957 struct device *dev = &priv->client->dev;
960 mutex_lock(&priv->reg_lock);
962 ret = ub960_select_ind_reg_block(priv, block);
966 ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_ADDR, reg);
969 "Write to IND_ACC_ADDR failed when writing %u:%x02x: %d\n",
974 ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_DATA, val);
977 "Write to IND_ACC_DATA failed when writing %u:%x02x: %d\n",
983 mutex_unlock(&priv->reg_lock);
988 static int ub960_ind_update_bits(struct ub960_data *priv, u8 block, u8 reg,
991 struct device *dev = &priv->client->dev;
994 mutex_lock(&priv->reg_lock);
996 ret = ub960_select_ind_reg_block(priv, block);
1000 ret = regmap_write(priv->regmap, UB960_SR_IND_ACC_ADDR, reg);
1003 "Write to IND_ACC_ADDR failed when updating %u:%x02x: %d\n",
1008 ret = regmap_update_bits(priv->regmap, UB960_SR_IND_ACC_DATA, mask,
1012 "Write to IND_ACC_DATA failed when updating %u:%x02x: %d\n",
1018 mutex_unlock(&priv->reg_lock);
1023 /* -----------------------------------------------------------------------------
1024 * I2C-ATR (address translator)
1027 static int ub960_atr_attach_client(struct i2c_atr *atr, u32 chan_id,
1028 const struct i2c_client *client, u16 alias)
1030 struct ub960_data *priv = i2c_atr_get_driver_data(atr);
1031 struct ub960_rxport *rxport = priv->rxports[chan_id];
1032 struct device *dev = &priv->client->dev;
1033 unsigned int reg_idx;
1035 for (reg_idx = 0; reg_idx < ARRAY_SIZE(rxport->aliased_clients); reg_idx++) {
1036 if (!rxport->aliased_clients[reg_idx])
1040 if (reg_idx == ARRAY_SIZE(rxport->aliased_clients)) {
1041 dev_err(dev, "rx%u: alias pool exhausted\n", rxport->nport);
1042 return -EADDRNOTAVAIL;
1045 rxport->aliased_clients[reg_idx] = client;
1047 ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ID(reg_idx),
1049 ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ALIAS(reg_idx),
1052 dev_dbg(dev, "rx%u: client 0x%02x assigned alias 0x%02x at slot %u\n",
1053 rxport->nport, client->addr, alias, reg_idx);
1058 static void ub960_atr_detach_client(struct i2c_atr *atr, u32 chan_id,
1059 const struct i2c_client *client)
1061 struct ub960_data *priv = i2c_atr_get_driver_data(atr);
1062 struct ub960_rxport *rxport = priv->rxports[chan_id];
1063 struct device *dev = &priv->client->dev;
1064 unsigned int reg_idx;
1066 for (reg_idx = 0; reg_idx < ARRAY_SIZE(rxport->aliased_clients); reg_idx++) {
1067 if (rxport->aliased_clients[reg_idx] == client)
1071 if (reg_idx == ARRAY_SIZE(rxport->aliased_clients)) {
1072 dev_err(dev, "rx%u: client 0x%02x is not mapped!\n",
1073 rxport->nport, client->addr);
1077 rxport->aliased_clients[reg_idx] = NULL;
1079 ub960_rxport_write(priv, chan_id, UB960_RR_SLAVE_ALIAS(reg_idx), 0);
1081 dev_dbg(dev, "rx%u: client 0x%02x released at slot %u\n", rxport->nport,
1082 client->addr, reg_idx);
1085 static const struct i2c_atr_ops ub960_atr_ops = {
1086 .attach_client = ub960_atr_attach_client,
1087 .detach_client = ub960_atr_detach_client,
1090 static int ub960_init_atr(struct ub960_data *priv)
1092 struct device *dev = &priv->client->dev;
1093 struct i2c_adapter *parent_adap = priv->client->adapter;
1095 priv->atr = i2c_atr_new(parent_adap, dev, &ub960_atr_ops,
1096 priv->hw_data->num_rxports);
1097 if (IS_ERR(priv->atr))
1098 return PTR_ERR(priv->atr);
1100 i2c_atr_set_driver_data(priv->atr, priv);
1105 static void ub960_uninit_atr(struct ub960_data *priv)
1107 i2c_atr_delete(priv->atr);
1111 /* -----------------------------------------------------------------------------
1115 static int ub960_parse_dt_txport(struct ub960_data *priv,
1116 struct fwnode_handle *ep_fwnode,
1119 struct device *dev = &priv->client->dev;
1120 struct v4l2_fwnode_endpoint vep = {};
1121 struct ub960_txport *txport;
1124 txport = kzalloc(sizeof(*txport), GFP_KERNEL);
1128 txport->priv = priv;
1129 txport->nport = nport;
1131 vep.bus_type = V4L2_MBUS_CSI2_DPHY;
1132 ret = v4l2_fwnode_endpoint_alloc_parse(ep_fwnode, &vep);
1134 dev_err(dev, "tx%u: failed to parse endpoint data\n", nport);
1135 goto err_free_txport;
1138 txport->non_continous_clk = vep.bus.mipi_csi2.flags &
1139 V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK;
1141 txport->num_data_lanes = vep.bus.mipi_csi2.num_data_lanes;
1143 if (vep.nr_of_link_frequencies != 1) {
1148 priv->tx_link_freq[0] = vep.link_frequencies[0];
1149 priv->tx_data_rate = priv->tx_link_freq[0] * 2;
1151 if (priv->tx_data_rate != MHZ(1600) &&
1152 priv->tx_data_rate != MHZ(1200) &&
1153 priv->tx_data_rate != MHZ(800) &&
1154 priv->tx_data_rate != MHZ(400)) {
1155 dev_err(dev, "tx%u: invalid 'link-frequencies' value\n", nport);
1160 v4l2_fwnode_endpoint_free(&vep);
1162 priv->txports[nport] = txport;
1167 v4l2_fwnode_endpoint_free(&vep);
1174 static void ub960_csi_handle_events(struct ub960_data *priv, u8 nport)
1176 struct device *dev = &priv->client->dev;
1180 ret = ub960_txport_read(priv, nport, UB960_TR_CSI_TX_ISR, &csi_tx_isr);
1184 if (csi_tx_isr & UB960_TR_CSI_TX_ISR_IS_CSI_SYNC_ERROR)
1185 dev_warn(dev, "TX%u: CSI_SYNC_ERROR\n", nport);
1187 if (csi_tx_isr & UB960_TR_CSI_TX_ISR_IS_CSI_PASS_ERROR)
1188 dev_warn(dev, "TX%u: CSI_PASS_ERROR\n", nport);
1191 /* -----------------------------------------------------------------------------
1195 static int ub960_rxport_enable_vpocs(struct ub960_data *priv)
1200 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1201 struct ub960_rxport *rxport = priv->rxports[nport];
1203 if (!rxport || !rxport->vpoc)
1206 ret = regulator_enable(rxport->vpoc);
1208 goto err_disable_vpocs;
1215 struct ub960_rxport *rxport = priv->rxports[nport];
1217 if (!rxport || !rxport->vpoc)
1220 regulator_disable(rxport->vpoc);
1226 static void ub960_rxport_disable_vpocs(struct ub960_data *priv)
1230 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1231 struct ub960_rxport *rxport = priv->rxports[nport];
1233 if (!rxport || !rxport->vpoc)
1236 regulator_disable(rxport->vpoc);
1240 static void ub960_rxport_clear_errors(struct ub960_data *priv,
1245 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v);
1246 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v);
1247 ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &v);
1248 ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &v);
1250 ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_HI, &v);
1251 ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_LO, &v);
1253 ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, &v);
1256 static void ub960_clear_rx_errors(struct ub960_data *priv)
1260 for (nport = 0; nport < priv->hw_data->num_rxports; nport++)
1261 ub960_rxport_clear_errors(priv, nport);
1264 static int ub960_rxport_get_strobe_pos(struct ub960_data *priv,
1265 unsigned int nport, s8 *strobe_pos)
1268 u8 clk_delay, data_delay;
1271 ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1272 UB960_IR_RX_ANA_STROBE_SET_CLK, &v);
1274 clk_delay = (v & UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY) ?
1275 0 : UB960_MANUAL_STROBE_EXTRA_DELAY;
1277 ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1278 UB960_IR_RX_ANA_STROBE_SET_DATA, &v);
1280 data_delay = (v & UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY) ?
1281 0 : UB960_MANUAL_STROBE_EXTRA_DELAY;
1283 ret = ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_0, &v);
1287 clk_delay += v & UB960_IR_RX_ANA_STROBE_SET_CLK_DELAY_MASK;
1289 ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_1, &v);
1293 data_delay += v & UB960_IR_RX_ANA_STROBE_SET_DATA_DELAY_MASK;
1295 *strobe_pos = data_delay - clk_delay;
1300 static void ub960_rxport_set_strobe_pos(struct ub960_data *priv,
1301 unsigned int nport, s8 strobe_pos)
1303 u8 clk_delay, data_delay;
1305 clk_delay = UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY;
1306 data_delay = UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY;
1308 if (strobe_pos < UB960_MIN_AEQ_STROBE_POS)
1309 clk_delay = abs(strobe_pos) - UB960_MANUAL_STROBE_EXTRA_DELAY;
1310 else if (strobe_pos > UB960_MAX_AEQ_STROBE_POS)
1311 data_delay = strobe_pos - UB960_MANUAL_STROBE_EXTRA_DELAY;
1312 else if (strobe_pos < 0)
1313 clk_delay = abs(strobe_pos) | UB960_IR_RX_ANA_STROBE_SET_CLK_NO_EXTRA_DELAY;
1314 else if (strobe_pos > 0)
1315 data_delay = strobe_pos | UB960_IR_RX_ANA_STROBE_SET_DATA_NO_EXTRA_DELAY;
1317 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1318 UB960_IR_RX_ANA_STROBE_SET_CLK, clk_delay);
1320 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1321 UB960_IR_RX_ANA_STROBE_SET_DATA, data_delay);
1324 static void ub960_rxport_set_strobe_range(struct ub960_data *priv,
1325 s8 strobe_min, s8 strobe_max)
1327 /* Convert the signed strobe pos to positive zero based value */
1328 strobe_min -= UB960_MIN_AEQ_STROBE_POS;
1329 strobe_max -= UB960_MIN_AEQ_STROBE_POS;
1331 ub960_write(priv, UB960_XR_SFILTER_CFG,
1332 ((u8)strobe_min << UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT) |
1333 ((u8)strobe_max << UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT));
1336 static int ub960_rxport_get_eq_level(struct ub960_data *priv,
1337 unsigned int nport, u8 *eq_level)
1342 ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_STATUS, &v);
1346 *eq_level = (v & UB960_RR_AEQ_STATUS_STATUS_1) +
1347 (v & UB960_RR_AEQ_STATUS_STATUS_2);
1352 static void ub960_rxport_set_eq_level(struct ub960_data *priv,
1353 unsigned int nport, u8 eq_level)
1355 u8 eq_stage_1_select_value, eq_stage_2_select_value;
1356 const unsigned int eq_stage_max = 7;
1359 if (eq_level <= eq_stage_max) {
1360 eq_stage_1_select_value = eq_level;
1361 eq_stage_2_select_value = 0;
1363 eq_stage_1_select_value = eq_stage_max;
1364 eq_stage_2_select_value = eq_level - eq_stage_max;
1367 ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v);
1369 v &= ~(UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_MASK |
1370 UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_MASK);
1371 v |= eq_stage_1_select_value << UB960_RR_AEQ_BYPASS_EQ_STAGE1_VALUE_SHIFT;
1372 v |= eq_stage_2_select_value << UB960_RR_AEQ_BYPASS_EQ_STAGE2_VALUE_SHIFT;
1373 v |= UB960_RR_AEQ_BYPASS_ENABLE;
1375 ub960_rxport_write(priv, nport, UB960_RR_AEQ_BYPASS, v);
1378 static void ub960_rxport_set_eq_range(struct ub960_data *priv,
1379 unsigned int nport, u8 eq_min, u8 eq_max)
1381 ub960_rxport_write(priv, nport, UB960_RR_AEQ_MIN_MAX,
1382 (eq_min << UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT) |
1383 (eq_max << UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT));
1385 /* Enable AEQ min setting */
1386 ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_CTL2,
1387 UB960_RR_AEQ_CTL2_SET_AEQ_FLOOR,
1388 UB960_RR_AEQ_CTL2_SET_AEQ_FLOOR);
1391 static void ub960_rxport_config_eq(struct ub960_data *priv, unsigned int nport)
1393 struct ub960_rxport *rxport = priv->rxports[nport];
1395 /* We also set common settings here. Should be moved elsewhere. */
1397 if (priv->strobe.manual) {
1398 /* Disable AEQ_SFILTER_EN */
1399 ub960_update_bits(priv, UB960_XR_AEQ_CTL1,
1400 UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN, 0);
1402 /* Enable SFILTER and error control */
1403 ub960_write(priv, UB960_XR_AEQ_CTL1,
1404 UB960_XR_AEQ_CTL1_AEQ_ERR_CTL_MASK |
1405 UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN);
1407 /* Set AEQ strobe range */
1408 ub960_rxport_set_strobe_range(priv, priv->strobe.min,
1412 /* The rest are port specific */
1414 if (priv->strobe.manual)
1415 ub960_rxport_set_strobe_pos(priv, nport, rxport->eq.strobe_pos);
1417 ub960_rxport_set_strobe_pos(priv, nport, 0);
1419 if (rxport->eq.manual_eq) {
1420 ub960_rxport_set_eq_level(priv, nport,
1421 rxport->eq.manual.eq_level);
1423 /* Enable AEQ Bypass */
1424 ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_BYPASS,
1425 UB960_RR_AEQ_BYPASS_ENABLE,
1426 UB960_RR_AEQ_BYPASS_ENABLE);
1428 ub960_rxport_set_eq_range(priv, nport,
1429 rxport->eq.aeq.eq_level_min,
1430 rxport->eq.aeq.eq_level_max);
1432 /* Disable AEQ Bypass */
1433 ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_BYPASS,
1434 UB960_RR_AEQ_BYPASS_ENABLE, 0);
1438 static int ub960_rxport_link_ok(struct ub960_data *priv, unsigned int nport,
1441 u8 rx_port_sts1, rx_port_sts2;
1449 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1,
1454 if (!(rx_port_sts1 & UB960_RR_RX_PORT_STS1_LOCK_STS)) {
1459 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2,
1464 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &csi_rx_sts);
1468 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER,
1473 ret = ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &bcc_sts);
1477 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI,
1482 errors = (rx_port_sts1 & UB960_RR_RX_PORT_STS1_ERROR_MASK) ||
1483 (rx_port_sts2 & UB960_RR_RX_PORT_STS2_ERROR_MASK) ||
1484 (bcc_sts & UB960_RR_BCC_STATUS_ERROR_MASK) ||
1485 (csi_rx_sts & UB960_RR_CSI_RX_STS_ERROR_MASK) || csi_err_cnt ||
1494 * Wait for the RX ports to lock, have no errors and have stable strobe position
1497 static int ub960_rxport_wait_locks(struct ub960_data *priv,
1498 unsigned long port_mask,
1499 unsigned int *lock_mask)
1501 struct device *dev = &priv->client->dev;
1502 unsigned long timeout;
1503 unsigned int link_ok_mask;
1504 unsigned int missing;
1509 if (port_mask == 0) {
1515 if (port_mask >= BIT(priv->hw_data->num_rxports))
1518 timeout = jiffies + msecs_to_jiffies(1000);
1522 while (time_before(jiffies, timeout)) {
1525 for_each_set_bit(nport, &port_mask,
1526 priv->hw_data->num_rxports) {
1527 struct ub960_rxport *rxport = priv->rxports[nport];
1533 ret = ub960_rxport_link_ok(priv, nport, &ok);
1538 * We want the link to be ok for two consecutive loops,
1539 * as a link could get established just before our test
1540 * and drop soon after.
1542 if (!ok || !(link_ok_mask & BIT(nport)))
1546 link_ok_mask |= BIT(nport);
1548 link_ok_mask &= ~BIT(nport);
1560 *lock_mask = link_ok_mask;
1562 dev_dbg(dev, "Wait locks done in %u loops\n", loops);
1563 for_each_set_bit(nport, &port_mask, priv->hw_data->num_rxports) {
1564 struct ub960_rxport *rxport = priv->rxports[nport];
1565 s8 strobe_pos, eq_level;
1571 if (!(link_ok_mask & BIT(nport))) {
1572 dev_dbg(dev, "\trx%u: not locked\n", nport);
1576 ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH, &v);
1578 ret = ub960_rxport_get_strobe_pos(priv, nport, &strobe_pos);
1582 ret = ub960_rxport_get_eq_level(priv, nport, &eq_level);
1586 dev_dbg(dev, "\trx%u: locked, SP: %d, EQ: %u, freq %llu Hz\n",
1587 nport, strobe_pos, eq_level, (v * 1000000ULL) >> 8);
1593 static unsigned long ub960_calc_bc_clk_rate_ub960(struct ub960_data *priv,
1594 struct ub960_rxport *rxport)
1599 switch (rxport->rx_mode) {
1600 case RXPORT_MODE_RAW10:
1601 case RXPORT_MODE_RAW12_HF:
1602 case RXPORT_MODE_RAW12_LF:
1607 case RXPORT_MODE_CSI2_SYNC:
1612 case RXPORT_MODE_CSI2_NONSYNC:
1621 return clk_get_rate(priv->refclk) * mult / div;
1624 static unsigned long ub960_calc_bc_clk_rate_ub9702(struct ub960_data *priv,
1625 struct ub960_rxport *rxport)
1627 switch (rxport->rx_mode) {
1628 case RXPORT_MODE_RAW10:
1629 case RXPORT_MODE_RAW12_HF:
1630 case RXPORT_MODE_RAW12_LF:
1633 case RXPORT_MODE_CSI2_SYNC:
1636 case RXPORT_MODE_CSI2_NONSYNC:
1644 static int ub960_rxport_add_serializer(struct ub960_data *priv, u8 nport)
1646 struct ub960_rxport *rxport = priv->rxports[nport];
1647 struct device *dev = &priv->client->dev;
1648 struct ds90ub9xx_platform_data *ser_pdata = &rxport->ser.pdata;
1649 struct i2c_board_info ser_info = {
1650 .of_node = to_of_node(rxport->ser.fwnode),
1651 .fwnode = rxport->ser.fwnode,
1652 .platform_data = ser_pdata,
1655 ser_pdata->port = nport;
1656 ser_pdata->atr = priv->atr;
1657 if (priv->hw_data->is_ub9702)
1658 ser_pdata->bc_rate = ub960_calc_bc_clk_rate_ub9702(priv, rxport);
1660 ser_pdata->bc_rate = ub960_calc_bc_clk_rate_ub960(priv, rxport);
1663 * The serializer is added under the same i2c adapter as the
1664 * deserializer. This is not quite right, as the serializer is behind
1667 ser_info.addr = rxport->ser.alias;
1668 rxport->ser.client =
1669 i2c_new_client_device(priv->client->adapter, &ser_info);
1670 if (IS_ERR(rxport->ser.client)) {
1671 dev_err(dev, "rx%u: cannot add %s i2c device", nport,
1673 return PTR_ERR(rxport->ser.client);
1676 dev_dbg(dev, "rx%u: remote serializer at alias 0x%02x (%u-%04x)\n",
1677 nport, rxport->ser.client->addr,
1678 rxport->ser.client->adapter->nr, rxport->ser.client->addr);
1683 static void ub960_rxport_remove_serializer(struct ub960_data *priv, u8 nport)
1685 struct ub960_rxport *rxport = priv->rxports[nport];
1687 i2c_unregister_device(rxport->ser.client);
1688 rxport->ser.client = NULL;
1691 /* Add serializer i2c devices for all initialized ports */
1692 static int ub960_rxport_add_serializers(struct ub960_data *priv)
1697 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1698 struct ub960_rxport *rxport = priv->rxports[nport];
1703 ret = ub960_rxport_add_serializer(priv, nport);
1705 goto err_remove_sers;
1712 struct ub960_rxport *rxport = priv->rxports[nport];
1717 ub960_rxport_remove_serializer(priv, nport);
1723 static void ub960_rxport_remove_serializers(struct ub960_data *priv)
1727 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1728 struct ub960_rxport *rxport = priv->rxports[nport];
1733 ub960_rxport_remove_serializer(priv, nport);
1737 static void ub960_init_tx_port(struct ub960_data *priv,
1738 struct ub960_txport *txport)
1740 unsigned int nport = txport->nport;
1744 * From the datasheet: "initial CSI Skew-Calibration
1745 * sequence [...] should be set when operating at 1.6 Gbps"
1747 if (priv->tx_data_rate == MHZ(1600))
1748 csi_ctl |= UB960_TR_CSI_CTL_CSI_CAL_EN;
1750 csi_ctl |= (4 - txport->num_data_lanes) << 4;
1752 if (!txport->non_continous_clk)
1753 csi_ctl |= UB960_TR_CSI_CTL_CSI_CONTS_CLOCK;
1755 ub960_txport_write(priv, nport, UB960_TR_CSI_CTL, csi_ctl);
1758 static int ub960_init_tx_ports(struct ub960_data *priv)
1766 switch (priv->tx_data_rate) {
1786 ub960_write(priv, UB960_SR_CSI_PLL_CTL, speed_select);
1788 if (priv->hw_data->is_ub9702) {
1789 ub960_write(priv, UB960_SR_CSI_PLL_DIV, pll_div);
1791 switch (priv->tx_data_rate) {
1794 ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x92, 0x80);
1795 ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x4b, 0x2a);
1798 ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x92, 0x90);
1799 ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x4f, 0x2a);
1800 ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x4b, 0x2a);
1803 ub960_write_ind(priv, UB960_IND_TARGET_CSI_ANA, 0x92, 0xa0);
1808 for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
1809 struct ub960_txport *txport = priv->txports[nport];
1814 ub960_init_tx_port(priv, txport);
1820 static void ub960_init_rx_port_ub960(struct ub960_data *priv,
1821 struct ub960_rxport *rxport)
1823 unsigned int nport = rxport->nport;
1827 * Back channel frequency select.
1828 * Override FREQ_SELECT from the strap.
1829 * 0 - 2.5 Mbps (DS90UB913A-Q1 / DS90UB933-Q1)
1831 * 6 - 50 Mbps (DS90UB953-Q1)
1833 * Note that changing this setting will result in some errors on the back
1834 * channel for a short period of time.
1837 switch (rxport->rx_mode) {
1838 case RXPORT_MODE_RAW10:
1839 case RXPORT_MODE_RAW12_HF:
1840 case RXPORT_MODE_RAW12_LF:
1844 case RXPORT_MODE_CSI2_NONSYNC:
1848 case RXPORT_MODE_CSI2_SYNC:
1856 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
1857 UB960_RR_BCC_CONFIG_BC_FREQ_SEL_MASK,
1860 switch (rxport->rx_mode) {
1861 case RXPORT_MODE_RAW10:
1862 /* FPD3_MODE = RAW10 Mode (DS90UB913A-Q1 / DS90UB933-Q1 compatible) */
1863 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG,
1864 UB960_RR_PORT_CONFIG_FPD3_MODE_MASK,
1868 * RAW10_8BIT_CTL = 0b10 : 8-bit processing using upper 8 bits
1870 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2,
1871 UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_MASK,
1872 0x2 << UB960_RR_PORT_CONFIG2_RAW10_8BIT_CTL_SHIFT);
1876 case RXPORT_MODE_RAW12_HF:
1877 case RXPORT_MODE_RAW12_LF:
1878 /* Not implemented */
1881 case RXPORT_MODE_CSI2_SYNC:
1882 case RXPORT_MODE_CSI2_NONSYNC:
1883 /* CSI-2 Mode (DS90UB953-Q1 compatible) */
1884 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG, 0x3,
1890 /* LV_POLARITY & FV_POLARITY */
1891 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3,
1894 /* Enable all interrupt sources from this port */
1895 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_HI, 0x07);
1896 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_LO, 0x7f);
1898 /* Enable I2C_PASS_THROUGH */
1899 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
1900 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH,
1901 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH);
1903 /* Enable I2C communication to the serializer via the alias addr */
1904 ub960_rxport_write(priv, nport, UB960_RR_SER_ALIAS_ID,
1905 rxport->ser.alias << 1);
1907 /* Configure EQ related settings */
1908 ub960_rxport_config_eq(priv, nport);
1910 /* Enable RX port */
1911 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport));
1914 static void ub960_init_rx_port_ub9702_fpd3(struct ub960_data *priv,
1915 struct ub960_rxport *rxport)
1917 unsigned int nport = rxport->nport;
1921 switch (rxport->rx_mode) {
1922 case RXPORT_MODE_RAW10:
1927 case RXPORT_MODE_RAW12_HF:
1932 case RXPORT_MODE_RAW12_LF:
1937 case RXPORT_MODE_CSI2_SYNC:
1942 case RXPORT_MODE_CSI2_NONSYNC:
1951 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 0x7,
1953 ub960_rxport_write(priv, nport, UB960_RR_CHANNEL_MODE, fpd_func_mode);
1955 /* set serdes_eq_mode = 1 */
1956 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xa8, 0x80);
1958 /* enable serdes driver */
1959 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x0d, 0x7f);
1961 /* set serdes_eq_offset=4 */
1962 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x04);
1964 /* init default serdes_eq_max in 0xa9 */
1965 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xa9, 0x23);
1967 /* init serdes_eq_min in 0xaa */
1968 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xaa, 0);
1970 /* serdes_driver_ctl2 control: DS90UB953-Q1/DS90UB933-Q1/DS90UB913A-Q1 */
1971 ub960_ind_update_bits(priv, UB960_IND_TARGET_RX_ANA(nport), 0x1b,
1974 /* RX port to half-rate */
1975 ub960_update_bits(priv, UB960_SR_FPD_RATE_CFG, 0x3 << (nport * 2),
1979 static void ub960_init_rx_port_ub9702_fpd4_aeq(struct ub960_data *priv,
1980 struct ub960_rxport *rxport)
1982 unsigned int nport = rxport->nport;
1983 bool first_time_power_up = true;
1985 if (first_time_power_up) {
1989 ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2c, &v);
1991 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x27, v);
1992 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x28, v + 1);
1994 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x00);
1997 /* enable serdes_eq_ctl2 */
1998 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x9e, 0x00);
2000 /* enable serdes_eq_ctl1 */
2001 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x90, 0x40);
2003 /* enable serdes_eq_en */
2004 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2e, 0x40);
2006 /* disable serdes_eq_override */
2007 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xf0, 0x00);
2009 /* disable serdes_gain_override */
2010 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x71, 0x00);
2013 static void ub960_init_rx_port_ub9702_fpd4(struct ub960_data *priv,
2014 struct ub960_rxport *rxport)
2016 unsigned int nport = rxport->nport;
2019 switch (rxport->rx_mode) {
2020 case RXPORT_MODE_RAW10:
2024 case RXPORT_MODE_RAW12_HF:
2028 case RXPORT_MODE_RAW12_LF:
2032 case RXPORT_MODE_CSI2_SYNC:
2036 case RXPORT_MODE_CSI2_NONSYNC:
2044 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 0x7,
2047 /* FPD4 Sync Mode */
2048 ub960_rxport_write(priv, nport, UB960_RR_CHANNEL_MODE, 0);
2050 /* add serdes_eq_offset of 4 */
2051 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x04);
2053 /* FPD4 serdes_start_eq in 0x27: assign default */
2054 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x27, 0x0);
2055 /* FPD4 serdes_end_eq in 0x28: assign default */
2056 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x28, 0x23);
2058 /* set serdes_driver_mode into FPD IV mode */
2059 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x04, 0x00);
2060 /* set FPD PBC drv into FPD IV mode */
2061 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x1b, 0x00);
2063 /* set serdes_system_init to 0x2f */
2064 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x21, 0x2f);
2065 /* set serdes_system_rst in reset mode */
2066 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x25, 0xc1);
2068 /* RX port to 7.55G mode */
2069 ub960_update_bits(priv, UB960_SR_FPD_RATE_CFG, 0x3 << (nport * 2),
2072 ub960_init_rx_port_ub9702_fpd4_aeq(priv, rxport);
2075 static void ub960_init_rx_port_ub9702(struct ub960_data *priv,
2076 struct ub960_rxport *rxport)
2078 unsigned int nport = rxport->nport;
2080 if (rxport->cdr_mode == RXPORT_CDR_FPD3)
2081 ub960_init_rx_port_ub9702_fpd3(priv, rxport);
2082 else /* RXPORT_CDR_FPD4 */
2083 ub960_init_rx_port_ub9702_fpd4(priv, rxport);
2085 switch (rxport->rx_mode) {
2086 case RXPORT_MODE_RAW10:
2088 * RAW10_8BIT_CTL = 0b11 : 8-bit processing using lower 8 bits
2089 * 0b10 : 8-bit processing using upper 8 bits
2091 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2,
2092 0x3 << 6, 0x2 << 6);
2096 case RXPORT_MODE_RAW12_HF:
2097 case RXPORT_MODE_RAW12_LF:
2098 /* Not implemented */
2101 case RXPORT_MODE_CSI2_SYNC:
2102 case RXPORT_MODE_CSI2_NONSYNC:
2107 /* LV_POLARITY & FV_POLARITY */
2108 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3,
2111 /* Enable all interrupt sources from this port */
2112 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_HI, 0x07);
2113 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_LO, 0x7f);
2115 /* Enable I2C_PASS_THROUGH */
2116 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2117 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH,
2118 UB960_RR_BCC_CONFIG_I2C_PASS_THROUGH);
2120 /* Enable I2C communication to the serializer via the alias addr */
2121 ub960_rxport_write(priv, nport, UB960_RR_SER_ALIAS_ID,
2122 rxport->ser.alias << 1);
2124 /* Enable RX port */
2125 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport));
2127 if (rxport->cdr_mode == RXPORT_CDR_FPD4) {
2128 /* unreset 960 AEQ */
2129 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x25, 0x41);
2133 static int ub960_init_rx_ports(struct ub960_data *priv)
2137 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2138 struct ub960_rxport *rxport = priv->rxports[nport];
2143 if (priv->hw_data->is_ub9702)
2144 ub960_init_rx_port_ub9702(priv, rxport);
2146 ub960_init_rx_port_ub960(priv, rxport);
2152 static void ub960_rxport_handle_events(struct ub960_data *priv, u8 nport)
2154 struct device *dev = &priv->client->dev;
2161 /* Read interrupts (also clears most of them) */
2163 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1,
2166 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2,
2169 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS,
2172 ret = ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS,
2178 if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_PARITY_ERROR) {
2181 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI,
2184 dev_err(dev, "rx%u parity errors: %u\n", nport, v);
2187 if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_BCC_CRC_ERROR)
2188 dev_err(dev, "rx%u BCC CRC error\n", nport);
2190 if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_BCC_SEQ_ERROR)
2191 dev_err(dev, "rx%u BCC SEQ error\n", nport);
2193 if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_LINE_LEN_UNSTABLE)
2194 dev_err(dev, "rx%u line length unstable\n", nport);
2196 if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_FPD3_ENCODE_ERROR)
2197 dev_err(dev, "rx%u FPD3 encode error\n", nport);
2199 if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_BUFFER_ERROR)
2200 dev_err(dev, "rx%u buffer error\n", nport);
2203 dev_err(dev, "rx%u CSI error: %#02x\n", nport, csi_rx_sts);
2205 if (csi_rx_sts & UB960_RR_CSI_RX_STS_ECC1_ERR)
2206 dev_err(dev, "rx%u CSI ECC1 error\n", nport);
2208 if (csi_rx_sts & UB960_RR_CSI_RX_STS_ECC2_ERR)
2209 dev_err(dev, "rx%u CSI ECC2 error\n", nport);
2211 if (csi_rx_sts & UB960_RR_CSI_RX_STS_CKSUM_ERR)
2212 dev_err(dev, "rx%u CSI checksum error\n", nport);
2214 if (csi_rx_sts & UB960_RR_CSI_RX_STS_LENGTH_ERR)
2215 dev_err(dev, "rx%u CSI length error\n", nport);
2218 dev_err(dev, "rx%u BCC error: %#02x\n", nport, bcc_sts);
2220 if (bcc_sts & UB960_RR_BCC_STATUS_RESP_ERR)
2221 dev_err(dev, "rx%u BCC response error", nport);
2223 if (bcc_sts & UB960_RR_BCC_STATUS_SLAVE_TO)
2224 dev_err(dev, "rx%u BCC slave timeout", nport);
2226 if (bcc_sts & UB960_RR_BCC_STATUS_SLAVE_ERR)
2227 dev_err(dev, "rx%u BCC slave error", nport);
2229 if (bcc_sts & UB960_RR_BCC_STATUS_MASTER_TO)
2230 dev_err(dev, "rx%u BCC master timeout", nport);
2232 if (bcc_sts & UB960_RR_BCC_STATUS_MASTER_ERR)
2233 dev_err(dev, "rx%u BCC master error", nport);
2235 if (bcc_sts & UB960_RR_BCC_STATUS_SEQ_ERROR)
2236 dev_err(dev, "rx%u BCC sequence error", nport);
2238 if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_LINE_LEN_CHG) {
2241 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_LEN_1, &v);
2243 dev_dbg(dev, "rx%u line len changed: %u\n", nport, v);
2246 if (rx_port_sts2 & UB960_RR_RX_PORT_STS2_LINE_CNT_CHG) {
2249 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_COUNT_HI,
2252 dev_dbg(dev, "rx%u line count changed: %u\n", nport, v);
2255 if (rx_port_sts1 & UB960_RR_RX_PORT_STS1_LOCK_STS_CHG) {
2256 dev_dbg(dev, "rx%u: %s, %s, %s, %s\n", nport,
2257 (rx_port_sts1 & UB960_RR_RX_PORT_STS1_LOCK_STS) ?
2260 (rx_port_sts1 & UB960_RR_RX_PORT_STS1_PORT_PASS) ?
2263 (rx_port_sts2 & UB960_RR_RX_PORT_STS2_CABLE_FAULT) ?
2266 (rx_port_sts2 & UB960_RR_RX_PORT_STS2_FREQ_STABLE) ?
2272 /* -----------------------------------------------------------------------------
2277 * The current implementation only supports a simple VC mapping, where all VCs
2278 * from a one RX port will be mapped to the same VC. Also, the hardware
2279 * dictates that all streams from an RX port must go to a single TX port.
2281 * This function decides the target VC numbers for each RX port with a simple
2282 * algorithm, so that for each TX port, we get VC numbers starting from 0,
2285 * E.g. if all four RX ports are in use, of which the first two go to the
2286 * first TX port and the secont two go to the second TX port, we would get
2287 * the following VCs for the four RX ports: 0, 1, 0, 1.
2289 * TODO: implement a more sophisticated VC mapping. As the driver cannot know
2290 * what VCs the sinks expect (say, an FPGA with hardcoded VC routing), this
2291 * probably needs to be somehow configurable. Device tree?
2293 static void ub960_get_vc_maps(struct ub960_data *priv,
2294 struct v4l2_subdev_state *state, u8 *vc)
2296 u8 cur_vc[UB960_MAX_TX_NPORTS] = {};
2297 struct v4l2_subdev_route *route;
2298 u8 handled_mask = 0;
2300 for_each_active_route(&state->routing, route) {
2301 unsigned int rx, tx;
2303 rx = ub960_pad_to_port(priv, route->sink_pad);
2304 if (BIT(rx) & handled_mask)
2307 tx = ub960_pad_to_port(priv, route->source_pad);
2309 vc[rx] = cur_vc[tx]++;
2310 handled_mask |= BIT(rx);
2314 static int ub960_enable_tx_port(struct ub960_data *priv, unsigned int nport)
2316 struct device *dev = &priv->client->dev;
2318 dev_dbg(dev, "enable TX port %u\n", nport);
2320 return ub960_txport_update_bits(priv, nport, UB960_TR_CSI_CTL,
2321 UB960_TR_CSI_CTL_CSI_ENABLE,
2322 UB960_TR_CSI_CTL_CSI_ENABLE);
2325 static void ub960_disable_tx_port(struct ub960_data *priv, unsigned int nport)
2327 struct device *dev = &priv->client->dev;
2329 dev_dbg(dev, "disable TX port %u\n", nport);
2331 ub960_txport_update_bits(priv, nport, UB960_TR_CSI_CTL,
2332 UB960_TR_CSI_CTL_CSI_ENABLE, 0);
2335 static int ub960_enable_rx_port(struct ub960_data *priv, unsigned int nport)
2337 struct device *dev = &priv->client->dev;
2339 dev_dbg(dev, "enable RX port %u\n", nport);
2341 /* Enable forwarding */
2342 return ub960_update_bits(priv, UB960_SR_FWD_CTL1,
2343 UB960_SR_FWD_CTL1_PORT_DIS(nport), 0);
2346 static void ub960_disable_rx_port(struct ub960_data *priv, unsigned int nport)
2348 struct device *dev = &priv->client->dev;
2350 dev_dbg(dev, "disable RX port %u\n", nport);
2352 /* Disable forwarding */
2353 ub960_update_bits(priv, UB960_SR_FWD_CTL1,
2354 UB960_SR_FWD_CTL1_PORT_DIS(nport),
2355 UB960_SR_FWD_CTL1_PORT_DIS(nport));
2359 * The driver only supports using a single VC for each source. This function
2360 * checks that each source only provides streams using a single VC.
2362 static int ub960_validate_stream_vcs(struct ub960_data *priv)
2367 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2368 struct ub960_rxport *rxport = priv->rxports[nport];
2369 struct v4l2_mbus_frame_desc desc;
2376 ret = v4l2_subdev_call(rxport->source.sd, pad, get_frame_desc,
2377 rxport->source.pad, &desc);
2381 if (desc.type != V4L2_MBUS_FRAME_DESC_TYPE_CSI2)
2384 if (desc.num_entries == 0)
2387 vc = desc.entry[0].bus.csi2.vc;
2389 for (i = 1; i < desc.num_entries; i++) {
2390 if (vc == desc.entry[i].bus.csi2.vc)
2393 dev_err(&priv->client->dev,
2394 "rx%u: source with multiple virtual-channels is not supported\n",
2403 static int ub960_configure_ports_for_streaming(struct ub960_data *priv,
2404 struct v4l2_subdev_state *state)
2413 } rx_data[UB960_MAX_RX_NPORTS] = {};
2414 u8 vc_map[UB960_MAX_RX_NPORTS] = {};
2415 struct v4l2_subdev_route *route;
2419 ret = ub960_validate_stream_vcs(priv);
2423 ub960_get_vc_maps(priv, state, vc_map);
2425 for_each_active_route(&state->routing, route) {
2426 struct ub960_rxport *rxport;
2427 struct ub960_txport *txport;
2428 struct v4l2_mbus_framefmt *fmt;
2429 const struct ub960_format_info *ub960_fmt;
2432 nport = ub960_pad_to_port(priv, route->sink_pad);
2434 rxport = priv->rxports[nport];
2438 txport = priv->txports[ub960_pad_to_port(priv, route->source_pad)];
2442 rx_data[nport].tx_port = ub960_pad_to_port(priv, route->source_pad);
2444 rx_data[nport].num_streams++;
2446 /* For the rest, we are only interested in parallel busses */
2447 if (rxport->rx_mode == RXPORT_MODE_CSI2_SYNC ||
2448 rxport->rx_mode == RXPORT_MODE_CSI2_NONSYNC)
2451 if (rx_data[nport].num_streams > 2)
2454 fmt = v4l2_subdev_state_get_stream_format(state,
2456 route->sink_stream);
2460 ub960_fmt = ub960_find_format(fmt->code);
2464 if (ub960_fmt->meta) {
2465 if (fmt->height > 3) {
2466 dev_err(&priv->client->dev,
2467 "rx%u: unsupported metadata height %u\n",
2468 nport, fmt->height);
2472 rx_data[nport].meta_dt = ub960_fmt->datatype;
2473 rx_data[nport].meta_lines = fmt->height;
2475 rx_data[nport].pixel_dt = ub960_fmt->datatype;
2479 /* Configure RX ports */
2482 * Keep all port forwardings disabled by default. Forwarding will be
2483 * enabled in ub960_enable_rx_port.
2485 fwd_ctl = GENMASK(7, 4);
2487 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2488 struct ub960_rxport *rxport = priv->rxports[nport];
2489 u8 vc = vc_map[nport];
2491 if (rx_data[nport].num_streams == 0)
2494 switch (rxport->rx_mode) {
2495 case RXPORT_MODE_RAW10:
2496 ub960_rxport_write(priv, nport, UB960_RR_RAW10_ID,
2497 rx_data[nport].pixel_dt | (vc << UB960_RR_RAW10_ID_VC_SHIFT));
2499 ub960_rxport_write(priv, rxport->nport,
2500 UB960_RR_RAW_EMBED_DTYPE,
2501 (rx_data[nport].meta_lines << UB960_RR_RAW_EMBED_DTYPE_LINES_SHIFT) |
2502 rx_data[nport].meta_dt);
2506 case RXPORT_MODE_RAW12_HF:
2507 case RXPORT_MODE_RAW12_LF:
2508 /* Not implemented */
2511 case RXPORT_MODE_CSI2_SYNC:
2512 case RXPORT_MODE_CSI2_NONSYNC:
2513 if (!priv->hw_data->is_ub9702) {
2514 /* Map all VCs from this port to the same VC */
2515 ub960_rxport_write(priv, nport, UB960_RR_CSI_VC_MAP,
2516 (vc << UB960_RR_CSI_VC_MAP_SHIFT(3)) |
2517 (vc << UB960_RR_CSI_VC_MAP_SHIFT(2)) |
2518 (vc << UB960_RR_CSI_VC_MAP_SHIFT(1)) |
2519 (vc << UB960_RR_CSI_VC_MAP_SHIFT(0)));
2523 /* Map all VCs from this port to VC(nport) */
2524 for (i = 0; i < 8; i++)
2525 ub960_rxport_write(priv, nport,
2526 UB960_RR_VC_ID_MAP(i),
2533 if (rx_data[nport].tx_port == 1)
2534 fwd_ctl |= BIT(nport); /* forward to TX1 */
2536 fwd_ctl &= ~BIT(nport); /* forward to TX0 */
2539 ub960_write(priv, UB960_SR_FWD_CTL1, fwd_ctl);
2544 static void ub960_update_streaming_status(struct ub960_data *priv)
2548 for (i = 0; i < UB960_MAX_NPORTS; i++) {
2549 if (priv->stream_enable_mask[i])
2553 priv->streaming = i < UB960_MAX_NPORTS;
2556 static int ub960_enable_streams(struct v4l2_subdev *sd,
2557 struct v4l2_subdev_state *state, u32 source_pad,
2558 u64 source_streams_mask)
2560 struct ub960_data *priv = sd_to_ub960(sd);
2561 struct device *dev = &priv->client->dev;
2562 u64 sink_streams[UB960_MAX_RX_NPORTS] = {};
2563 struct v4l2_subdev_route *route;
2564 unsigned int failed_port;
2568 if (!priv->streaming) {
2569 dev_dbg(dev, "Prepare for streaming\n");
2570 ret = ub960_configure_ports_for_streaming(priv, state);
2575 /* Enable TX port if not yet enabled */
2576 if (!priv->stream_enable_mask[source_pad]) {
2577 ret = ub960_enable_tx_port(priv,
2578 ub960_pad_to_port(priv, source_pad));
2583 priv->stream_enable_mask[source_pad] |= source_streams_mask;
2585 /* Collect sink streams per pad which we need to enable */
2586 for_each_active_route(&state->routing, route) {
2587 if (route->source_pad != source_pad)
2590 if (!(source_streams_mask & BIT_ULL(route->source_stream)))
2593 nport = ub960_pad_to_port(priv, route->sink_pad);
2595 sink_streams[nport] |= BIT_ULL(route->sink_stream);
2598 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2599 if (!sink_streams[nport])
2602 /* Enable the RX port if not yet enabled */
2603 if (!priv->stream_enable_mask[nport]) {
2604 ret = ub960_enable_rx_port(priv, nport);
2606 failed_port = nport;
2611 priv->stream_enable_mask[nport] |= sink_streams[nport];
2613 dev_dbg(dev, "enable RX port %u streams %#llx\n", nport,
2614 sink_streams[nport]);
2616 ret = v4l2_subdev_enable_streams(
2617 priv->rxports[nport]->source.sd,
2618 priv->rxports[nport]->source.pad,
2619 sink_streams[nport]);
2621 priv->stream_enable_mask[nport] &= ~sink_streams[nport];
2623 if (!priv->stream_enable_mask[nport])
2624 ub960_disable_rx_port(priv, nport);
2626 failed_port = nport;
2631 priv->streaming = true;
2636 for (nport = 0; nport < failed_port; nport++) {
2637 if (!sink_streams[nport])
2640 dev_dbg(dev, "disable RX port %u streams %#llx\n", nport,
2641 sink_streams[nport]);
2643 ret = v4l2_subdev_disable_streams(
2644 priv->rxports[nport]->source.sd,
2645 priv->rxports[nport]->source.pad,
2646 sink_streams[nport]);
2648 dev_err(dev, "Failed to disable streams: %d\n", ret);
2650 priv->stream_enable_mask[nport] &= ~sink_streams[nport];
2652 /* Disable RX port if no active streams */
2653 if (!priv->stream_enable_mask[nport])
2654 ub960_disable_rx_port(priv, nport);
2657 priv->stream_enable_mask[source_pad] &= ~source_streams_mask;
2659 if (!priv->stream_enable_mask[source_pad])
2660 ub960_disable_tx_port(priv,
2661 ub960_pad_to_port(priv, source_pad));
2663 ub960_update_streaming_status(priv);
2668 static int ub960_disable_streams(struct v4l2_subdev *sd,
2669 struct v4l2_subdev_state *state,
2670 u32 source_pad, u64 source_streams_mask)
2672 struct ub960_data *priv = sd_to_ub960(sd);
2673 struct device *dev = &priv->client->dev;
2674 u64 sink_streams[UB960_MAX_RX_NPORTS] = {};
2675 struct v4l2_subdev_route *route;
2679 /* Collect sink streams per pad which we need to disable */
2680 for_each_active_route(&state->routing, route) {
2681 if (route->source_pad != source_pad)
2684 if (!(source_streams_mask & BIT_ULL(route->source_stream)))
2687 nport = ub960_pad_to_port(priv, route->sink_pad);
2689 sink_streams[nport] |= BIT_ULL(route->sink_stream);
2692 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2693 if (!sink_streams[nport])
2696 dev_dbg(dev, "disable RX port %u streams %#llx\n", nport,
2697 sink_streams[nport]);
2699 ret = v4l2_subdev_disable_streams(
2700 priv->rxports[nport]->source.sd,
2701 priv->rxports[nport]->source.pad,
2702 sink_streams[nport]);
2704 dev_err(dev, "Failed to disable streams: %d\n", ret);
2706 priv->stream_enable_mask[nport] &= ~sink_streams[nport];
2708 /* Disable RX port if no active streams */
2709 if (!priv->stream_enable_mask[nport])
2710 ub960_disable_rx_port(priv, nport);
2713 /* Disable TX port if no active streams */
2715 priv->stream_enable_mask[source_pad] &= ~source_streams_mask;
2717 if (!priv->stream_enable_mask[source_pad])
2718 ub960_disable_tx_port(priv,
2719 ub960_pad_to_port(priv, source_pad));
2721 ub960_update_streaming_status(priv);
2726 static int _ub960_set_routing(struct v4l2_subdev *sd,
2727 struct v4l2_subdev_state *state,
2728 struct v4l2_subdev_krouting *routing)
2730 static const struct v4l2_mbus_framefmt format = {
2733 .code = MEDIA_BUS_FMT_UYVY8_1X16,
2734 .field = V4L2_FIELD_NONE,
2735 .colorspace = V4L2_COLORSPACE_SRGB,
2736 .ycbcr_enc = V4L2_YCBCR_ENC_601,
2737 .quantization = V4L2_QUANTIZATION_LIM_RANGE,
2738 .xfer_func = V4L2_XFER_FUNC_SRGB,
2743 * Note: we can only support up to V4L2_FRAME_DESC_ENTRY_MAX, until
2744 * frame desc is made dynamically allocated.
2747 if (routing->num_routes > V4L2_FRAME_DESC_ENTRY_MAX)
2750 ret = v4l2_subdev_routing_validate(sd, routing,
2751 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1 |
2752 V4L2_SUBDEV_ROUTING_NO_SINK_STREAM_MIX);
2756 ret = v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format);
2763 static int ub960_set_routing(struct v4l2_subdev *sd,
2764 struct v4l2_subdev_state *state,
2765 enum v4l2_subdev_format_whence which,
2766 struct v4l2_subdev_krouting *routing)
2768 struct ub960_data *priv = sd_to_ub960(sd);
2770 if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->streaming)
2773 return _ub960_set_routing(sd, state, routing);
2776 static int ub960_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
2777 struct v4l2_mbus_frame_desc *fd)
2779 struct ub960_data *priv = sd_to_ub960(sd);
2780 struct v4l2_subdev_route *route;
2781 struct v4l2_subdev_state *state;
2783 struct device *dev = &priv->client->dev;
2784 u8 vc_map[UB960_MAX_RX_NPORTS] = {};
2786 if (!ub960_pad_is_source(priv, pad))
2789 fd->type = V4L2_MBUS_FRAME_DESC_TYPE_CSI2;
2791 state = v4l2_subdev_lock_and_get_active_state(&priv->sd);
2793 ub960_get_vc_maps(priv, state, vc_map);
2795 for_each_active_route(&state->routing, route) {
2796 struct v4l2_mbus_frame_desc_entry *source_entry = NULL;
2797 struct v4l2_mbus_frame_desc source_fd;
2801 if (route->source_pad != pad)
2804 nport = ub960_pad_to_port(priv, route->sink_pad);
2806 ret = v4l2_subdev_call(priv->rxports[nport]->source.sd, pad,
2808 priv->rxports[nport]->source.pad,
2812 "Failed to get source frame desc for pad %u\n",
2817 for (i = 0; i < source_fd.num_entries; i++) {
2818 if (source_fd.entry[i].stream == route->sink_stream) {
2819 source_entry = &source_fd.entry[i];
2824 if (!source_entry) {
2826 "Failed to find stream from source frame desc\n");
2831 fd->entry[fd->num_entries].stream = route->source_stream;
2832 fd->entry[fd->num_entries].flags = source_entry->flags;
2833 fd->entry[fd->num_entries].length = source_entry->length;
2834 fd->entry[fd->num_entries].pixelcode = source_entry->pixelcode;
2836 fd->entry[fd->num_entries].bus.csi2.vc = vc_map[nport];
2838 if (source_fd.type == V4L2_MBUS_FRAME_DESC_TYPE_CSI2) {
2839 fd->entry[fd->num_entries].bus.csi2.dt =
2840 source_entry->bus.csi2.dt;
2842 const struct ub960_format_info *ub960_fmt;
2843 struct v4l2_mbus_framefmt *fmt;
2845 fmt = v4l2_subdev_state_get_stream_format(state, pad,
2846 route->source_stream);
2853 ub960_fmt = ub960_find_format(fmt->code);
2855 dev_err(dev, "Unable to find format\n");
2860 fd->entry[fd->num_entries].bus.csi2.dt =
2861 ub960_fmt->datatype;
2868 v4l2_subdev_unlock_state(state);
2873 static int ub960_set_fmt(struct v4l2_subdev *sd,
2874 struct v4l2_subdev_state *state,
2875 struct v4l2_subdev_format *format)
2877 struct ub960_data *priv = sd_to_ub960(sd);
2878 struct v4l2_mbus_framefmt *fmt;
2880 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->streaming)
2883 /* No transcoding, source and sink formats must match. */
2884 if (ub960_pad_is_source(priv, format->pad))
2885 return v4l2_subdev_get_fmt(sd, state, format);
2888 * Default to the first format if the requested media bus code isn't
2891 if (!ub960_find_format(format->format.code))
2892 format->format.code = ub960_formats[0].code;
2894 fmt = v4l2_subdev_state_get_stream_format(state, format->pad,
2899 *fmt = format->format;
2901 fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad,
2906 *fmt = format->format;
2911 static int ub960_init_cfg(struct v4l2_subdev *sd,
2912 struct v4l2_subdev_state *state)
2914 struct ub960_data *priv = sd_to_ub960(sd);
2916 struct v4l2_subdev_route routes[] = {
2920 .source_pad = priv->hw_data->num_rxports,
2922 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
2926 struct v4l2_subdev_krouting routing = {
2927 .num_routes = ARRAY_SIZE(routes),
2931 return _ub960_set_routing(sd, state, &routing);
2934 static const struct v4l2_subdev_pad_ops ub960_pad_ops = {
2935 .enable_streams = ub960_enable_streams,
2936 .disable_streams = ub960_disable_streams,
2938 .set_routing = ub960_set_routing,
2939 .get_frame_desc = ub960_get_frame_desc,
2941 .get_fmt = v4l2_subdev_get_fmt,
2942 .set_fmt = ub960_set_fmt,
2944 .init_cfg = ub960_init_cfg,
2947 static int ub960_log_status(struct v4l2_subdev *sd)
2949 struct ub960_data *priv = sd_to_ub960(sd);
2950 struct device *dev = &priv->client->dev;
2951 struct v4l2_subdev_state *state;
2956 u8 id[UB960_SR_FPD3_RX_ID_LEN];
2958 state = v4l2_subdev_lock_and_get_active_state(sd);
2960 for (i = 0; i < sizeof(id); i++)
2961 ub960_read(priv, UB960_SR_FPD3_RX_ID(i), &id[i]);
2963 dev_info(dev, "ID '%.*s'\n", (int)sizeof(id), id);
2965 for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
2966 struct ub960_txport *txport = priv->txports[nport];
2968 dev_info(dev, "TX %u\n", nport);
2971 dev_info(dev, "\tNot initialized\n");
2975 ub960_txport_read(priv, nport, UB960_TR_CSI_STS, &v);
2976 dev_info(dev, "\tsync %u, pass %u\n", v & (u8)BIT(1),
2979 ub960_read16(priv, UB960_SR_CSI_FRAME_COUNT_HI(nport), &v16);
2980 dev_info(dev, "\tframe counter %u\n", v16);
2982 ub960_read16(priv, UB960_SR_CSI_FRAME_ERR_COUNT_HI(nport), &v16);
2983 dev_info(dev, "\tframe error counter %u\n", v16);
2985 ub960_read16(priv, UB960_SR_CSI_LINE_COUNT_HI(nport), &v16);
2986 dev_info(dev, "\tline counter %u\n", v16);
2988 ub960_read16(priv, UB960_SR_CSI_LINE_ERR_COUNT_HI(nport), &v16);
2989 dev_info(dev, "\tline error counter %u\n", v16);
2992 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2993 struct ub960_rxport *rxport = priv->rxports[nport];
2998 dev_info(dev, "RX %u\n", nport);
3001 dev_info(dev, "\tNot initialized\n");
3005 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v);
3007 if (v & UB960_RR_RX_PORT_STS1_LOCK_STS)
3008 dev_info(dev, "\tLocked\n");
3010 dev_info(dev, "\tNot locked\n");
3012 dev_info(dev, "\trx_port_sts1 %#02x\n", v);
3013 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v);
3014 dev_info(dev, "\trx_port_sts2 %#02x\n", v);
3016 ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH, &v16);
3017 dev_info(dev, "\tlink freq %llu Hz\n", (v16 * 1000000ULL) >> 8);
3019 ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI, &v16);
3020 dev_info(dev, "\tparity errors %u\n", v16);
3022 ub960_rxport_read16(priv, nport, UB960_RR_LINE_COUNT_HI, &v16);
3023 dev_info(dev, "\tlines per frame %u\n", v16);
3025 ub960_rxport_read16(priv, nport, UB960_RR_LINE_LEN_1, &v16);
3026 dev_info(dev, "\tbytes per line %u\n", v16);
3028 ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, &v);
3029 dev_info(dev, "\tcsi_err_counter %u\n", v);
3033 ub960_read(priv, UB960_XR_AEQ_CTL1, &v);
3035 dev_info(dev, "\t%s strobe\n",
3036 (v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) ? "Adaptive" :
3039 if (v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) {
3040 ub960_read(priv, UB960_XR_SFILTER_CFG, &v);
3042 dev_info(dev, "\tStrobe range [%d, %d]\n",
3043 ((v >> UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT) & 0xf) - 7,
3044 ((v >> UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT) & 0xf) - 7);
3047 ub960_rxport_get_strobe_pos(priv, nport, &strobe_pos);
3049 dev_info(dev, "\tStrobe pos %d\n", strobe_pos);
3053 ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v);
3055 dev_info(dev, "\t%s EQ\n",
3056 (v & UB960_RR_AEQ_BYPASS_ENABLE) ? "Manual" :
3059 if (!(v & UB960_RR_AEQ_BYPASS_ENABLE)) {
3060 ub960_rxport_read(priv, nport, UB960_RR_AEQ_MIN_MAX, &v);
3062 dev_info(dev, "\tEQ range [%u, %u]\n",
3063 (v >> UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT) & 0xf,
3064 (v >> UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT) & 0xf);
3067 if (ub960_rxport_get_eq_level(priv, nport, &eq_level) == 0)
3068 dev_info(dev, "\tEQ level %u\n", eq_level);
3071 for (i = 0; i < UB960_NUM_BC_GPIOS; i++) {
3075 ctl_reg = UB960_RR_BC_GPIO_CTL(i / 2);
3076 ctl_shift = (i % 2) * 4;
3078 ub960_rxport_read(priv, nport, ctl_reg, &v);
3080 dev_info(dev, "\tGPIO%u: mode %u\n", i,
3081 (v >> ctl_shift) & 0xf);
3085 v4l2_subdev_unlock_state(state);
3090 static const struct v4l2_subdev_core_ops ub960_subdev_core_ops = {
3091 .log_status = ub960_log_status,
3092 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
3093 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
3096 static const struct v4l2_subdev_ops ub960_subdev_ops = {
3097 .core = &ub960_subdev_core_ops,
3098 .pad = &ub960_pad_ops,
3101 static const struct media_entity_operations ub960_entity_ops = {
3102 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
3103 .link_validate = v4l2_subdev_link_validate,
3104 .has_pad_interdep = v4l2_subdev_has_pad_interdep,
3107 /* -----------------------------------------------------------------------------
3111 static irqreturn_t ub960_handle_events(int irq, void *arg)
3113 struct ub960_data *priv = arg;
3119 ret = ub960_read(priv, UB960_SR_INTERRUPT_STS, &int_sts);
3120 if (ret || !int_sts)
3123 dev_dbg(&priv->client->dev, "INTERRUPT_STS %x\n", int_sts);
3125 ret = ub960_read(priv, UB960_SR_FWD_STS, &fwd_sts);
3129 dev_dbg(&priv->client->dev, "FWD_STS %#02x\n", fwd_sts);
3131 for (i = 0; i < priv->hw_data->num_txports; i++) {
3132 if (int_sts & UB960_SR_INTERRUPT_STS_IS_CSI_TX(i))
3133 ub960_csi_handle_events(priv, i);
3136 for (i = 0; i < priv->hw_data->num_rxports; i++) {
3137 if (!priv->rxports[i])
3140 if (int_sts & UB960_SR_INTERRUPT_STS_IS_RX(i))
3141 ub960_rxport_handle_events(priv, i);
3147 static void ub960_handler_work(struct work_struct *work)
3149 struct delayed_work *dwork = to_delayed_work(work);
3150 struct ub960_data *priv =
3151 container_of(dwork, struct ub960_data, poll_work);
3153 ub960_handle_events(0, priv);
3155 schedule_delayed_work(&priv->poll_work,
3156 msecs_to_jiffies(UB960_POLL_TIME_MS));
3159 static void ub960_txport_free_ports(struct ub960_data *priv)
3163 for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
3164 struct ub960_txport *txport = priv->txports[nport];
3170 priv->txports[nport] = NULL;
3174 static void ub960_rxport_free_ports(struct ub960_data *priv)
3178 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
3179 struct ub960_rxport *rxport = priv->rxports[nport];
3184 fwnode_handle_put(rxport->source.ep_fwnode);
3185 fwnode_handle_put(rxport->ser.fwnode);
3188 priv->rxports[nport] = NULL;
3193 ub960_parse_dt_rxport_link_properties(struct ub960_data *priv,
3194 struct fwnode_handle *link_fwnode,
3195 struct ub960_rxport *rxport)
3197 struct device *dev = &priv->client->dev;
3198 unsigned int nport = rxport->nport;
3206 cdr_mode = RXPORT_CDR_FPD3;
3208 ret = fwnode_property_read_u32(link_fwnode, "ti,cdr-mode", &cdr_mode);
3209 if (ret < 0 && ret != -EINVAL) {
3210 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3211 "ti,cdr-mode", ret);
3215 if (cdr_mode > RXPORT_CDR_LAST) {
3216 dev_err(dev, "rx%u: bad 'ti,cdr-mode' %u\n", nport, cdr_mode);
3220 if (!priv->hw_data->is_fpdlink4 && cdr_mode == RXPORT_CDR_FPD4) {
3221 dev_err(dev, "rx%u: FPD-Link 4 CDR not supported\n", nport);
3225 rxport->cdr_mode = cdr_mode;
3227 ret = fwnode_property_read_u32(link_fwnode, "ti,rx-mode", &rx_mode);
3229 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3234 if (rx_mode > RXPORT_MODE_LAST) {
3235 dev_err(dev, "rx%u: bad 'ti,rx-mode' %u\n", nport, rx_mode);
3240 case RXPORT_MODE_RAW12_HF:
3241 case RXPORT_MODE_RAW12_LF:
3242 dev_err(dev, "rx%u: unsupported 'ti,rx-mode' %u\n", nport,
3249 rxport->rx_mode = rx_mode;
3251 /* EQ & Strobe related */
3254 rxport->eq.manual_eq = false;
3255 rxport->eq.aeq.eq_level_min = UB960_MIN_EQ_LEVEL;
3256 rxport->eq.aeq.eq_level_max = UB960_MAX_EQ_LEVEL;
3258 ret = fwnode_property_read_u32(link_fwnode, "ti,strobe-pos",
3261 if (ret != -EINVAL) {
3262 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3263 "ti,strobe-pos", ret);
3267 if (strobe_pos < UB960_MIN_MANUAL_STROBE_POS ||
3268 strobe_pos > UB960_MAX_MANUAL_STROBE_POS) {
3269 dev_err(dev, "rx%u: illegal 'strobe-pos' value: %d\n",
3274 /* NOTE: ignored unless global manual strobe pos is also set */
3275 rxport->eq.strobe_pos = strobe_pos;
3276 if (!priv->strobe.manual)
3278 "rx%u: 'ti,strobe-pos' ignored as 'ti,manual-strobe' not set\n",
3282 ret = fwnode_property_read_u32(link_fwnode, "ti,eq-level", &eq_level);
3284 if (ret != -EINVAL) {
3285 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3286 "ti,eq-level", ret);
3290 if (eq_level > UB960_MAX_EQ_LEVEL) {
3291 dev_err(dev, "rx%u: illegal 'ti,eq-level' value: %d\n",
3296 rxport->eq.manual_eq = true;
3297 rxport->eq.manual.eq_level = eq_level;
3300 ret = fwnode_property_read_u32(link_fwnode, "i2c-alias",
3303 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3307 rxport->ser.alias = ser_i2c_alias;
3309 rxport->ser.fwnode = fwnode_get_named_child_node(link_fwnode, "serializer");
3310 if (!rxport->ser.fwnode) {
3311 dev_err(dev, "rx%u: missing 'serializer' node\n", nport);
3318 static int ub960_parse_dt_rxport_ep_properties(struct ub960_data *priv,
3319 struct fwnode_handle *ep_fwnode,
3320 struct ub960_rxport *rxport)
3322 struct device *dev = &priv->client->dev;
3323 struct v4l2_fwnode_endpoint vep = {};
3324 unsigned int nport = rxport->nport;
3329 rxport->source.ep_fwnode = fwnode_graph_get_remote_endpoint(ep_fwnode);
3330 if (!rxport->source.ep_fwnode) {
3331 dev_err(dev, "rx%u: no remote endpoint\n", nport);
3335 /* We currently have properties only for RAW modes */
3337 switch (rxport->rx_mode) {
3338 case RXPORT_MODE_RAW10:
3339 case RXPORT_MODE_RAW12_HF:
3340 case RXPORT_MODE_RAW12_LF:
3346 vep.bus_type = V4L2_MBUS_PARALLEL;
3347 ret = v4l2_fwnode_endpoint_parse(ep_fwnode, &vep);
3349 dev_err(dev, "rx%u: failed to parse endpoint data\n", nport);
3350 goto err_put_source_ep_fwnode;
3353 hsync_hi = !!(vep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH);
3354 vsync_hi = !!(vep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH);
3356 /* LineValid and FrameValid are inverse to the h/vsync active */
3357 rxport->lv_fv_pol = (hsync_hi ? UB960_RR_PORT_CONFIG2_LV_POL_LOW : 0) |
3358 (vsync_hi ? UB960_RR_PORT_CONFIG2_FV_POL_LOW : 0);
3362 err_put_source_ep_fwnode:
3363 fwnode_handle_put(rxport->source.ep_fwnode);
3367 static int ub960_parse_dt_rxport(struct ub960_data *priv, unsigned int nport,
3368 struct fwnode_handle *link_fwnode,
3369 struct fwnode_handle *ep_fwnode)
3371 static const char *vpoc_names[UB960_MAX_RX_NPORTS] = {
3372 "vpoc0", "vpoc1", "vpoc2", "vpoc3"
3374 struct device *dev = &priv->client->dev;
3375 struct ub960_rxport *rxport;
3378 rxport = kzalloc(sizeof(*rxport), GFP_KERNEL);
3382 priv->rxports[nport] = rxport;
3384 rxport->nport = nport;
3385 rxport->priv = priv;
3387 ret = ub960_parse_dt_rxport_link_properties(priv, link_fwnode, rxport);
3389 goto err_free_rxport;
3391 rxport->vpoc = devm_regulator_get_optional(dev, vpoc_names[nport]);
3392 if (IS_ERR(rxport->vpoc)) {
3393 ret = PTR_ERR(rxport->vpoc);
3394 if (ret == -ENODEV) {
3395 rxport->vpoc = NULL;
3397 dev_err(dev, "rx%u: failed to get VPOC supply: %d\n",
3399 goto err_put_remote_fwnode;
3403 ret = ub960_parse_dt_rxport_ep_properties(priv, ep_fwnode, rxport);
3405 goto err_put_remote_fwnode;
3409 err_put_remote_fwnode:
3410 fwnode_handle_put(rxport->ser.fwnode);
3412 priv->rxports[nport] = NULL;
3417 static struct fwnode_handle *
3418 ub960_fwnode_get_link_by_regs(struct fwnode_handle *links_fwnode,
3421 struct fwnode_handle *link_fwnode;
3424 fwnode_for_each_child_node(links_fwnode, link_fwnode) {
3427 if (!str_has_prefix(fwnode_get_name(link_fwnode), "link@"))
3430 ret = fwnode_property_read_u32(link_fwnode, "reg", &link_num);
3432 fwnode_handle_put(link_fwnode);
3436 if (nport == link_num)
3443 static int ub960_parse_dt_rxports(struct ub960_data *priv)
3445 struct device *dev = &priv->client->dev;
3446 struct fwnode_handle *links_fwnode;
3450 links_fwnode = fwnode_get_named_child_node(dev_fwnode(dev), "links");
3451 if (!links_fwnode) {
3452 dev_err(dev, "'links' node missing\n");
3456 /* Defaults, recommended by TI */
3457 priv->strobe.min = 2;
3458 priv->strobe.max = 3;
3460 priv->strobe.manual = fwnode_property_read_bool(links_fwnode, "ti,manual-strobe");
3462 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
3463 struct fwnode_handle *link_fwnode;
3464 struct fwnode_handle *ep_fwnode;
3466 link_fwnode = ub960_fwnode_get_link_by_regs(links_fwnode, nport);
3470 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
3473 fwnode_handle_put(link_fwnode);
3477 ret = ub960_parse_dt_rxport(priv, nport, link_fwnode,
3480 fwnode_handle_put(link_fwnode);
3481 fwnode_handle_put(ep_fwnode);
3484 dev_err(dev, "rx%u: failed to parse RX port\n", nport);
3489 fwnode_handle_put(links_fwnode);
3494 fwnode_handle_put(links_fwnode);
3499 static int ub960_parse_dt_txports(struct ub960_data *priv)
3501 struct device *dev = &priv->client->dev;
3505 for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
3506 unsigned int port = nport + priv->hw_data->num_rxports;
3507 struct fwnode_handle *ep_fwnode;
3509 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
3514 ret = ub960_parse_dt_txport(priv, ep_fwnode, nport);
3516 fwnode_handle_put(ep_fwnode);
3525 static int ub960_parse_dt(struct ub960_data *priv)
3529 ret = ub960_parse_dt_rxports(priv);
3533 ret = ub960_parse_dt_txports(priv);
3535 goto err_free_rxports;
3540 ub960_rxport_free_ports(priv);
3545 static int ub960_notify_bound(struct v4l2_async_notifier *notifier,
3546 struct v4l2_subdev *subdev,
3547 struct v4l2_async_connection *asd)
3549 struct ub960_data *priv = sd_to_ub960(notifier->sd);
3550 struct ub960_rxport *rxport = to_ub960_asd(asd)->rxport;
3551 struct device *dev = &priv->client->dev;
3552 u8 nport = rxport->nport;
3556 ret = media_entity_get_fwnode_pad(&subdev->entity,
3557 rxport->source.ep_fwnode,
3558 MEDIA_PAD_FL_SOURCE);
3560 dev_err(dev, "Failed to find pad for %s\n", subdev->name);
3564 rxport->source.sd = subdev;
3565 rxport->source.pad = ret;
3567 ret = media_create_pad_link(&rxport->source.sd->entity,
3568 rxport->source.pad, &priv->sd.entity, nport,
3569 MEDIA_LNK_FL_ENABLED |
3570 MEDIA_LNK_FL_IMMUTABLE);
3572 dev_err(dev, "Unable to link %s:%u -> %s:%u\n",
3573 rxport->source.sd->name, rxport->source.pad,
3574 priv->sd.name, nport);
3578 for (i = 0; i < priv->hw_data->num_rxports; i++) {
3579 if (priv->rxports[i] && !priv->rxports[i]->source.sd) {
3580 dev_dbg(dev, "Waiting for more subdevs to be bound\n");
3588 static void ub960_notify_unbind(struct v4l2_async_notifier *notifier,
3589 struct v4l2_subdev *subdev,
3590 struct v4l2_async_connection *asd)
3592 struct ub960_rxport *rxport = to_ub960_asd(asd)->rxport;
3594 rxport->source.sd = NULL;
3597 static const struct v4l2_async_notifier_operations ub960_notify_ops = {
3598 .bound = ub960_notify_bound,
3599 .unbind = ub960_notify_unbind,
3602 static int ub960_v4l2_notifier_register(struct ub960_data *priv)
3604 struct device *dev = &priv->client->dev;
3608 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd);
3610 for (i = 0; i < priv->hw_data->num_rxports; i++) {
3611 struct ub960_rxport *rxport = priv->rxports[i];
3612 struct ub960_asd *asd;
3617 asd = v4l2_async_nf_add_fwnode(&priv->notifier,
3618 rxport->source.ep_fwnode,
3621 dev_err(dev, "Failed to add subdev for source %u: %pe",
3623 v4l2_async_nf_cleanup(&priv->notifier);
3624 return PTR_ERR(asd);
3627 asd->rxport = rxport;
3630 priv->notifier.ops = &ub960_notify_ops;
3632 ret = v4l2_async_nf_register(&priv->notifier);
3634 dev_err(dev, "Failed to register subdev_notifier");
3635 v4l2_async_nf_cleanup(&priv->notifier);
3642 static void ub960_v4l2_notifier_unregister(struct ub960_data *priv)
3644 v4l2_async_nf_unregister(&priv->notifier);
3645 v4l2_async_nf_cleanup(&priv->notifier);
3648 static int ub960_create_subdev(struct ub960_data *priv)
3650 struct device *dev = &priv->client->dev;
3654 v4l2_i2c_subdev_init(&priv->sd, priv->client, &ub960_subdev_ops);
3656 v4l2_ctrl_handler_init(&priv->ctrl_handler, 1);
3657 priv->sd.ctrl_handler = &priv->ctrl_handler;
3659 v4l2_ctrl_new_int_menu(&priv->ctrl_handler, NULL, V4L2_CID_LINK_FREQ,
3660 ARRAY_SIZE(priv->tx_link_freq) - 1, 0,
3661 priv->tx_link_freq);
3663 if (priv->ctrl_handler.error) {
3664 ret = priv->ctrl_handler.error;
3668 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
3669 V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_STREAMS;
3670 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
3671 priv->sd.entity.ops = &ub960_entity_ops;
3673 for (i = 0; i < priv->hw_data->num_rxports + priv->hw_data->num_txports; i++) {
3674 priv->pads[i].flags = ub960_pad_is_sink(priv, i) ?
3676 MEDIA_PAD_FL_SOURCE;
3679 ret = media_entity_pads_init(&priv->sd.entity,
3680 priv->hw_data->num_rxports +
3681 priv->hw_data->num_txports,
3686 priv->sd.state_lock = priv->sd.ctrl_handler->lock;
3688 ret = v4l2_subdev_init_finalize(&priv->sd);
3690 goto err_entity_cleanup;
3692 ret = ub960_v4l2_notifier_register(priv);
3694 dev_err(dev, "v4l2 subdev notifier register failed: %d\n", ret);
3695 goto err_subdev_cleanup;
3698 ret = v4l2_async_register_subdev(&priv->sd);
3700 dev_err(dev, "v4l2_async_register_subdev error: %d\n", ret);
3701 goto err_unreg_notif;
3707 ub960_v4l2_notifier_unregister(priv);
3709 v4l2_subdev_cleanup(&priv->sd);
3711 media_entity_cleanup(&priv->sd.entity);
3713 v4l2_ctrl_handler_free(&priv->ctrl_handler);
3718 static void ub960_destroy_subdev(struct ub960_data *priv)
3720 ub960_v4l2_notifier_unregister(priv);
3721 v4l2_async_unregister_subdev(&priv->sd);
3723 v4l2_subdev_cleanup(&priv->sd);
3725 media_entity_cleanup(&priv->sd.entity);
3726 v4l2_ctrl_handler_free(&priv->ctrl_handler);
3729 static const struct regmap_config ub960_regmap_config = {
3730 .name = "ds90ub960",
3735 .max_register = 0xff,
3738 * We do locking in the driver to cover the TX/RX port selection and the
3739 * indirect register access.
3741 .disable_locking = true,
3744 static void ub960_reset(struct ub960_data *priv, bool reset_regs)
3746 struct device *dev = &priv->client->dev;
3751 bit = reset_regs ? UB960_SR_RESET_DIGITAL_RESET1 :
3752 UB960_SR_RESET_DIGITAL_RESET0;
3754 ub960_write(priv, UB960_SR_RESET, bit);
3756 mutex_lock(&priv->reg_lock);
3758 ret = regmap_read_poll_timeout(priv->regmap, UB960_SR_RESET, v,
3759 (v & bit) == 0, 2000, 100000);
3761 mutex_unlock(&priv->reg_lock);
3764 dev_err(dev, "reset failed: %d\n", ret);
3767 static int ub960_get_hw_resources(struct ub960_data *priv)
3769 struct device *dev = &priv->client->dev;
3771 priv->regmap = devm_regmap_init_i2c(priv->client, &ub960_regmap_config);
3772 if (IS_ERR(priv->regmap))
3773 return PTR_ERR(priv->regmap);
3775 priv->vddio = devm_regulator_get(dev, "vddio");
3776 if (IS_ERR(priv->vddio))
3777 return dev_err_probe(dev, PTR_ERR(priv->vddio),
3778 "cannot get VDDIO regulator\n");
3780 /* get power-down pin from DT */
3782 devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
3783 if (IS_ERR(priv->pd_gpio))
3784 return dev_err_probe(dev, PTR_ERR(priv->pd_gpio),
3785 "Cannot get powerdown GPIO\n");
3787 priv->refclk = devm_clk_get(dev, "refclk");
3788 if (IS_ERR(priv->refclk))
3789 return dev_err_probe(dev, PTR_ERR(priv->refclk),
3790 "Cannot get REFCLK\n");
3795 static int ub960_enable_core_hw(struct ub960_data *priv)
3797 struct device *dev = &priv->client->dev;
3803 ret = regulator_enable(priv->vddio);
3805 return dev_err_probe(dev, ret,
3806 "failed to enable VDDIO regulator\n");
3808 ret = clk_prepare_enable(priv->refclk);
3810 dev_err_probe(dev, ret, "Failed to enable refclk\n");
3811 goto err_disable_vddio;
3814 if (priv->pd_gpio) {
3815 gpiod_set_value_cansleep(priv->pd_gpio, 1);
3816 /* wait min 2 ms for reset to complete */
3818 gpiod_set_value_cansleep(priv->pd_gpio, 0);
3819 /* wait min 2 ms for power up to finish */
3823 ub960_reset(priv, true);
3825 /* Runtime check register accessibility */
3826 ret = ub960_read(priv, UB960_SR_REV_MASK, &rev_mask);
3828 dev_err_probe(dev, ret, "Cannot read first register, abort\n");
3832 dev_dbg(dev, "Found %s (rev/mask %#04x)\n", priv->hw_data->model,
3835 ret = ub960_read(priv, UB960_SR_DEVICE_STS, &dev_sts);
3839 ret = ub960_read(priv, UB960_XR_REFCLK_FREQ, &refclk_freq);
3843 dev_dbg(dev, "refclk valid %u freq %u MHz (clk fw freq %lu MHz)\n",
3844 !!(dev_sts & BIT(4)), refclk_freq,
3845 clk_get_rate(priv->refclk) / 1000000);
3847 /* Disable all RX ports by default */
3848 ret = ub960_write(priv, UB960_SR_RX_PORT_CTL, 0);
3852 /* release GPIO lock */
3853 if (priv->hw_data->is_ub9702) {
3854 ret = ub960_update_bits(priv, UB960_SR_RESET,
3855 UB960_SR_RESET_GPIO_LOCK_RELEASE,
3856 UB960_SR_RESET_GPIO_LOCK_RELEASE);
3864 gpiod_set_value_cansleep(priv->pd_gpio, 1);
3865 clk_disable_unprepare(priv->refclk);
3867 regulator_disable(priv->vddio);
3872 static void ub960_disable_core_hw(struct ub960_data *priv)
3874 gpiod_set_value_cansleep(priv->pd_gpio, 1);
3875 clk_disable_unprepare(priv->refclk);
3876 regulator_disable(priv->vddio);
3879 static int ub960_probe(struct i2c_client *client)
3881 struct device *dev = &client->dev;
3882 struct ub960_data *priv;
3883 unsigned int port_lock_mask;
3884 unsigned int port_mask;
3888 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3892 priv->client = client;
3894 priv->hw_data = device_get_match_data(dev);
3896 mutex_init(&priv->reg_lock);
3898 INIT_DELAYED_WORK(&priv->poll_work, ub960_handler_work);
3901 * Initialize these to invalid values so that the first reg writes will
3902 * configure the target.
3904 priv->reg_current.indirect_target = 0xff;
3905 priv->reg_current.rxport = 0xff;
3906 priv->reg_current.txport = 0xff;
3908 ret = ub960_get_hw_resources(priv);
3910 goto err_mutex_destroy;
3912 ret = ub960_enable_core_hw(priv);
3914 goto err_mutex_destroy;
3916 ret = ub960_parse_dt(priv);
3918 goto err_disable_core_hw;
3920 ret = ub960_init_tx_ports(priv);
3922 goto err_free_ports;
3924 ret = ub960_rxport_enable_vpocs(priv);
3926 goto err_free_ports;
3928 ret = ub960_init_rx_ports(priv);
3930 goto err_disable_vpocs;
3932 ub960_reset(priv, false);
3936 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
3937 struct ub960_rxport *rxport = priv->rxports[nport];
3942 port_mask |= BIT(nport);
3945 ret = ub960_rxport_wait_locks(priv, port_mask, &port_lock_mask);
3947 goto err_disable_vpocs;
3949 if (port_mask != port_lock_mask) {
3951 dev_err_probe(dev, ret, "Failed to lock all RX ports\n");
3952 goto err_disable_vpocs;
3956 * Clear any errors caused by switching the RX port settings while
3959 ub960_clear_rx_errors(priv);
3961 ret = ub960_init_atr(priv);
3963 goto err_disable_vpocs;
3965 ret = ub960_rxport_add_serializers(priv);
3967 goto err_uninit_atr;
3969 ret = ub960_create_subdev(priv);
3974 dev_warn(dev, "irq support not implemented, using polling\n");
3976 schedule_delayed_work(&priv->poll_work,
3977 msecs_to_jiffies(UB960_POLL_TIME_MS));
3982 ub960_rxport_remove_serializers(priv);
3984 ub960_uninit_atr(priv);
3986 ub960_rxport_disable_vpocs(priv);
3988 ub960_rxport_free_ports(priv);
3989 ub960_txport_free_ports(priv);
3990 err_disable_core_hw:
3991 ub960_disable_core_hw(priv);
3993 mutex_destroy(&priv->reg_lock);
3997 static void ub960_remove(struct i2c_client *client)
3999 struct v4l2_subdev *sd = i2c_get_clientdata(client);
4000 struct ub960_data *priv = sd_to_ub960(sd);
4002 cancel_delayed_work_sync(&priv->poll_work);
4004 ub960_destroy_subdev(priv);
4005 ub960_rxport_remove_serializers(priv);
4006 ub960_uninit_atr(priv);
4007 ub960_rxport_disable_vpocs(priv);
4008 ub960_rxport_free_ports(priv);
4009 ub960_txport_free_ports(priv);
4010 ub960_disable_core_hw(priv);
4011 mutex_destroy(&priv->reg_lock);
4014 static const struct ub960_hw_data ds90ub960_hw = {
4020 static const struct ub960_hw_data ds90ub9702_hw = {
4025 .is_fpdlink4 = true,
4028 static const struct i2c_device_id ub960_id[] = {
4029 { "ds90ub960-q1", (kernel_ulong_t)&ds90ub960_hw },
4030 { "ds90ub9702-q1", (kernel_ulong_t)&ds90ub9702_hw },
4033 MODULE_DEVICE_TABLE(i2c, ub960_id);
4035 static const struct of_device_id ub960_dt_ids[] = {
4036 { .compatible = "ti,ds90ub960-q1", .data = &ds90ub960_hw },
4037 { .compatible = "ti,ds90ub9702-q1", .data = &ds90ub9702_hw },
4040 MODULE_DEVICE_TABLE(of, ub960_dt_ids);
4042 static struct i2c_driver ds90ub960_driver = {
4043 .probe = ub960_probe,
4044 .remove = ub960_remove,
4045 .id_table = ub960_id,
4047 .name = "ds90ub960",
4048 .of_match_table = ub960_dt_ids,
4051 module_i2c_driver(ds90ub960_driver);
4053 MODULE_LICENSE("GPL");
4054 MODULE_DESCRIPTION("Texas Instruments FPD-Link III/IV Deserializers Driver");
4055 MODULE_AUTHOR("Luca Ceresoli <luca@lucaceresoli.net>");
4056 MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>");
4057 MODULE_IMPORT_NS(I2C_ATR);