drivers/media/i2c/ar0521.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2021 Sieć Badawcza Łukasiewicz
   4  * - Przemysłowy Instytut Automatyki i Pomiarów PIAP
   5  * Written by Krzysztof Hałasa
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/pm_runtime.h>
  11
  12 #include <media/v4l2-ctrls.h>
  13 #include <media/v4l2-fwnode.h>
  14 #include <media/v4l2-subdev.h>
  15
  16 /* External clock (extclk) frequencies */
  17 #define AR0521_EXTCLK_MIN         (10 * 1000 * 1000)
  18 #define AR0521_EXTCLK_MAX         (48 * 1000 * 1000)
  19
  20 /* PLL and PLL2 */
  21 #define AR0521_PLL_MIN           (320 * 1000 * 1000)
  22 #define AR0521_PLL_MAX          (1280 * 1000 * 1000)
  23
  24 /* Effective pixel clocks, the registers may be DDR */
  25 #define AR0521_PIXEL_CLOCK_RATE  (184 * 1000 * 1000)
  26 #define AR0521_PIXEL_CLOCK_MIN   (168 * 1000 * 1000)
  27 #define AR0521_PIXEL_CLOCK_MAX   (414 * 1000 * 1000)
  28
  29 #define AR0521_WIDTH_MIN               8u
  30 #define AR0521_WIDTH_MAX            2608u
  31 #define AR0521_HEIGHT_MIN              8u
  32 #define AR0521_HEIGHT_MAX           1958u
  33
  34 #define AR0521_WIDTH_BLANKING_MIN     572u
  35 #define AR0521_HEIGHT_BLANKING_MIN     38u /* must be even */
  36 #define AR0521_TOTAL_WIDTH_MIN       2968u
  37
  38 /* AR0521 registers */
  39 #define AR0521_REG_VT_PIX_CLK_DIV               0x0300
  40 #define AR0521_REG_FRAME_LENGTH_LINES           0x0340
  41
  42 #define AR0521_REG_CHIP_ID                      0x3000
  43 #define AR0521_REG_COARSE_INTEGRATION_TIME      0x3012
  44 #define AR0521_REG_ROW_SPEED                    0x3016
  45 #define AR0521_REG_EXTRA_DELAY                  0x3018
  46 #define AR0521_REG_RESET                        0x301A
  47 #define   AR0521_REG_RESET_DEFAULTS               0x0238
  48 #define   AR0521_REG_RESET_GROUP_PARAM_HOLD       0x8000
  49 #define   AR0521_REG_RESET_STREAM                 BIT(2)
  50 #define   AR0521_REG_RESET_RESTART                BIT(1)
  51 #define   AR0521_REG_RESET_INIT                   BIT(0)
  52
  53 #define AR0521_REG_GREEN1_GAIN                  0x3056
  54 #define AR0521_REG_BLUE_GAIN                    0x3058
  55 #define AR0521_REG_RED_GAIN                     0x305A
  56 #define AR0521_REG_GREEN2_GAIN                  0x305C
  57 #define AR0521_REG_GLOBAL_GAIN                  0x305E
  58
  59 #define AR0521_REG_HISPI_TEST_MODE              0x3066
  60 #define AR0521_REG_HISPI_TEST_MODE_LP11           0x0004
  61
  62 #define AR0521_REG_TEST_PATTERN_MODE            0x3070
  63
  64 #define AR0521_REG_SERIAL_FORMAT                0x31AE
  65 #define AR0521_REG_SERIAL_FORMAT_MIPI             0x0200
  66
  67 #define AR0521_REG_HISPI_CONTROL_STATUS         0x31C6
  68 #define AR0521_REG_HISPI_CONTROL_STATUS_FRAMER_TEST_MODE_ENABLE 0x80
  69
  70 #define be              cpu_to_be16
  71
  72 static const char * const ar0521_supply_names[] = {
  73         "vdd_io",       /* I/O (1.8V) supply */
  74         "vdd",          /* Core, PLL and MIPI (1.2V) supply */
  75         "vaa",          /* Analog (2.7V) supply */
  76 };
  77
  78 struct ar0521_ctrls {
  79         struct v4l2_ctrl_handler handler;
  80         struct {
  81                 struct v4l2_ctrl *gain;
  82                 struct v4l2_ctrl *red_balance;
  83                 struct v4l2_ctrl *blue_balance;
  84         };
  85         struct {
  86                 struct v4l2_ctrl *hblank;
  87                 struct v4l2_ctrl *vblank;
  88         };
  89         struct v4l2_ctrl *pixrate;
  90         struct v4l2_ctrl *exposure;
  91         struct v4l2_ctrl *test_pattern;
  92 };
  93
  94 struct ar0521_dev {
  95         struct i2c_client *i2c_client;
  96         struct v4l2_subdev sd;
  97         struct media_pad pad;
  98         struct clk *extclk;
  99         u32 extclk_freq;
 100
 101         struct regulator *supplies[ARRAY_SIZE(ar0521_supply_names)];
 102         struct gpio_desc *reset_gpio;
 103
 104         /* lock to protect all members below */
 105         struct mutex lock;
 106
 107         struct v4l2_mbus_framefmt fmt;
 108         struct ar0521_ctrls ctrls;
 109         unsigned int lane_count;
 110         u16 total_width;
 111         u16 total_height;
 112         u16 pll_pre;
 113         u16 pll_mult;
 114         u16 pll_pre2;
 115         u16 pll_mult2;
 116         bool streaming;
 117 };
 118
 119 static inline struct ar0521_dev *to_ar0521_dev(struct v4l2_subdev *sd)
 120 {
 121         return container_of(sd, struct ar0521_dev, sd);
 122 }
 123
 124 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
 125 {
 126         return &container_of(ctrl->handler, struct ar0521_dev,
 127                              ctrls.handler)->sd;
 128 }
 129
 130 static u32 div64_round(u64 v, u32 d)
 131 {
 132         return div_u64(v + (d >> 1), d);
 133 }
 134
 135 static u32 div64_round_up(u64 v, u32 d)
 136 {
 137         return div_u64(v + d - 1, d);
 138 }
 139
 140 /* Data must be BE16, the first value is the register address */
 141 static int ar0521_write_regs(struct ar0521_dev *sensor, const __be16 *data,
 142                              unsigned int count)
 143 {
 144         struct i2c_client *client = sensor->i2c_client;
 145         struct i2c_msg msg;
 146         int ret;
 147
 148         msg.addr = client->addr;
 149         msg.flags = client->flags;
 150         msg.buf = (u8 *)data;
 151         msg.len = count * sizeof(*data);
 152
 153         ret = i2c_transfer(client->adapter, &msg, 1);
 154
 155         if (ret < 0) {
 156                 v4l2_err(&sensor->sd, "%s: I2C write error\n", __func__);
 157                 return ret;
 158         }
 159
 160         return 0;
 161 }
 162
 163 static int ar0521_write_reg(struct ar0521_dev *sensor, u16 reg, u16 val)
 164 {
 165         __be16 buf[2] = {be(reg), be(val)};
 166
 167         return ar0521_write_regs(sensor, buf, 2);
 168 }
 169
 170 static int ar0521_set_geometry(struct ar0521_dev *sensor)
 171 {
 172         /* All dimensions are unsigned 12-bit integers */
 173         u16 x = (AR0521_WIDTH_MAX - sensor->fmt.width) / 2;
 174         u16 y = ((AR0521_HEIGHT_MAX - sensor->fmt.height) / 2) & ~1;
 175         __be16 regs[] = {
 176                 be(AR0521_REG_FRAME_LENGTH_LINES),
 177                 be(sensor->total_height),
 178                 be(sensor->total_width),
 179                 be(x),
 180                 be(y),
 181                 be(x + sensor->fmt.width - 1),
 182                 be(y + sensor->fmt.height - 1),
 183                 be(sensor->fmt.width),
 184                 be(sensor->fmt.height)
 185         };
 186
 187         return ar0521_write_regs(sensor, regs, ARRAY_SIZE(regs));
 188 }
 189
 190 static int ar0521_set_gains(struct ar0521_dev *sensor)
 191 {
 192         int green = sensor->ctrls.gain->val;
 193         int red = max(green + sensor->ctrls.red_balance->val, 0);
 194         int blue = max(green + sensor->ctrls.blue_balance->val, 0);
 195         unsigned int gain = min(red, min(green, blue));
 196         unsigned int analog = min(gain, 64u); /* range is 0 - 127 */
 197         __be16 regs[5];
 198
 199         red   = min(red   - analog + 64, 511u);
 200         green = min(green - analog + 64, 511u);
 201         blue  = min(blue  - analog + 64, 511u);
 202         regs[0] = be(AR0521_REG_GREEN1_GAIN);
 203         regs[1] = be(green << 7 | analog);
 204         regs[2] = be(blue  << 7 | analog);
 205         regs[3] = be(red   << 7 | analog);
 206         regs[4] = be(green << 7 | analog);
 207
 208         return ar0521_write_regs(sensor, regs, ARRAY_SIZE(regs));
 209 }
 210
 211 static u32 calc_pll(struct ar0521_dev *sensor, int num, u32 freq, u16 *pre_ptr,
 212                     u16 *mult_ptr)
 213 {
 214         u16 pre = 1, mult = 1, new_pre;
 215         u32 pll = AR0521_PLL_MAX + 1;
 216
 217         for (new_pre = 1; new_pre < 64; new_pre++) {
 218                 u32 new_pll;
 219                 u32 new_mult = div64_round_up((u64)freq * new_pre,
 220                                               sensor->extclk_freq);
 221
 222                 if (new_mult < 32)
 223                         continue; /* Minimum value */
 224                 if (new_mult > 254)
 225                         break; /* Maximum, larger pre won't work either */
 226                 if (sensor->extclk_freq * (u64)new_mult < AR0521_PLL_MIN *
 227                     new_pre)
 228                         continue;
 229                 if (sensor->extclk_freq * (u64)new_mult > AR0521_PLL_MAX *
 230                     new_pre)
 231                         break; /* Larger pre won't work either */
 232                 new_pll = div64_round_up(sensor->extclk_freq * (u64)new_mult,
 233                                          new_pre);
 234                 if (new_pll < pll) {
 235                         pll = new_pll;
 236                         pre = new_pre;
 237                         mult = new_mult;
 238                 }
 239         }
 240
 241         pll = div64_round(sensor->extclk_freq * (u64)mult, pre);
 242         *pre_ptr = pre;
 243         *mult_ptr = mult;
 244         return pll;
 245 }
 246
 247 #define DIV 4
 248 static void ar0521_calc_mode(struct ar0521_dev *sensor)
 249 {
 250         unsigned int speed_mod = 4 / sensor->lane_count; /* 1 with 4 DDR lanes */
 251         u16 total_width = max(sensor->fmt.width + AR0521_WIDTH_BLANKING_MIN,
 252                               AR0521_TOTAL_WIDTH_MIN);
 253         u16 total_height = sensor->fmt.height + AR0521_HEIGHT_BLANKING_MIN;
 254
 255         /* Calculate approximate pixel clock first */
 256         u64 pix_clk = AR0521_PIXEL_CLOCK_RATE;
 257
 258         /* PLL1 drives pixel clock - dual rate */
 259         pix_clk = calc_pll(sensor, 1, pix_clk * (DIV / 2), &sensor->pll_pre,
 260                            &sensor->pll_mult);
 261         pix_clk = div64_round(pix_clk, (DIV / 2));
 262         calc_pll(sensor, 2, pix_clk * (DIV / 2) * speed_mod, &sensor->pll_pre2,
 263                  &sensor->pll_mult2);
 264
 265         sensor->total_width = total_width;
 266         sensor->total_height = total_height;
 267 }
 268
 269 static int ar0521_write_mode(struct ar0521_dev *sensor)
 270 {
 271         __be16 pll_regs[] = {
 272                 be(AR0521_REG_VT_PIX_CLK_DIV),
 273                 /* 0x300 */ be(4), /* vt_pix_clk_div = number of bits / 2 */
 274                 /* 0x302 */ be(1), /* vt_sys_clk_div */
 275                 /* 0x304 */ be((sensor->pll_pre2 << 8) | sensor->pll_pre),
 276                 /* 0x306 */ be((sensor->pll_mult2 << 8) | sensor->pll_mult),
 277                 /* 0x308 */ be(8), /* op_pix_clk_div = 2 * vt_pix_clk_div */
 278                 /* 0x30A */ be(1)  /* op_sys_clk_div */
 279         };
 280         int ret;
 281
 282         /* Stop streaming for just a moment */
 283         ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
 284                                AR0521_REG_RESET_DEFAULTS);
 285         if (ret)
 286                 return ret;
 287
 288         ret = ar0521_set_geometry(sensor);
 289         if (ret)
 290                 return ret;
 291
 292         ret = ar0521_write_regs(sensor, pll_regs, ARRAY_SIZE(pll_regs));
 293         if (ret)
 294                 return ret;
 295
 296         ret = ar0521_write_reg(sensor, AR0521_REG_COARSE_INTEGRATION_TIME,
 297                                sensor->ctrls.exposure->val);
 298         if (ret)
 299                 return ret;
 300
 301         ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
 302                                AR0521_REG_RESET_DEFAULTS |
 303                                AR0521_REG_RESET_STREAM);
 304         if (ret)
 305                 return ret;
 306
 307         ret = ar0521_write_reg(sensor, AR0521_REG_TEST_PATTERN_MODE,
 308                                sensor->ctrls.test_pattern->val);
 309         return ret;
 310 }
 311
 312 static int ar0521_set_stream(struct ar0521_dev *sensor, bool on)
 313 {
 314         int ret;
 315
 316         if (on) {
 317                 ret = pm_runtime_resume_and_get(&sensor->i2c_client->dev);
 318                 if (ret < 0)
 319                         return ret;
 320
 321                 ar0521_calc_mode(sensor);
 322                 ret = ar0521_write_mode(sensor);
 323                 if (ret)
 324                         goto err;
 325
 326                 ret = ar0521_set_gains(sensor);
 327                 if (ret)
 328                         goto err;
 329
 330                 /* Exit LP-11 mode on clock and data lanes */
 331                 ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_CONTROL_STATUS,
 332                                        0);
 333                 if (ret)
 334                         goto err;
 335
 336                 /* Start streaming */
 337                 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
 338                                        AR0521_REG_RESET_DEFAULTS |
 339                                        AR0521_REG_RESET_STREAM);
 340                 if (ret)
 341                         goto err;
 342
 343                 return 0;
 344
 345 err:
 346                 pm_runtime_put(&sensor->i2c_client->dev);
 347                 return ret;
 348
 349         } else {
 350                 /*
 351                  * Reset gain, the sensor may produce all white pixels without
 352                  * this
 353                  */
 354                 ret = ar0521_write_reg(sensor, AR0521_REG_GLOBAL_GAIN, 0x2000);
 355                 if (ret)
 356                         return ret;
 357
 358                 /* Stop streaming */
 359                 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
 360                                        AR0521_REG_RESET_DEFAULTS);
 361                 if (ret)
 362                         return ret;
 363
 364                 pm_runtime_put(&sensor->i2c_client->dev);
 365                 return 0;
 366         }
 367 }
 368
 369 static void ar0521_adj_fmt(struct v4l2_mbus_framefmt *fmt)
 370 {
 371         fmt->width = clamp(ALIGN(fmt->width, 4), AR0521_WIDTH_MIN,
 372                            AR0521_WIDTH_MAX);
 373         fmt->height = clamp(ALIGN(fmt->height, 4), AR0521_HEIGHT_MIN,
 374                             AR0521_HEIGHT_MAX);
 375         fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8;
 376         fmt->field = V4L2_FIELD_NONE;
 377         fmt->colorspace = V4L2_COLORSPACE_SRGB;
 378         fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
 379         fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
 380         fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
 381 }
 382
 383 static int ar0521_get_fmt(struct v4l2_subdev *sd,
 384                           struct v4l2_subdev_state *sd_state,
 385                           struct v4l2_subdev_format *format)
 386 {
 387         struct ar0521_dev *sensor = to_ar0521_dev(sd);
 388         struct v4l2_mbus_framefmt *fmt;
 389
 390         mutex_lock(&sensor->lock);
 391
 392         if (format->which == V4L2_SUBDEV_FORMAT_TRY)
 393                 fmt = v4l2_subdev_get_try_format(&sensor->sd, sd_state, 0
 394                                                  /* pad */);
 395         else
 396                 fmt = &sensor->fmt;
 397
 398         format->format = *fmt;
 399
 400         mutex_unlock(&sensor->lock);
 401         return 0;
 402 }
 403
 404 static int ar0521_set_fmt(struct v4l2_subdev *sd,
 405                           struct v4l2_subdev_state *sd_state,
 406                           struct v4l2_subdev_format *format)
 407 {
 408         struct ar0521_dev *sensor = to_ar0521_dev(sd);
 409
 410         ar0521_adj_fmt(&format->format);
 411
 412         mutex_lock(&sensor->lock);
 413
 414         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
 415                 struct v4l2_mbus_framefmt *fmt;
 416
 417                 fmt = v4l2_subdev_get_try_format(sd, sd_state, 0 /* pad */);
 418                 *fmt = format->format;
 419         } else {
 420                 sensor->fmt = format->format;
 421                 ar0521_calc_mode(sensor);
 422         }
 423
 424         mutex_unlock(&sensor->lock);
 425         return 0;
 426 }
 427
 428 static int ar0521_s_ctrl(struct v4l2_ctrl *ctrl)
 429 {
 430         struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
 431         struct ar0521_dev *sensor = to_ar0521_dev(sd);
 432         int ret;
 433
 434         /* v4l2_ctrl_lock() locks our own mutex */
 435
 436         switch (ctrl->id) {
 437         case V4L2_CID_HBLANK:
 438         case V4L2_CID_VBLANK:
 439                 sensor->total_width = sensor->fmt.width +
 440                         sensor->ctrls.hblank->val;
 441                 sensor->total_height = sensor->fmt.width +
 442                         sensor->ctrls.vblank->val;
 443                 break;
 444         default:
 445                 ret = -EINVAL;
 446                 break;
 447         }
 448
 449         /* access the sensor only if it's powered up */
 450         if (!pm_runtime_get_if_in_use(&sensor->i2c_client->dev))
 451                 return 0;
 452
 453         switch (ctrl->id) {
 454         case V4L2_CID_HBLANK:
 455         case V4L2_CID_VBLANK:
 456                 ret = ar0521_set_geometry(sensor);
 457                 break;
 458         case V4L2_CID_GAIN:
 459         case V4L2_CID_RED_BALANCE:
 460         case V4L2_CID_BLUE_BALANCE:
 461                 ret = ar0521_set_gains(sensor);
 462                 break;
 463         case V4L2_CID_EXPOSURE:
 464                 ret = ar0521_write_reg(sensor,
 465                                        AR0521_REG_COARSE_INTEGRATION_TIME,
 466                                        ctrl->val);
 467                 break;
 468         case V4L2_CID_TEST_PATTERN:
 469                 ret = ar0521_write_reg(sensor, AR0521_REG_TEST_PATTERN_MODE,
 470                                        ctrl->val);
 471                 break;
 472         }
 473
 474         pm_runtime_put(&sensor->i2c_client->dev);
 475         return ret;
 476 }
 477
 478 static const struct v4l2_ctrl_ops ar0521_ctrl_ops = {
 479         .s_ctrl = ar0521_s_ctrl,
 480 };
 481
 482 static const char * const test_pattern_menu[] = {
 483         "Disabled",
 484         "Solid color",
 485         "Color bars",
 486         "Faded color bars"
 487 };
 488
 489 static int ar0521_init_controls(struct ar0521_dev *sensor)
 490 {
 491         const struct v4l2_ctrl_ops *ops = &ar0521_ctrl_ops;
 492         struct ar0521_ctrls *ctrls = &sensor->ctrls;
 493         struct v4l2_ctrl_handler *hdl = &ctrls->handler;
 494         int ret;
 495
 496         v4l2_ctrl_handler_init(hdl, 32);
 497
 498         /* We can use our own mutex for the ctrl lock */
 499         hdl->lock = &sensor->lock;
 500
 501         /* Manual gain */
 502         ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, 0, 511, 1, 0);
 503         ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
 504                                                -512, 511, 1, 0);
 505         ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
 506                                                 -512, 511, 1, 0);
 507         v4l2_ctrl_cluster(3, &ctrls->gain);
 508
 509         ctrls->hblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK,
 510                                           AR0521_WIDTH_BLANKING_MIN, 4094, 1,
 511                                           AR0521_WIDTH_BLANKING_MIN);
 512         ctrls->vblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK,
 513                                           AR0521_HEIGHT_BLANKING_MIN, 4094, 2,
 514                                           AR0521_HEIGHT_BLANKING_MIN);
 515         v4l2_ctrl_cluster(2, &ctrls->hblank);
 516
 517         /* Read-only */
 518         ctrls->pixrate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,
 519                                            AR0521_PIXEL_CLOCK_MIN,
 520                                            AR0521_PIXEL_CLOCK_MAX, 1,
 521                                            AR0521_PIXEL_CLOCK_RATE);
 522
 523         /* Manual exposure time */
 524         ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE, 0,
 525                                             65535, 1, 360);
 526
 527         ctrls->test_pattern = v4l2_ctrl_new_std_menu_items(hdl, ops,
 528                                         V4L2_CID_TEST_PATTERN,
 529                                         ARRAY_SIZE(test_pattern_menu) - 1,
 530                                         0, 0, test_pattern_menu);
 531
 532         if (hdl->error) {
 533                 ret = hdl->error;
 534                 goto free_ctrls;
 535         }
 536
 537         sensor->sd.ctrl_handler = hdl;
 538         return 0;
 539
 540 free_ctrls:
 541         v4l2_ctrl_handler_free(hdl);
 542         return ret;
 543 }
 544
 545 #define REGS_ENTRY(a)   {(a), ARRAY_SIZE(a)}
 546 #define REGS(...)       REGS_ENTRY(((const __be16[]){__VA_ARGS__}))
 547
 548 static const struct initial_reg {
 549         const __be16 *data; /* data[0] is register address */
 550         unsigned int count;
 551 } initial_regs[] = {
 552         REGS(be(0x0112), be(0x0808)), /* 8-bit/8-bit mode */
 553
 554         /* PEDESTAL+2 :+2 is a workaround for 10bit mode +0.5 rounding */
 555         REGS(be(0x301E), be(0x00AA)),
 556
 557         /* corrections_recommended_bayer */
 558         REGS(be(0x3042),
 559              be(0x0004),  /* 3042: RNC: enable b/w rnc mode */
 560              be(0x4580)), /* 3044: RNC: enable row noise correction */
 561
 562         REGS(be(0x30D2),
 563              be(0x0000),  /* 30D2: CRM/CC: enable crm on Visible and CC rows */
 564              be(0x0000),  /* 30D4: CC: CC enabled with 16 samples per column */
 565              /* 30D6: CC: bw mode enabled/12 bit data resolution/bw mode */
 566              be(0x2FFF)),
 567
 568         REGS(be(0x30DA),
 569              be(0x0FFF),  /* 30DA: CC: column correction clip level 2 is 0 */
 570              be(0x0FFF),  /* 30DC: CC: column correction clip level 3 is 0 */
 571              be(0x0000)), /* 30DE: CC: Group FPN correction */
 572
 573         /* RNC: rnc scaling factor = * 54 / 64 (32 / 38 * 64 = 53.9) */
 574         REGS(be(0x30EE), be(0x1136)),
 575         REGS(be(0x30FA), be(0xFD00)), /* GPIO0 = flash, GPIO1 = shutter */
 576         REGS(be(0x3120), be(0x0005)), /* p1 dither enabled for 10bit mode */
 577         REGS(be(0x3172), be(0x0206)), /* txlo clk divider options */
 578         /* FDOC:fdoc settings with fdoc every frame turned of */
 579         REGS(be(0x3180), be(0x9434)),
 580
 581         REGS(be(0x31B0),
 582              be(0x008B),  /* 31B0: frame_preamble - FIXME check WRT lanes# */
 583              be(0x0050)), /* 31B2: line_preamble - FIXME check WRT lanes# */
 584
 585         /* don't use continuous clock mode while shut down */
 586         REGS(be(0x31BC), be(0x068C)),
 587         REGS(be(0x31E0), be(0x0781)), /* Fuse/2DDC: enable 2ddc */
 588
 589         /* analog_setup_recommended_10bit */
 590         REGS(be(0x341A), be(0x4735)), /* Samp&Hold pulse in ADC */
 591         REGS(be(0x3420), be(0x4735)), /* Samp&Hold pulse in ADC */
 592         REGS(be(0x3426), be(0x8A1A)), /* ADC offset distribution pulse */
 593         REGS(be(0x342A), be(0x0018)), /* pulse_config */
 594
 595         /* pixel_timing_recommended */
 596         REGS(be(0x3D00),
 597              /* 3D00 */ be(0x043E), be(0x4760), be(0xFFFF), be(0xFFFF),
 598              /* 3D08 */ be(0x8000), be(0x0510), be(0xAF08), be(0x0252),
 599              /* 3D10 */ be(0x486F), be(0x5D5D), be(0x8056), be(0x8313),
 600              /* 3D18 */ be(0x0087), be(0x6A48), be(0x6982), be(0x0280),
 601              /* 3D20 */ be(0x8359), be(0x8D02), be(0x8020), be(0x4882),
 602              /* 3D28 */ be(0x4269), be(0x6A95), be(0x5988), be(0x5A83),
 603              /* 3D30 */ be(0x5885), be(0x6280), be(0x6289), be(0x6097),
 604              /* 3D38 */ be(0x5782), be(0x605C), be(0xBF18), be(0x0961),
 605              /* 3D40 */ be(0x5080), be(0x2090), be(0x4390), be(0x4382),
 606              /* 3D48 */ be(0x5F8A), be(0x5D5D), be(0x9C63), be(0x8063),
 607              /* 3D50 */ be(0xA960), be(0x9757), be(0x8260), be(0x5CFF),
 608              /* 3D58 */ be(0xBF10), be(0x1681), be(0x0802), be(0x8000),
 609              /* 3D60 */ be(0x141C), be(0x6000), be(0x6022), be(0x4D80),
 610              /* 3D68 */ be(0x5C97), be(0x6A69), be(0xAC6F), be(0x4645),
 611              /* 3D70 */ be(0x4400), be(0x0513), be(0x8069), be(0x6AC6),
 612              /* 3D78 */ be(0x5F95), be(0x5F70), be(0x8040), be(0x4A81),
 613              /* 3D80 */ be(0x0300), be(0xE703), be(0x0088), be(0x4A83),
 614              /* 3D88 */ be(0x40FF), be(0xFFFF), be(0xFD70), be(0x8040),
 615              /* 3D90 */ be(0x4A85), be(0x4FA8), be(0x4F8C), be(0x0070),
 616              /* 3D98 */ be(0xBE47), be(0x8847), be(0xBC78), be(0x6B89),
 617              /* 3DA0 */ be(0x6A80), be(0x6986), be(0x6B8E), be(0x6B80),
 618              /* 3DA8 */ be(0x6980), be(0x6A88), be(0x7C9F), be(0x866B),
 619              /* 3DB0 */ be(0x8765), be(0x46FF), be(0xE365), be(0xA679),
 620              /* 3DB8 */ be(0x4A40), be(0x4580), be(0x44BC), be(0x7000),
 621              /* 3DC0 */ be(0x8040), be(0x0802), be(0x10EF), be(0x0104),
 622              /* 3DC8 */ be(0x3860), be(0x5D5D), be(0x5682), be(0x1300),
 623              /* 3DD0 */ be(0x8648), be(0x8202), be(0x8082), be(0x598A),
 624              /* 3DD8 */ be(0x0280), be(0x2048), be(0x3060), be(0x8042),
 625              /* 3DE0 */ be(0x9259), be(0x865A), be(0x8258), be(0x8562),
 626              /* 3DE8 */ be(0x8062), be(0x8560), be(0x9257), be(0x8221),
 627              /* 3DF0 */ be(0x10FF), be(0xB757), be(0x9361), be(0x1019),
 628              /* 3DF8 */ be(0x8020), be(0x9043), be(0x8E43), be(0x845F),
 629              /* 3E00 */ be(0x835D), be(0x805D), be(0x8163), be(0x8063),
 630              /* 3E08 */ be(0xA060), be(0x9157), be(0x8260), be(0x5CFF),
 631              /* 3E10 */ be(0xFFFF), be(0xFFE5), be(0x1016), be(0x2048),
 632              /* 3E18 */ be(0x0802), be(0x1C60), be(0x0014), be(0x0060),
 633              /* 3E20 */ be(0x2205), be(0x8120), be(0x908F), be(0x6A80),
 634              /* 3E28 */ be(0x6982), be(0x5F9F), be(0x6F46), be(0x4544),
 635              /* 3E30 */ be(0x0005), be(0x8013), be(0x8069), be(0x6A80),
 636              /* 3E38 */ be(0x7000), be(0x0000), be(0x0000), be(0x0000),
 637              /* 3E40 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 638              /* 3E48 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 639              /* 3E50 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 640              /* 3E58 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 641              /* 3E60 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 642              /* 3E68 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 643              /* 3E70 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 644              /* 3E78 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 645              /* 3E80 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 646              /* 3E88 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 647              /* 3E90 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 648              /* 3E98 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 649              /* 3EA0 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 650              /* 3EA8 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
 651              /* 3EB0 */ be(0x0000), be(0x0000), be(0x0000)),
 652
 653         REGS(be(0x3EB6), be(0x004C)), /* ECL */
 654
 655         REGS(be(0x3EBA),
 656              be(0xAAAD),  /* 3EBA */
 657              be(0x0086)), /* 3EBC: Bias currents for FSC/ECL */
 658
 659         REGS(be(0x3EC0),
 660              be(0x1E00),  /* 3EC0: SFbin/SH mode settings */
 661              be(0x100A),  /* 3EC2: CLK divider for ramp for 10 bit 400MH */
 662              /* 3EC4: FSC clamps for HDR mode and adc comp power down co */
 663              be(0x3300),
 664              be(0xEA44),  /* 3EC6: VLN and clk gating controls */
 665              be(0x6F6F),  /* 3EC8: Txl0 and Txlo1 settings for normal mode */
 666              be(0x2F4A),  /* 3ECA: CDAC/Txlo2/RSTGHI/RSTGLO settings */
 667              be(0x0506),  /* 3ECC: RSTDHI/RSTDLO/CDAC/TXHI settings */
 668              /* 3ECE: Ramp buffer settings and Booster enable (bits 0-5) */
 669              be(0x203B),
 670              be(0x13F0),  /* 3ED0: TXLO from atest/sf bin settings */
 671              be(0xA53D),  /* 3ED2: Ramp offset */
 672              be(0x862F),  /* 3ED4: TXLO open loop/row driver settings */
 673              be(0x4081),  /* 3ED6: Txlatch fr cfpn rows/vln bias */
 674              be(0x8003),  /* 3ED8: Ramp step setting for 10 bit 400 Mhz */
 675              be(0xA580),  /* 3EDA: Ramp Offset */
 676              be(0xC000),  /* 3EDC: over range for rst and under range for sig */
 677              be(0xC103)), /* 3EDE: over range for sig and col dec clk settings */
 678
 679         /* corrections_recommended_bayer */
 680         REGS(be(0x3F00),
 681              be(0x0017),  /* 3F00: BM_T0 */
 682              be(0x02DD),  /* 3F02: BM_T1 */
 683              /* 3F04: if Ana_gain less than 2, use noise_floor0, multipl */
 684              be(0x0020),
 685              /* 3F06: if Ana_gain between 4 and 7, use noise_floor2 and */
 686              be(0x0040),
 687              /* 3F08: if Ana_gain between 4 and 7, use noise_floor2 and */
 688              be(0x0070),
 689              /* 3F0A: Define noise_floor0(low address) and noise_floor1 */
 690              be(0x0101),
 691              be(0x0302)), /* 3F0C: Define noise_floor2 and noise_floor3 */
 692
 693         REGS(be(0x3F10),
 694              be(0x0505),  /* 3F10: single k factor 0 */
 695              be(0x0505),  /* 3F12: single k factor 1 */
 696              be(0x0505),  /* 3F14: single k factor 2 */
 697              be(0x01FF),  /* 3F16: cross factor 0 */
 698              be(0x01FF),  /* 3F18: cross factor 1 */
 699              be(0x01FF),  /* 3F1A: cross factor 2 */
 700              be(0x0022)), /* 3F1E */
 701
 702         /* GTH_THRES_RTN: 4max,4min filtered out of every 46 samples and */
 703         REGS(be(0x3F2C), be(0x442E)),
 704
 705         REGS(be(0x3F3E),
 706              be(0x0000),  /* 3F3E: Switch ADC from 12 bit to 10 bit mode */
 707              be(0x1511),  /* 3F40: couple k factor 0 */
 708              be(0x1511),  /* 3F42: couple k factor 1 */
 709              be(0x0707)), /* 3F44: couple k factor 2 */
 710 };
 711
 712 static int ar0521_power_off(struct device *dev)
 713 {
 714         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 715         struct ar0521_dev *sensor = to_ar0521_dev(sd);
 716         int i;
 717
 718         clk_disable_unprepare(sensor->extclk);
 719
 720         if (sensor->reset_gpio)
 721                 gpiod_set_value(sensor->reset_gpio, 1); /* assert RESET signal */
 722
 723         for (i = ARRAY_SIZE(ar0521_supply_names) - 1; i >= 0; i--) {
 724                 if (sensor->supplies[i])
 725                         regulator_disable(sensor->supplies[i]);
 726         }
 727         return 0;
 728 }
 729
 730 static int ar0521_power_on(struct device *dev)
 731 {
 732         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 733         struct ar0521_dev *sensor = to_ar0521_dev(sd);
 734         unsigned int cnt;
 735         int ret;
 736
 737         for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++)
 738                 if (sensor->supplies[cnt]) {
 739                         ret = regulator_enable(sensor->supplies[cnt]);
 740                         if (ret < 0)
 741                                 goto off;
 742
 743                         usleep_range(1000, 1500); /* min 1 ms */
 744                 }
 745
 746         ret = clk_prepare_enable(sensor->extclk);
 747         if (ret < 0) {
 748                 v4l2_err(&sensor->sd, "error enabling sensor clock\n");
 749                 goto off;
 750         }
 751         usleep_range(1000, 1500); /* min 1 ms */
 752
 753         if (sensor->reset_gpio)
 754                 /* deassert RESET signal */
 755                 gpiod_set_value(sensor->reset_gpio, 0);
 756         usleep_range(4500, 5000); /* min 45000 clocks */
 757
 758         for (cnt = 0; cnt < ARRAY_SIZE(initial_regs); cnt++) {
 759                 ret = ar0521_write_regs(sensor, initial_regs[cnt].data,
 760                                         initial_regs[cnt].count);
 761                 if (ret)
 762                         goto off;
 763         }
 764
 765         ret = ar0521_write_reg(sensor, AR0521_REG_SERIAL_FORMAT,
 766                                AR0521_REG_SERIAL_FORMAT_MIPI |
 767                                sensor->lane_count);
 768         if (ret)
 769                 goto off;
 770
 771         /* set MIPI test mode - disabled for now */
 772         ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_TEST_MODE,
 773                                ((0x40 << sensor->lane_count) - 0x40) |
 774                                AR0521_REG_HISPI_TEST_MODE_LP11);
 775         if (ret)
 776                 goto off;
 777
 778         ret = ar0521_write_reg(sensor, AR0521_REG_ROW_SPEED, 0x110 |
 779                                4 / sensor->lane_count);
 780         if (ret)
 781                 goto off;
 782
 783         return 0;
 784 off:
 785         ar0521_power_off(dev);
 786         return ret;
 787 }
 788
 789 static int ar0521_enum_mbus_code(struct v4l2_subdev *sd,
 790                                  struct v4l2_subdev_state *sd_state,
 791                                  struct v4l2_subdev_mbus_code_enum *code)
 792 {
 793         struct ar0521_dev *sensor = to_ar0521_dev(sd);
 794
 795         if (code->index)
 796                 return -EINVAL;
 797
 798         code->code = sensor->fmt.code;
 799         return 0;
 800 }
 801
 802 static int ar0521_pre_streamon(struct v4l2_subdev *sd, u32 flags)
 803 {
 804         struct ar0521_dev *sensor = to_ar0521_dev(sd);
 805         int ret;
 806
 807         if (!(flags & V4L2_SUBDEV_PRE_STREAMON_FL_MANUAL_LP))
 808                 return -EACCES;
 809
 810         ret = pm_runtime_resume_and_get(&sensor->i2c_client->dev);
 811         if (ret < 0)
 812                 return ret;
 813
 814         /* Set LP-11 on clock and data lanes */
 815         ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_CONTROL_STATUS,
 816                         AR0521_REG_HISPI_CONTROL_STATUS_FRAMER_TEST_MODE_ENABLE);
 817         if (ret)
 818                 goto err;
 819
 820         /* Start streaming LP-11 */
 821         ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
 822                                AR0521_REG_RESET_DEFAULTS |
 823                                AR0521_REG_RESET_STREAM);
 824         if (ret)
 825                 goto err;
 826         return 0;
 827
 828 err:
 829         pm_runtime_put(&sensor->i2c_client->dev);
 830         return ret;
 831 }
 832
 833 static int ar0521_post_streamoff(struct v4l2_subdev *sd)
 834 {
 835         struct ar0521_dev *sensor = to_ar0521_dev(sd);
 836
 837         pm_runtime_put(&sensor->i2c_client->dev);
 838         return 0;
 839 }
 840
 841 static int ar0521_s_stream(struct v4l2_subdev *sd, int enable)
 842 {
 843         struct ar0521_dev *sensor = to_ar0521_dev(sd);
 844         int ret;
 845
 846         mutex_lock(&sensor->lock);
 847
 848         ret = ar0521_set_stream(sensor, enable);
 849         if (!ret)
 850                 sensor->streaming = enable;
 851
 852         mutex_unlock(&sensor->lock);
 853         return ret;
 854 }
 855
 856 static const struct v4l2_subdev_core_ops ar0521_core_ops = {
 857         .log_status = v4l2_ctrl_subdev_log_status,
 858 };
 859
 860 static const struct v4l2_subdev_video_ops ar0521_video_ops = {
 861         .s_stream = ar0521_s_stream,
 862         .pre_streamon = ar0521_pre_streamon,
 863         .post_streamoff = ar0521_post_streamoff,
 864 };
 865
 866 static const struct v4l2_subdev_pad_ops ar0521_pad_ops = {
 867         .enum_mbus_code = ar0521_enum_mbus_code,
 868         .get_fmt = ar0521_get_fmt,
 869         .set_fmt = ar0521_set_fmt,
 870 };
 871
 872 static const struct v4l2_subdev_ops ar0521_subdev_ops = {
 873         .core = &ar0521_core_ops,
 874         .video = &ar0521_video_ops,
 875         .pad = &ar0521_pad_ops,
 876 };
 877
 878 static int __maybe_unused ar0521_suspend(struct device *dev)
 879 {
 880         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 881         struct ar0521_dev *sensor = to_ar0521_dev(sd);
 882
 883         if (sensor->streaming)
 884                 ar0521_set_stream(sensor, 0);
 885
 886         return 0;
 887 }
 888
 889 static int __maybe_unused ar0521_resume(struct device *dev)
 890 {
 891         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 892         struct ar0521_dev *sensor = to_ar0521_dev(sd);
 893
 894         if (sensor->streaming)
 895                 return ar0521_set_stream(sensor, 1);
 896
 897         return 0;
 898 }
 899
 900 static int ar0521_probe(struct i2c_client *client)
 901 {
 902         struct v4l2_fwnode_endpoint ep = {
 903                 .bus_type = V4L2_MBUS_CSI2_DPHY
 904         };
 905         struct device *dev = &client->dev;
 906         struct fwnode_handle *endpoint;
 907         struct ar0521_dev *sensor;
 908         unsigned int cnt;
 909         int ret;
 910
 911         sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
 912         if (!sensor)
 913                 return -ENOMEM;
 914
 915         sensor->i2c_client = client;
 916         sensor->fmt.width = AR0521_WIDTH_MAX;
 917         sensor->fmt.height = AR0521_HEIGHT_MAX;
 918
 919         endpoint = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0,
 920                                                    FWNODE_GRAPH_ENDPOINT_NEXT);
 921         if (!endpoint) {
 922                 dev_err(dev, "endpoint node not found\n");
 923                 return -EINVAL;
 924         }
 925
 926         ret = v4l2_fwnode_endpoint_parse(endpoint, &ep);
 927         fwnode_handle_put(endpoint);
 928         if (ret) {
 929                 dev_err(dev, "could not parse endpoint\n");
 930                 return ret;
 931         }
 932
 933         if (ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
 934                 dev_err(dev, "invalid bus type, must be MIPI CSI2\n");
 935                 return -EINVAL;
 936         }
 937
 938         sensor->lane_count = ep.bus.mipi_csi2.num_data_lanes;
 939         switch (sensor->lane_count) {
 940         case 1:
 941         case 2:
 942         case 4:
 943                 break;
 944         default:
 945                 dev_err(dev, "invalid number of MIPI data lanes\n");
 946                 return -EINVAL;
 947         }
 948
 949         /* Get master clock (extclk) */
 950         sensor->extclk = devm_clk_get(dev, "extclk");
 951         if (IS_ERR(sensor->extclk)) {
 952                 dev_err(dev, "failed to get extclk\n");
 953                 return PTR_ERR(sensor->extclk);
 954         }
 955
 956         sensor->extclk_freq = clk_get_rate(sensor->extclk);
 957
 958         if (sensor->extclk_freq < AR0521_EXTCLK_MIN ||
 959             sensor->extclk_freq > AR0521_EXTCLK_MAX) {
 960                 dev_err(dev, "extclk frequency out of range: %u Hz\n",
 961                         sensor->extclk_freq);
 962                 return -EINVAL;
 963         }
 964
 965         /* Request optional reset pin (usually active low) and assert it */
 966         sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset",
 967                                                      GPIOD_OUT_HIGH);
 968
 969         v4l2_i2c_subdev_init(&sensor->sd, client, &ar0521_subdev_ops);
 970
 971         sensor->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
 972         sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
 973         sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
 974         ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
 975         if (ret)
 976                 return ret;
 977
 978         for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++) {
 979                 struct regulator *supply = devm_regulator_get(dev,
 980                                                 ar0521_supply_names[cnt]);
 981
 982                 if (IS_ERR(supply)) {
 983                         dev_info(dev, "no %s regulator found: %li\n",
 984                                  ar0521_supply_names[cnt], PTR_ERR(supply));
 985                         return PTR_ERR(supply);
 986                 }
 987                 sensor->supplies[cnt] = supply;
 988         }
 989
 990         mutex_init(&sensor->lock);
 991
 992         ret = ar0521_init_controls(sensor);
 993         if (ret)
 994                 goto entity_cleanup;
 995
 996         ar0521_adj_fmt(&sensor->fmt);
 997
 998         ret = v4l2_async_register_subdev(&sensor->sd);
 999         if (ret)
1000                 goto free_ctrls;
1001
1002         /* Turn on the device and enable runtime PM */
1003         ret = ar0521_power_on(&client->dev);
1004         if (ret)
1005                 goto disable;
1006         pm_runtime_set_active(&client->dev);
1007         pm_runtime_enable(&client->dev);
1008         pm_runtime_idle(&client->dev);
1009         return 0;
1010
1011 disable:
1012         v4l2_async_unregister_subdev(&sensor->sd);
1013         media_entity_cleanup(&sensor->sd.entity);
1014 free_ctrls:
1015         v4l2_ctrl_handler_free(&sensor->ctrls.handler);
1016 entity_cleanup:
1017         media_entity_cleanup(&sensor->sd.entity);
1018         mutex_destroy(&sensor->lock);
1019         return ret;
1020 }
1021
1022 static void ar0521_remove(struct i2c_client *client)
1023 {
1024         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1025         struct ar0521_dev *sensor = to_ar0521_dev(sd);
1026
1027         v4l2_async_unregister_subdev(&sensor->sd);
1028         media_entity_cleanup(&sensor->sd.entity);
1029         v4l2_ctrl_handler_free(&sensor->ctrls.handler);
1030         pm_runtime_disable(&client->dev);
1031         if (!pm_runtime_status_suspended(&client->dev))
1032                 ar0521_power_off(&client->dev);
1033         pm_runtime_set_suspended(&client->dev);
1034         mutex_destroy(&sensor->lock);
1035 }
1036
1037 static const struct dev_pm_ops ar0521_pm_ops = {
1038         SET_SYSTEM_SLEEP_PM_OPS(ar0521_suspend, ar0521_resume)
1039         SET_RUNTIME_PM_OPS(ar0521_power_off, ar0521_power_on, NULL)
1040 };
1041 static const struct of_device_id ar0521_dt_ids[] = {
1042         {.compatible = "onnn,ar0521"},
1043         {}
1044 };
1045 MODULE_DEVICE_TABLE(of, ar0521_dt_ids);
1046
1047 static struct i2c_driver ar0521_i2c_driver = {
1048         .driver = {
1049                 .name  = "ar0521",
1050                 .pm = &ar0521_pm_ops,
1051                 .of_match_table = ar0521_dt_ids,
1052         },
1053         .probe_new = ar0521_probe,
1054         .remove = ar0521_remove,
1055 };
1056
1057 module_i2c_driver(ar0521_i2c_driver);
1058
1059 MODULE_DESCRIPTION("AR0521 MIPI Camera subdev driver");
1060 MODULE_AUTHOR("Krzysztof Hałasa <khalasa@piap.pl>");
1061 MODULE_LICENSE("GPL");