1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021 Sieć Badawcza Łukasiewicz
4 * - Przemysłowy Instytut Automatyki i Pomiarów PIAP
5 * Written by Krzysztof Hałasa
9 #include <linux/delay.h>
10 #include <linux/pm_runtime.h>
12 #include <media/v4l2-ctrls.h>
13 #include <media/v4l2-fwnode.h>
14 #include <media/v4l2-subdev.h>
16 /* External clock (extclk) frequencies */
17 #define AR0521_EXTCLK_MIN (10 * 1000 * 1000)
18 #define AR0521_EXTCLK_MAX (48 * 1000 * 1000)
21 #define AR0521_PLL_MIN (320 * 1000 * 1000)
22 #define AR0521_PLL_MAX (1280 * 1000 * 1000)
24 /* Effective pixel sample rate on the pixel array. */
25 #define AR0521_PIXEL_CLOCK_RATE (184 * 1000 * 1000)
26 #define AR0521_PIXEL_CLOCK_MIN (168 * 1000 * 1000)
27 #define AR0521_PIXEL_CLOCK_MAX (414 * 1000 * 1000)
29 #define AR0521_NATIVE_WIDTH 2604u
30 #define AR0521_NATIVE_HEIGHT 1964u
31 #define AR0521_MIN_X_ADDR_START 0u
32 #define AR0521_MIN_Y_ADDR_START 0u
33 #define AR0521_MAX_X_ADDR_END 2603u
34 #define AR0521_MAX_Y_ADDR_END 1955u
36 #define AR0521_WIDTH_MIN 8u
37 #define AR0521_WIDTH_MAX 2592u
38 #define AR0521_HEIGHT_MIN 8u
39 #define AR0521_HEIGHT_MAX 1944u
41 #define AR0521_WIDTH_BLANKING_MIN 572u
42 #define AR0521_HEIGHT_BLANKING_MIN 38u /* must be even */
43 #define AR0521_TOTAL_HEIGHT_MAX 65535u /* max_frame_length_lines */
44 #define AR0521_TOTAL_WIDTH_MAX 65532u /* max_line_length_pck */
46 #define AR0521_ANA_GAIN_MIN 0x00
47 #define AR0521_ANA_GAIN_MAX 0x3f
48 #define AR0521_ANA_GAIN_STEP 0x01
49 #define AR0521_ANA_GAIN_DEFAULT 0x00
51 /* AR0521 registers */
52 #define AR0521_REG_VT_PIX_CLK_DIV 0x0300
53 #define AR0521_REG_FRAME_LENGTH_LINES 0x0340
55 #define AR0521_REG_CHIP_ID 0x3000
56 #define AR0521_REG_COARSE_INTEGRATION_TIME 0x3012
57 #define AR0521_REG_ROW_SPEED 0x3016
58 #define AR0521_REG_EXTRA_DELAY 0x3018
59 #define AR0521_REG_RESET 0x301A
60 #define AR0521_REG_RESET_DEFAULTS 0x0238
61 #define AR0521_REG_RESET_GROUP_PARAM_HOLD 0x8000
62 #define AR0521_REG_RESET_STREAM BIT(2)
63 #define AR0521_REG_RESET_RESTART BIT(1)
64 #define AR0521_REG_RESET_INIT BIT(0)
66 #define AR0521_REG_ANA_GAIN_CODE_GLOBAL 0x3028
68 #define AR0521_REG_GREEN1_GAIN 0x3056
69 #define AR0521_REG_BLUE_GAIN 0x3058
70 #define AR0521_REG_RED_GAIN 0x305A
71 #define AR0521_REG_GREEN2_GAIN 0x305C
72 #define AR0521_REG_GLOBAL_GAIN 0x305E
74 #define AR0521_REG_HISPI_TEST_MODE 0x3066
75 #define AR0521_REG_HISPI_TEST_MODE_LP11 0x0004
77 #define AR0521_REG_TEST_PATTERN_MODE 0x3070
79 #define AR0521_REG_SERIAL_FORMAT 0x31AE
80 #define AR0521_REG_SERIAL_FORMAT_MIPI 0x0200
82 #define AR0521_REG_HISPI_CONTROL_STATUS 0x31C6
83 #define AR0521_REG_HISPI_CONTROL_STATUS_FRAMER_TEST_MODE_ENABLE 0x80
85 #define be cpu_to_be16
87 static const char * const ar0521_supply_names[] = {
88 "vdd_io", /* I/O (1.8V) supply */
89 "vdd", /* Core, PLL and MIPI (1.2V) supply */
90 "vaa", /* Analog (2.7V) supply */
93 static const s64 ar0521_link_frequencies[] = {
98 struct v4l2_ctrl_handler handler;
100 struct v4l2_ctrl *gain;
101 struct v4l2_ctrl *red_balance;
102 struct v4l2_ctrl *blue_balance;
105 struct v4l2_ctrl *hblank;
106 struct v4l2_ctrl *vblank;
108 struct v4l2_ctrl *pixrate;
109 struct v4l2_ctrl *exposure;
110 struct v4l2_ctrl *test_pattern;
114 struct i2c_client *i2c_client;
115 struct v4l2_subdev sd;
116 struct media_pad pad;
120 struct regulator *supplies[ARRAY_SIZE(ar0521_supply_names)];
121 struct gpio_desc *reset_gpio;
123 /* lock to protect all members below */
126 struct v4l2_mbus_framefmt fmt;
127 struct ar0521_ctrls ctrls;
128 unsigned int lane_count;
138 static inline struct ar0521_dev *to_ar0521_dev(struct v4l2_subdev *sd)
140 return container_of(sd, struct ar0521_dev, sd);
143 static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
145 return &container_of(ctrl->handler, struct ar0521_dev,
149 static u32 div64_round(u64 v, u32 d)
151 return div_u64(v + (d >> 1), d);
154 static u32 div64_round_up(u64 v, u32 d)
156 return div_u64(v + d - 1, d);
159 static int ar0521_code_to_bpp(struct ar0521_dev *sensor)
161 switch (sensor->fmt.code) {
162 case MEDIA_BUS_FMT_SGRBG8_1X8:
169 /* Data must be BE16, the first value is the register address */
170 static int ar0521_write_regs(struct ar0521_dev *sensor, const __be16 *data,
173 struct i2c_client *client = sensor->i2c_client;
177 msg.addr = client->addr;
178 msg.flags = client->flags;
179 msg.buf = (u8 *)data;
180 msg.len = count * sizeof(*data);
182 ret = i2c_transfer(client->adapter, &msg, 1);
185 v4l2_err(&sensor->sd, "%s: I2C write error\n", __func__);
192 static int ar0521_write_reg(struct ar0521_dev *sensor, u16 reg, u16 val)
194 __be16 buf[2] = {be(reg), be(val)};
196 return ar0521_write_regs(sensor, buf, 2);
199 static int ar0521_set_geometry(struct ar0521_dev *sensor)
201 /* Center the image in the visible output window. */
202 u16 x = clamp((AR0521_WIDTH_MAX - sensor->fmt.width) / 2,
203 AR0521_MIN_X_ADDR_START, AR0521_MAX_X_ADDR_END);
204 u16 y = clamp(((AR0521_HEIGHT_MAX - sensor->fmt.height) / 2) & ~1,
205 AR0521_MIN_Y_ADDR_START, AR0521_MAX_Y_ADDR_END);
207 /* All dimensions are unsigned 12-bit integers */
209 be(AR0521_REG_FRAME_LENGTH_LINES),
210 be(sensor->fmt.height + sensor->ctrls.vblank->val),
211 be(sensor->fmt.width + sensor->ctrls.hblank->val),
214 be(x + sensor->fmt.width - 1),
215 be(y + sensor->fmt.height - 1),
216 be(sensor->fmt.width),
217 be(sensor->fmt.height)
220 return ar0521_write_regs(sensor, regs, ARRAY_SIZE(regs));
223 static int ar0521_set_gains(struct ar0521_dev *sensor)
225 int green = sensor->ctrls.gain->val;
226 int red = max(green + sensor->ctrls.red_balance->val, 0);
227 int blue = max(green + sensor->ctrls.blue_balance->val, 0);
228 unsigned int gain = min(red, min(green, blue));
229 unsigned int analog = min(gain, 64u); /* range is 0 - 127 */
232 red = min(red - analog + 64, 511u);
233 green = min(green - analog + 64, 511u);
234 blue = min(blue - analog + 64, 511u);
235 regs[0] = be(AR0521_REG_GREEN1_GAIN);
236 regs[1] = be(green << 7 | analog);
237 regs[2] = be(blue << 7 | analog);
238 regs[3] = be(red << 7 | analog);
239 regs[4] = be(green << 7 | analog);
241 return ar0521_write_regs(sensor, regs, ARRAY_SIZE(regs));
244 static u32 calc_pll(struct ar0521_dev *sensor, u32 freq, u16 *pre_ptr, u16 *mult_ptr)
246 u16 pre = 1, mult = 1, new_pre;
247 u32 pll = AR0521_PLL_MAX + 1;
249 for (new_pre = 1; new_pre < 64; new_pre++) {
251 u32 new_mult = div64_round_up((u64)freq * new_pre,
252 sensor->extclk_freq);
255 continue; /* Minimum value */
257 break; /* Maximum, larger pre won't work either */
258 if (sensor->extclk_freq * (u64)new_mult < AR0521_PLL_MIN *
261 if (sensor->extclk_freq * (u64)new_mult > AR0521_PLL_MAX *
263 break; /* Larger pre won't work either */
264 new_pll = div64_round_up(sensor->extclk_freq * (u64)new_mult,
273 pll = div64_round(sensor->extclk_freq * (u64)mult, pre);
279 static void ar0521_calc_pll(struct ar0521_dev *sensor)
281 unsigned int pixel_clock;
287 * PLL1 and PLL2 are computed equally even if the application note
288 * suggests a slower PLL1 clock. Maintain pll1 and pll2 divider and
289 * multiplier separated to later specialize the calculation procedure.
292 * - mclk -> / pre_div1 * pre_mul1 = VCO1 = COUNTER_CLOCK
295 * - mclk -> / pre_div * pre_mul = VCO
297 * VCO -> / vt_pix = PIXEL_CLOCK
298 * VCO -> / vt_pix / 2 = WORD_CLOCK
299 * VCO -> / op_sys = SERIAL_CLOCK
303 * - WORD_CLOCK = PIXEL_CLOCK / 2
304 * - SERIAL_CLOCK = MIPI data rate (Mbps / lane) = WORD_CLOCK * bpp
305 * NOTE: this implies the MIPI clock is divided internally by 2
306 * to account for DDR.
308 * As op_sys_div is fixed to 1:
312 * VCO = PIXEL_CLOCK * bpp / 2
315 * MIPI_CLK = PIXEL_CLOCK * bpp / 2 / 2
317 * Generic pixel_rate to bus clock frequencey equation:
318 * MIPI_CLK = V4L2_CID_PIXEL_RATE * bpp / lanes / 2
320 * From which we derive the PIXEL_CLOCK to use in the clock tree:
321 * PIXEL_CLOCK = V4L2_CID_PIXEL_RATE * 2 / lanes
323 * Documented clock ranges:
324 * WORD_CLOCK = (35MHz - 120 MHz)
325 * PIXEL_CLOCK = (84MHz - 207MHz)
326 * VCO = (320MHz - 1280MHz)
328 * TODO: in case we have less data lanes we have to reduce the desired
329 * VCO not to exceed the limits specified by the datasheet and
330 * consequentially reduce the obtained pixel clock.
332 pixel_clock = AR0521_PIXEL_CLOCK_RATE * 2 / sensor->lane_count;
333 bpp = ar0521_code_to_bpp(sensor);
334 sensor->pll.vt_pix = bpp / 2;
335 vco = pixel_clock * sensor->pll.vt_pix;
337 calc_pll(sensor, vco, &pre, &mult);
339 sensor->pll.pre = sensor->pll.pre2 = pre;
340 sensor->pll.mult = sensor->pll.mult2 = mult;
343 static int ar0521_pll_config(struct ar0521_dev *sensor)
345 __be16 pll_regs[] = {
346 be(AR0521_REG_VT_PIX_CLK_DIV),
347 /* 0x300 */ be(sensor->pll.vt_pix), /* vt_pix_clk_div = bpp / 2 */
348 /* 0x302 */ be(1), /* vt_sys_clk_div */
349 /* 0x304 */ be((sensor->pll.pre2 << 8) | sensor->pll.pre),
350 /* 0x306 */ be((sensor->pll.mult2 << 8) | sensor->pll.mult),
351 /* 0x308 */ be(sensor->pll.vt_pix * 2), /* op_pix_clk_div = 2 * vt_pix_clk_div */
352 /* 0x30A */ be(1) /* op_sys_clk_div */
355 ar0521_calc_pll(sensor);
356 return ar0521_write_regs(sensor, pll_regs, ARRAY_SIZE(pll_regs));
359 static int ar0521_set_stream(struct ar0521_dev *sensor, bool on)
364 ret = pm_runtime_resume_and_get(&sensor->i2c_client->dev);
368 /* Stop streaming for just a moment */
369 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
370 AR0521_REG_RESET_DEFAULTS);
374 ret = ar0521_set_geometry(sensor);
378 ret = ar0521_pll_config(sensor);
382 ret = __v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
386 /* Exit LP-11 mode on clock and data lanes */
387 ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_CONTROL_STATUS,
392 /* Start streaming */
393 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
394 AR0521_REG_RESET_DEFAULTS |
395 AR0521_REG_RESET_STREAM);
402 pm_runtime_put(&sensor->i2c_client->dev);
407 * Reset gain, the sensor may produce all white pixels without
410 ret = ar0521_write_reg(sensor, AR0521_REG_GLOBAL_GAIN, 0x2000);
415 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
416 AR0521_REG_RESET_DEFAULTS);
420 pm_runtime_put(&sensor->i2c_client->dev);
425 static void ar0521_adj_fmt(struct v4l2_mbus_framefmt *fmt)
427 fmt->width = clamp(ALIGN(fmt->width, 4), AR0521_WIDTH_MIN,
429 fmt->height = clamp(ALIGN(fmt->height, 4), AR0521_HEIGHT_MIN,
431 fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8;
432 fmt->field = V4L2_FIELD_NONE;
433 fmt->colorspace = V4L2_COLORSPACE_SRGB;
434 fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
435 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
436 fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
439 static int ar0521_get_fmt(struct v4l2_subdev *sd,
440 struct v4l2_subdev_state *sd_state,
441 struct v4l2_subdev_format *format)
443 struct ar0521_dev *sensor = to_ar0521_dev(sd);
444 struct v4l2_mbus_framefmt *fmt;
446 mutex_lock(&sensor->lock);
448 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
449 fmt = v4l2_subdev_get_try_format(&sensor->sd, sd_state, 0
454 format->format = *fmt;
456 mutex_unlock(&sensor->lock);
460 static int ar0521_set_fmt(struct v4l2_subdev *sd,
461 struct v4l2_subdev_state *sd_state,
462 struct v4l2_subdev_format *format)
464 struct ar0521_dev *sensor = to_ar0521_dev(sd);
465 int max_vblank, max_hblank, exposure_max;
468 ar0521_adj_fmt(&format->format);
470 mutex_lock(&sensor->lock);
472 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
473 struct v4l2_mbus_framefmt *fmt;
475 fmt = v4l2_subdev_get_try_format(sd, sd_state, 0 /* pad */);
476 *fmt = format->format;
478 mutex_unlock(&sensor->lock);
483 sensor->fmt = format->format;
484 ar0521_calc_pll(sensor);
487 * Update the exposure and blankings limits. Blankings are also reset
490 max_hblank = AR0521_TOTAL_WIDTH_MAX - sensor->fmt.width;
491 ret = __v4l2_ctrl_modify_range(sensor->ctrls.hblank,
492 sensor->ctrls.hblank->minimum,
493 max_hblank, sensor->ctrls.hblank->step,
494 sensor->ctrls.hblank->minimum);
498 ret = __v4l2_ctrl_s_ctrl(sensor->ctrls.hblank,
499 sensor->ctrls.hblank->minimum);
503 max_vblank = AR0521_TOTAL_HEIGHT_MAX - sensor->fmt.height;
504 ret = __v4l2_ctrl_modify_range(sensor->ctrls.vblank,
505 sensor->ctrls.vblank->minimum,
506 max_vblank, sensor->ctrls.vblank->step,
507 sensor->ctrls.vblank->minimum);
511 ret = __v4l2_ctrl_s_ctrl(sensor->ctrls.vblank,
512 sensor->ctrls.vblank->minimum);
516 exposure_max = sensor->fmt.height + AR0521_HEIGHT_BLANKING_MIN - 4;
517 ret = __v4l2_ctrl_modify_range(sensor->ctrls.exposure,
518 sensor->ctrls.exposure->minimum,
520 sensor->ctrls.exposure->step,
521 sensor->ctrls.exposure->default_value);
523 mutex_unlock(&sensor->lock);
528 static int ar0521_s_ctrl(struct v4l2_ctrl *ctrl)
530 struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
531 struct ar0521_dev *sensor = to_ar0521_dev(sd);
535 /* v4l2_ctrl_lock() locks our own mutex */
538 case V4L2_CID_VBLANK:
539 exp_max = sensor->fmt.height + ctrl->val - 4;
540 __v4l2_ctrl_modify_range(sensor->ctrls.exposure,
541 sensor->ctrls.exposure->minimum,
542 exp_max, sensor->ctrls.exposure->step,
543 sensor->ctrls.exposure->default_value);
547 /* access the sensor only if it's powered up */
548 if (!pm_runtime_get_if_in_use(&sensor->i2c_client->dev))
552 case V4L2_CID_HBLANK:
553 case V4L2_CID_VBLANK:
554 ret = ar0521_set_geometry(sensor);
556 case V4L2_CID_ANALOGUE_GAIN:
557 ret = ar0521_write_reg(sensor, AR0521_REG_ANA_GAIN_CODE_GLOBAL,
561 case V4L2_CID_RED_BALANCE:
562 case V4L2_CID_BLUE_BALANCE:
563 ret = ar0521_set_gains(sensor);
565 case V4L2_CID_EXPOSURE:
566 ret = ar0521_write_reg(sensor,
567 AR0521_REG_COARSE_INTEGRATION_TIME,
570 case V4L2_CID_TEST_PATTERN:
571 ret = ar0521_write_reg(sensor, AR0521_REG_TEST_PATTERN_MODE,
575 dev_err(&sensor->i2c_client->dev,
576 "Unsupported control %x\n", ctrl->id);
581 pm_runtime_put(&sensor->i2c_client->dev);
585 static const struct v4l2_ctrl_ops ar0521_ctrl_ops = {
586 .s_ctrl = ar0521_s_ctrl,
589 static const char * const test_pattern_menu[] = {
596 static int ar0521_init_controls(struct ar0521_dev *sensor)
598 const struct v4l2_ctrl_ops *ops = &ar0521_ctrl_ops;
599 struct ar0521_ctrls *ctrls = &sensor->ctrls;
600 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
601 int max_vblank, max_hblank, exposure_max;
602 struct v4l2_ctrl *link_freq;
605 v4l2_ctrl_handler_init(hdl, 32);
607 /* We can use our own mutex for the ctrl lock */
608 hdl->lock = &sensor->lock;
611 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
612 AR0521_ANA_GAIN_MIN, AR0521_ANA_GAIN_MAX,
613 AR0521_ANA_GAIN_STEP, AR0521_ANA_GAIN_DEFAULT);
616 ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, 0, 511, 1, 0);
617 ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
619 ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
621 v4l2_ctrl_cluster(3, &ctrls->gain);
623 /* Initialize blanking limits using the default 2592x1944 format. */
624 max_hblank = AR0521_TOTAL_WIDTH_MAX - AR0521_WIDTH_MAX;
625 ctrls->hblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK,
626 AR0521_WIDTH_BLANKING_MIN,
628 AR0521_WIDTH_BLANKING_MIN);
630 max_vblank = AR0521_TOTAL_HEIGHT_MAX - AR0521_HEIGHT_MAX;
631 ctrls->vblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK,
632 AR0521_HEIGHT_BLANKING_MIN,
634 AR0521_HEIGHT_BLANKING_MIN);
635 v4l2_ctrl_cluster(2, &ctrls->hblank);
638 ctrls->pixrate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,
639 AR0521_PIXEL_CLOCK_MIN,
640 AR0521_PIXEL_CLOCK_MAX, 1,
641 AR0521_PIXEL_CLOCK_RATE);
643 /* Manual exposure time: max exposure time = visible + blank - 4 */
644 exposure_max = AR0521_HEIGHT_MAX + AR0521_HEIGHT_BLANKING_MIN - 4;
645 ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE, 0,
646 exposure_max, 1, 0x70);
648 link_freq = v4l2_ctrl_new_int_menu(hdl, ops, V4L2_CID_LINK_FREQ,
649 ARRAY_SIZE(ar0521_link_frequencies) - 1,
650 0, ar0521_link_frequencies);
652 link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
654 ctrls->test_pattern = v4l2_ctrl_new_std_menu_items(hdl, ops,
655 V4L2_CID_TEST_PATTERN,
656 ARRAY_SIZE(test_pattern_menu) - 1,
657 0, 0, test_pattern_menu);
664 sensor->sd.ctrl_handler = hdl;
668 v4l2_ctrl_handler_free(hdl);
672 #define REGS_ENTRY(a) {(a), ARRAY_SIZE(a)}
673 #define REGS(...) REGS_ENTRY(((const __be16[]){__VA_ARGS__}))
675 static const struct initial_reg {
676 const __be16 *data; /* data[0] is register address */
679 REGS(be(0x0112), be(0x0808)), /* 8-bit/8-bit mode */
681 /* PEDESTAL+2 :+2 is a workaround for 10bit mode +0.5 rounding */
682 REGS(be(0x301E), be(0x00AA)),
684 /* corrections_recommended_bayer */
686 be(0x0004), /* 3042: RNC: enable b/w rnc mode */
687 be(0x4580)), /* 3044: RNC: enable row noise correction */
690 be(0x0000), /* 30D2: CRM/CC: enable crm on Visible and CC rows */
691 be(0x0000), /* 30D4: CC: CC enabled with 16 samples per column */
692 /* 30D6: CC: bw mode enabled/12 bit data resolution/bw mode */
696 be(0x0FFF), /* 30DA: CC: column correction clip level 2 is 0 */
697 be(0x0FFF), /* 30DC: CC: column correction clip level 3 is 0 */
698 be(0x0000)), /* 30DE: CC: Group FPN correction */
700 /* RNC: rnc scaling factor = * 54 / 64 (32 / 38 * 64 = 53.9) */
701 REGS(be(0x30EE), be(0x1136)),
702 REGS(be(0x30FA), be(0xFD00)), /* GPIO0 = flash, GPIO1 = shutter */
703 REGS(be(0x3120), be(0x0005)), /* p1 dither enabled for 10bit mode */
704 REGS(be(0x3172), be(0x0206)), /* txlo clk divider options */
705 /* FDOC:fdoc settings with fdoc every frame turned of */
706 REGS(be(0x3180), be(0x9434)),
709 be(0x008B), /* 31B0: frame_preamble - FIXME check WRT lanes# */
710 be(0x0050)), /* 31B2: line_preamble - FIXME check WRT lanes# */
712 /* don't use continuous clock mode while shut down */
713 REGS(be(0x31BC), be(0x068C)),
714 REGS(be(0x31E0), be(0x0781)), /* Fuse/2DDC: enable 2ddc */
716 /* analog_setup_recommended_10bit */
717 REGS(be(0x341A), be(0x4735)), /* Samp&Hold pulse in ADC */
718 REGS(be(0x3420), be(0x4735)), /* Samp&Hold pulse in ADC */
719 REGS(be(0x3426), be(0x8A1A)), /* ADC offset distribution pulse */
720 REGS(be(0x342A), be(0x0018)), /* pulse_config */
722 /* pixel_timing_recommended */
724 /* 3D00 */ be(0x043E), be(0x4760), be(0xFFFF), be(0xFFFF),
725 /* 3D08 */ be(0x8000), be(0x0510), be(0xAF08), be(0x0252),
726 /* 3D10 */ be(0x486F), be(0x5D5D), be(0x8056), be(0x8313),
727 /* 3D18 */ be(0x0087), be(0x6A48), be(0x6982), be(0x0280),
728 /* 3D20 */ be(0x8359), be(0x8D02), be(0x8020), be(0x4882),
729 /* 3D28 */ be(0x4269), be(0x6A95), be(0x5988), be(0x5A83),
730 /* 3D30 */ be(0x5885), be(0x6280), be(0x6289), be(0x6097),
731 /* 3D38 */ be(0x5782), be(0x605C), be(0xBF18), be(0x0961),
732 /* 3D40 */ be(0x5080), be(0x2090), be(0x4390), be(0x4382),
733 /* 3D48 */ be(0x5F8A), be(0x5D5D), be(0x9C63), be(0x8063),
734 /* 3D50 */ be(0xA960), be(0x9757), be(0x8260), be(0x5CFF),
735 /* 3D58 */ be(0xBF10), be(0x1681), be(0x0802), be(0x8000),
736 /* 3D60 */ be(0x141C), be(0x6000), be(0x6022), be(0x4D80),
737 /* 3D68 */ be(0x5C97), be(0x6A69), be(0xAC6F), be(0x4645),
738 /* 3D70 */ be(0x4400), be(0x0513), be(0x8069), be(0x6AC6),
739 /* 3D78 */ be(0x5F95), be(0x5F70), be(0x8040), be(0x4A81),
740 /* 3D80 */ be(0x0300), be(0xE703), be(0x0088), be(0x4A83),
741 /* 3D88 */ be(0x40FF), be(0xFFFF), be(0xFD70), be(0x8040),
742 /* 3D90 */ be(0x4A85), be(0x4FA8), be(0x4F8C), be(0x0070),
743 /* 3D98 */ be(0xBE47), be(0x8847), be(0xBC78), be(0x6B89),
744 /* 3DA0 */ be(0x6A80), be(0x6986), be(0x6B8E), be(0x6B80),
745 /* 3DA8 */ be(0x6980), be(0x6A88), be(0x7C9F), be(0x866B),
746 /* 3DB0 */ be(0x8765), be(0x46FF), be(0xE365), be(0xA679),
747 /* 3DB8 */ be(0x4A40), be(0x4580), be(0x44BC), be(0x7000),
748 /* 3DC0 */ be(0x8040), be(0x0802), be(0x10EF), be(0x0104),
749 /* 3DC8 */ be(0x3860), be(0x5D5D), be(0x5682), be(0x1300),
750 /* 3DD0 */ be(0x8648), be(0x8202), be(0x8082), be(0x598A),
751 /* 3DD8 */ be(0x0280), be(0x2048), be(0x3060), be(0x8042),
752 /* 3DE0 */ be(0x9259), be(0x865A), be(0x8258), be(0x8562),
753 /* 3DE8 */ be(0x8062), be(0x8560), be(0x9257), be(0x8221),
754 /* 3DF0 */ be(0x10FF), be(0xB757), be(0x9361), be(0x1019),
755 /* 3DF8 */ be(0x8020), be(0x9043), be(0x8E43), be(0x845F),
756 /* 3E00 */ be(0x835D), be(0x805D), be(0x8163), be(0x8063),
757 /* 3E08 */ be(0xA060), be(0x9157), be(0x8260), be(0x5CFF),
758 /* 3E10 */ be(0xFFFF), be(0xFFE5), be(0x1016), be(0x2048),
759 /* 3E18 */ be(0x0802), be(0x1C60), be(0x0014), be(0x0060),
760 /* 3E20 */ be(0x2205), be(0x8120), be(0x908F), be(0x6A80),
761 /* 3E28 */ be(0x6982), be(0x5F9F), be(0x6F46), be(0x4544),
762 /* 3E30 */ be(0x0005), be(0x8013), be(0x8069), be(0x6A80),
763 /* 3E38 */ be(0x7000), be(0x0000), be(0x0000), be(0x0000),
764 /* 3E40 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
765 /* 3E48 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
766 /* 3E50 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
767 /* 3E58 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
768 /* 3E60 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
769 /* 3E68 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
770 /* 3E70 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
771 /* 3E78 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
772 /* 3E80 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
773 /* 3E88 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
774 /* 3E90 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
775 /* 3E98 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
776 /* 3EA0 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
777 /* 3EA8 */ be(0x0000), be(0x0000), be(0x0000), be(0x0000),
778 /* 3EB0 */ be(0x0000), be(0x0000), be(0x0000)),
780 REGS(be(0x3EB6), be(0x004C)), /* ECL */
783 be(0xAAAD), /* 3EBA */
784 be(0x0086)), /* 3EBC: Bias currents for FSC/ECL */
787 be(0x1E00), /* 3EC0: SFbin/SH mode settings */
788 be(0x100A), /* 3EC2: CLK divider for ramp for 10 bit 400MH */
789 /* 3EC4: FSC clamps for HDR mode and adc comp power down co */
791 be(0xEA44), /* 3EC6: VLN and clk gating controls */
792 be(0x6F6F), /* 3EC8: Txl0 and Txlo1 settings for normal mode */
793 be(0x2F4A), /* 3ECA: CDAC/Txlo2/RSTGHI/RSTGLO settings */
794 be(0x0506), /* 3ECC: RSTDHI/RSTDLO/CDAC/TXHI settings */
795 /* 3ECE: Ramp buffer settings and Booster enable (bits 0-5) */
797 be(0x13F0), /* 3ED0: TXLO from atest/sf bin settings */
798 be(0xA53D), /* 3ED2: Ramp offset */
799 be(0x862F), /* 3ED4: TXLO open loop/row driver settings */
800 be(0x4081), /* 3ED6: Txlatch fr cfpn rows/vln bias */
801 be(0x8003), /* 3ED8: Ramp step setting for 10 bit 400 Mhz */
802 be(0xA580), /* 3EDA: Ramp Offset */
803 be(0xC000), /* 3EDC: over range for rst and under range for sig */
804 be(0xC103)), /* 3EDE: over range for sig and col dec clk settings */
806 /* corrections_recommended_bayer */
808 be(0x0017), /* 3F00: BM_T0 */
809 be(0x02DD), /* 3F02: BM_T1 */
810 /* 3F04: if Ana_gain less than 2, use noise_floor0, multipl */
812 /* 3F06: if Ana_gain between 4 and 7, use noise_floor2 and */
814 /* 3F08: if Ana_gain between 4 and 7, use noise_floor2 and */
816 /* 3F0A: Define noise_floor0(low address) and noise_floor1 */
818 be(0x0302)), /* 3F0C: Define noise_floor2 and noise_floor3 */
821 be(0x0505), /* 3F10: single k factor 0 */
822 be(0x0505), /* 3F12: single k factor 1 */
823 be(0x0505), /* 3F14: single k factor 2 */
824 be(0x01FF), /* 3F16: cross factor 0 */
825 be(0x01FF), /* 3F18: cross factor 1 */
826 be(0x01FF), /* 3F1A: cross factor 2 */
827 be(0x0022)), /* 3F1E */
829 /* GTH_THRES_RTN: 4max,4min filtered out of every 46 samples and */
830 REGS(be(0x3F2C), be(0x442E)),
833 be(0x0000), /* 3F3E: Switch ADC from 12 bit to 10 bit mode */
834 be(0x1511), /* 3F40: couple k factor 0 */
835 be(0x1511), /* 3F42: couple k factor 1 */
836 be(0x0707)), /* 3F44: couple k factor 2 */
839 static int ar0521_power_off(struct device *dev)
841 struct v4l2_subdev *sd = dev_get_drvdata(dev);
842 struct ar0521_dev *sensor = to_ar0521_dev(sd);
845 clk_disable_unprepare(sensor->extclk);
847 if (sensor->reset_gpio)
848 gpiod_set_value(sensor->reset_gpio, 1); /* assert RESET signal */
850 for (i = ARRAY_SIZE(ar0521_supply_names) - 1; i >= 0; i--) {
851 if (sensor->supplies[i])
852 regulator_disable(sensor->supplies[i]);
857 static int ar0521_power_on(struct device *dev)
859 struct v4l2_subdev *sd = dev_get_drvdata(dev);
860 struct ar0521_dev *sensor = to_ar0521_dev(sd);
864 for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++)
865 if (sensor->supplies[cnt]) {
866 ret = regulator_enable(sensor->supplies[cnt]);
870 usleep_range(1000, 1500); /* min 1 ms */
873 ret = clk_prepare_enable(sensor->extclk);
875 v4l2_err(&sensor->sd, "error enabling sensor clock\n");
878 usleep_range(1000, 1500); /* min 1 ms */
880 if (sensor->reset_gpio)
881 /* deassert RESET signal */
882 gpiod_set_value(sensor->reset_gpio, 0);
883 usleep_range(4500, 5000); /* min 45000 clocks */
885 for (cnt = 0; cnt < ARRAY_SIZE(initial_regs); cnt++) {
886 ret = ar0521_write_regs(sensor, initial_regs[cnt].data,
887 initial_regs[cnt].count);
892 ret = ar0521_write_reg(sensor, AR0521_REG_SERIAL_FORMAT,
893 AR0521_REG_SERIAL_FORMAT_MIPI |
898 /* set MIPI test mode - disabled for now */
899 ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_TEST_MODE,
900 ((0x40 << sensor->lane_count) - 0x40) |
901 AR0521_REG_HISPI_TEST_MODE_LP11);
905 ret = ar0521_write_reg(sensor, AR0521_REG_ROW_SPEED, 0x110 |
906 4 / sensor->lane_count);
912 ar0521_power_off(dev);
916 static int ar0521_enum_mbus_code(struct v4l2_subdev *sd,
917 struct v4l2_subdev_state *sd_state,
918 struct v4l2_subdev_mbus_code_enum *code)
920 struct ar0521_dev *sensor = to_ar0521_dev(sd);
925 code->code = sensor->fmt.code;
929 static int ar0521_enum_frame_size(struct v4l2_subdev *sd,
930 struct v4l2_subdev_state *sd_state,
931 struct v4l2_subdev_frame_size_enum *fse)
936 if (fse->code != MEDIA_BUS_FMT_SGRBG8_1X8)
939 fse->min_width = AR0521_WIDTH_MIN;
940 fse->max_width = AR0521_WIDTH_MAX;
941 fse->min_height = AR0521_HEIGHT_MIN;
942 fse->max_height = AR0521_HEIGHT_MAX;
947 static int ar0521_pre_streamon(struct v4l2_subdev *sd, u32 flags)
949 struct ar0521_dev *sensor = to_ar0521_dev(sd);
952 if (!(flags & V4L2_SUBDEV_PRE_STREAMON_FL_MANUAL_LP))
955 ret = pm_runtime_resume_and_get(&sensor->i2c_client->dev);
959 /* Set LP-11 on clock and data lanes */
960 ret = ar0521_write_reg(sensor, AR0521_REG_HISPI_CONTROL_STATUS,
961 AR0521_REG_HISPI_CONTROL_STATUS_FRAMER_TEST_MODE_ENABLE);
965 /* Start streaming LP-11 */
966 ret = ar0521_write_reg(sensor, AR0521_REG_RESET,
967 AR0521_REG_RESET_DEFAULTS |
968 AR0521_REG_RESET_STREAM);
974 pm_runtime_put(&sensor->i2c_client->dev);
978 static int ar0521_post_streamoff(struct v4l2_subdev *sd)
980 struct ar0521_dev *sensor = to_ar0521_dev(sd);
982 pm_runtime_put(&sensor->i2c_client->dev);
986 static int ar0521_s_stream(struct v4l2_subdev *sd, int enable)
988 struct ar0521_dev *sensor = to_ar0521_dev(sd);
991 mutex_lock(&sensor->lock);
992 ret = ar0521_set_stream(sensor, enable);
993 mutex_unlock(&sensor->lock);
998 static const struct v4l2_subdev_core_ops ar0521_core_ops = {
999 .log_status = v4l2_ctrl_subdev_log_status,
1002 static const struct v4l2_subdev_video_ops ar0521_video_ops = {
1003 .s_stream = ar0521_s_stream,
1004 .pre_streamon = ar0521_pre_streamon,
1005 .post_streamoff = ar0521_post_streamoff,
1008 static const struct v4l2_subdev_pad_ops ar0521_pad_ops = {
1009 .enum_mbus_code = ar0521_enum_mbus_code,
1010 .enum_frame_size = ar0521_enum_frame_size,
1011 .get_fmt = ar0521_get_fmt,
1012 .set_fmt = ar0521_set_fmt,
1015 static const struct v4l2_subdev_ops ar0521_subdev_ops = {
1016 .core = &ar0521_core_ops,
1017 .video = &ar0521_video_ops,
1018 .pad = &ar0521_pad_ops,
1021 static int ar0521_probe(struct i2c_client *client)
1023 struct v4l2_fwnode_endpoint ep = {
1024 .bus_type = V4L2_MBUS_CSI2_DPHY
1026 struct device *dev = &client->dev;
1027 struct fwnode_handle *endpoint;
1028 struct ar0521_dev *sensor;
1032 sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
1036 sensor->i2c_client = client;
1037 sensor->fmt.width = AR0521_WIDTH_MAX;
1038 sensor->fmt.height = AR0521_HEIGHT_MAX;
1040 endpoint = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0,
1041 FWNODE_GRAPH_ENDPOINT_NEXT);
1043 dev_err(dev, "endpoint node not found\n");
1047 ret = v4l2_fwnode_endpoint_parse(endpoint, &ep);
1048 fwnode_handle_put(endpoint);
1050 dev_err(dev, "could not parse endpoint\n");
1054 if (ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
1055 dev_err(dev, "invalid bus type, must be MIPI CSI2\n");
1059 sensor->lane_count = ep.bus.mipi_csi2.num_data_lanes;
1060 switch (sensor->lane_count) {
1066 dev_err(dev, "invalid number of MIPI data lanes\n");
1070 /* Get master clock (extclk) */
1071 sensor->extclk = devm_clk_get(dev, "extclk");
1072 if (IS_ERR(sensor->extclk)) {
1073 dev_err(dev, "failed to get extclk\n");
1074 return PTR_ERR(sensor->extclk);
1077 sensor->extclk_freq = clk_get_rate(sensor->extclk);
1079 if (sensor->extclk_freq < AR0521_EXTCLK_MIN ||
1080 sensor->extclk_freq > AR0521_EXTCLK_MAX) {
1081 dev_err(dev, "extclk frequency out of range: %u Hz\n",
1082 sensor->extclk_freq);
1086 /* Request optional reset pin (usually active low) and assert it */
1087 sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1090 v4l2_i2c_subdev_init(&sensor->sd, client, &ar0521_subdev_ops);
1092 sensor->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1093 sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
1094 sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1095 ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
1099 for (cnt = 0; cnt < ARRAY_SIZE(ar0521_supply_names); cnt++) {
1100 struct regulator *supply = devm_regulator_get(dev,
1101 ar0521_supply_names[cnt]);
1103 if (IS_ERR(supply)) {
1104 dev_info(dev, "no %s regulator found: %li\n",
1105 ar0521_supply_names[cnt], PTR_ERR(supply));
1106 return PTR_ERR(supply);
1108 sensor->supplies[cnt] = supply;
1111 mutex_init(&sensor->lock);
1113 ret = ar0521_init_controls(sensor);
1115 goto entity_cleanup;
1117 ar0521_adj_fmt(&sensor->fmt);
1119 ret = v4l2_async_register_subdev(&sensor->sd);
1123 /* Turn on the device and enable runtime PM */
1124 ret = ar0521_power_on(&client->dev);
1127 pm_runtime_set_active(&client->dev);
1128 pm_runtime_enable(&client->dev);
1129 pm_runtime_idle(&client->dev);
1133 v4l2_async_unregister_subdev(&sensor->sd);
1134 media_entity_cleanup(&sensor->sd.entity);
1136 v4l2_ctrl_handler_free(&sensor->ctrls.handler);
1138 media_entity_cleanup(&sensor->sd.entity);
1139 mutex_destroy(&sensor->lock);
1143 static void ar0521_remove(struct i2c_client *client)
1145 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1146 struct ar0521_dev *sensor = to_ar0521_dev(sd);
1148 v4l2_async_unregister_subdev(&sensor->sd);
1149 media_entity_cleanup(&sensor->sd.entity);
1150 v4l2_ctrl_handler_free(&sensor->ctrls.handler);
1151 pm_runtime_disable(&client->dev);
1152 if (!pm_runtime_status_suspended(&client->dev))
1153 ar0521_power_off(&client->dev);
1154 pm_runtime_set_suspended(&client->dev);
1155 mutex_destroy(&sensor->lock);
1158 static const struct dev_pm_ops ar0521_pm_ops = {
1159 SET_RUNTIME_PM_OPS(ar0521_power_off, ar0521_power_on, NULL)
1161 static const struct of_device_id ar0521_dt_ids[] = {
1162 {.compatible = "onnn,ar0521"},
1165 MODULE_DEVICE_TABLE(of, ar0521_dt_ids);
1167 static struct i2c_driver ar0521_i2c_driver = {
1170 .pm = &ar0521_pm_ops,
1171 .of_match_table = ar0521_dt_ids,
1173 .probe = ar0521_probe,
1174 .remove = ar0521_remove,
1177 module_i2c_driver(ar0521_i2c_driver);
1179 MODULE_DESCRIPTION("AR0521 MIPI Camera subdev driver");
1180 MODULE_AUTHOR("Krzysztof Hałasa <khalasa@piap.pl>");
1181 MODULE_LICENSE("GPL");