2 * adv7842 - Analog Devices ADV7842 video decoder driver
4 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7842,
24 * Register Settings Recommendations, Rev. 1.9, April 2011
25 * REF_02 - Analog devices, Software User Guide, UG-206,
26 * ADV7842 I2C Register Maps, Rev. 0, November 2010
27 * REF_03 - Analog devices, Hardware User Guide, UG-214,
28 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
29 * Decoder and Digitizer , Rev. 0, January 2011
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/slab.h>
36 #include <linux/i2c.h>
37 #include <linux/delay.h>
38 #include <linux/videodev2.h>
39 #include <linux/workqueue.h>
40 #include <linux/v4l2-dv-timings.h>
41 #include <linux/hdmi.h>
42 #include <media/cec.h>
43 #include <media/v4l2-device.h>
44 #include <media/v4l2-event.h>
45 #include <media/v4l2-ctrls.h>
46 #include <media/v4l2-dv-timings.h>
47 #include <media/i2c/adv7842.h>
50 module_param(debug, int, 0644);
51 MODULE_PARM_DESC(debug, "debug level (0-2)");
53 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
54 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
55 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
56 MODULE_LICENSE("GPL");
58 /* ADV7842 system clock frequency */
59 #define ADV7842_fsc (28636360)
61 #define ADV7842_RGB_OUT (1 << 1)
63 #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0)
64 #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0)
65 #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0)
67 #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5)
68 #define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5)
69 #define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5)
70 #define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5)
71 #define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5)
72 #define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5)
74 #define ADV7842_OP_CH_SEL_GBR (0 << 5)
75 #define ADV7842_OP_CH_SEL_GRB (1 << 5)
76 #define ADV7842_OP_CH_SEL_BGR (2 << 5)
77 #define ADV7842_OP_CH_SEL_RGB (3 << 5)
78 #define ADV7842_OP_CH_SEL_BRG (4 << 5)
79 #define ADV7842_OP_CH_SEL_RBG (5 << 5)
81 #define ADV7842_OP_SWAP_CB_CR (1 << 0)
83 #define ADV7842_MAX_ADDRS (3)
86 **********************************************************************
88 * Arrays with configuration parameters for the ADV7842
90 **********************************************************************
93 struct adv7842_format_info {
101 struct adv7842_state {
102 struct adv7842_platform_data pdata;
103 struct v4l2_subdev sd;
104 struct media_pad pad;
105 struct v4l2_ctrl_handler hdl;
106 enum adv7842_mode mode;
107 struct v4l2_dv_timings timings;
108 enum adv7842_vid_std_select vid_std_select;
110 const struct adv7842_format_info *format;
121 struct v4l2_fract aspect_ratio;
122 u32 rgb_quantization_range;
124 struct delayed_work delayed_work_enable_hotplug;
125 bool restart_stdi_once;
129 struct i2c_client *i2c_sdp_io;
130 struct i2c_client *i2c_sdp;
131 struct i2c_client *i2c_cp;
132 struct i2c_client *i2c_vdp;
133 struct i2c_client *i2c_afe;
134 struct i2c_client *i2c_hdmi;
135 struct i2c_client *i2c_repeater;
136 struct i2c_client *i2c_edid;
137 struct i2c_client *i2c_infoframe;
138 struct i2c_client *i2c_cec;
139 struct i2c_client *i2c_avlink;
142 struct v4l2_ctrl *detect_tx_5v_ctrl;
143 struct v4l2_ctrl *analog_sampling_phase_ctrl;
144 struct v4l2_ctrl *free_run_color_ctrl_manual;
145 struct v4l2_ctrl *free_run_color_ctrl;
146 struct v4l2_ctrl *rgb_quantization_range_ctrl;
148 struct cec_adapter *cec_adap;
149 u8 cec_addr[ADV7842_MAX_ADDRS];
151 bool cec_enabled_adap;
154 /* Unsupported timings. This device cannot support 720p30. */
155 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
156 V4L2_DV_BT_CEA_1280X720P30,
160 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
164 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
165 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false))
170 struct adv7842_video_standards {
171 struct v4l2_dv_timings timings;
176 /* sorted by number of lines */
177 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
178 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
179 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
180 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
181 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
182 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
183 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
184 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
185 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
186 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
187 /* TODO add 1920x1080P60_RB (CVT timing) */
191 /* sorted by number of lines */
192 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
193 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
196 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
201 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
205 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
206 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
207 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
208 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
209 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
210 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
211 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
212 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
213 /* TODO add 1600X1200P60_RB (not a DMT timing) */
214 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
215 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
219 /* sorted by number of lines */
220 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
221 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
222 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
223 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
224 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
225 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
226 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
227 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
228 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
229 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
233 /* sorted by number of lines */
234 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
235 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
236 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
237 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
238 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
240 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
241 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
242 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
243 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
244 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
245 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
246 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
247 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
248 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
249 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
253 static const struct v4l2_event adv7842_ev_fmt = {
254 .type = V4L2_EVENT_SOURCE_CHANGE,
255 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
258 /* ----------------------------------------------------------------------- */
260 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
262 return container_of(sd, struct adv7842_state, sd);
265 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
267 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
270 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
272 return V4L2_DV_BT_BLANKING_WIDTH(t);
275 static inline unsigned htotal(const struct v4l2_bt_timings *t)
277 return V4L2_DV_BT_FRAME_WIDTH(t);
280 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
282 return V4L2_DV_BT_BLANKING_HEIGHT(t);
285 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
287 return V4L2_DV_BT_FRAME_HEIGHT(t);
291 /* ----------------------------------------------------------------------- */
293 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
294 u8 command, bool check)
296 union i2c_smbus_data data;
298 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
299 I2C_SMBUS_READ, command,
300 I2C_SMBUS_BYTE_DATA, &data))
303 v4l_err(client, "error reading %02x, %02x\n",
304 client->addr, command);
308 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
312 for (i = 0; i < 3; i++) {
313 int ret = adv_smbus_read_byte_data_check(client, command, true);
317 v4l_err(client, "read ok after %d retries\n", i);
321 v4l_err(client, "read failed\n");
325 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
326 u8 command, u8 value)
328 union i2c_smbus_data data;
333 for (i = 0; i < 3; i++) {
334 err = i2c_smbus_xfer(client->adapter, client->addr,
336 I2C_SMBUS_WRITE, command,
337 I2C_SMBUS_BYTE_DATA, &data);
342 v4l_err(client, "error writing %02x, %02x, %02x\n",
343 client->addr, command, value);
347 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
348 u8 command, u8 value)
350 union i2c_smbus_data data;
353 i2c_smbus_xfer(client->adapter, client->addr,
355 I2C_SMBUS_WRITE, command,
356 I2C_SMBUS_BYTE_DATA, &data);
359 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
360 u8 command, unsigned length, const u8 *values)
362 union i2c_smbus_data data;
364 if (length > I2C_SMBUS_BLOCK_MAX)
365 length = I2C_SMBUS_BLOCK_MAX;
366 data.block[0] = length;
367 memcpy(data.block + 1, values, length);
368 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
369 I2C_SMBUS_WRITE, command,
370 I2C_SMBUS_I2C_BLOCK_DATA, &data);
373 /* ----------------------------------------------------------------------- */
375 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
377 struct i2c_client *client = v4l2_get_subdevdata(sd);
379 return adv_smbus_read_byte_data(client, reg);
382 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
384 struct i2c_client *client = v4l2_get_subdevdata(sd);
386 return adv_smbus_write_byte_data(client, reg, val);
389 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
391 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
394 static inline int io_write_clr_set(struct v4l2_subdev *sd,
395 u8 reg, u8 mask, u8 val)
397 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
400 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
402 struct adv7842_state *state = to_state(sd);
404 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
407 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
409 struct adv7842_state *state = to_state(sd);
411 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
414 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
416 struct adv7842_state *state = to_state(sd);
418 return adv_smbus_read_byte_data(state->i2c_cec, reg);
421 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
423 struct adv7842_state *state = to_state(sd);
425 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
428 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
430 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
433 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
435 struct adv7842_state *state = to_state(sd);
437 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
440 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
442 struct adv7842_state *state = to_state(sd);
444 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
447 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
449 struct adv7842_state *state = to_state(sd);
451 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
454 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
456 struct adv7842_state *state = to_state(sd);
458 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
461 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
463 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
466 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
468 struct adv7842_state *state = to_state(sd);
470 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
473 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
475 struct adv7842_state *state = to_state(sd);
477 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
480 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
482 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
485 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
487 struct adv7842_state *state = to_state(sd);
489 return adv_smbus_read_byte_data(state->i2c_afe, reg);
492 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
494 struct adv7842_state *state = to_state(sd);
496 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
499 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
501 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
504 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
506 struct adv7842_state *state = to_state(sd);
508 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
511 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
513 struct adv7842_state *state = to_state(sd);
515 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
518 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
520 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
523 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
525 struct adv7842_state *state = to_state(sd);
527 return adv_smbus_read_byte_data(state->i2c_edid, reg);
530 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
532 struct adv7842_state *state = to_state(sd);
534 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
537 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
539 struct adv7842_state *state = to_state(sd);
541 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
544 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
546 struct adv7842_state *state = to_state(sd);
548 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
551 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
553 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
556 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
558 struct adv7842_state *state = to_state(sd);
560 return adv_smbus_read_byte_data(state->i2c_cp, reg);
563 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
565 struct adv7842_state *state = to_state(sd);
567 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
570 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
572 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
575 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
577 struct adv7842_state *state = to_state(sd);
579 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
582 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
584 struct adv7842_state *state = to_state(sd);
586 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
589 static void main_reset(struct v4l2_subdev *sd)
591 struct i2c_client *client = v4l2_get_subdevdata(sd);
593 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
595 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
600 /* -----------------------------------------------------------------------------
604 static const struct adv7842_format_info adv7842_formats[] = {
605 { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false,
606 ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT },
607 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false,
608 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
609 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true,
610 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
611 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false,
612 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
613 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true,
614 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
615 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false,
616 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
617 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true,
618 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
619 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false,
620 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
621 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true,
622 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
623 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false,
624 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
625 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true,
626 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
627 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false,
628 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
629 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true,
630 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
631 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false,
632 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
633 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true,
634 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
635 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false,
636 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
637 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true,
638 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
639 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false,
640 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
641 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true,
642 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
645 static const struct adv7842_format_info *
646 adv7842_format_info(struct adv7842_state *state, u32 code)
650 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) {
651 if (adv7842_formats[i].code == code)
652 return &adv7842_formats[i];
658 /* ----------------------------------------------------------------------- */
660 static inline bool is_analog_input(struct v4l2_subdev *sd)
662 struct adv7842_state *state = to_state(sd);
664 return ((state->mode == ADV7842_MODE_RGB) ||
665 (state->mode == ADV7842_MODE_COMP));
668 static inline bool is_digital_input(struct v4l2_subdev *sd)
670 struct adv7842_state *state = to_state(sd);
672 return state->mode == ADV7842_MODE_HDMI;
675 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
676 .type = V4L2_DV_BT_656_1120,
677 /* keep this initialization for compatibility with GCC < 4.4.6 */
679 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
680 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
681 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
682 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
683 V4L2_DV_BT_CAP_CUSTOM)
686 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
687 .type = V4L2_DV_BT_656_1120,
688 /* keep this initialization for compatibility with GCC < 4.4.6 */
690 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
691 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
692 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
693 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
694 V4L2_DV_BT_CAP_CUSTOM)
697 static inline const struct v4l2_dv_timings_cap *
698 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
700 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
701 &adv7842_timings_cap_analog;
704 /* ----------------------------------------------------------------------- */
706 static u16 adv7842_read_cable_det(struct v4l2_subdev *sd)
708 u8 reg = io_read(sd, 0x6f);
712 val |= 1; /* port A */
714 val |= 2; /* port B */
718 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
720 struct delayed_work *dwork = to_delayed_work(work);
721 struct adv7842_state *state = container_of(dwork,
722 struct adv7842_state, delayed_work_enable_hotplug);
723 struct v4l2_subdev *sd = &state->sd;
724 int present = state->hdmi_edid.present;
727 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
730 if (present & (0x04 << ADV7842_EDID_PORT_A))
732 if (present & (0x04 << ADV7842_EDID_PORT_B))
734 io_write_and_or(sd, 0x20, 0xcf, mask);
737 static int edid_write_vga_segment(struct v4l2_subdev *sd)
739 struct i2c_client *client = v4l2_get_subdevdata(sd);
740 struct adv7842_state *state = to_state(sd);
741 const u8 *val = state->vga_edid.edid;
745 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
747 /* HPA disable on port A and B */
748 io_write_and_or(sd, 0x20, 0xcf, 0x00);
750 /* Disable I2C access to internal EDID ram from VGA DDC port */
751 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
753 /* edid segment pointer '1' for VGA port */
754 rep_write_and_or(sd, 0x77, 0xef, 0x10);
756 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
757 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
758 I2C_SMBUS_BLOCK_MAX, val + i);
762 /* Calculates the checksums and enables I2C access
763 * to internal EDID ram from VGA DDC port.
765 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
767 for (i = 0; i < 1000; i++) {
768 if (rep_read(sd, 0x79) & 0x20)
773 v4l_err(client, "error enabling edid on VGA port\n");
777 /* enable hotplug after 200 ms */
778 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
783 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
785 struct i2c_client *client = v4l2_get_subdevdata(sd);
786 struct adv7842_state *state = to_state(sd);
787 const u8 *edid = state->hdmi_edid.edid;
793 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n",
794 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
796 /* HPA disable on port A and B */
797 io_write_and_or(sd, 0x20, 0xcf, 0x00);
799 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
800 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
802 if (!state->hdmi_edid.present) {
803 cec_phys_addr_invalidate(state->cec_adap);
807 pa = cec_get_edid_phys_addr(edid, 256, &spa_loc);
808 err = cec_phys_addr_validate(pa, &pa, NULL);
813 * Return an error if no location of the source physical address
819 /* edid segment pointer '0' for HDMI ports */
820 rep_write_and_or(sd, 0x77, 0xef, 0x00);
822 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
823 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
824 I2C_SMBUS_BLOCK_MAX, edid + i);
828 if (port == ADV7842_EDID_PORT_A) {
829 rep_write(sd, 0x72, edid[spa_loc]);
830 rep_write(sd, 0x73, edid[spa_loc + 1]);
832 rep_write(sd, 0x74, edid[spa_loc]);
833 rep_write(sd, 0x75, edid[spa_loc + 1]);
835 rep_write(sd, 0x76, spa_loc & 0xff);
836 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
838 /* Calculates the checksums and enables I2C access to internal
839 * EDID ram from HDMI DDC ports
841 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
843 for (i = 0; i < 1000; i++) {
844 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
849 v4l_err(client, "error enabling edid on port %c\n",
850 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
853 cec_s_phys_addr(state->cec_adap, pa, false);
855 /* enable hotplug after 200 ms */
856 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
861 /* ----------------------------------------------------------------------- */
863 #ifdef CONFIG_VIDEO_ADV_DEBUG
864 static void adv7842_inv_register(struct v4l2_subdev *sd)
866 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
867 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
868 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
869 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
870 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
871 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
872 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
873 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
874 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
875 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
876 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
877 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
880 static int adv7842_g_register(struct v4l2_subdev *sd,
881 struct v4l2_dbg_register *reg)
884 switch (reg->reg >> 8) {
886 reg->val = io_read(sd, reg->reg & 0xff);
889 reg->val = avlink_read(sd, reg->reg & 0xff);
892 reg->val = cec_read(sd, reg->reg & 0xff);
895 reg->val = infoframe_read(sd, reg->reg & 0xff);
898 reg->val = sdp_io_read(sd, reg->reg & 0xff);
901 reg->val = sdp_read(sd, reg->reg & 0xff);
904 reg->val = afe_read(sd, reg->reg & 0xff);
907 reg->val = rep_read(sd, reg->reg & 0xff);
910 reg->val = edid_read(sd, reg->reg & 0xff);
913 reg->val = hdmi_read(sd, reg->reg & 0xff);
916 reg->val = cp_read(sd, reg->reg & 0xff);
919 reg->val = vdp_read(sd, reg->reg & 0xff);
922 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
923 adv7842_inv_register(sd);
929 static int adv7842_s_register(struct v4l2_subdev *sd,
930 const struct v4l2_dbg_register *reg)
932 u8 val = reg->val & 0xff;
934 switch (reg->reg >> 8) {
936 io_write(sd, reg->reg & 0xff, val);
939 avlink_write(sd, reg->reg & 0xff, val);
942 cec_write(sd, reg->reg & 0xff, val);
945 infoframe_write(sd, reg->reg & 0xff, val);
948 sdp_io_write(sd, reg->reg & 0xff, val);
951 sdp_write(sd, reg->reg & 0xff, val);
954 afe_write(sd, reg->reg & 0xff, val);
957 rep_write(sd, reg->reg & 0xff, val);
960 edid_write(sd, reg->reg & 0xff, val);
963 hdmi_write(sd, reg->reg & 0xff, val);
966 cp_write(sd, reg->reg & 0xff, val);
969 vdp_write(sd, reg->reg & 0xff, val);
972 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
973 adv7842_inv_register(sd);
980 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
982 struct adv7842_state *state = to_state(sd);
983 u16 cable_det = adv7842_read_cable_det(sd);
985 v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det);
987 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
990 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
992 const struct adv7842_video_standards *predef_vid_timings,
993 const struct v4l2_dv_timings *timings)
997 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
998 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
999 is_digital_input(sd) ? 250000 : 1000000, false))
1002 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
1003 /* v_freq and prim mode */
1004 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
1011 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
1012 struct v4l2_dv_timings *timings)
1014 struct adv7842_state *state = to_state(sd);
1017 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1019 /* reset to default values */
1020 io_write(sd, 0x16, 0x43);
1021 io_write(sd, 0x17, 0x5a);
1022 /* disable embedded syncs for auto graphics mode */
1023 cp_write_and_or(sd, 0x81, 0xef, 0x00);
1024 cp_write(sd, 0x26, 0x00);
1025 cp_write(sd, 0x27, 0x00);
1026 cp_write(sd, 0x28, 0x00);
1027 cp_write(sd, 0x29, 0x00);
1028 cp_write(sd, 0x8f, 0x40);
1029 cp_write(sd, 0x90, 0x00);
1030 cp_write(sd, 0xa5, 0x00);
1031 cp_write(sd, 0xa6, 0x00);
1032 cp_write(sd, 0xa7, 0x00);
1033 cp_write(sd, 0xab, 0x00);
1034 cp_write(sd, 0xac, 0x00);
1036 switch (state->mode) {
1037 case ADV7842_MODE_COMP:
1038 case ADV7842_MODE_RGB:
1039 err = find_and_set_predefined_video_timings(sd,
1040 0x01, adv7842_prim_mode_comp, timings);
1042 err = find_and_set_predefined_video_timings(sd,
1043 0x02, adv7842_prim_mode_gr, timings);
1045 case ADV7842_MODE_HDMI:
1046 err = find_and_set_predefined_video_timings(sd,
1047 0x05, adv7842_prim_mode_hdmi_comp, timings);
1049 err = find_and_set_predefined_video_timings(sd,
1050 0x06, adv7842_prim_mode_hdmi_gr, timings);
1053 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1054 __func__, state->mode);
1063 static void configure_custom_video_timings(struct v4l2_subdev *sd,
1064 const struct v4l2_bt_timings *bt)
1066 struct adv7842_state *state = to_state(sd);
1067 struct i2c_client *client = v4l2_get_subdevdata(sd);
1068 u32 width = htotal(bt);
1069 u32 height = vtotal(bt);
1070 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1071 u16 cp_start_eav = width - bt->hfrontporch;
1072 u16 cp_start_vbi = height - bt->vfrontporch + 1;
1073 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
1074 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1075 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1077 0xc0 | ((width >> 8) & 0x1f),
1081 v4l2_dbg(2, debug, sd, "%s\n", __func__);
1083 switch (state->mode) {
1084 case ADV7842_MODE_COMP:
1085 case ADV7842_MODE_RGB:
1087 io_write(sd, 0x00, 0x07); /* video std */
1088 io_write(sd, 0x01, 0x02); /* prim mode */
1089 /* enable embedded syncs for auto graphics mode */
1090 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1092 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1093 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1094 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1095 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
1096 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1100 /* active video - horizontal timing */
1101 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1102 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1103 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1104 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1106 /* active video - vertical timing */
1107 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1108 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1109 ((cp_end_vbi >> 8) & 0xf));
1110 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1112 case ADV7842_MODE_HDMI:
1113 /* set default prim_mode/vid_std for HDMI
1114 according to [REF_03, c. 4.2] */
1115 io_write(sd, 0x00, 0x02); /* video std */
1116 io_write(sd, 0x01, 0x06); /* prim mode */
1119 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1120 __func__, state->mode);
1124 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1125 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1126 cp_write(sd, 0xab, (height >> 4) & 0xff);
1127 cp_write(sd, 0xac, (height & 0x0f) << 4);
1130 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1132 struct adv7842_state *state = to_state(sd);
1141 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1142 __func__, auto_offset ? "Auto" : "Manual",
1143 offset_a, offset_b, offset_c);
1145 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1146 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1147 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1148 offset_buf[3] = offset_c & 0x0ff;
1150 /* Registers must be written in this order with no i2c access in between */
1151 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
1152 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1155 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1157 struct adv7842_state *state = to_state(sd);
1160 u8 agc_mode_man = 1;
1170 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1171 __func__, auto_gain ? "Auto" : "Manual",
1172 gain_a, gain_b, gain_c);
1174 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1175 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1176 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1177 gain_buf[3] = ((gain_c & 0x0ff));
1179 /* Registers must be written in this order with no i2c access in between */
1180 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
1181 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1184 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1186 struct adv7842_state *state = to_state(sd);
1187 bool rgb_output = io_read(sd, 0x02) & 0x02;
1188 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1189 u8 y = HDMI_COLORSPACE_RGB;
1191 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1192 y = infoframe_read(sd, 0x01) >> 5;
1194 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1195 __func__, state->rgb_quantization_range,
1196 rgb_output, hdmi_signal);
1198 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
1199 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
1200 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1202 switch (state->rgb_quantization_range) {
1203 case V4L2_DV_RGB_RANGE_AUTO:
1204 if (state->mode == ADV7842_MODE_RGB) {
1205 /* Receiving analog RGB signal
1206 * Set RGB full range (0-255) */
1207 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1211 if (state->mode == ADV7842_MODE_COMP) {
1212 /* Receiving analog YPbPr signal
1214 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1219 /* Receiving HDMI signal
1221 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1225 /* Receiving DVI-D signal
1226 * ADV7842 selects RGB limited range regardless of
1227 * input format (CE/IT) in automatic mode */
1228 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1229 /* RGB limited range (16-235) */
1230 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1232 /* RGB full range (0-255) */
1233 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1235 if (is_digital_input(sd) && rgb_output) {
1236 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1238 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1239 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1243 case V4L2_DV_RGB_RANGE_LIMITED:
1244 if (state->mode == ADV7842_MODE_COMP) {
1245 /* YCrCb limited range (16-235) */
1246 io_write_and_or(sd, 0x02, 0x0f, 0x20);
1250 if (y != HDMI_COLORSPACE_RGB)
1253 /* RGB limited range (16-235) */
1254 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1257 case V4L2_DV_RGB_RANGE_FULL:
1258 if (state->mode == ADV7842_MODE_COMP) {
1259 /* YCrCb full range (0-255) */
1260 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1264 if (y != HDMI_COLORSPACE_RGB)
1267 /* RGB full range (0-255) */
1268 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1270 if (is_analog_input(sd) || hdmi_signal)
1273 /* Adjust gain/offset for DVI-D signals only */
1275 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1277 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1278 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1284 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1286 struct v4l2_subdev *sd = to_sd(ctrl);
1287 struct adv7842_state *state = to_state(sd);
1290 contrast/brightness/hue/free run is acting a bit strange,
1291 not sure if sdp csc is correct.
1294 /* standard ctrls */
1295 case V4L2_CID_BRIGHTNESS:
1296 cp_write(sd, 0x3c, ctrl->val);
1297 sdp_write(sd, 0x14, ctrl->val);
1298 /* ignore lsb sdp 0x17[3:2] */
1300 case V4L2_CID_CONTRAST:
1301 cp_write(sd, 0x3a, ctrl->val);
1302 sdp_write(sd, 0x13, ctrl->val);
1303 /* ignore lsb sdp 0x17[1:0] */
1305 case V4L2_CID_SATURATION:
1306 cp_write(sd, 0x3b, ctrl->val);
1307 sdp_write(sd, 0x15, ctrl->val);
1308 /* ignore lsb sdp 0x17[5:4] */
1311 cp_write(sd, 0x3d, ctrl->val);
1312 sdp_write(sd, 0x16, ctrl->val);
1313 /* ignore lsb sdp 0x17[7:6] */
1316 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1317 afe_write(sd, 0xc8, ctrl->val);
1319 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1320 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1321 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1323 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1324 u8 R = (ctrl->val & 0xff0000) >> 16;
1325 u8 G = (ctrl->val & 0x00ff00) >> 8;
1326 u8 B = (ctrl->val & 0x0000ff);
1327 /* RGB -> YUV, numerical approximation */
1328 int Y = 66 * R + 129 * G + 25 * B;
1329 int U = -38 * R - 74 * G + 112 * B;
1330 int V = 112 * R - 94 * G - 18 * B;
1332 /* Scale down to 8 bits with rounding */
1336 /* make U,V positive */
1341 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1342 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1345 cp_write(sd, 0xc1, R);
1346 cp_write(sd, 0xc0, G);
1347 cp_write(sd, 0xc2, B);
1349 sdp_write(sd, 0xde, Y);
1350 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1353 case V4L2_CID_DV_RX_RGB_RANGE:
1354 state->rgb_quantization_range = ctrl->val;
1355 set_rgb_quantization_range(sd);
1361 static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1363 struct v4l2_subdev *sd = to_sd(ctrl);
1365 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1366 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1367 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1368 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1374 static inline bool no_power(struct v4l2_subdev *sd)
1376 return io_read(sd, 0x0c) & 0x24;
1379 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1381 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1384 static inline bool is_hdmi(struct v4l2_subdev *sd)
1386 return hdmi_read(sd, 0x05) & 0x80;
1389 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1391 struct adv7842_state *state = to_state(sd);
1395 if (io_read(sd, 0x0c) & 0x24)
1396 *status |= V4L2_IN_ST_NO_POWER;
1398 if (state->mode == ADV7842_MODE_SDP) {
1399 /* status from SDP block */
1400 if (!(sdp_read(sd, 0x5A) & 0x01))
1401 *status |= V4L2_IN_ST_NO_SIGNAL;
1403 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1407 /* status from CP block */
1408 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1409 !(cp_read(sd, 0xb1) & 0x80))
1410 /* TODO channel 2 */
1411 *status |= V4L2_IN_ST_NO_SIGNAL;
1413 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1414 *status |= V4L2_IN_ST_NO_SIGNAL;
1416 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1422 struct stdi_readback {
1428 static int stdi2dv_timings(struct v4l2_subdev *sd,
1429 struct stdi_readback *stdi,
1430 struct v4l2_dv_timings *timings)
1432 struct adv7842_state *state = to_state(sd);
1433 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1437 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1438 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1440 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1441 adv7842_get_dv_timings_cap(sd),
1442 adv7842_check_dv_timings, NULL))
1444 if (vtotal(bt) != stdi->lcf + 1)
1446 if (bt->vsync != stdi->lcvs)
1449 pix_clk = hfreq * htotal(bt);
1451 if ((pix_clk < bt->pixelclock + 1000000) &&
1452 (pix_clk > bt->pixelclock - 1000000)) {
1453 *timings = v4l2_dv_timings_presets[i];
1458 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1459 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1460 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1463 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1464 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1465 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1466 false, state->aspect_ratio, timings))
1469 v4l2_dbg(2, debug, sd,
1470 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1471 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1472 stdi->hs_pol, stdi->vs_pol);
1476 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1480 adv7842_g_input_status(sd, &status);
1481 if (status & V4L2_IN_ST_NO_SIGNAL) {
1482 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1486 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1487 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1488 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1490 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1491 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1492 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1493 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1494 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1499 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1501 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1502 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1506 v4l2_dbg(2, debug, sd,
1507 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1508 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1509 stdi->hs_pol, stdi->vs_pol,
1510 stdi->interlaced ? "interlaced" : "progressive");
1515 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1516 struct v4l2_enum_dv_timings *timings)
1518 if (timings->pad != 0)
1521 return v4l2_enum_dv_timings_cap(timings,
1522 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1525 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1526 struct v4l2_dv_timings_cap *cap)
1531 *cap = *adv7842_get_dv_timings_cap(sd);
1535 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1536 if the format is listed in adv7842_timings[] */
1537 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1538 struct v4l2_dv_timings *timings)
1540 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1541 is_digital_input(sd) ? 250000 : 1000000,
1542 adv7842_check_dv_timings, NULL);
1545 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1546 struct v4l2_dv_timings *timings)
1548 struct adv7842_state *state = to_state(sd);
1549 struct v4l2_bt_timings *bt = &timings->bt;
1550 struct stdi_readback stdi = { 0 };
1552 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1554 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1557 if (state->mode == ADV7842_MODE_SDP)
1561 if (read_stdi(sd, &stdi)) {
1562 state->restart_stdi_once = true;
1563 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1566 bt->interlaced = stdi.interlaced ?
1567 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1568 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1569 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1571 if (is_digital_input(sd)) {
1574 timings->type = V4L2_DV_BT_656_1120;
1576 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1577 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1578 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
1579 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
1581 /* adjust for deep color mode */
1582 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
1584 bt->pixelclock = freq;
1585 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1586 hdmi_read(sd, 0x21);
1587 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1588 hdmi_read(sd, 0x23);
1589 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1590 hdmi_read(sd, 0x25);
1591 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1592 hdmi_read(sd, 0x2b)) / 2;
1593 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1594 hdmi_read(sd, 0x2f)) / 2;
1595 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1596 hdmi_read(sd, 0x33)) / 2;
1597 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1598 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1599 if (bt->interlaced == V4L2_DV_INTERLACED) {
1600 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1601 hdmi_read(sd, 0x0c);
1602 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1603 hdmi_read(sd, 0x2d)) / 2;
1604 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1605 hdmi_read(sd, 0x31)) / 2;
1606 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1607 hdmi_read(sd, 0x35)) / 2;
1609 bt->il_vfrontporch = 0;
1611 bt->il_vbackporch = 0;
1613 adv7842_fill_optional_dv_timings_fields(sd, timings);
1616 * Since LCVS values are inaccurate [REF_03, p. 339-340],
1617 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1619 if (!stdi2dv_timings(sd, &stdi, timings))
1622 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1623 if (!stdi2dv_timings(sd, &stdi, timings))
1626 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1627 if (stdi2dv_timings(sd, &stdi, timings)) {
1629 * The STDI block may measure wrong values, especially
1630 * for lcvs and lcf. If the driver can not find any
1631 * valid timing, the STDI block is restarted to measure
1632 * the video timings again. The function will return an
1633 * error, but the restart of STDI will generate a new
1634 * STDI interrupt and the format detection process will
1637 if (state->restart_stdi_once) {
1638 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1639 /* TODO restart STDI for Sync Channel 2 */
1640 /* enter one-shot mode */
1641 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1642 /* trigger STDI restart */
1643 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1644 /* reset to continuous mode */
1645 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1646 state->restart_stdi_once = false;
1649 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1652 state->restart_stdi_once = true;
1657 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1662 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1663 struct v4l2_dv_timings *timings)
1665 struct adv7842_state *state = to_state(sd);
1666 struct v4l2_bt_timings *bt;
1669 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1671 if (state->mode == ADV7842_MODE_SDP)
1674 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1675 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1681 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1682 adv7842_check_dv_timings, NULL))
1685 adv7842_fill_optional_dv_timings_fields(sd, timings);
1687 state->timings = *timings;
1689 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1691 /* Use prim_mode and vid_std when available */
1692 err = configure_predefined_video_timings(sd, timings);
1694 /* custom settings when the video format
1695 does not have prim_mode/vid_std */
1696 configure_custom_video_timings(sd, bt);
1699 set_rgb_quantization_range(sd);
1703 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1708 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1709 struct v4l2_dv_timings *timings)
1711 struct adv7842_state *state = to_state(sd);
1713 if (state->mode == ADV7842_MODE_SDP)
1715 *timings = state->timings;
1719 static void enable_input(struct v4l2_subdev *sd)
1721 struct adv7842_state *state = to_state(sd);
1723 set_rgb_quantization_range(sd);
1724 switch (state->mode) {
1725 case ADV7842_MODE_SDP:
1726 case ADV7842_MODE_COMP:
1727 case ADV7842_MODE_RGB:
1728 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1730 case ADV7842_MODE_HDMI:
1731 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1732 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1733 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1736 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1737 __func__, state->mode);
1742 static void disable_input(struct v4l2_subdev *sd)
1744 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1745 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
1746 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1747 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1750 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1751 const struct adv7842_sdp_csc_coeff *c)
1753 /* csc auto/manual */
1754 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1760 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1763 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1764 sdp_io_write(sd, 0xe1, c->A1);
1765 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1766 sdp_io_write(sd, 0xe3, c->A2);
1767 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1768 sdp_io_write(sd, 0xe5, c->A3);
1771 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1772 sdp_io_write(sd, 0xe7, c->A4);
1775 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1776 sdp_io_write(sd, 0xe9, c->B1);
1777 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1778 sdp_io_write(sd, 0xeb, c->B2);
1779 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1780 sdp_io_write(sd, 0xed, c->B3);
1783 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1784 sdp_io_write(sd, 0xef, c->B4);
1787 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1788 sdp_io_write(sd, 0xf1, c->C1);
1789 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1790 sdp_io_write(sd, 0xf3, c->C2);
1791 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1792 sdp_io_write(sd, 0xf5, c->C3);
1795 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1796 sdp_io_write(sd, 0xf7, c->C4);
1799 static void select_input(struct v4l2_subdev *sd,
1800 enum adv7842_vid_std_select vid_std_select)
1802 struct adv7842_state *state = to_state(sd);
1804 switch (state->mode) {
1805 case ADV7842_MODE_SDP:
1806 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1807 io_write(sd, 0x01, 0); /* prim mode */
1808 /* enable embedded syncs for auto graphics mode */
1809 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1811 afe_write(sd, 0x00, 0x00); /* power up ADC */
1812 afe_write(sd, 0xc8, 0x00); /* phase control */
1814 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1815 /* script says register 0xde, which don't exist in manual */
1817 /* Manual analog input muxing mode, CVBS (6.4)*/
1818 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1819 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1820 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1821 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1823 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1824 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1826 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1827 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1829 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1830 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1832 /* SDP recommended settings */
1833 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1834 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1836 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1837 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1838 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1839 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1840 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1841 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1842 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1844 /* deinterlacer enabled and 3D comb */
1845 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1849 case ADV7842_MODE_COMP:
1850 case ADV7842_MODE_RGB:
1851 /* Automatic analog input muxing mode */
1852 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1853 /* set mode and select free run resolution */
1854 io_write(sd, 0x00, vid_std_select); /* video std */
1855 io_write(sd, 0x01, 0x02); /* prim mode */
1856 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1857 for auto graphics mode */
1859 afe_write(sd, 0x00, 0x00); /* power up ADC */
1860 afe_write(sd, 0xc8, 0x00); /* phase control */
1861 if (state->mode == ADV7842_MODE_COMP) {
1862 /* force to YCrCb */
1863 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1866 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1869 /* set ADI recommended settings for digitizer */
1870 /* "ADV7842 Register Settings Recommendations
1871 * (rev. 1.8, November 2010)" p. 9. */
1872 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1873 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1875 /* set to default gain for RGB */
1876 cp_write(sd, 0x73, 0x10);
1877 cp_write(sd, 0x74, 0x04);
1878 cp_write(sd, 0x75, 0x01);
1879 cp_write(sd, 0x76, 0x00);
1881 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1882 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1883 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1886 case ADV7842_MODE_HDMI:
1887 /* Automatic analog input muxing mode */
1888 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1889 /* set mode and select free run resolution */
1890 if (state->hdmi_port_a)
1891 hdmi_write(sd, 0x00, 0x02); /* select port A */
1893 hdmi_write(sd, 0x00, 0x03); /* select port B */
1894 io_write(sd, 0x00, vid_std_select); /* video std */
1895 io_write(sd, 0x01, 5); /* prim mode */
1896 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1897 for auto graphics mode */
1899 /* set ADI recommended settings for HDMI: */
1900 /* "ADV7842 Register Settings Recommendations
1901 * (rev. 1.8, November 2010)" p. 3. */
1902 hdmi_write(sd, 0xc0, 0x00);
1903 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1904 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1905 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1906 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1907 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1908 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1909 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1910 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1911 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1912 Improve robustness */
1913 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1914 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1915 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1916 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1917 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1918 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1919 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1920 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1921 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1922 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1924 afe_write(sd, 0x00, 0xff); /* power down ADC */
1925 afe_write(sd, 0xc8, 0x40); /* phase control */
1927 /* set to default gain for HDMI */
1928 cp_write(sd, 0x73, 0x10);
1929 cp_write(sd, 0x74, 0x04);
1930 cp_write(sd, 0x75, 0x01);
1931 cp_write(sd, 0x76, 0x00);
1933 /* reset ADI recommended settings for digitizer */
1934 /* "ADV7842 Register Settings Recommendations
1935 * (rev. 2.5, June 2010)" p. 17. */
1936 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1937 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1938 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1940 /* CP coast control */
1941 cp_write(sd, 0xc3, 0x33); /* Component mode */
1943 /* color space conversion, autodetect color space */
1944 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1948 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1949 __func__, state->mode);
1954 static int adv7842_s_routing(struct v4l2_subdev *sd,
1955 u32 input, u32 output, u32 config)
1957 struct adv7842_state *state = to_state(sd);
1959 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1962 case ADV7842_SELECT_HDMI_PORT_A:
1963 state->mode = ADV7842_MODE_HDMI;
1964 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1965 state->hdmi_port_a = true;
1967 case ADV7842_SELECT_HDMI_PORT_B:
1968 state->mode = ADV7842_MODE_HDMI;
1969 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1970 state->hdmi_port_a = false;
1972 case ADV7842_SELECT_VGA_COMP:
1973 state->mode = ADV7842_MODE_COMP;
1974 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1976 case ADV7842_SELECT_VGA_RGB:
1977 state->mode = ADV7842_MODE_RGB;
1978 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1980 case ADV7842_SELECT_SDP_CVBS:
1981 state->mode = ADV7842_MODE_SDP;
1982 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1984 case ADV7842_SELECT_SDP_YC:
1985 state->mode = ADV7842_MODE_SDP;
1986 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1993 select_input(sd, state->vid_std_select);
1996 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
2001 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,
2002 struct v4l2_subdev_pad_config *cfg,
2003 struct v4l2_subdev_mbus_code_enum *code)
2005 if (code->index >= ARRAY_SIZE(adv7842_formats))
2007 code->code = adv7842_formats[code->index].code;
2011 static void adv7842_fill_format(struct adv7842_state *state,
2012 struct v4l2_mbus_framefmt *format)
2014 memset(format, 0, sizeof(*format));
2016 format->width = state->timings.bt.width;
2017 format->height = state->timings.bt.height;
2018 format->field = V4L2_FIELD_NONE;
2019 format->colorspace = V4L2_COLORSPACE_SRGB;
2021 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
2022 format->colorspace = (state->timings.bt.height <= 576) ?
2023 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
2027 * Compute the op_ch_sel value required to obtain on the bus the component order
2028 * corresponding to the selected format taking into account bus reordering
2029 * applied by the board at the output of the device.
2031 * The following table gives the op_ch_value from the format component order
2032 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
2033 * adv7842_bus_order value in row).
2035 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
2036 * ----------+-------------------------------------------------
2037 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
2038 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
2039 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
2040 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
2041 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
2042 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
2044 static unsigned int adv7842_op_ch_sel(struct adv7842_state *state)
2046 #define _SEL(a, b, c, d, e, f) { \
2047 ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \
2048 ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f }
2049 #define _BUS(x) [ADV7842_BUS_ORDER_##x]
2051 static const unsigned int op_ch_sel[6][6] = {
2052 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
2053 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
2054 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
2055 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
2056 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
2057 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
2060 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
2063 static void adv7842_setup_format(struct adv7842_state *state)
2065 struct v4l2_subdev *sd = &state->sd;
2067 io_write_clr_set(sd, 0x02, 0x02,
2068 state->format->rgb_out ? ADV7842_RGB_OUT : 0);
2069 io_write(sd, 0x03, state->format->op_format_sel |
2070 state->pdata.op_format_mode_sel);
2071 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));
2072 io_write_clr_set(sd, 0x05, 0x01,
2073 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0);
2074 set_rgb_quantization_range(sd);
2077 static int adv7842_get_format(struct v4l2_subdev *sd,
2078 struct v4l2_subdev_pad_config *cfg,
2079 struct v4l2_subdev_format *format)
2081 struct adv7842_state *state = to_state(sd);
2083 if (format->pad != ADV7842_PAD_SOURCE)
2086 if (state->mode == ADV7842_MODE_SDP) {
2088 if (!(sdp_read(sd, 0x5a) & 0x01))
2090 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8;
2091 format->format.width = 720;
2093 if (state->norm & V4L2_STD_525_60)
2094 format->format.height = 480;
2096 format->format.height = 576;
2097 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
2101 adv7842_fill_format(state, &format->format);
2103 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2104 struct v4l2_mbus_framefmt *fmt;
2106 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2107 format->format.code = fmt->code;
2109 format->format.code = state->format->code;
2115 static int adv7842_set_format(struct v4l2_subdev *sd,
2116 struct v4l2_subdev_pad_config *cfg,
2117 struct v4l2_subdev_format *format)
2119 struct adv7842_state *state = to_state(sd);
2120 const struct adv7842_format_info *info;
2122 if (format->pad != ADV7842_PAD_SOURCE)
2125 if (state->mode == ADV7842_MODE_SDP)
2126 return adv7842_get_format(sd, cfg, format);
2128 info = adv7842_format_info(state, format->format.code);
2130 info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2132 adv7842_fill_format(state, &format->format);
2133 format->format.code = info->code;
2135 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2136 struct v4l2_mbus_framefmt *fmt;
2138 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2139 fmt->code = format->format.code;
2141 state->format = info;
2142 adv7842_setup_format(state);
2148 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
2151 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
2152 io_write(sd, 0x46, 0x9c);
2153 /* ESDP_50HZ_DET interrupt */
2154 io_write(sd, 0x5a, 0x10);
2155 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
2156 io_write(sd, 0x73, 0x03);
2157 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2158 io_write(sd, 0x78, 0x03);
2159 /* Enable SDP Standard Detection Change and SDP Video Detected */
2160 io_write(sd, 0xa0, 0x09);
2161 /* Enable HDMI_MODE interrupt */
2162 io_write(sd, 0x69, 0x08);
2164 io_write(sd, 0x46, 0x0);
2165 io_write(sd, 0x5a, 0x0);
2166 io_write(sd, 0x73, 0x0);
2167 io_write(sd, 0x78, 0x0);
2168 io_write(sd, 0xa0, 0x0);
2169 io_write(sd, 0x69, 0x0);
2173 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
2174 static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
2176 struct adv7842_state *state = to_state(sd);
2178 if ((cec_read(sd, 0x11) & 0x01) == 0) {
2179 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
2183 if (tx_raw_status & 0x02) {
2184 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
2186 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
2190 if (tx_raw_status & 0x04) {
2195 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
2197 * We set this status bit since this hardware performs
2200 status = CEC_TX_STATUS_MAX_RETRIES;
2201 nack_cnt = cec_read(sd, 0x14) & 0xf;
2203 status |= CEC_TX_STATUS_NACK;
2204 low_drive_cnt = cec_read(sd, 0x14) >> 4;
2206 status |= CEC_TX_STATUS_LOW_DRIVE;
2207 cec_transmit_done(state->cec_adap, status,
2208 0, nack_cnt, low_drive_cnt, 0);
2211 if (tx_raw_status & 0x01) {
2212 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2213 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
2218 static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled)
2222 /* cec controller */
2223 cec_irq = io_read(sd, 0x93) & 0x0f;
2227 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2228 adv7842_cec_tx_raw_status(sd, cec_irq);
2229 if (cec_irq & 0x08) {
2230 struct adv7842_state *state = to_state(sd);
2233 msg.len = cec_read(sd, 0x25) & 0x1f;
2240 for (i = 0; i < msg.len; i++)
2241 msg.msg[i] = cec_read(sd, i + 0x15);
2242 cec_write(sd, 0x26, 0x01); /* re-enable rx */
2243 cec_received_msg(state->cec_adap, &msg);
2247 io_write(sd, 0x94, cec_irq);
2253 static int adv7842_cec_adap_enable(struct cec_adapter *adap, bool enable)
2255 struct adv7842_state *state = cec_get_drvdata(adap);
2256 struct v4l2_subdev *sd = &state->sd;
2258 if (!state->cec_enabled_adap && enable) {
2259 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2260 cec_write(sd, 0x2c, 0x01); /* cec soft reset */
2261 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2264 /* tx: arbitration lost */
2265 /* tx: retry timeout */
2267 io_write_clr_set(sd, 0x96, 0x0f, 0x0f);
2268 cec_write(sd, 0x26, 0x01); /* enable rx */
2269 } else if (state->cec_enabled_adap && !enable) {
2270 /* disable cec interrupts */
2271 io_write_clr_set(sd, 0x96, 0x0f, 0x00);
2272 /* disable address mask 1-3 */
2273 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2274 /* power down cec section */
2275 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2276 state->cec_valid_addrs = 0;
2278 state->cec_enabled_adap = enable;
2282 static int adv7842_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2284 struct adv7842_state *state = cec_get_drvdata(adap);
2285 struct v4l2_subdev *sd = &state->sd;
2286 unsigned int i, free_idx = ADV7842_MAX_ADDRS;
2288 if (!state->cec_enabled_adap)
2289 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2291 if (addr == CEC_LOG_ADDR_INVALID) {
2292 cec_write_clr_set(sd, 0x27, 0x70, 0);
2293 state->cec_valid_addrs = 0;
2297 for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
2298 bool is_valid = state->cec_valid_addrs & (1 << i);
2300 if (free_idx == ADV7842_MAX_ADDRS && !is_valid)
2302 if (is_valid && state->cec_addr[i] == addr)
2305 if (i == ADV7842_MAX_ADDRS) {
2307 if (i == ADV7842_MAX_ADDRS)
2310 state->cec_addr[i] = addr;
2311 state->cec_valid_addrs |= 1 << i;
2315 /* enable address mask 0 */
2316 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2317 /* set address for mask 0 */
2318 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2321 /* enable address mask 1 */
2322 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2323 /* set address for mask 1 */
2324 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2327 /* enable address mask 2 */
2328 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2329 /* set address for mask 1 */
2330 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2336 static int adv7842_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2337 u32 signal_free_time, struct cec_msg *msg)
2339 struct adv7842_state *state = cec_get_drvdata(adap);
2340 struct v4l2_subdev *sd = &state->sd;
2345 * The number of retries is the number of attempts - 1, but retry
2346 * at least once. It's not clear if a value of 0 is allowed, so
2347 * let's do at least one retry.
2349 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2352 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2357 for (i = 0; i < len; i++)
2358 cec_write(sd, i, msg->msg[i]);
2360 /* set length (data + header) */
2361 cec_write(sd, 0x10, len);
2362 /* start transmit, enable tx */
2363 cec_write(sd, 0x11, 0x01);
2367 static const struct cec_adap_ops adv7842_cec_adap_ops = {
2368 .adap_enable = adv7842_cec_adap_enable,
2369 .adap_log_addr = adv7842_cec_adap_log_addr,
2370 .adap_transmit = adv7842_cec_adap_transmit,
2374 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2376 struct adv7842_state *state = to_state(sd);
2377 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
2380 adv7842_irq_enable(sd, false);
2383 irq_status[0] = io_read(sd, 0x43);
2384 irq_status[1] = io_read(sd, 0x57);
2385 irq_status[2] = io_read(sd, 0x70);
2386 irq_status[3] = io_read(sd, 0x75);
2387 irq_status[4] = io_read(sd, 0x9d);
2388 irq_status[5] = io_read(sd, 0x66);
2392 io_write(sd, 0x44, irq_status[0]);
2394 io_write(sd, 0x58, irq_status[1]);
2396 io_write(sd, 0x71, irq_status[2]);
2398 io_write(sd, 0x76, irq_status[3]);
2400 io_write(sd, 0x9e, irq_status[4]);
2402 io_write(sd, 0x67, irq_status[5]);
2404 adv7842_irq_enable(sd, true);
2406 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
2407 irq_status[0], irq_status[1], irq_status[2],
2408 irq_status[3], irq_status[4], irq_status[5]);
2410 /* format change CP */
2411 fmt_change_cp = irq_status[0] & 0x9c;
2413 /* format change SDP */
2414 if (state->mode == ADV7842_MODE_SDP)
2415 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
2419 /* digital format CP */
2420 if (is_digital_input(sd))
2421 fmt_change_digital = irq_status[3] & 0x03;
2423 fmt_change_digital = 0;
2426 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
2427 v4l2_dbg(1, debug, sd,
2428 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
2429 __func__, fmt_change_cp, fmt_change_digital,
2431 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
2437 if (irq_status[5] & 0x08) {
2438 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2439 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
2440 set_rgb_quantization_range(sd);
2445 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
2447 adv7842_cec_isr(sd, handled);
2451 if (irq_status[2] & 0x3) {
2452 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
2453 adv7842_s_detect_tx_5v_ctrl(sd);
2460 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2462 struct adv7842_state *state = to_state(sd);
2465 memset(edid->reserved, 0, sizeof(edid->reserved));
2467 switch (edid->pad) {
2468 case ADV7842_EDID_PORT_A:
2469 case ADV7842_EDID_PORT_B:
2470 if (state->hdmi_edid.present & (0x04 << edid->pad))
2471 data = state->hdmi_edid.edid;
2473 case ADV7842_EDID_PORT_VGA:
2474 if (state->vga_edid.present)
2475 data = state->vga_edid.edid;
2481 if (edid->start_block == 0 && edid->blocks == 0) {
2482 edid->blocks = data ? 2 : 0;
2489 if (edid->start_block >= 2)
2492 if (edid->start_block + edid->blocks > 2)
2493 edid->blocks = 2 - edid->start_block;
2495 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2500 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
2502 struct adv7842_state *state = to_state(sd);
2505 memset(e->reserved, 0, sizeof(e->reserved));
2507 if (e->pad > ADV7842_EDID_PORT_VGA)
2509 if (e->start_block != 0)
2511 if (e->blocks > 2) {
2516 /* todo, per edid */
2517 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
2521 case ADV7842_EDID_PORT_VGA:
2522 memset(&state->vga_edid.edid, 0, 256);
2523 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
2524 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
2525 err = edid_write_vga_segment(sd);
2527 case ADV7842_EDID_PORT_A:
2528 case ADV7842_EDID_PORT_B:
2529 memset(&state->hdmi_edid.edid, 0, 256);
2531 state->hdmi_edid.present |= 0x04 << e->pad;
2533 state->hdmi_edid.present &= ~(0x04 << e->pad);
2534 adv7842_s_detect_tx_5v_ctrl(sd);
2536 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
2537 err = edid_write_hdmi_segment(sd, e->pad);
2543 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2547 struct adv7842_cfg_read_infoframe {
2554 static void log_infoframe(struct v4l2_subdev *sd, struct adv7842_cfg_read_infoframe *cri)
2558 union hdmi_infoframe frame;
2560 struct i2c_client *client = v4l2_get_subdevdata(sd);
2561 struct device *dev = &client->dev;
2563 if (!(io_read(sd, 0x60) & cri->present_mask)) {
2564 v4l2_info(sd, "%s infoframe not received\n", cri->desc);
2568 for (i = 0; i < 3; i++)
2569 buffer[i] = infoframe_read(sd, cri->head_addr + i);
2571 len = buffer[2] + 1;
2573 if (len + 3 > sizeof(buffer)) {
2574 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
2578 for (i = 0; i < len; i++)
2579 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);
2581 if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
2582 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
2586 hdmi_infoframe_log(KERN_INFO, dev, &frame);
2589 static void adv7842_log_infoframes(struct v4l2_subdev *sd)
2592 struct adv7842_cfg_read_infoframe cri[] = {
2593 { "AVI", 0x01, 0xe0, 0x00 },
2594 { "Audio", 0x02, 0xe3, 0x1c },
2595 { "SDP", 0x04, 0xe6, 0x2a },
2596 { "Vendor", 0x10, 0xec, 0x54 }
2599 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2600 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2604 for (i = 0; i < ARRAY_SIZE(cri); i++)
2605 log_infoframe(sd, &cri[i]);
2609 /* Let's keep it here for now, as it could be useful for debug */
2610 static const char * const prim_mode_txt[] = {
2615 "CVBS & HDMI AUDIO",
2630 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2632 /* SDP (Standard definition processor) block */
2633 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2635 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2636 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2637 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2639 v4l2_info(sd, "SDP: free run: %s\n",
2640 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2641 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2642 "valid SD/PR signal detected" : "invalid/no signal");
2643 if (sdp_signal_detected) {
2644 static const char * const sdp_std_txt[] = {
2652 "7?", "8?", "9?", "a?", "b?",
2658 v4l2_info(sd, "SDP: standard %s\n",
2659 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2660 v4l2_info(sd, "SDP: %s\n",
2661 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2662 v4l2_info(sd, "SDP: %s\n",
2663 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2664 v4l2_info(sd, "SDP: deinterlacer %s\n",
2665 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2666 v4l2_info(sd, "SDP: csc %s mode\n",
2667 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2672 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2675 struct adv7842_state *state = to_state(sd);
2676 struct v4l2_dv_timings timings;
2677 u8 reg_io_0x02 = io_read(sd, 0x02);
2678 u8 reg_io_0x21 = io_read(sd, 0x21);
2679 u8 reg_rep_0x77 = rep_read(sd, 0x77);
2680 u8 reg_rep_0x7d = rep_read(sd, 0x7d);
2681 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2682 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2683 bool audio_mute = io_read(sd, 0x65) & 0x40;
2685 static const char * const csc_coeff_sel_rb[16] = {
2686 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2687 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2688 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2689 "reserved", "reserved", "reserved", "reserved", "manual"
2691 static const char * const input_color_space_txt[16] = {
2692 "RGB limited range (16-235)", "RGB full range (0-255)",
2693 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2694 "xvYCC Bt.601", "xvYCC Bt.709",
2695 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2696 "invalid", "invalid", "invalid", "invalid", "invalid",
2697 "invalid", "invalid", "automatic"
2699 static const char * const rgb_quantization_range_txt[] = {
2701 "RGB limited range (16-235)",
2702 "RGB full range (0-255)",
2704 static const char * const deep_color_mode_txt[4] = {
2705 "8-bits per channel",
2706 "10-bits per channel",
2707 "12-bits per channel",
2708 "16-bits per channel (not supported)"
2711 v4l2_info(sd, "-----Chip status-----\n");
2712 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2713 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2714 state->hdmi_port_a ? "A" : "B");
2715 v4l2_info(sd, "EDID A %s, B %s\n",
2716 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2717 "enabled" : "disabled",
2718 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2719 "enabled" : "disabled");
2720 v4l2_info(sd, "HPD A %s, B %s\n",
2721 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2722 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2723 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2724 "enabled" : "disabled");
2725 if (state->cec_enabled_adap) {
2728 for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
2729 bool is_valid = state->cec_valid_addrs & (1 << i);
2732 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2733 state->cec_addr[i]);
2737 v4l2_info(sd, "-----Signal status-----\n");
2738 if (state->hdmi_port_a) {
2739 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2740 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2741 v4l2_info(sd, "TMDS signal detected: %s\n",
2742 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2743 v4l2_info(sd, "TMDS signal locked: %s\n",
2744 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2746 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2747 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2748 v4l2_info(sd, "TMDS signal detected: %s\n",
2749 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2750 v4l2_info(sd, "TMDS signal locked: %s\n",
2751 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2753 v4l2_info(sd, "CP free run: %s\n",
2754 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2755 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2756 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2757 (io_read(sd, 0x01) & 0x70) >> 4);
2759 v4l2_info(sd, "-----Video Timings-----\n");
2760 if (no_cp_signal(sd)) {
2761 v4l2_info(sd, "STDI: not locked\n");
2763 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2764 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2765 u32 lcvs = cp_read(sd, 0xb3) >> 3;
2766 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2767 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2768 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2769 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2770 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2772 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2774 (cp_read(sd, 0xb1) & 0x40) ?
2775 "interlaced" : "progressive",
2778 if (adv7842_query_dv_timings(sd, &timings))
2779 v4l2_info(sd, "No video detected\n");
2781 v4l2_print_dv_timings(sd->name, "Detected format: ",
2783 v4l2_print_dv_timings(sd->name, "Configured format: ",
2784 &state->timings, true);
2786 if (no_cp_signal(sd))
2789 v4l2_info(sd, "-----Color space-----\n");
2790 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2791 rgb_quantization_range_txt[state->rgb_quantization_range]);
2792 v4l2_info(sd, "Input color space: %s\n",
2793 input_color_space_txt[reg_io_0x02 >> 4]);
2794 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2795 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2796 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2797 "(16-235)" : "(0-255)",
2798 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2799 v4l2_info(sd, "Color space conversion: %s\n",
2800 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2802 if (!is_digital_input(sd))
2805 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2806 v4l2_info(sd, "HDCP encrypted content: %s\n",
2807 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2808 v4l2_info(sd, "HDCP keys read: %s%s\n",
2809 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2810 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2814 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2815 audio_pll_locked ? "locked" : "not locked",
2816 audio_sample_packet_detect ? "detected" : "not detected",
2817 audio_mute ? "muted" : "enabled");
2818 if (audio_pll_locked && audio_sample_packet_detect) {
2819 v4l2_info(sd, "Audio format: %s\n",
2820 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2822 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2823 (hdmi_read(sd, 0x5c) << 8) +
2824 (hdmi_read(sd, 0x5d) & 0xf0));
2825 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2826 (hdmi_read(sd, 0x5e) << 8) +
2827 hdmi_read(sd, 0x5f));
2828 v4l2_info(sd, "AV Mute: %s\n",
2829 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2830 v4l2_info(sd, "Deep color mode: %s\n",
2831 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2833 adv7842_log_infoframes(sd);
2838 static int adv7842_log_status(struct v4l2_subdev *sd)
2840 struct adv7842_state *state = to_state(sd);
2842 if (state->mode == ADV7842_MODE_SDP)
2843 return adv7842_sdp_log_status(sd);
2844 return adv7842_cp_log_status(sd);
2847 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2849 struct adv7842_state *state = to_state(sd);
2851 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2853 if (state->mode != ADV7842_MODE_SDP)
2856 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2858 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2862 switch (sdp_read(sd, 0x52) & 0x0f) {
2865 *std &= V4L2_STD_NTSC;
2869 *std &= V4L2_STD_NTSC_443;
2873 *std &= V4L2_STD_SECAM;
2877 *std &= V4L2_STD_PAL_M;
2881 *std &= V4L2_STD_PAL_60;
2885 *std &= V4L2_STD_PAL_Nc;
2889 *std &= V4L2_STD_PAL;
2893 *std &= V4L2_STD_SECAM;
2896 *std &= V4L2_STD_ALL;
2902 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2904 if (s && s->adjust) {
2905 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2906 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2907 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2908 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2909 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2910 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2911 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2912 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2913 sdp_io_write(sd, 0xa8, s->vs_beg_o);
2914 sdp_io_write(sd, 0xa9, s->vs_beg_e);
2915 sdp_io_write(sd, 0xaa, s->vs_end_o);
2916 sdp_io_write(sd, 0xab, s->vs_end_e);
2917 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2918 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2919 sdp_io_write(sd, 0xae, s->de_v_end_o);
2920 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2922 /* set to default */
2923 sdp_io_write(sd, 0x94, 0x00);
2924 sdp_io_write(sd, 0x95, 0x00);
2925 sdp_io_write(sd, 0x96, 0x00);
2926 sdp_io_write(sd, 0x97, 0x20);
2927 sdp_io_write(sd, 0x98, 0x00);
2928 sdp_io_write(sd, 0x99, 0x00);
2929 sdp_io_write(sd, 0x9a, 0x00);
2930 sdp_io_write(sd, 0x9b, 0x00);
2931 sdp_io_write(sd, 0xa8, 0x04);
2932 sdp_io_write(sd, 0xa9, 0x04);
2933 sdp_io_write(sd, 0xaa, 0x04);
2934 sdp_io_write(sd, 0xab, 0x04);
2935 sdp_io_write(sd, 0xac, 0x04);
2936 sdp_io_write(sd, 0xad, 0x04);
2937 sdp_io_write(sd, 0xae, 0x04);
2938 sdp_io_write(sd, 0xaf, 0x04);
2942 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2944 struct adv7842_state *state = to_state(sd);
2945 struct adv7842_platform_data *pdata = &state->pdata;
2947 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2949 if (state->mode != ADV7842_MODE_SDP)
2952 if (norm & V4L2_STD_625_50)
2953 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2954 else if (norm & V4L2_STD_525_60)
2955 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2957 adv7842_s_sdp_io(sd, NULL);
2959 if (norm & V4L2_STD_ALL) {
2966 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2968 struct adv7842_state *state = to_state(sd);
2970 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2972 if (state->mode != ADV7842_MODE_SDP)
2975 *norm = state->norm;
2979 /* ----------------------------------------------------------------------- */
2981 static int adv7842_core_init(struct v4l2_subdev *sd)
2983 struct adv7842_state *state = to_state(sd);
2984 struct adv7842_platform_data *pdata = &state->pdata;
2985 hdmi_write(sd, 0x48,
2986 (pdata->disable_pwrdnb ? 0x80 : 0) |
2987 (pdata->disable_cable_det_rst ? 0x40 : 0));
2992 * Disable I2C access to internal EDID ram from HDMI DDC ports
2993 * Disable auto edid enable when leaving powerdown mode
2995 rep_write_and_or(sd, 0x77, 0xd3, 0x20);
2998 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2999 io_write(sd, 0x15, 0x80); /* Power up pads */
3002 io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3);
3003 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
3004 pdata->insert_av_codes << 2 |
3005 pdata->replicate_av_codes << 1);
3006 adv7842_setup_format(state);
3009 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
3011 /* Drive strength */
3012 io_write_and_or(sd, 0x14, 0xc0,
3013 pdata->dr_str_data << 4 |
3014 pdata->dr_str_clk << 2 |
3015 pdata->dr_str_sync);
3018 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
3019 (pdata->hdmi_free_run_mode << 1));
3022 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
3023 (pdata->sdp_free_run_cbar_en << 1) |
3024 (pdata->sdp_free_run_man_col_en << 2) |
3025 (pdata->sdp_free_run_auto << 3));
3027 /* TODO from platform data */
3028 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
3029 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
3030 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
3031 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
3033 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
3034 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
3036 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
3038 /* todo, improve settings for sdram */
3039 if (pdata->sd_ram_size >= 128) {
3040 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
3041 if (pdata->sd_ram_ddr) {
3042 /* SDP setup for the AD eval board */
3043 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
3044 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
3045 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3046 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3047 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3049 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
3050 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
3051 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
3052 depends on memory */
3053 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
3054 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3055 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3056 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3060 * Manual UG-214, rev 0 is bit confusing on this bit
3061 * but a '1' disables any signal if the Ram is active.
3063 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
3066 select_input(sd, pdata->vid_std_select);
3070 if (pdata->hpa_auto) {
3071 /* HPA auto, HPA 0.5s after Edid set and Cable detect */
3072 hdmi_write(sd, 0x69, 0x5c);
3075 hdmi_write(sd, 0x69, 0xa3);
3076 /* HPA disable on port A and B */
3077 io_write_and_or(sd, 0x20, 0xcf, 0x00);
3081 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
3082 io_write(sd, 0x33, 0x40);
3085 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
3087 adv7842_irq_enable(sd, true);
3089 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
3092 /* ----------------------------------------------------------------------- */
3094 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
3097 * From ADV784x external Memory test.pdf
3099 * Reset must just been performed before running test.
3100 * Recommended to reset after test.
3107 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
3108 io_write(sd, 0x01, 0x00); /* Program SDP mode */
3109 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
3110 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
3111 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
3112 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
3113 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
3114 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
3115 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
3116 io_write(sd, 0x15, 0xBA); /* Enable outputs */
3117 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
3118 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
3122 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
3123 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
3124 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
3125 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
3126 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
3127 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
3128 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
3129 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
3130 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
3131 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
3132 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
3136 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
3137 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
3141 for (i = 0; i < 10; i++) {
3142 u8 result = sdp_io_read(sd, 0xdb);
3143 if (result & 0x10) {
3153 v4l2_dbg(1, debug, sd,
3154 "Ram Test: completed %d of %d: pass %d, fail %d\n",
3155 complete, i, pass, fail);
3157 if (!complete || fail)
3162 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
3163 struct adv7842_platform_data *pdata)
3165 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
3166 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
3167 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
3168 io_write(sd, 0xf4, pdata->i2c_cec << 1);
3169 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
3171 io_write(sd, 0xf8, pdata->i2c_afe << 1);
3172 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
3173 io_write(sd, 0xfa, pdata->i2c_edid << 1);
3174 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
3176 io_write(sd, 0xfd, pdata->i2c_cp << 1);
3177 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
3180 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
3182 struct i2c_client *client = v4l2_get_subdevdata(sd);
3183 struct adv7842_state *state = to_state(sd);
3184 struct adv7842_platform_data *pdata = client->dev.platform_data;
3185 struct v4l2_dv_timings timings;
3191 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
3192 v4l2_info(sd, "no sdram or no ddr sdram\n");
3198 adv7842_rewrite_i2c_addresses(sd, pdata);
3201 ret = adv7842_ddr_ram_test(sd);
3205 adv7842_rewrite_i2c_addresses(sd, pdata);
3207 /* and re-init chip and state */
3208 adv7842_core_init(sd);
3212 select_input(sd, state->vid_std_select);
3216 edid_write_vga_segment(sd);
3217 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
3218 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
3220 timings = state->timings;
3222 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
3224 adv7842_s_dv_timings(sd, &timings);
3229 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
3232 case ADV7842_CMD_RAM_TEST:
3233 return adv7842_command_ram_test(sd);
3238 static int adv7842_subscribe_event(struct v4l2_subdev *sd,
3240 struct v4l2_event_subscription *sub)
3242 switch (sub->type) {
3243 case V4L2_EVENT_SOURCE_CHANGE:
3244 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
3245 case V4L2_EVENT_CTRL:
3246 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
3252 static int adv7842_registered(struct v4l2_subdev *sd)
3254 struct adv7842_state *state = to_state(sd);
3255 struct i2c_client *client = v4l2_get_subdevdata(sd);
3258 err = cec_register_adapter(state->cec_adap, &client->dev);
3260 cec_delete_adapter(state->cec_adap);
3264 static void adv7842_unregistered(struct v4l2_subdev *sd)
3266 struct adv7842_state *state = to_state(sd);
3268 cec_unregister_adapter(state->cec_adap);
3271 /* ----------------------------------------------------------------------- */
3273 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
3274 .s_ctrl = adv7842_s_ctrl,
3275 .g_volatile_ctrl = adv7842_g_volatile_ctrl,
3278 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
3279 .log_status = adv7842_log_status,
3280 .ioctl = adv7842_ioctl,
3281 .interrupt_service_routine = adv7842_isr,
3282 .subscribe_event = adv7842_subscribe_event,
3283 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
3284 #ifdef CONFIG_VIDEO_ADV_DEBUG
3285 .g_register = adv7842_g_register,
3286 .s_register = adv7842_s_register,
3290 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
3291 .g_std = adv7842_g_std,
3292 .s_std = adv7842_s_std,
3293 .s_routing = adv7842_s_routing,
3294 .querystd = adv7842_querystd,
3295 .g_input_status = adv7842_g_input_status,
3296 .s_dv_timings = adv7842_s_dv_timings,
3297 .g_dv_timings = adv7842_g_dv_timings,
3298 .query_dv_timings = adv7842_query_dv_timings,
3301 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
3302 .enum_mbus_code = adv7842_enum_mbus_code,
3303 .get_fmt = adv7842_get_format,
3304 .set_fmt = adv7842_set_format,
3305 .get_edid = adv7842_get_edid,
3306 .set_edid = adv7842_set_edid,
3307 .enum_dv_timings = adv7842_enum_dv_timings,
3308 .dv_timings_cap = adv7842_dv_timings_cap,
3311 static const struct v4l2_subdev_ops adv7842_ops = {
3312 .core = &adv7842_core_ops,
3313 .video = &adv7842_video_ops,
3314 .pad = &adv7842_pad_ops,
3317 static const struct v4l2_subdev_internal_ops adv7842_int_ops = {
3318 .registered = adv7842_registered,
3319 .unregistered = adv7842_unregistered,
3322 /* -------------------------- custom ctrls ---------------------------------- */
3324 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
3325 .ops = &adv7842_ctrl_ops,
3326 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
3327 .name = "Analog Sampling Phase",
3328 .type = V4L2_CTRL_TYPE_INTEGER,
3335 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
3336 .ops = &adv7842_ctrl_ops,
3337 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
3338 .name = "Free Running Color, Manual",
3339 .type = V4L2_CTRL_TYPE_BOOLEAN,
3345 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
3346 .ops = &adv7842_ctrl_ops,
3347 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
3348 .name = "Free Running Color",
3349 .type = V4L2_CTRL_TYPE_INTEGER,
3355 static void adv7842_unregister_clients(struct v4l2_subdev *sd)
3357 struct adv7842_state *state = to_state(sd);
3358 if (state->i2c_avlink)
3359 i2c_unregister_device(state->i2c_avlink);
3361 i2c_unregister_device(state->i2c_cec);
3362 if (state->i2c_infoframe)
3363 i2c_unregister_device(state->i2c_infoframe);
3364 if (state->i2c_sdp_io)
3365 i2c_unregister_device(state->i2c_sdp_io);
3367 i2c_unregister_device(state->i2c_sdp);
3369 i2c_unregister_device(state->i2c_afe);
3370 if (state->i2c_repeater)
3371 i2c_unregister_device(state->i2c_repeater);
3372 if (state->i2c_edid)
3373 i2c_unregister_device(state->i2c_edid);
3374 if (state->i2c_hdmi)
3375 i2c_unregister_device(state->i2c_hdmi);
3377 i2c_unregister_device(state->i2c_cp);
3379 i2c_unregister_device(state->i2c_vdp);
3381 state->i2c_avlink = NULL;
3382 state->i2c_cec = NULL;
3383 state->i2c_infoframe = NULL;
3384 state->i2c_sdp_io = NULL;
3385 state->i2c_sdp = NULL;
3386 state->i2c_afe = NULL;
3387 state->i2c_repeater = NULL;
3388 state->i2c_edid = NULL;
3389 state->i2c_hdmi = NULL;
3390 state->i2c_cp = NULL;
3391 state->i2c_vdp = NULL;
3394 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
3397 struct i2c_client *client = v4l2_get_subdevdata(sd);
3398 struct i2c_client *cp;
3400 io_write(sd, io_reg, addr << 1);
3403 v4l2_err(sd, "no %s i2c addr configured\n", desc);
3407 cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
3409 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr);
3414 static int adv7842_register_clients(struct v4l2_subdev *sd)
3416 struct adv7842_state *state = to_state(sd);
3417 struct adv7842_platform_data *pdata = &state->pdata;
3419 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
3420 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
3421 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
3422 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
3423 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
3424 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
3425 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
3426 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
3427 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
3428 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
3429 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
3431 if (!state->i2c_avlink ||
3433 !state->i2c_infoframe ||
3434 !state->i2c_sdp_io ||
3437 !state->i2c_repeater ||
3447 static int adv7842_probe(struct i2c_client *client,
3448 const struct i2c_device_id *id)
3450 struct adv7842_state *state;
3451 static const struct v4l2_dv_timings cea640x480 =
3452 V4L2_DV_BT_CEA_640X480P59_94;
3453 struct adv7842_platform_data *pdata = client->dev.platform_data;
3454 struct v4l2_ctrl_handler *hdl;
3455 struct v4l2_ctrl *ctrl;
3456 struct v4l2_subdev *sd;
3460 /* Check if the adapter supports the needed features */
3461 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3464 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
3468 v4l_err(client, "No platform data!\n");
3472 state = devm_kzalloc(&client->dev, sizeof(struct adv7842_state), GFP_KERNEL);
3474 v4l_err(client, "Could not allocate adv7842_state memory!\n");
3479 state->pdata = *pdata;
3480 state->timings = cea640x480;
3481 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3484 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
3485 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3486 sd->internal_ops = &adv7842_int_ops;
3487 state->mode = pdata->mode;
3489 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
3490 state->restart_stdi_once = true;
3492 /* i2c access to adv7842? */
3493 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3494 adv_smbus_read_byte_data_check(client, 0xeb, false);
3495 if (rev != 0x2012) {
3496 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
3497 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3498 adv_smbus_read_byte_data_check(client, 0xeb, false);
3500 if (rev != 0x2012) {
3501 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3502 client->addr << 1, rev);
3506 if (pdata->chip_reset)
3509 /* control handlers */
3511 v4l2_ctrl_handler_init(hdl, 6);
3513 /* add in ascending ID order */
3514 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3515 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3516 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3517 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3518 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3519 V4L2_CID_SATURATION, 0, 255, 1, 128);
3520 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3521 V4L2_CID_HUE, 0, 128, 1, 0);
3522 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3523 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3524 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3526 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3528 /* custom controls */
3529 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3530 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
3531 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
3532 &adv7842_ctrl_analog_sampling_phase, NULL);
3533 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
3534 &adv7842_ctrl_free_run_color_manual, NULL);
3535 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
3536 &adv7842_ctrl_free_run_color, NULL);
3537 state->rgb_quantization_range_ctrl =
3538 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3539 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3540 0, V4L2_DV_RGB_RANGE_AUTO);
3541 sd->ctrl_handler = hdl;
3546 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3551 if (adv7842_register_clients(sd) < 0) {
3553 v4l2_err(sd, "failed to create all i2c clients\n");
3558 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3559 adv7842_delayed_work_enable_hotplug);
3561 state->pad.flags = MEDIA_PAD_FL_SOURCE;
3562 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
3564 goto err_work_queues;
3566 err = adv7842_core_init(sd);
3570 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
3571 state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops,
3572 state, dev_name(&client->dev),
3573 CEC_CAP_DEFAULTS, ADV7842_MAX_ADDRS);
3574 err = PTR_ERR_OR_ZERO(state->cec_adap);
3579 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3580 client->addr << 1, client->adapter->name);
3584 media_entity_cleanup(&sd->entity);
3586 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3588 adv7842_unregister_clients(sd);
3590 v4l2_ctrl_handler_free(hdl);
3594 /* ----------------------------------------------------------------------- */
3596 static int adv7842_remove(struct i2c_client *client)
3598 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3599 struct adv7842_state *state = to_state(sd);
3601 adv7842_irq_enable(sd, false);
3602 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
3603 v4l2_device_unregister_subdev(sd);
3604 media_entity_cleanup(&sd->entity);
3605 adv7842_unregister_clients(sd);
3606 v4l2_ctrl_handler_free(sd->ctrl_handler);
3610 /* ----------------------------------------------------------------------- */
3612 static const struct i2c_device_id adv7842_id[] = {
3616 MODULE_DEVICE_TABLE(i2c, adv7842_id);
3618 /* ----------------------------------------------------------------------- */
3620 static struct i2c_driver adv7842_driver = {
3624 .probe = adv7842_probe,
3625 .remove = adv7842_remove,
3626 .id_table = adv7842_id,
3629 module_i2c_driver(adv7842_driver);