1 // SPDX-License-Identifier: GPL-2.0-only
3 * adv7842 - Analog Devices ADV7842 video decoder driver
5 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
9 * References (c = chapter, p = page):
10 * REF_01 - Analog devices, ADV7842,
11 * Register Settings Recommendations, Rev. 1.9, April 2011
12 * REF_02 - Analog devices, Software User Guide, UG-206,
13 * ADV7842 I2C Register Maps, Rev. 0, November 2010
14 * REF_03 - Analog devices, Hardware User Guide, UG-214,
15 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
16 * Decoder and Digitizer , Rev. 0, January 2011
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/slab.h>
23 #include <linux/i2c.h>
24 #include <linux/delay.h>
25 #include <linux/videodev2.h>
26 #include <linux/workqueue.h>
27 #include <linux/v4l2-dv-timings.h>
28 #include <linux/hdmi.h>
29 #include <media/cec.h>
30 #include <media/v4l2-device.h>
31 #include <media/v4l2-event.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-dv-timings.h>
34 #include <media/i2c/adv7842.h>
37 module_param(debug, int, 0644);
38 MODULE_PARM_DESC(debug, "debug level (0-2)");
40 MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");
41 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
42 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
43 MODULE_LICENSE("GPL");
45 /* ADV7842 system clock frequency */
46 #define ADV7842_fsc (28636360)
48 #define ADV7842_RGB_OUT (1 << 1)
50 #define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0)
51 #define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0)
52 #define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0)
54 #define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5)
55 #define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5)
56 #define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5)
57 #define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5)
58 #define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5)
59 #define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5)
61 #define ADV7842_OP_CH_SEL_GBR (0 << 5)
62 #define ADV7842_OP_CH_SEL_GRB (1 << 5)
63 #define ADV7842_OP_CH_SEL_BGR (2 << 5)
64 #define ADV7842_OP_CH_SEL_RGB (3 << 5)
65 #define ADV7842_OP_CH_SEL_BRG (4 << 5)
66 #define ADV7842_OP_CH_SEL_RBG (5 << 5)
68 #define ADV7842_OP_SWAP_CB_CR (1 << 0)
70 #define ADV7842_MAX_ADDRS (3)
73 **********************************************************************
75 * Arrays with configuration parameters for the ADV7842
77 **********************************************************************
80 struct adv7842_format_info {
88 struct adv7842_state {
89 struct adv7842_platform_data pdata;
90 struct v4l2_subdev sd;
92 struct v4l2_ctrl_handler hdl;
93 enum adv7842_mode mode;
94 struct v4l2_dv_timings timings;
95 enum adv7842_vid_std_select vid_std_select;
97 const struct adv7842_format_info *format;
108 struct v4l2_fract aspect_ratio;
109 u32 rgb_quantization_range;
111 struct delayed_work delayed_work_enable_hotplug;
112 bool restart_stdi_once;
116 struct i2c_client *i2c_sdp_io;
117 struct i2c_client *i2c_sdp;
118 struct i2c_client *i2c_cp;
119 struct i2c_client *i2c_vdp;
120 struct i2c_client *i2c_afe;
121 struct i2c_client *i2c_hdmi;
122 struct i2c_client *i2c_repeater;
123 struct i2c_client *i2c_edid;
124 struct i2c_client *i2c_infoframe;
125 struct i2c_client *i2c_cec;
126 struct i2c_client *i2c_avlink;
129 struct v4l2_ctrl *detect_tx_5v_ctrl;
130 struct v4l2_ctrl *analog_sampling_phase_ctrl;
131 struct v4l2_ctrl *free_run_color_ctrl_manual;
132 struct v4l2_ctrl *free_run_color_ctrl;
133 struct v4l2_ctrl *rgb_quantization_range_ctrl;
135 struct cec_adapter *cec_adap;
136 u8 cec_addr[ADV7842_MAX_ADDRS];
138 bool cec_enabled_adap;
141 /* Unsupported timings. This device cannot support 720p30. */
142 static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {
143 V4L2_DV_BT_CEA_1280X720P30,
147 static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
151 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)
152 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false))
157 struct adv7842_video_standards {
158 struct v4l2_dv_timings timings;
163 /* sorted by number of lines */
164 static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {
165 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
166 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
167 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
168 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
169 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
170 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
171 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
172 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
173 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
174 /* TODO add 1920x1080P60_RB (CVT timing) */
178 /* sorted by number of lines */
179 static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {
180 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
181 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
182 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
183 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
184 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
185 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
186 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
187 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
188 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
189 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
190 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
191 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
192 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
193 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
194 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
195 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
196 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
197 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
198 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
199 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
200 /* TODO add 1600X1200P60_RB (not a DMT timing) */
201 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
202 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
206 /* sorted by number of lines */
207 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {
208 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
209 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
210 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
211 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
212 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
213 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
214 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
215 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
216 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
220 /* sorted by number of lines */
221 static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {
222 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
223 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
224 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
225 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
226 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
227 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
228 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
229 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
230 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
231 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
232 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
233 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
234 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
235 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
236 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
240 static const struct v4l2_event adv7842_ev_fmt = {
241 .type = V4L2_EVENT_SOURCE_CHANGE,
242 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
245 /* ----------------------------------------------------------------------- */
247 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
249 return container_of(sd, struct adv7842_state, sd);
252 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
254 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
257 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
259 return V4L2_DV_BT_BLANKING_WIDTH(t);
262 static inline unsigned htotal(const struct v4l2_bt_timings *t)
264 return V4L2_DV_BT_FRAME_WIDTH(t);
267 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
269 return V4L2_DV_BT_BLANKING_HEIGHT(t);
272 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
274 return V4L2_DV_BT_FRAME_HEIGHT(t);
278 /* ----------------------------------------------------------------------- */
280 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
281 u8 command, bool check)
283 union i2c_smbus_data data;
285 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
286 I2C_SMBUS_READ, command,
287 I2C_SMBUS_BYTE_DATA, &data))
290 v4l_err(client, "error reading %02x, %02x\n",
291 client->addr, command);
295 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
299 for (i = 0; i < 3; i++) {
300 int ret = adv_smbus_read_byte_data_check(client, command, true);
304 v4l_err(client, "read ok after %d retries\n", i);
308 v4l_err(client, "read failed\n");
312 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
313 u8 command, u8 value)
315 union i2c_smbus_data data;
320 for (i = 0; i < 3; i++) {
321 err = i2c_smbus_xfer(client->adapter, client->addr,
323 I2C_SMBUS_WRITE, command,
324 I2C_SMBUS_BYTE_DATA, &data);
329 v4l_err(client, "error writing %02x, %02x, %02x\n",
330 client->addr, command, value);
334 static void adv_smbus_write_byte_no_check(struct i2c_client *client,
335 u8 command, u8 value)
337 union i2c_smbus_data data;
340 i2c_smbus_xfer(client->adapter, client->addr,
342 I2C_SMBUS_WRITE, command,
343 I2C_SMBUS_BYTE_DATA, &data);
346 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
347 u8 command, unsigned length, const u8 *values)
349 union i2c_smbus_data data;
351 if (length > I2C_SMBUS_BLOCK_MAX)
352 length = I2C_SMBUS_BLOCK_MAX;
353 data.block[0] = length;
354 memcpy(data.block + 1, values, length);
355 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
356 I2C_SMBUS_WRITE, command,
357 I2C_SMBUS_I2C_BLOCK_DATA, &data);
360 /* ----------------------------------------------------------------------- */
362 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
364 struct i2c_client *client = v4l2_get_subdevdata(sd);
366 return adv_smbus_read_byte_data(client, reg);
369 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
371 struct i2c_client *client = v4l2_get_subdevdata(sd);
373 return adv_smbus_write_byte_data(client, reg, val);
376 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
378 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
381 static inline int io_write_clr_set(struct v4l2_subdev *sd,
382 u8 reg, u8 mask, u8 val)
384 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
387 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
389 struct adv7842_state *state = to_state(sd);
391 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
394 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
396 struct adv7842_state *state = to_state(sd);
398 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
401 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
403 struct adv7842_state *state = to_state(sd);
405 return adv_smbus_read_byte_data(state->i2c_cec, reg);
408 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
410 struct adv7842_state *state = to_state(sd);
412 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
415 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
417 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
420 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
422 struct adv7842_state *state = to_state(sd);
424 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
427 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
429 struct adv7842_state *state = to_state(sd);
431 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
434 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
436 struct adv7842_state *state = to_state(sd);
438 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);
441 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
443 struct adv7842_state *state = to_state(sd);
445 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);
448 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
450 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
453 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
455 struct adv7842_state *state = to_state(sd);
457 return adv_smbus_read_byte_data(state->i2c_sdp, reg);
460 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
462 struct adv7842_state *state = to_state(sd);
464 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);
467 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
469 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
472 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
474 struct adv7842_state *state = to_state(sd);
476 return adv_smbus_read_byte_data(state->i2c_afe, reg);
479 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
481 struct adv7842_state *state = to_state(sd);
483 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
486 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
488 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
491 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
493 struct adv7842_state *state = to_state(sd);
495 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
498 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
500 struct adv7842_state *state = to_state(sd);
502 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
505 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
507 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
510 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
512 struct adv7842_state *state = to_state(sd);
514 return adv_smbus_read_byte_data(state->i2c_edid, reg);
517 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
519 struct adv7842_state *state = to_state(sd);
521 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
524 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
526 struct adv7842_state *state = to_state(sd);
528 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
531 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
533 struct adv7842_state *state = to_state(sd);
535 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
538 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
540 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
543 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
545 struct adv7842_state *state = to_state(sd);
547 return adv_smbus_read_byte_data(state->i2c_cp, reg);
550 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
552 struct adv7842_state *state = to_state(sd);
554 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
557 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
559 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
562 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
564 struct adv7842_state *state = to_state(sd);
566 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
569 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
571 struct adv7842_state *state = to_state(sd);
573 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
576 static void main_reset(struct v4l2_subdev *sd)
578 struct i2c_client *client = v4l2_get_subdevdata(sd);
580 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
582 adv_smbus_write_byte_no_check(client, 0xff, 0x80);
587 /* -----------------------------------------------------------------------------
591 static const struct adv7842_format_info adv7842_formats[] = {
592 { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false,
593 ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT },
594 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false,
595 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
596 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true,
597 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },
598 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false,
599 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
600 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true,
601 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },
602 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false,
603 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
604 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true,
605 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },
606 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false,
607 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
608 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true,
609 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
610 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false,
611 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
612 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true,
613 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },
614 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false,
615 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
616 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true,
617 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
618 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false,
619 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
620 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true,
621 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },
622 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false,
623 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
624 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true,
625 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
626 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false,
627 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
628 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true,
629 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },
632 static const struct adv7842_format_info *
633 adv7842_format_info(struct adv7842_state *state, u32 code)
637 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) {
638 if (adv7842_formats[i].code == code)
639 return &adv7842_formats[i];
645 /* ----------------------------------------------------------------------- */
647 static inline bool is_analog_input(struct v4l2_subdev *sd)
649 struct adv7842_state *state = to_state(sd);
651 return ((state->mode == ADV7842_MODE_RGB) ||
652 (state->mode == ADV7842_MODE_COMP));
655 static inline bool is_digital_input(struct v4l2_subdev *sd)
657 struct adv7842_state *state = to_state(sd);
659 return state->mode == ADV7842_MODE_HDMI;
662 static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
663 .type = V4L2_DV_BT_656_1120,
664 /* keep this initialization for compatibility with GCC < 4.4.6 */
666 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
667 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
668 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
669 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
670 V4L2_DV_BT_CAP_CUSTOM)
673 static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
674 .type = V4L2_DV_BT_656_1120,
675 /* keep this initialization for compatibility with GCC < 4.4.6 */
677 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
678 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
679 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
680 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
681 V4L2_DV_BT_CAP_CUSTOM)
684 static inline const struct v4l2_dv_timings_cap *
685 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
687 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
688 &adv7842_timings_cap_analog;
691 /* ----------------------------------------------------------------------- */
693 static u16 adv7842_read_cable_det(struct v4l2_subdev *sd)
695 u8 reg = io_read(sd, 0x6f);
699 val |= 1; /* port A */
701 val |= 2; /* port B */
705 static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)
707 struct delayed_work *dwork = to_delayed_work(work);
708 struct adv7842_state *state = container_of(dwork,
709 struct adv7842_state, delayed_work_enable_hotplug);
710 struct v4l2_subdev *sd = &state->sd;
711 int present = state->hdmi_edid.present;
714 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
717 if (present & (0x04 << ADV7842_EDID_PORT_A))
719 if (present & (0x04 << ADV7842_EDID_PORT_B))
721 io_write_and_or(sd, 0x20, 0xcf, mask);
724 static int edid_write_vga_segment(struct v4l2_subdev *sd)
726 struct i2c_client *client = v4l2_get_subdevdata(sd);
727 struct adv7842_state *state = to_state(sd);
728 const u8 *val = state->vga_edid.edid;
732 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
734 /* HPA disable on port A and B */
735 io_write_and_or(sd, 0x20, 0xcf, 0x00);
737 /* Disable I2C access to internal EDID ram from VGA DDC port */
738 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
740 /* edid segment pointer '1' for VGA port */
741 rep_write_and_or(sd, 0x77, 0xef, 0x10);
743 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
744 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
745 I2C_SMBUS_BLOCK_MAX, val + i);
749 /* Calculates the checksums and enables I2C access
750 * to internal EDID ram from VGA DDC port.
752 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
754 for (i = 0; i < 1000; i++) {
755 if (rep_read(sd, 0x79) & 0x20)
760 v4l_err(client, "error enabling edid on VGA port\n");
764 /* enable hotplug after 200 ms */
765 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
770 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
772 struct i2c_client *client = v4l2_get_subdevdata(sd);
773 struct adv7842_state *state = to_state(sd);
774 const u8 *edid = state->hdmi_edid.edid;
780 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n",
781 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
783 /* HPA disable on port A and B */
784 io_write_and_or(sd, 0x20, 0xcf, 0x00);
786 /* Disable I2C access to internal EDID ram from HDMI DDC ports */
787 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
789 if (!state->hdmi_edid.present) {
790 cec_phys_addr_invalidate(state->cec_adap);
794 pa = v4l2_get_edid_phys_addr(edid, 256, &spa_loc);
795 err = v4l2_phys_addr_validate(pa, &pa, NULL);
800 * Return an error if no location of the source physical address
806 /* edid segment pointer '0' for HDMI ports */
807 rep_write_and_or(sd, 0x77, 0xef, 0x00);
809 for (i = 0; !err && i < 256; i += I2C_SMBUS_BLOCK_MAX)
810 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
811 I2C_SMBUS_BLOCK_MAX, edid + i);
815 if (port == ADV7842_EDID_PORT_A) {
816 rep_write(sd, 0x72, edid[spa_loc]);
817 rep_write(sd, 0x73, edid[spa_loc + 1]);
819 rep_write(sd, 0x74, edid[spa_loc]);
820 rep_write(sd, 0x75, edid[spa_loc + 1]);
822 rep_write(sd, 0x76, spa_loc & 0xff);
823 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
825 /* Calculates the checksums and enables I2C access to internal
826 * EDID ram from HDMI DDC ports
828 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
830 for (i = 0; i < 1000; i++) {
831 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
836 v4l_err(client, "error enabling edid on port %c\n",
837 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');
840 cec_s_phys_addr(state->cec_adap, pa, false);
842 /* enable hotplug after 200 ms */
843 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);
848 /* ----------------------------------------------------------------------- */
850 #ifdef CONFIG_VIDEO_ADV_DEBUG
851 static void adv7842_inv_register(struct v4l2_subdev *sd)
853 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
854 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
855 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
856 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
857 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
858 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
859 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
860 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
861 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
862 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
863 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
864 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
867 static int adv7842_g_register(struct v4l2_subdev *sd,
868 struct v4l2_dbg_register *reg)
871 switch (reg->reg >> 8) {
873 reg->val = io_read(sd, reg->reg & 0xff);
876 reg->val = avlink_read(sd, reg->reg & 0xff);
879 reg->val = cec_read(sd, reg->reg & 0xff);
882 reg->val = infoframe_read(sd, reg->reg & 0xff);
885 reg->val = sdp_io_read(sd, reg->reg & 0xff);
888 reg->val = sdp_read(sd, reg->reg & 0xff);
891 reg->val = afe_read(sd, reg->reg & 0xff);
894 reg->val = rep_read(sd, reg->reg & 0xff);
897 reg->val = edid_read(sd, reg->reg & 0xff);
900 reg->val = hdmi_read(sd, reg->reg & 0xff);
903 reg->val = cp_read(sd, reg->reg & 0xff);
906 reg->val = vdp_read(sd, reg->reg & 0xff);
909 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
910 adv7842_inv_register(sd);
916 static int adv7842_s_register(struct v4l2_subdev *sd,
917 const struct v4l2_dbg_register *reg)
919 u8 val = reg->val & 0xff;
921 switch (reg->reg >> 8) {
923 io_write(sd, reg->reg & 0xff, val);
926 avlink_write(sd, reg->reg & 0xff, val);
929 cec_write(sd, reg->reg & 0xff, val);
932 infoframe_write(sd, reg->reg & 0xff, val);
935 sdp_io_write(sd, reg->reg & 0xff, val);
938 sdp_write(sd, reg->reg & 0xff, val);
941 afe_write(sd, reg->reg & 0xff, val);
944 rep_write(sd, reg->reg & 0xff, val);
947 edid_write(sd, reg->reg & 0xff, val);
950 hdmi_write(sd, reg->reg & 0xff, val);
953 cp_write(sd, reg->reg & 0xff, val);
956 vdp_write(sd, reg->reg & 0xff, val);
959 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
960 adv7842_inv_register(sd);
967 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
969 struct adv7842_state *state = to_state(sd);
970 u16 cable_det = adv7842_read_cable_det(sd);
972 v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det);
974 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
977 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
979 const struct adv7842_video_standards *predef_vid_timings,
980 const struct v4l2_dv_timings *timings)
984 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
985 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
986 is_digital_input(sd) ? 250000 : 1000000, false))
989 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
990 /* v_freq and prim mode */
991 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
998 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
999 struct v4l2_dv_timings *timings)
1001 struct adv7842_state *state = to_state(sd);
1004 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1006 /* reset to default values */
1007 io_write(sd, 0x16, 0x43);
1008 io_write(sd, 0x17, 0x5a);
1009 /* disable embedded syncs for auto graphics mode */
1010 cp_write_and_or(sd, 0x81, 0xef, 0x00);
1011 cp_write(sd, 0x26, 0x00);
1012 cp_write(sd, 0x27, 0x00);
1013 cp_write(sd, 0x28, 0x00);
1014 cp_write(sd, 0x29, 0x00);
1015 cp_write(sd, 0x8f, 0x40);
1016 cp_write(sd, 0x90, 0x00);
1017 cp_write(sd, 0xa5, 0x00);
1018 cp_write(sd, 0xa6, 0x00);
1019 cp_write(sd, 0xa7, 0x00);
1020 cp_write(sd, 0xab, 0x00);
1021 cp_write(sd, 0xac, 0x00);
1023 switch (state->mode) {
1024 case ADV7842_MODE_COMP:
1025 case ADV7842_MODE_RGB:
1026 err = find_and_set_predefined_video_timings(sd,
1027 0x01, adv7842_prim_mode_comp, timings);
1029 err = find_and_set_predefined_video_timings(sd,
1030 0x02, adv7842_prim_mode_gr, timings);
1032 case ADV7842_MODE_HDMI:
1033 err = find_and_set_predefined_video_timings(sd,
1034 0x05, adv7842_prim_mode_hdmi_comp, timings);
1036 err = find_and_set_predefined_video_timings(sd,
1037 0x06, adv7842_prim_mode_hdmi_gr, timings);
1040 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1041 __func__, state->mode);
1050 static void configure_custom_video_timings(struct v4l2_subdev *sd,
1051 const struct v4l2_bt_timings *bt)
1053 struct adv7842_state *state = to_state(sd);
1054 struct i2c_client *client = v4l2_get_subdevdata(sd);
1055 u32 width = htotal(bt);
1056 u32 height = vtotal(bt);
1057 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1058 u16 cp_start_eav = width - bt->hfrontporch;
1059 u16 cp_start_vbi = height - bt->vfrontporch + 1;
1060 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;
1061 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1062 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1064 0xc0 | ((width >> 8) & 0x1f),
1068 v4l2_dbg(2, debug, sd, "%s\n", __func__);
1070 switch (state->mode) {
1071 case ADV7842_MODE_COMP:
1072 case ADV7842_MODE_RGB:
1074 io_write(sd, 0x00, 0x07); /* video std */
1075 io_write(sd, 0x01, 0x02); /* prim mode */
1076 /* enable embedded syncs for auto graphics mode */
1077 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1079 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1080 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1081 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1082 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
1083 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1087 /* active video - horizontal timing */
1088 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1089 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1090 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1091 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1093 /* active video - vertical timing */
1094 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1095 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1096 ((cp_end_vbi >> 8) & 0xf));
1097 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1099 case ADV7842_MODE_HDMI:
1100 /* set default prim_mode/vid_std for HDMI
1101 according to [REF_03, c. 4.2] */
1102 io_write(sd, 0x00, 0x02); /* video std */
1103 io_write(sd, 0x01, 0x06); /* prim mode */
1106 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1107 __func__, state->mode);
1111 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1112 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1113 cp_write(sd, 0xab, (height >> 4) & 0xff);
1114 cp_write(sd, 0xac, (height & 0x0f) << 4);
1117 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1119 struct adv7842_state *state = to_state(sd);
1128 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1129 __func__, auto_offset ? "Auto" : "Manual",
1130 offset_a, offset_b, offset_c);
1132 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1133 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1134 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1135 offset_buf[3] = offset_c & 0x0ff;
1137 /* Registers must be written in this order with no i2c access in between */
1138 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
1139 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1142 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1144 struct adv7842_state *state = to_state(sd);
1147 u8 agc_mode_man = 1;
1157 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1158 __func__, auto_gain ? "Auto" : "Manual",
1159 gain_a, gain_b, gain_c);
1161 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1162 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1163 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1164 gain_buf[3] = ((gain_c & 0x0ff));
1166 /* Registers must be written in this order with no i2c access in between */
1167 if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
1168 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1171 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1173 struct adv7842_state *state = to_state(sd);
1174 bool rgb_output = io_read(sd, 0x02) & 0x02;
1175 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1176 u8 y = HDMI_COLORSPACE_RGB;
1178 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1179 y = infoframe_read(sd, 0x01) >> 5;
1181 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1182 __func__, state->rgb_quantization_range,
1183 rgb_output, hdmi_signal);
1185 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
1186 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
1187 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1189 switch (state->rgb_quantization_range) {
1190 case V4L2_DV_RGB_RANGE_AUTO:
1191 if (state->mode == ADV7842_MODE_RGB) {
1192 /* Receiving analog RGB signal
1193 * Set RGB full range (0-255) */
1194 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1198 if (state->mode == ADV7842_MODE_COMP) {
1199 /* Receiving analog YPbPr signal
1201 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1206 /* Receiving HDMI signal
1208 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1212 /* Receiving DVI-D signal
1213 * ADV7842 selects RGB limited range regardless of
1214 * input format (CE/IT) in automatic mode */
1215 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1216 /* RGB limited range (16-235) */
1217 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1219 /* RGB full range (0-255) */
1220 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1222 if (is_digital_input(sd) && rgb_output) {
1223 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1225 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1226 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1230 case V4L2_DV_RGB_RANGE_LIMITED:
1231 if (state->mode == ADV7842_MODE_COMP) {
1232 /* YCrCb limited range (16-235) */
1233 io_write_and_or(sd, 0x02, 0x0f, 0x20);
1237 if (y != HDMI_COLORSPACE_RGB)
1240 /* RGB limited range (16-235) */
1241 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1244 case V4L2_DV_RGB_RANGE_FULL:
1245 if (state->mode == ADV7842_MODE_COMP) {
1246 /* YCrCb full range (0-255) */
1247 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1251 if (y != HDMI_COLORSPACE_RGB)
1254 /* RGB full range (0-255) */
1255 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1257 if (is_analog_input(sd) || hdmi_signal)
1260 /* Adjust gain/offset for DVI-D signals only */
1262 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1264 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1265 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1271 static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)
1273 struct v4l2_subdev *sd = to_sd(ctrl);
1274 struct adv7842_state *state = to_state(sd);
1277 contrast/brightness/hue/free run is acting a bit strange,
1278 not sure if sdp csc is correct.
1281 /* standard ctrls */
1282 case V4L2_CID_BRIGHTNESS:
1283 cp_write(sd, 0x3c, ctrl->val);
1284 sdp_write(sd, 0x14, ctrl->val);
1285 /* ignore lsb sdp 0x17[3:2] */
1287 case V4L2_CID_CONTRAST:
1288 cp_write(sd, 0x3a, ctrl->val);
1289 sdp_write(sd, 0x13, ctrl->val);
1290 /* ignore lsb sdp 0x17[1:0] */
1292 case V4L2_CID_SATURATION:
1293 cp_write(sd, 0x3b, ctrl->val);
1294 sdp_write(sd, 0x15, ctrl->val);
1295 /* ignore lsb sdp 0x17[5:4] */
1298 cp_write(sd, 0x3d, ctrl->val);
1299 sdp_write(sd, 0x16, ctrl->val);
1300 /* ignore lsb sdp 0x17[7:6] */
1303 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1304 afe_write(sd, 0xc8, ctrl->val);
1306 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1307 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1308 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1310 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {
1311 u8 R = (ctrl->val & 0xff0000) >> 16;
1312 u8 G = (ctrl->val & 0x00ff00) >> 8;
1313 u8 B = (ctrl->val & 0x0000ff);
1314 /* RGB -> YUV, numerical approximation */
1315 int Y = 66 * R + 129 * G + 25 * B;
1316 int U = -38 * R - 74 * G + 112 * B;
1317 int V = 112 * R - 94 * G - 18 * B;
1319 /* Scale down to 8 bits with rounding */
1323 /* make U,V positive */
1328 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1329 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1332 cp_write(sd, 0xc1, R);
1333 cp_write(sd, 0xc0, G);
1334 cp_write(sd, 0xc2, B);
1336 sdp_write(sd, 0xde, Y);
1337 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1340 case V4L2_CID_DV_RX_RGB_RANGE:
1341 state->rgb_quantization_range = ctrl->val;
1342 set_rgb_quantization_range(sd);
1348 static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1350 struct v4l2_subdev *sd = to_sd(ctrl);
1352 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1353 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1354 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1355 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1361 static inline bool no_power(struct v4l2_subdev *sd)
1363 return io_read(sd, 0x0c) & 0x24;
1366 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1368 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1371 static inline bool is_hdmi(struct v4l2_subdev *sd)
1373 return hdmi_read(sd, 0x05) & 0x80;
1376 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1378 struct adv7842_state *state = to_state(sd);
1382 if (io_read(sd, 0x0c) & 0x24)
1383 *status |= V4L2_IN_ST_NO_POWER;
1385 if (state->mode == ADV7842_MODE_SDP) {
1386 /* status from SDP block */
1387 if (!(sdp_read(sd, 0x5A) & 0x01))
1388 *status |= V4L2_IN_ST_NO_SIGNAL;
1390 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1394 /* status from CP block */
1395 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1396 !(cp_read(sd, 0xb1) & 0x80))
1397 /* TODO channel 2 */
1398 *status |= V4L2_IN_ST_NO_SIGNAL;
1400 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1401 *status |= V4L2_IN_ST_NO_SIGNAL;
1403 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1409 struct stdi_readback {
1415 static int stdi2dv_timings(struct v4l2_subdev *sd,
1416 struct stdi_readback *stdi,
1417 struct v4l2_dv_timings *timings)
1419 struct adv7842_state *state = to_state(sd);
1420 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;
1424 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1425 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1427 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1428 adv7842_get_dv_timings_cap(sd),
1429 adv7842_check_dv_timings, NULL))
1431 if (vtotal(bt) != stdi->lcf + 1)
1433 if (bt->vsync != stdi->lcvs)
1436 pix_clk = hfreq * htotal(bt);
1438 if ((pix_clk < bt->pixelclock + 1000000) &&
1439 (pix_clk > bt->pixelclock - 1000000)) {
1440 *timings = v4l2_dv_timings_presets[i];
1445 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1446 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1447 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1450 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1451 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1452 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1453 false, state->aspect_ratio, timings))
1456 v4l2_dbg(2, debug, sd,
1457 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1458 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1459 stdi->hs_pol, stdi->vs_pol);
1463 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1467 adv7842_g_input_status(sd, &status);
1468 if (status & V4L2_IN_ST_NO_SIGNAL) {
1469 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1473 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1474 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1475 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1477 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1478 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1479 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1480 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1481 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1486 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1488 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1489 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1493 v4l2_dbg(2, debug, sd,
1494 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1495 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1496 stdi->hs_pol, stdi->vs_pol,
1497 stdi->interlaced ? "interlaced" : "progressive");
1502 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1503 struct v4l2_enum_dv_timings *timings)
1505 if (timings->pad != 0)
1508 return v4l2_enum_dv_timings_cap(timings,
1509 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1512 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1513 struct v4l2_dv_timings_cap *cap)
1518 *cap = *adv7842_get_dv_timings_cap(sd);
1522 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1523 if the format is listed in adv7842_timings[] */
1524 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1525 struct v4l2_dv_timings *timings)
1527 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1528 is_digital_input(sd) ? 250000 : 1000000,
1529 adv7842_check_dv_timings, NULL);
1532 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1533 struct v4l2_dv_timings *timings)
1535 struct adv7842_state *state = to_state(sd);
1536 struct v4l2_bt_timings *bt = &timings->bt;
1537 struct stdi_readback stdi = { 0 };
1539 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1541 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1544 if (state->mode == ADV7842_MODE_SDP)
1548 if (read_stdi(sd, &stdi)) {
1549 state->restart_stdi_once = true;
1550 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1553 bt->interlaced = stdi.interlaced ?
1554 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1555 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1556 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1558 if (is_digital_input(sd)) {
1561 timings->type = V4L2_DV_BT_656_1120;
1563 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1564 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1565 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
1566 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
1568 /* adjust for deep color mode */
1569 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
1571 bt->pixelclock = freq;
1572 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1573 hdmi_read(sd, 0x21);
1574 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1575 hdmi_read(sd, 0x23);
1576 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1577 hdmi_read(sd, 0x25);
1578 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1579 hdmi_read(sd, 0x2b)) / 2;
1580 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1581 hdmi_read(sd, 0x2f)) / 2;
1582 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1583 hdmi_read(sd, 0x33)) / 2;
1584 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1585 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1586 if (bt->interlaced == V4L2_DV_INTERLACED) {
1587 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1588 hdmi_read(sd, 0x0c);
1589 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1590 hdmi_read(sd, 0x2d)) / 2;
1591 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1592 hdmi_read(sd, 0x31)) / 2;
1593 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1594 hdmi_read(sd, 0x35)) / 2;
1596 bt->il_vfrontporch = 0;
1598 bt->il_vbackporch = 0;
1600 adv7842_fill_optional_dv_timings_fields(sd, timings);
1603 * Since LCVS values are inaccurate [REF_03, p. 339-340],
1604 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1606 if (!stdi2dv_timings(sd, &stdi, timings))
1609 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1610 if (!stdi2dv_timings(sd, &stdi, timings))
1613 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1614 if (stdi2dv_timings(sd, &stdi, timings)) {
1616 * The STDI block may measure wrong values, especially
1617 * for lcvs and lcf. If the driver can not find any
1618 * valid timing, the STDI block is restarted to measure
1619 * the video timings again. The function will return an
1620 * error, but the restart of STDI will generate a new
1621 * STDI interrupt and the format detection process will
1624 if (state->restart_stdi_once) {
1625 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1626 /* TODO restart STDI for Sync Channel 2 */
1627 /* enter one-shot mode */
1628 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1629 /* trigger STDI restart */
1630 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1631 /* reset to continuous mode */
1632 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1633 state->restart_stdi_once = false;
1636 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1639 state->restart_stdi_once = true;
1644 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1649 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1650 struct v4l2_dv_timings *timings)
1652 struct adv7842_state *state = to_state(sd);
1653 struct v4l2_bt_timings *bt;
1656 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1658 if (state->mode == ADV7842_MODE_SDP)
1661 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1662 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1668 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1669 adv7842_check_dv_timings, NULL))
1672 adv7842_fill_optional_dv_timings_fields(sd, timings);
1674 state->timings = *timings;
1676 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1678 /* Use prim_mode and vid_std when available */
1679 err = configure_predefined_video_timings(sd, timings);
1681 /* custom settings when the video format
1682 does not have prim_mode/vid_std */
1683 configure_custom_video_timings(sd, bt);
1686 set_rgb_quantization_range(sd);
1690 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1695 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1696 struct v4l2_dv_timings *timings)
1698 struct adv7842_state *state = to_state(sd);
1700 if (state->mode == ADV7842_MODE_SDP)
1702 *timings = state->timings;
1706 static void enable_input(struct v4l2_subdev *sd)
1708 struct adv7842_state *state = to_state(sd);
1710 set_rgb_quantization_range(sd);
1711 switch (state->mode) {
1712 case ADV7842_MODE_SDP:
1713 case ADV7842_MODE_COMP:
1714 case ADV7842_MODE_RGB:
1715 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1717 case ADV7842_MODE_HDMI:
1718 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1719 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1720 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1723 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1724 __func__, state->mode);
1729 static void disable_input(struct v4l2_subdev *sd)
1731 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1732 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */
1733 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1734 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1737 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1738 const struct adv7842_sdp_csc_coeff *c)
1740 /* csc auto/manual */
1741 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1747 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1750 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1751 sdp_io_write(sd, 0xe1, c->A1);
1752 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1753 sdp_io_write(sd, 0xe3, c->A2);
1754 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1755 sdp_io_write(sd, 0xe5, c->A3);
1758 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1759 sdp_io_write(sd, 0xe7, c->A4);
1762 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1763 sdp_io_write(sd, 0xe9, c->B1);
1764 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1765 sdp_io_write(sd, 0xeb, c->B2);
1766 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1767 sdp_io_write(sd, 0xed, c->B3);
1770 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1771 sdp_io_write(sd, 0xef, c->B4);
1774 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1775 sdp_io_write(sd, 0xf1, c->C1);
1776 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1777 sdp_io_write(sd, 0xf3, c->C2);
1778 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1779 sdp_io_write(sd, 0xf5, c->C3);
1782 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1783 sdp_io_write(sd, 0xf7, c->C4);
1786 static void select_input(struct v4l2_subdev *sd,
1787 enum adv7842_vid_std_select vid_std_select)
1789 struct adv7842_state *state = to_state(sd);
1791 switch (state->mode) {
1792 case ADV7842_MODE_SDP:
1793 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1794 io_write(sd, 0x01, 0); /* prim mode */
1795 /* enable embedded syncs for auto graphics mode */
1796 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1798 afe_write(sd, 0x00, 0x00); /* power up ADC */
1799 afe_write(sd, 0xc8, 0x00); /* phase control */
1801 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1802 /* script says register 0xde, which don't exist in manual */
1804 /* Manual analog input muxing mode, CVBS (6.4)*/
1805 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1806 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {
1807 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1808 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1810 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1811 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1813 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1814 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1816 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1817 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1819 /* SDP recommended settings */
1820 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1821 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1823 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1824 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1825 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1826 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1827 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1828 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1829 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1831 /* deinterlacer enabled and 3D comb */
1832 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1836 case ADV7842_MODE_COMP:
1837 case ADV7842_MODE_RGB:
1838 /* Automatic analog input muxing mode */
1839 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1840 /* set mode and select free run resolution */
1841 io_write(sd, 0x00, vid_std_select); /* video std */
1842 io_write(sd, 0x01, 0x02); /* prim mode */
1843 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1844 for auto graphics mode */
1846 afe_write(sd, 0x00, 0x00); /* power up ADC */
1847 afe_write(sd, 0xc8, 0x00); /* phase control */
1848 if (state->mode == ADV7842_MODE_COMP) {
1849 /* force to YCrCb */
1850 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1853 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1856 /* set ADI recommended settings for digitizer */
1857 /* "ADV7842 Register Settings Recommendations
1858 * (rev. 1.8, November 2010)" p. 9. */
1859 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1860 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1862 /* set to default gain for RGB */
1863 cp_write(sd, 0x73, 0x10);
1864 cp_write(sd, 0x74, 0x04);
1865 cp_write(sd, 0x75, 0x01);
1866 cp_write(sd, 0x76, 0x00);
1868 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1869 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1870 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1873 case ADV7842_MODE_HDMI:
1874 /* Automatic analog input muxing mode */
1875 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1876 /* set mode and select free run resolution */
1877 if (state->hdmi_port_a)
1878 hdmi_write(sd, 0x00, 0x02); /* select port A */
1880 hdmi_write(sd, 0x00, 0x03); /* select port B */
1881 io_write(sd, 0x00, vid_std_select); /* video std */
1882 io_write(sd, 0x01, 5); /* prim mode */
1883 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1884 for auto graphics mode */
1886 /* set ADI recommended settings for HDMI: */
1887 /* "ADV7842 Register Settings Recommendations
1888 * (rev. 1.8, November 2010)" p. 3. */
1889 hdmi_write(sd, 0xc0, 0x00);
1890 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1891 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1892 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1893 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1894 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1895 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1896 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1897 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1898 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1899 Improve robustness */
1900 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1901 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1902 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1903 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1904 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1905 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1906 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1907 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1908 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1909 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1911 afe_write(sd, 0x00, 0xff); /* power down ADC */
1912 afe_write(sd, 0xc8, 0x40); /* phase control */
1914 /* set to default gain for HDMI */
1915 cp_write(sd, 0x73, 0x10);
1916 cp_write(sd, 0x74, 0x04);
1917 cp_write(sd, 0x75, 0x01);
1918 cp_write(sd, 0x76, 0x00);
1920 /* reset ADI recommended settings for digitizer */
1921 /* "ADV7842 Register Settings Recommendations
1922 * (rev. 2.5, June 2010)" p. 17. */
1923 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1924 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1925 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1927 /* CP coast control */
1928 cp_write(sd, 0xc3, 0x33); /* Component mode */
1930 /* color space conversion, autodetect color space */
1931 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1935 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1936 __func__, state->mode);
1941 static int adv7842_s_routing(struct v4l2_subdev *sd,
1942 u32 input, u32 output, u32 config)
1944 struct adv7842_state *state = to_state(sd);
1946 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1949 case ADV7842_SELECT_HDMI_PORT_A:
1950 state->mode = ADV7842_MODE_HDMI;
1951 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1952 state->hdmi_port_a = true;
1954 case ADV7842_SELECT_HDMI_PORT_B:
1955 state->mode = ADV7842_MODE_HDMI;
1956 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;
1957 state->hdmi_port_a = false;
1959 case ADV7842_SELECT_VGA_COMP:
1960 state->mode = ADV7842_MODE_COMP;
1961 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1963 case ADV7842_SELECT_VGA_RGB:
1964 state->mode = ADV7842_MODE_RGB;
1965 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;
1967 case ADV7842_SELECT_SDP_CVBS:
1968 state->mode = ADV7842_MODE_SDP;
1969 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;
1971 case ADV7842_SELECT_SDP_YC:
1972 state->mode = ADV7842_MODE_SDP;
1973 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;
1980 select_input(sd, state->vid_std_select);
1983 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
1988 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,
1989 struct v4l2_subdev_pad_config *cfg,
1990 struct v4l2_subdev_mbus_code_enum *code)
1992 if (code->index >= ARRAY_SIZE(adv7842_formats))
1994 code->code = adv7842_formats[code->index].code;
1998 static void adv7842_fill_format(struct adv7842_state *state,
1999 struct v4l2_mbus_framefmt *format)
2001 memset(format, 0, sizeof(*format));
2003 format->width = state->timings.bt.width;
2004 format->height = state->timings.bt.height;
2005 format->field = V4L2_FIELD_NONE;
2006 format->colorspace = V4L2_COLORSPACE_SRGB;
2008 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
2009 format->colorspace = (state->timings.bt.height <= 576) ?
2010 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
2014 * Compute the op_ch_sel value required to obtain on the bus the component order
2015 * corresponding to the selected format taking into account bus reordering
2016 * applied by the board at the output of the device.
2018 * The following table gives the op_ch_value from the format component order
2019 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
2020 * adv7842_bus_order value in row).
2022 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
2023 * ----------+-------------------------------------------------
2024 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
2025 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
2026 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
2027 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
2028 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
2029 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
2031 static unsigned int adv7842_op_ch_sel(struct adv7842_state *state)
2033 #define _SEL(a, b, c, d, e, f) { \
2034 ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \
2035 ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f }
2036 #define _BUS(x) [ADV7842_BUS_ORDER_##x]
2038 static const unsigned int op_ch_sel[6][6] = {
2039 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
2040 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
2041 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
2042 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
2043 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
2044 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
2047 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
2050 static void adv7842_setup_format(struct adv7842_state *state)
2052 struct v4l2_subdev *sd = &state->sd;
2054 io_write_clr_set(sd, 0x02, 0x02,
2055 state->format->rgb_out ? ADV7842_RGB_OUT : 0);
2056 io_write(sd, 0x03, state->format->op_format_sel |
2057 state->pdata.op_format_mode_sel);
2058 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));
2059 io_write_clr_set(sd, 0x05, 0x01,
2060 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0);
2061 set_rgb_quantization_range(sd);
2064 static int adv7842_get_format(struct v4l2_subdev *sd,
2065 struct v4l2_subdev_pad_config *cfg,
2066 struct v4l2_subdev_format *format)
2068 struct adv7842_state *state = to_state(sd);
2070 if (format->pad != ADV7842_PAD_SOURCE)
2073 if (state->mode == ADV7842_MODE_SDP) {
2075 if (!(sdp_read(sd, 0x5a) & 0x01))
2077 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8;
2078 format->format.width = 720;
2080 if (state->norm & V4L2_STD_525_60)
2081 format->format.height = 480;
2083 format->format.height = 576;
2084 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
2088 adv7842_fill_format(state, &format->format);
2090 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2091 struct v4l2_mbus_framefmt *fmt;
2093 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2094 format->format.code = fmt->code;
2096 format->format.code = state->format->code;
2102 static int adv7842_set_format(struct v4l2_subdev *sd,
2103 struct v4l2_subdev_pad_config *cfg,
2104 struct v4l2_subdev_format *format)
2106 struct adv7842_state *state = to_state(sd);
2107 const struct adv7842_format_info *info;
2109 if (format->pad != ADV7842_PAD_SOURCE)
2112 if (state->mode == ADV7842_MODE_SDP)
2113 return adv7842_get_format(sd, cfg, format);
2115 info = adv7842_format_info(state, format->format.code);
2117 info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2119 adv7842_fill_format(state, &format->format);
2120 format->format.code = info->code;
2122 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
2123 struct v4l2_mbus_framefmt *fmt;
2125 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
2126 fmt->code = format->format.code;
2128 state->format = info;
2129 adv7842_setup_format(state);
2135 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
2138 /* Enable SSPD, STDI and CP locked/unlocked interrupts */
2139 io_write(sd, 0x46, 0x9c);
2140 /* ESDP_50HZ_DET interrupt */
2141 io_write(sd, 0x5a, 0x10);
2142 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */
2143 io_write(sd, 0x73, 0x03);
2144 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2145 io_write(sd, 0x78, 0x03);
2146 /* Enable SDP Standard Detection Change and SDP Video Detected */
2147 io_write(sd, 0xa0, 0x09);
2148 /* Enable HDMI_MODE interrupt */
2149 io_write(sd, 0x69, 0x08);
2151 io_write(sd, 0x46, 0x0);
2152 io_write(sd, 0x5a, 0x0);
2153 io_write(sd, 0x73, 0x0);
2154 io_write(sd, 0x78, 0x0);
2155 io_write(sd, 0xa0, 0x0);
2156 io_write(sd, 0x69, 0x0);
2160 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
2161 static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
2163 struct adv7842_state *state = to_state(sd);
2165 if ((cec_read(sd, 0x11) & 0x01) == 0) {
2166 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
2170 if (tx_raw_status & 0x02) {
2171 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
2173 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
2177 if (tx_raw_status & 0x04) {
2182 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
2184 * We set this status bit since this hardware performs
2187 status = CEC_TX_STATUS_MAX_RETRIES;
2188 nack_cnt = cec_read(sd, 0x14) & 0xf;
2190 status |= CEC_TX_STATUS_NACK;
2191 low_drive_cnt = cec_read(sd, 0x14) >> 4;
2193 status |= CEC_TX_STATUS_LOW_DRIVE;
2194 cec_transmit_done(state->cec_adap, status,
2195 0, nack_cnt, low_drive_cnt, 0);
2198 if (tx_raw_status & 0x01) {
2199 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2200 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
2205 static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled)
2209 /* cec controller */
2210 cec_irq = io_read(sd, 0x93) & 0x0f;
2214 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2215 adv7842_cec_tx_raw_status(sd, cec_irq);
2216 if (cec_irq & 0x08) {
2217 struct adv7842_state *state = to_state(sd);
2220 msg.len = cec_read(sd, 0x25) & 0x1f;
2227 for (i = 0; i < msg.len; i++)
2228 msg.msg[i] = cec_read(sd, i + 0x15);
2229 cec_write(sd, 0x26, 0x01); /* re-enable rx */
2230 cec_received_msg(state->cec_adap, &msg);
2234 io_write(sd, 0x94, cec_irq);
2240 static int adv7842_cec_adap_enable(struct cec_adapter *adap, bool enable)
2242 struct adv7842_state *state = cec_get_drvdata(adap);
2243 struct v4l2_subdev *sd = &state->sd;
2245 if (!state->cec_enabled_adap && enable) {
2246 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2247 cec_write(sd, 0x2c, 0x01); /* cec soft reset */
2248 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2251 /* tx: arbitration lost */
2252 /* tx: retry timeout */
2254 io_write_clr_set(sd, 0x96, 0x0f, 0x0f);
2255 cec_write(sd, 0x26, 0x01); /* enable rx */
2256 } else if (state->cec_enabled_adap && !enable) {
2257 /* disable cec interrupts */
2258 io_write_clr_set(sd, 0x96, 0x0f, 0x00);
2259 /* disable address mask 1-3 */
2260 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2261 /* power down cec section */
2262 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2263 state->cec_valid_addrs = 0;
2265 state->cec_enabled_adap = enable;
2269 static int adv7842_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2271 struct adv7842_state *state = cec_get_drvdata(adap);
2272 struct v4l2_subdev *sd = &state->sd;
2273 unsigned int i, free_idx = ADV7842_MAX_ADDRS;
2275 if (!state->cec_enabled_adap)
2276 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2278 if (addr == CEC_LOG_ADDR_INVALID) {
2279 cec_write_clr_set(sd, 0x27, 0x70, 0);
2280 state->cec_valid_addrs = 0;
2284 for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
2285 bool is_valid = state->cec_valid_addrs & (1 << i);
2287 if (free_idx == ADV7842_MAX_ADDRS && !is_valid)
2289 if (is_valid && state->cec_addr[i] == addr)
2292 if (i == ADV7842_MAX_ADDRS) {
2294 if (i == ADV7842_MAX_ADDRS)
2297 state->cec_addr[i] = addr;
2298 state->cec_valid_addrs |= 1 << i;
2302 /* enable address mask 0 */
2303 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2304 /* set address for mask 0 */
2305 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2308 /* enable address mask 1 */
2309 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2310 /* set address for mask 1 */
2311 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2314 /* enable address mask 2 */
2315 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2316 /* set address for mask 1 */
2317 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2323 static int adv7842_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2324 u32 signal_free_time, struct cec_msg *msg)
2326 struct adv7842_state *state = cec_get_drvdata(adap);
2327 struct v4l2_subdev *sd = &state->sd;
2332 * The number of retries is the number of attempts - 1, but retry
2333 * at least once. It's not clear if a value of 0 is allowed, so
2334 * let's do at least one retry.
2336 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2339 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2344 for (i = 0; i < len; i++)
2345 cec_write(sd, i, msg->msg[i]);
2347 /* set length (data + header) */
2348 cec_write(sd, 0x10, len);
2349 /* start transmit, enable tx */
2350 cec_write(sd, 0x11, 0x01);
2354 static const struct cec_adap_ops adv7842_cec_adap_ops = {
2355 .adap_enable = adv7842_cec_adap_enable,
2356 .adap_log_addr = adv7842_cec_adap_log_addr,
2357 .adap_transmit = adv7842_cec_adap_transmit,
2361 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2363 struct adv7842_state *state = to_state(sd);
2364 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;
2367 adv7842_irq_enable(sd, false);
2370 irq_status[0] = io_read(sd, 0x43);
2371 irq_status[1] = io_read(sd, 0x57);
2372 irq_status[2] = io_read(sd, 0x70);
2373 irq_status[3] = io_read(sd, 0x75);
2374 irq_status[4] = io_read(sd, 0x9d);
2375 irq_status[5] = io_read(sd, 0x66);
2379 io_write(sd, 0x44, irq_status[0]);
2381 io_write(sd, 0x58, irq_status[1]);
2383 io_write(sd, 0x71, irq_status[2]);
2385 io_write(sd, 0x76, irq_status[3]);
2387 io_write(sd, 0x9e, irq_status[4]);
2389 io_write(sd, 0x67, irq_status[5]);
2391 adv7842_irq_enable(sd, true);
2393 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
2394 irq_status[0], irq_status[1], irq_status[2],
2395 irq_status[3], irq_status[4], irq_status[5]);
2397 /* format change CP */
2398 fmt_change_cp = irq_status[0] & 0x9c;
2400 /* format change SDP */
2401 if (state->mode == ADV7842_MODE_SDP)
2402 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);
2406 /* digital format CP */
2407 if (is_digital_input(sd))
2408 fmt_change_digital = irq_status[3] & 0x03;
2410 fmt_change_digital = 0;
2413 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {
2414 v4l2_dbg(1, debug, sd,
2415 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",
2416 __func__, fmt_change_cp, fmt_change_digital,
2418 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
2424 if (irq_status[5] & 0x08) {
2425 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2426 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
2427 set_rgb_quantization_range(sd);
2432 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
2434 adv7842_cec_isr(sd, handled);
2438 if (irq_status[2] & 0x3) {
2439 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
2440 adv7842_s_detect_tx_5v_ctrl(sd);
2447 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2449 struct adv7842_state *state = to_state(sd);
2452 memset(edid->reserved, 0, sizeof(edid->reserved));
2454 switch (edid->pad) {
2455 case ADV7842_EDID_PORT_A:
2456 case ADV7842_EDID_PORT_B:
2457 if (state->hdmi_edid.present & (0x04 << edid->pad))
2458 data = state->hdmi_edid.edid;
2460 case ADV7842_EDID_PORT_VGA:
2461 if (state->vga_edid.present)
2462 data = state->vga_edid.edid;
2468 if (edid->start_block == 0 && edid->blocks == 0) {
2469 edid->blocks = data ? 2 : 0;
2476 if (edid->start_block >= 2)
2479 if (edid->start_block + edid->blocks > 2)
2480 edid->blocks = 2 - edid->start_block;
2482 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2487 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
2489 struct adv7842_state *state = to_state(sd);
2492 memset(e->reserved, 0, sizeof(e->reserved));
2494 if (e->pad > ADV7842_EDID_PORT_VGA)
2496 if (e->start_block != 0)
2498 if (e->blocks > 2) {
2503 /* todo, per edid */
2504 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],
2508 case ADV7842_EDID_PORT_VGA:
2509 memset(&state->vga_edid.edid, 0, 256);
2510 state->vga_edid.present = e->blocks ? 0x1 : 0x0;
2511 memcpy(&state->vga_edid.edid, e->edid, 128 * e->blocks);
2512 err = edid_write_vga_segment(sd);
2514 case ADV7842_EDID_PORT_A:
2515 case ADV7842_EDID_PORT_B:
2516 memset(&state->hdmi_edid.edid, 0, 256);
2518 state->hdmi_edid.present |= 0x04 << e->pad;
2520 state->hdmi_edid.present &= ~(0x04 << e->pad);
2521 adv7842_s_detect_tx_5v_ctrl(sd);
2523 memcpy(&state->hdmi_edid.edid, e->edid, 128 * e->blocks);
2524 err = edid_write_hdmi_segment(sd, e->pad);
2530 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2534 struct adv7842_cfg_read_infoframe {
2541 static void log_infoframe(struct v4l2_subdev *sd, struct adv7842_cfg_read_infoframe *cri)
2545 union hdmi_infoframe frame;
2547 struct i2c_client *client = v4l2_get_subdevdata(sd);
2548 struct device *dev = &client->dev;
2550 if (!(io_read(sd, 0x60) & cri->present_mask)) {
2551 v4l2_info(sd, "%s infoframe not received\n", cri->desc);
2555 for (i = 0; i < 3; i++)
2556 buffer[i] = infoframe_read(sd, cri->head_addr + i);
2558 len = buffer[2] + 1;
2560 if (len + 3 > sizeof(buffer)) {
2561 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
2565 for (i = 0; i < len; i++)
2566 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);
2568 if (hdmi_infoframe_unpack(&frame, buffer) < 0) {
2569 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
2573 hdmi_infoframe_log(KERN_INFO, dev, &frame);
2576 static void adv7842_log_infoframes(struct v4l2_subdev *sd)
2579 struct adv7842_cfg_read_infoframe cri[] = {
2580 { "AVI", 0x01, 0xe0, 0x00 },
2581 { "Audio", 0x02, 0xe3, 0x1c },
2582 { "SDP", 0x04, 0xe6, 0x2a },
2583 { "Vendor", 0x10, 0xec, 0x54 }
2586 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2587 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2591 for (i = 0; i < ARRAY_SIZE(cri); i++)
2592 log_infoframe(sd, &cri[i]);
2596 /* Let's keep it here for now, as it could be useful for debug */
2597 static const char * const prim_mode_txt[] = {
2602 "CVBS & HDMI AUDIO",
2617 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2619 /* SDP (Standard definition processor) block */
2620 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2622 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2623 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2624 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2626 v4l2_info(sd, "SDP: free run: %s\n",
2627 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2628 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2629 "valid SD/PR signal detected" : "invalid/no signal");
2630 if (sdp_signal_detected) {
2631 static const char * const sdp_std_txt[] = {
2639 "7?", "8?", "9?", "a?", "b?",
2645 v4l2_info(sd, "SDP: standard %s\n",
2646 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2647 v4l2_info(sd, "SDP: %s\n",
2648 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2649 v4l2_info(sd, "SDP: %s\n",
2650 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2651 v4l2_info(sd, "SDP: deinterlacer %s\n",
2652 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2653 v4l2_info(sd, "SDP: csc %s mode\n",
2654 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2659 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2662 struct adv7842_state *state = to_state(sd);
2663 struct v4l2_dv_timings timings;
2664 u8 reg_io_0x02 = io_read(sd, 0x02);
2665 u8 reg_io_0x21 = io_read(sd, 0x21);
2666 u8 reg_rep_0x77 = rep_read(sd, 0x77);
2667 u8 reg_rep_0x7d = rep_read(sd, 0x7d);
2668 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2669 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2670 bool audio_mute = io_read(sd, 0x65) & 0x40;
2672 static const char * const csc_coeff_sel_rb[16] = {
2673 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2674 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2675 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2676 "reserved", "reserved", "reserved", "reserved", "manual"
2678 static const char * const input_color_space_txt[16] = {
2679 "RGB limited range (16-235)", "RGB full range (0-255)",
2680 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2681 "xvYCC Bt.601", "xvYCC Bt.709",
2682 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2683 "invalid", "invalid", "invalid", "invalid", "invalid",
2684 "invalid", "invalid", "automatic"
2686 static const char * const rgb_quantization_range_txt[] = {
2688 "RGB limited range (16-235)",
2689 "RGB full range (0-255)",
2691 static const char * const deep_color_mode_txt[4] = {
2692 "8-bits per channel",
2693 "10-bits per channel",
2694 "12-bits per channel",
2695 "16-bits per channel (not supported)"
2698 v4l2_info(sd, "-----Chip status-----\n");
2699 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2700 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2701 state->hdmi_port_a ? "A" : "B");
2702 v4l2_info(sd, "EDID A %s, B %s\n",
2703 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?
2704 "enabled" : "disabled",
2705 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?
2706 "enabled" : "disabled");
2707 v4l2_info(sd, "HPD A %s, B %s\n",
2708 reg_io_0x21 & 0x02 ? "enabled" : "disabled",
2709 reg_io_0x21 & 0x01 ? "enabled" : "disabled");
2710 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2711 "enabled" : "disabled");
2712 if (state->cec_enabled_adap) {
2715 for (i = 0; i < ADV7842_MAX_ADDRS; i++) {
2716 bool is_valid = state->cec_valid_addrs & (1 << i);
2719 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2720 state->cec_addr[i]);
2724 v4l2_info(sd, "-----Signal status-----\n");
2725 if (state->hdmi_port_a) {
2726 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2727 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2728 v4l2_info(sd, "TMDS signal detected: %s\n",
2729 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2730 v4l2_info(sd, "TMDS signal locked: %s\n",
2731 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2733 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2734 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2735 v4l2_info(sd, "TMDS signal detected: %s\n",
2736 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2737 v4l2_info(sd, "TMDS signal locked: %s\n",
2738 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2740 v4l2_info(sd, "CP free run: %s\n",
2741 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2742 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2743 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2744 (io_read(sd, 0x01) & 0x70) >> 4);
2746 v4l2_info(sd, "-----Video Timings-----\n");
2747 if (no_cp_signal(sd)) {
2748 v4l2_info(sd, "STDI: not locked\n");
2750 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2751 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2752 u32 lcvs = cp_read(sd, 0xb3) >> 3;
2753 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2754 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2755 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2756 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2757 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2759 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",
2761 (cp_read(sd, 0xb1) & 0x40) ?
2762 "interlaced" : "progressive",
2765 if (adv7842_query_dv_timings(sd, &timings))
2766 v4l2_info(sd, "No video detected\n");
2768 v4l2_print_dv_timings(sd->name, "Detected format: ",
2770 v4l2_print_dv_timings(sd->name, "Configured format: ",
2771 &state->timings, true);
2773 if (no_cp_signal(sd))
2776 v4l2_info(sd, "-----Color space-----\n");
2777 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2778 rgb_quantization_range_txt[state->rgb_quantization_range]);
2779 v4l2_info(sd, "Input color space: %s\n",
2780 input_color_space_txt[reg_io_0x02 >> 4]);
2781 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2782 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2783 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2784 "(16-235)" : "(0-255)",
2785 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2786 v4l2_info(sd, "Color space conversion: %s\n",
2787 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2789 if (!is_digital_input(sd))
2792 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2793 v4l2_info(sd, "HDCP encrypted content: %s\n",
2794 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2795 v4l2_info(sd, "HDCP keys read: %s%s\n",
2796 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2797 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2801 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2802 audio_pll_locked ? "locked" : "not locked",
2803 audio_sample_packet_detect ? "detected" : "not detected",
2804 audio_mute ? "muted" : "enabled");
2805 if (audio_pll_locked && audio_sample_packet_detect) {
2806 v4l2_info(sd, "Audio format: %s\n",
2807 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2809 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2810 (hdmi_read(sd, 0x5c) << 8) +
2811 (hdmi_read(sd, 0x5d) & 0xf0));
2812 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2813 (hdmi_read(sd, 0x5e) << 8) +
2814 hdmi_read(sd, 0x5f));
2815 v4l2_info(sd, "AV Mute: %s\n",
2816 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2817 v4l2_info(sd, "Deep color mode: %s\n",
2818 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2820 adv7842_log_infoframes(sd);
2825 static int adv7842_log_status(struct v4l2_subdev *sd)
2827 struct adv7842_state *state = to_state(sd);
2829 if (state->mode == ADV7842_MODE_SDP)
2830 return adv7842_sdp_log_status(sd);
2831 return adv7842_cp_log_status(sd);
2834 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2836 struct adv7842_state *state = to_state(sd);
2838 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2840 if (state->mode != ADV7842_MODE_SDP)
2843 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2845 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2849 switch (sdp_read(sd, 0x52) & 0x0f) {
2852 *std &= V4L2_STD_NTSC;
2856 *std &= V4L2_STD_NTSC_443;
2860 *std &= V4L2_STD_SECAM;
2864 *std &= V4L2_STD_PAL_M;
2868 *std &= V4L2_STD_PAL_60;
2872 *std &= V4L2_STD_PAL_Nc;
2876 *std &= V4L2_STD_PAL;
2880 *std &= V4L2_STD_SECAM;
2883 *std &= V4L2_STD_ALL;
2889 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2891 if (s && s->adjust) {
2892 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2893 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2894 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2895 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2896 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2897 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2898 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2899 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2900 sdp_io_write(sd, 0xa8, s->vs_beg_o);
2901 sdp_io_write(sd, 0xa9, s->vs_beg_e);
2902 sdp_io_write(sd, 0xaa, s->vs_end_o);
2903 sdp_io_write(sd, 0xab, s->vs_end_e);
2904 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2905 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2906 sdp_io_write(sd, 0xae, s->de_v_end_o);
2907 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2909 /* set to default */
2910 sdp_io_write(sd, 0x94, 0x00);
2911 sdp_io_write(sd, 0x95, 0x00);
2912 sdp_io_write(sd, 0x96, 0x00);
2913 sdp_io_write(sd, 0x97, 0x20);
2914 sdp_io_write(sd, 0x98, 0x00);
2915 sdp_io_write(sd, 0x99, 0x00);
2916 sdp_io_write(sd, 0x9a, 0x00);
2917 sdp_io_write(sd, 0x9b, 0x00);
2918 sdp_io_write(sd, 0xa8, 0x04);
2919 sdp_io_write(sd, 0xa9, 0x04);
2920 sdp_io_write(sd, 0xaa, 0x04);
2921 sdp_io_write(sd, 0xab, 0x04);
2922 sdp_io_write(sd, 0xac, 0x04);
2923 sdp_io_write(sd, 0xad, 0x04);
2924 sdp_io_write(sd, 0xae, 0x04);
2925 sdp_io_write(sd, 0xaf, 0x04);
2929 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2931 struct adv7842_state *state = to_state(sd);
2932 struct adv7842_platform_data *pdata = &state->pdata;
2934 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2936 if (state->mode != ADV7842_MODE_SDP)
2939 if (norm & V4L2_STD_625_50)
2940 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2941 else if (norm & V4L2_STD_525_60)
2942 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2944 adv7842_s_sdp_io(sd, NULL);
2946 if (norm & V4L2_STD_ALL) {
2953 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2955 struct adv7842_state *state = to_state(sd);
2957 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2959 if (state->mode != ADV7842_MODE_SDP)
2962 *norm = state->norm;
2966 /* ----------------------------------------------------------------------- */
2968 static int adv7842_core_init(struct v4l2_subdev *sd)
2970 struct adv7842_state *state = to_state(sd);
2971 struct adv7842_platform_data *pdata = &state->pdata;
2972 hdmi_write(sd, 0x48,
2973 (pdata->disable_pwrdnb ? 0x80 : 0) |
2974 (pdata->disable_cable_det_rst ? 0x40 : 0));
2979 * Disable I2C access to internal EDID ram from HDMI DDC ports
2980 * Disable auto edid enable when leaving powerdown mode
2982 rep_write_and_or(sd, 0x77, 0xd3, 0x20);
2985 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2986 io_write(sd, 0x15, 0x80); /* Power up pads */
2989 io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3);
2990 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2991 pdata->insert_av_codes << 2 |
2992 pdata->replicate_av_codes << 1);
2993 adv7842_setup_format(state);
2996 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2998 /* Drive strength */
2999 io_write_and_or(sd, 0x14, 0xc0,
3000 pdata->dr_str_data << 4 |
3001 pdata->dr_str_clk << 2 |
3002 pdata->dr_str_sync);
3005 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
3006 (pdata->hdmi_free_run_mode << 1));
3009 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
3010 (pdata->sdp_free_run_cbar_en << 1) |
3011 (pdata->sdp_free_run_man_col_en << 2) |
3012 (pdata->sdp_free_run_auto << 3));
3014 /* TODO from platform data */
3015 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
3016 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
3017 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
3018 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
3020 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
3021 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
3023 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
3025 /* todo, improve settings for sdram */
3026 if (pdata->sd_ram_size >= 128) {
3027 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
3028 if (pdata->sd_ram_ddr) {
3029 /* SDP setup for the AD eval board */
3030 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
3031 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
3032 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3033 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3034 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3036 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
3037 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
3038 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
3039 depends on memory */
3040 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
3041 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3042 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3043 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3047 * Manual UG-214, rev 0 is bit confusing on this bit
3048 * but a '1' disables any signal if the Ram is active.
3050 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
3053 select_input(sd, pdata->vid_std_select);
3057 if (pdata->hpa_auto) {
3058 /* HPA auto, HPA 0.5s after Edid set and Cable detect */
3059 hdmi_write(sd, 0x69, 0x5c);
3062 hdmi_write(sd, 0x69, 0xa3);
3063 /* HPA disable on port A and B */
3064 io_write_and_or(sd, 0x20, 0xcf, 0x00);
3068 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
3069 io_write(sd, 0x33, 0x40);
3072 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
3074 adv7842_irq_enable(sd, true);
3076 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
3079 /* ----------------------------------------------------------------------- */
3081 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
3084 * From ADV784x external Memory test.pdf
3086 * Reset must just been performed before running test.
3087 * Recommended to reset after test.
3094 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
3095 io_write(sd, 0x01, 0x00); /* Program SDP mode */
3096 afe_write(sd, 0x80, 0x92); /* SDP Recommeneded Write */
3097 afe_write(sd, 0x9B, 0x01); /* SDP Recommeneded Write ADV7844ES1 */
3098 afe_write(sd, 0x9C, 0x60); /* SDP Recommeneded Write ADV7844ES1 */
3099 afe_write(sd, 0x9E, 0x02); /* SDP Recommeneded Write ADV7844ES1 */
3100 afe_write(sd, 0xA0, 0x0B); /* SDP Recommeneded Write ADV7844ES1 */
3101 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
3102 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
3103 io_write(sd, 0x15, 0xBA); /* Enable outputs */
3104 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
3105 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
3107 usleep_range(5000, 6000);
3109 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
3110 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
3111 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
3112 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
3113 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
3114 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
3115 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
3116 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
3117 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
3118 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
3119 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
3121 usleep_range(5000, 6000);
3123 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
3124 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
3128 for (i = 0; i < 10; i++) {
3129 u8 result = sdp_io_read(sd, 0xdb);
3130 if (result & 0x10) {
3140 v4l2_dbg(1, debug, sd,
3141 "Ram Test: completed %d of %d: pass %d, fail %d\n",
3142 complete, i, pass, fail);
3144 if (!complete || fail)
3149 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
3150 struct adv7842_platform_data *pdata)
3152 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
3153 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
3154 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
3155 io_write(sd, 0xf4, pdata->i2c_cec << 1);
3156 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
3158 io_write(sd, 0xf8, pdata->i2c_afe << 1);
3159 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
3160 io_write(sd, 0xfa, pdata->i2c_edid << 1);
3161 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
3163 io_write(sd, 0xfd, pdata->i2c_cp << 1);
3164 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
3167 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
3169 struct i2c_client *client = v4l2_get_subdevdata(sd);
3170 struct adv7842_state *state = to_state(sd);
3171 struct adv7842_platform_data *pdata = client->dev.platform_data;
3172 struct v4l2_dv_timings timings;
3178 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {
3179 v4l2_info(sd, "no sdram or no ddr sdram\n");
3185 adv7842_rewrite_i2c_addresses(sd, pdata);
3188 ret = adv7842_ddr_ram_test(sd);
3192 adv7842_rewrite_i2c_addresses(sd, pdata);
3194 /* and re-init chip and state */
3195 adv7842_core_init(sd);
3199 select_input(sd, state->vid_std_select);
3203 edid_write_vga_segment(sd);
3204 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
3205 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
3207 timings = state->timings;
3209 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));
3211 adv7842_s_dv_timings(sd, &timings);
3216 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
3219 case ADV7842_CMD_RAM_TEST:
3220 return adv7842_command_ram_test(sd);
3225 static int adv7842_subscribe_event(struct v4l2_subdev *sd,
3227 struct v4l2_event_subscription *sub)
3229 switch (sub->type) {
3230 case V4L2_EVENT_SOURCE_CHANGE:
3231 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
3232 case V4L2_EVENT_CTRL:
3233 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
3239 static int adv7842_registered(struct v4l2_subdev *sd)
3241 struct adv7842_state *state = to_state(sd);
3242 struct i2c_client *client = v4l2_get_subdevdata(sd);
3245 err = cec_register_adapter(state->cec_adap, &client->dev);
3247 cec_delete_adapter(state->cec_adap);
3251 static void adv7842_unregistered(struct v4l2_subdev *sd)
3253 struct adv7842_state *state = to_state(sd);
3255 cec_unregister_adapter(state->cec_adap);
3258 /* ----------------------------------------------------------------------- */
3260 static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {
3261 .s_ctrl = adv7842_s_ctrl,
3262 .g_volatile_ctrl = adv7842_g_volatile_ctrl,
3265 static const struct v4l2_subdev_core_ops adv7842_core_ops = {
3266 .log_status = adv7842_log_status,
3267 .ioctl = adv7842_ioctl,
3268 .interrupt_service_routine = adv7842_isr,
3269 .subscribe_event = adv7842_subscribe_event,
3270 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
3271 #ifdef CONFIG_VIDEO_ADV_DEBUG
3272 .g_register = adv7842_g_register,
3273 .s_register = adv7842_s_register,
3277 static const struct v4l2_subdev_video_ops adv7842_video_ops = {
3278 .g_std = adv7842_g_std,
3279 .s_std = adv7842_s_std,
3280 .s_routing = adv7842_s_routing,
3281 .querystd = adv7842_querystd,
3282 .g_input_status = adv7842_g_input_status,
3283 .s_dv_timings = adv7842_s_dv_timings,
3284 .g_dv_timings = adv7842_g_dv_timings,
3285 .query_dv_timings = adv7842_query_dv_timings,
3288 static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {
3289 .enum_mbus_code = adv7842_enum_mbus_code,
3290 .get_fmt = adv7842_get_format,
3291 .set_fmt = adv7842_set_format,
3292 .get_edid = adv7842_get_edid,
3293 .set_edid = adv7842_set_edid,
3294 .enum_dv_timings = adv7842_enum_dv_timings,
3295 .dv_timings_cap = adv7842_dv_timings_cap,
3298 static const struct v4l2_subdev_ops adv7842_ops = {
3299 .core = &adv7842_core_ops,
3300 .video = &adv7842_video_ops,
3301 .pad = &adv7842_pad_ops,
3304 static const struct v4l2_subdev_internal_ops adv7842_int_ops = {
3305 .registered = adv7842_registered,
3306 .unregistered = adv7842_unregistered,
3309 /* -------------------------- custom ctrls ---------------------------------- */
3311 static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {
3312 .ops = &adv7842_ctrl_ops,
3313 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
3314 .name = "Analog Sampling Phase",
3315 .type = V4L2_CTRL_TYPE_INTEGER,
3322 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {
3323 .ops = &adv7842_ctrl_ops,
3324 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
3325 .name = "Free Running Color, Manual",
3326 .type = V4L2_CTRL_TYPE_BOOLEAN,
3332 static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {
3333 .ops = &adv7842_ctrl_ops,
3334 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
3335 .name = "Free Running Color",
3336 .type = V4L2_CTRL_TYPE_INTEGER,
3342 static void adv7842_unregister_clients(struct v4l2_subdev *sd)
3344 struct adv7842_state *state = to_state(sd);
3345 if (state->i2c_avlink)
3346 i2c_unregister_device(state->i2c_avlink);
3348 i2c_unregister_device(state->i2c_cec);
3349 if (state->i2c_infoframe)
3350 i2c_unregister_device(state->i2c_infoframe);
3351 if (state->i2c_sdp_io)
3352 i2c_unregister_device(state->i2c_sdp_io);
3354 i2c_unregister_device(state->i2c_sdp);
3356 i2c_unregister_device(state->i2c_afe);
3357 if (state->i2c_repeater)
3358 i2c_unregister_device(state->i2c_repeater);
3359 if (state->i2c_edid)
3360 i2c_unregister_device(state->i2c_edid);
3361 if (state->i2c_hdmi)
3362 i2c_unregister_device(state->i2c_hdmi);
3364 i2c_unregister_device(state->i2c_cp);
3366 i2c_unregister_device(state->i2c_vdp);
3368 state->i2c_avlink = NULL;
3369 state->i2c_cec = NULL;
3370 state->i2c_infoframe = NULL;
3371 state->i2c_sdp_io = NULL;
3372 state->i2c_sdp = NULL;
3373 state->i2c_afe = NULL;
3374 state->i2c_repeater = NULL;
3375 state->i2c_edid = NULL;
3376 state->i2c_hdmi = NULL;
3377 state->i2c_cp = NULL;
3378 state->i2c_vdp = NULL;
3381 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
3384 struct i2c_client *client = v4l2_get_subdevdata(sd);
3385 struct i2c_client *cp;
3387 io_write(sd, io_reg, addr << 1);
3390 v4l2_err(sd, "no %s i2c addr configured\n", desc);
3394 cp = i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
3396 v4l2_err(sd, "register %s on i2c addr 0x%x failed\n", desc, addr);
3401 static int adv7842_register_clients(struct v4l2_subdev *sd)
3403 struct adv7842_state *state = to_state(sd);
3404 struct adv7842_platform_data *pdata = &state->pdata;
3406 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
3407 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
3408 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
3409 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
3410 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
3411 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
3412 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
3413 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
3414 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
3415 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
3416 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
3418 if (!state->i2c_avlink ||
3420 !state->i2c_infoframe ||
3421 !state->i2c_sdp_io ||
3424 !state->i2c_repeater ||
3434 static int adv7842_probe(struct i2c_client *client,
3435 const struct i2c_device_id *id)
3437 struct adv7842_state *state;
3438 static const struct v4l2_dv_timings cea640x480 =
3439 V4L2_DV_BT_CEA_640X480P59_94;
3440 struct adv7842_platform_data *pdata = client->dev.platform_data;
3441 struct v4l2_ctrl_handler *hdl;
3442 struct v4l2_ctrl *ctrl;
3443 struct v4l2_subdev *sd;
3447 /* Check if the adapter supports the needed features */
3448 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3451 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",
3455 v4l_err(client, "No platform data!\n");
3459 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3464 state->pdata = *pdata;
3465 state->timings = cea640x480;
3466 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3469 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
3470 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3471 sd->internal_ops = &adv7842_int_ops;
3472 state->mode = pdata->mode;
3474 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;
3475 state->restart_stdi_once = true;
3477 /* i2c access to adv7842? */
3478 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3479 adv_smbus_read_byte_data_check(client, 0xeb, false);
3480 if (rev != 0x2012) {
3481 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
3482 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |
3483 adv_smbus_read_byte_data_check(client, 0xeb, false);
3485 if (rev != 0x2012) {
3486 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3487 client->addr << 1, rev);
3491 if (pdata->chip_reset)
3494 /* control handlers */
3496 v4l2_ctrl_handler_init(hdl, 6);
3498 /* add in ascending ID order */
3499 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3500 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3501 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3502 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3503 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3504 V4L2_CID_SATURATION, 0, 255, 1, 128);
3505 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,
3506 V4L2_CID_HUE, 0, 128, 1, 0);
3507 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3508 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3509 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3511 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3513 /* custom controls */
3514 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3515 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);
3516 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,
3517 &adv7842_ctrl_analog_sampling_phase, NULL);
3518 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,
3519 &adv7842_ctrl_free_run_color_manual, NULL);
3520 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,
3521 &adv7842_ctrl_free_run_color, NULL);
3522 state->rgb_quantization_range_ctrl =
3523 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,
3524 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3525 0, V4L2_DV_RGB_RANGE_AUTO);
3526 sd->ctrl_handler = hdl;
3531 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3536 if (adv7842_register_clients(sd) < 0) {
3538 v4l2_err(sd, "failed to create all i2c clients\n");
3543 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3544 adv7842_delayed_work_enable_hotplug);
3546 sd->entity.function = MEDIA_ENT_F_DV_DECODER;
3547 state->pad.flags = MEDIA_PAD_FL_SOURCE;
3548 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
3550 goto err_work_queues;
3552 err = adv7842_core_init(sd);
3556 #if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)
3557 state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops,
3558 state, dev_name(&client->dev),
3559 CEC_CAP_DEFAULTS, ADV7842_MAX_ADDRS);
3560 err = PTR_ERR_OR_ZERO(state->cec_adap);
3565 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3566 client->addr << 1, client->adapter->name);
3570 media_entity_cleanup(&sd->entity);
3572 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3574 adv7842_unregister_clients(sd);
3576 v4l2_ctrl_handler_free(hdl);
3580 /* ----------------------------------------------------------------------- */
3582 static int adv7842_remove(struct i2c_client *client)
3584 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3585 struct adv7842_state *state = to_state(sd);
3587 adv7842_irq_enable(sd, false);
3588 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
3589 v4l2_device_unregister_subdev(sd);
3590 media_entity_cleanup(&sd->entity);
3591 adv7842_unregister_clients(sd);
3592 v4l2_ctrl_handler_free(sd->ctrl_handler);
3596 /* ----------------------------------------------------------------------- */
3598 static const struct i2c_device_id adv7842_id[] = {
3602 MODULE_DEVICE_TABLE(i2c, adv7842_id);
3604 /* ----------------------------------------------------------------------- */
3606 static struct i2c_driver adv7842_driver = {
3610 .probe = adv7842_probe,
3611 .remove = adv7842_remove,
3612 .id_table = adv7842_id,
3615 module_i2c_driver(adv7842_driver);