drivers/media/i2c/adv7604.c

   1 /*
   2  * adv7604 - Analog Devices ADV7604 video decoder driver
   3  *
   4  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
  24  *              Revision 2.5, June 2010
  25  * REF_02 - Analog devices, Register map documentation, Documentation of
  26  *              the register maps, Software manual, Rev. F, June 2010
  27  * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
  28  */
  29
  30 #include <linux/delay.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/hdmi.h>
  33 #include <linux/i2c.h>
  34 #include <linux/kernel.h>
  35 #include <linux/module.h>
  36 #include <linux/of_graph.h>
  37 #include <linux/slab.h>
  38 #include <linux/v4l2-dv-timings.h>
  39 #include <linux/videodev2.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/regmap.h>
  42
  43 #include <media/i2c/adv7604.h>
  44 #include <media/cec.h>
  45 #include <media/v4l2-ctrls.h>
  46 #include <media/v4l2-device.h>
  47 #include <media/v4l2-event.h>
  48 #include <media/v4l2-dv-timings.h>
  49 #include <media/v4l2-fwnode.h>
  50
  51 static int debug;
  52 module_param(debug, int, 0644);
  53 MODULE_PARM_DESC(debug, "debug level (0-2)");
  54
  55 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
  56 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  57 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  58 MODULE_LICENSE("GPL");
  59
  60 /* ADV7604 system clock frequency */
  61 #define ADV76XX_FSC (28636360)
  62
  63 #define ADV76XX_RGB_OUT                                 (1 << 1)
  64
  65 #define ADV76XX_OP_FORMAT_SEL_8BIT                      (0 << 0)
  66 #define ADV7604_OP_FORMAT_SEL_10BIT                     (1 << 0)
  67 #define ADV76XX_OP_FORMAT_SEL_12BIT                     (2 << 0)
  68
  69 #define ADV76XX_OP_MODE_SEL_SDR_422                     (0 << 5)
  70 #define ADV7604_OP_MODE_SEL_DDR_422                     (1 << 5)
  71 #define ADV76XX_OP_MODE_SEL_SDR_444                     (2 << 5)
  72 #define ADV7604_OP_MODE_SEL_DDR_444                     (3 << 5)
  73 #define ADV76XX_OP_MODE_SEL_SDR_422_2X                  (4 << 5)
  74 #define ADV7604_OP_MODE_SEL_ADI_CM                      (5 << 5)
  75
  76 #define ADV76XX_OP_CH_SEL_GBR                           (0 << 5)
  77 #define ADV76XX_OP_CH_SEL_GRB                           (1 << 5)
  78 #define ADV76XX_OP_CH_SEL_BGR                           (2 << 5)
  79 #define ADV76XX_OP_CH_SEL_RGB                           (3 << 5)
  80 #define ADV76XX_OP_CH_SEL_BRG                           (4 << 5)
  81 #define ADV76XX_OP_CH_SEL_RBG                           (5 << 5)
  82
  83 #define ADV76XX_OP_SWAP_CB_CR                           (1 << 0)
  84
  85 #define ADV76XX_MAX_ADDRS (3)
  86
  87 enum adv76xx_type {
  88         ADV7604,
  89         ADV7611,
  90         ADV7612,
  91 };
  92
  93 struct adv76xx_reg_seq {
  94         unsigned int reg;
  95         u8 val;
  96 };
  97
  98 struct adv76xx_format_info {
  99         u32 code;
 100         u8 op_ch_sel;
 101         bool rgb_out;
 102         bool swap_cb_cr;
 103         u8 op_format_sel;
 104 };
 105
 106 struct adv76xx_cfg_read_infoframe {
 107         const char *desc;
 108         u8 present_mask;
 109         u8 head_addr;
 110         u8 payload_addr;
 111 };
 112
 113 struct adv76xx_chip_info {
 114         enum adv76xx_type type;
 115
 116         bool has_afe;
 117         unsigned int max_port;
 118         unsigned int num_dv_ports;
 119
 120         unsigned int edid_enable_reg;
 121         unsigned int edid_status_reg;
 122         unsigned int lcf_reg;
 123
 124         unsigned int cable_det_mask;
 125         unsigned int tdms_lock_mask;
 126         unsigned int fmt_change_digital_mask;
 127         unsigned int cp_csc;
 128
 129         const struct adv76xx_format_info *formats;
 130         unsigned int nformats;
 131
 132         void (*set_termination)(struct v4l2_subdev *sd, bool enable);
 133         void (*setup_irqs)(struct v4l2_subdev *sd);
 134         unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
 135         unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
 136
 137         /* 0 = AFE, 1 = HDMI */
 138         const struct adv76xx_reg_seq *recommended_settings[2];
 139         unsigned int num_recommended_settings[2];
 140
 141         unsigned long page_mask;
 142
 143         /* Masks for timings */
 144         unsigned int linewidth_mask;
 145         unsigned int field0_height_mask;
 146         unsigned int field1_height_mask;
 147         unsigned int hfrontporch_mask;
 148         unsigned int hsync_mask;
 149         unsigned int hbackporch_mask;
 150         unsigned int field0_vfrontporch_mask;
 151         unsigned int field1_vfrontporch_mask;
 152         unsigned int field0_vsync_mask;
 153         unsigned int field1_vsync_mask;
 154         unsigned int field0_vbackporch_mask;
 155         unsigned int field1_vbackporch_mask;
 156 };
 157
 158 /*
 159  **********************************************************************
 160  *
 161  *  Arrays with configuration parameters for the ADV7604
 162  *
 163  **********************************************************************
 164  */
 165
 166 struct adv76xx_state {
 167         const struct adv76xx_chip_info *info;
 168         struct adv76xx_platform_data pdata;
 169
 170         struct gpio_desc *hpd_gpio[4];
 171         struct gpio_desc *reset_gpio;
 172
 173         struct v4l2_subdev sd;
 174         struct media_pad pads[ADV76XX_PAD_MAX];
 175         unsigned int source_pad;
 176
 177         struct v4l2_ctrl_handler hdl;
 178
 179         enum adv76xx_pad selected_input;
 180
 181         struct v4l2_dv_timings timings;
 182         const struct adv76xx_format_info *format;
 183
 184         struct {
 185                 u8 edid[256];
 186                 u32 present;
 187                 unsigned blocks;
 188         } edid;
 189         u16 spa_port_a[2];
 190         struct v4l2_fract aspect_ratio;
 191         u32 rgb_quantization_range;
 192         struct delayed_work delayed_work_enable_hotplug;
 193         bool restart_stdi_once;
 194
 195         /* CEC */
 196         struct cec_adapter *cec_adap;
 197         u8   cec_addr[ADV76XX_MAX_ADDRS];
 198         u8   cec_valid_addrs;
 199         bool cec_enabled_adap;
 200
 201         /* i2c clients */
 202         struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
 203
 204         /* Regmaps */
 205         struct regmap *regmap[ADV76XX_PAGE_MAX];
 206
 207         /* controls */
 208         struct v4l2_ctrl *detect_tx_5v_ctrl;
 209         struct v4l2_ctrl *analog_sampling_phase_ctrl;
 210         struct v4l2_ctrl *free_run_color_manual_ctrl;
 211         struct v4l2_ctrl *free_run_color_ctrl;
 212         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 213 };
 214
 215 static bool adv76xx_has_afe(struct adv76xx_state *state)
 216 {
 217         return state->info->has_afe;
 218 }
 219
 220 /* Unsupported timings. This device cannot support 720p30. */
 221 static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
 222         V4L2_DV_BT_CEA_1280X720P30,
 223         { }
 224 };
 225
 226 static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
 227 {
 228         int i;
 229
 230         for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
 231                 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
 232                         return false;
 233         return true;
 234 }
 235
 236 struct adv76xx_video_standards {
 237         struct v4l2_dv_timings timings;
 238         u8 vid_std;
 239         u8 v_freq;
 240 };
 241
 242 /* sorted by number of lines */
 243 static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
 244         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 245         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 246         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 247         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 248         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 249         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 250         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 251         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 252         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 253         /* TODO add 1920x1080P60_RB (CVT timing) */
 254         { },
 255 };
 256
 257 /* sorted by number of lines */
 258 static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
 259         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 260         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 261         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 262         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 263         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 264         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 265         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 266         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 267         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 268         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 269         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 270         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 271         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 272         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 273         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 274         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 275         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 276         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 277         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 278         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 279         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 280         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 281         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 282         { },
 283 };
 284
 285 /* sorted by number of lines */
 286 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
 287         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 288         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 289         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 290         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 291         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 292         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 293         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 294         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 295         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 296         { },
 297 };
 298
 299 /* sorted by number of lines */
 300 static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
 301         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 302         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 303         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 304         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 305         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 306         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 307         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 308         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 309         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 310         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 311         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 312         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 313         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 314         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 315         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 316         { },
 317 };
 318
 319 static const struct v4l2_event adv76xx_ev_fmt = {
 320         .type = V4L2_EVENT_SOURCE_CHANGE,
 321         .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
 322 };
 323
 324 /* ----------------------------------------------------------------------- */
 325
 326 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
 327 {
 328         return container_of(sd, struct adv76xx_state, sd);
 329 }
 330
 331 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 332 {
 333         return V4L2_DV_BT_FRAME_WIDTH(t);
 334 }
 335
 336 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 337 {
 338         return V4L2_DV_BT_FRAME_HEIGHT(t);
 339 }
 340
 341 /* ----------------------------------------------------------------------- */
 342
 343 static int adv76xx_read_check(struct adv76xx_state *state,
 344                              int client_page, u8 reg)
 345 {
 346         struct i2c_client *client = state->i2c_clients[client_page];
 347         int err;
 348         unsigned int val;
 349
 350         err = regmap_read(state->regmap[client_page], reg, &val);
 351
 352         if (err) {
 353                 v4l_err(client, "error reading %02x, %02x\n",
 354                                 client->addr, reg);
 355                 return err;
 356         }
 357         return val;
 358 }
 359
 360 /* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
 361  * size to one or more registers.
 362  *
 363  * A value of zero will be returned on success, a negative errno will
 364  * be returned in error cases.
 365  */
 366 static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
 367                               unsigned int init_reg, const void *val,
 368                               size_t val_len)
 369 {
 370         struct regmap *regmap = state->regmap[client_page];
 371
 372         if (val_len > I2C_SMBUS_BLOCK_MAX)
 373                 val_len = I2C_SMBUS_BLOCK_MAX;
 374
 375         return regmap_raw_write(regmap, init_reg, val, val_len);
 376 }
 377
 378 /* ----------------------------------------------------------------------- */
 379
 380 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 381 {
 382         struct adv76xx_state *state = to_state(sd);
 383
 384         return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
 385 }
 386
 387 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 388 {
 389         struct adv76xx_state *state = to_state(sd);
 390
 391         return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
 392 }
 393
 394 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
 395                                    u8 val)
 396 {
 397         return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
 398 }
 399
 400 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 401 {
 402         struct adv76xx_state *state = to_state(sd);
 403
 404         return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
 405 }
 406
 407 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 408 {
 409         struct adv76xx_state *state = to_state(sd);
 410
 411         return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
 412 }
 413
 414 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 415 {
 416         struct adv76xx_state *state = to_state(sd);
 417
 418         return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
 419 }
 420
 421 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 422 {
 423         struct adv76xx_state *state = to_state(sd);
 424
 425         return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
 426 }
 427
 428 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
 429                                    u8 val)
 430 {
 431         return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
 432 }
 433
 434 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 435 {
 436         struct adv76xx_state *state = to_state(sd);
 437
 438         return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
 439 }
 440
 441 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 442 {
 443         struct adv76xx_state *state = to_state(sd);
 444
 445         return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
 446 }
 447
 448 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 449 {
 450         struct adv76xx_state *state = to_state(sd);
 451
 452         return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
 453 }
 454
 455 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 456 {
 457         struct adv76xx_state *state = to_state(sd);
 458
 459         return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
 460 }
 461
 462 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 463 {
 464         struct adv76xx_state *state = to_state(sd);
 465
 466         return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
 467 }
 468
 469 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 470 {
 471         struct adv76xx_state *state = to_state(sd);
 472
 473         return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
 474 }
 475
 476 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 477 {
 478         return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
 479 }
 480
 481 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 482 {
 483         struct adv76xx_state *state = to_state(sd);
 484
 485         return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
 486 }
 487
 488 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 489 {
 490         struct adv76xx_state *state = to_state(sd);
 491
 492         return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
 493 }
 494
 495 static inline int edid_write_block(struct v4l2_subdev *sd,
 496                                         unsigned int total_len, const u8 *val)
 497 {
 498         struct adv76xx_state *state = to_state(sd);
 499         int err = 0;
 500         int i = 0;
 501         int len = 0;
 502
 503         v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
 504                                 __func__, total_len);
 505
 506         while (!err && i < total_len) {
 507                 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
 508                                 I2C_SMBUS_BLOCK_MAX :
 509                                 (total_len - i);
 510
 511                 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
 512                                 i, val + i, len);
 513                 i += len;
 514         }
 515
 516         return err;
 517 }
 518
 519 static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
 520 {
 521         unsigned int i;
 522
 523         for (i = 0; i < state->info->num_dv_ports; ++i)
 524                 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
 525
 526         v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
 527 }
 528
 529 static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
 530 {
 531         struct delayed_work *dwork = to_delayed_work(work);
 532         struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
 533                                                 delayed_work_enable_hotplug);
 534         struct v4l2_subdev *sd = &state->sd;
 535
 536         v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
 537
 538         adv76xx_set_hpd(state, state->edid.present);
 539 }
 540
 541 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 542 {
 543         struct adv76xx_state *state = to_state(sd);
 544
 545         return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
 546 }
 547
 548 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
 549 {
 550         return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
 551 }
 552
 553 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 554 {
 555         struct adv76xx_state *state = to_state(sd);
 556
 557         return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
 558 }
 559
 560 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 561 {
 562         return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
 563 }
 564
 565 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 566 {
 567         struct adv76xx_state *state = to_state(sd);
 568
 569         return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
 570 }
 571
 572 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 573 {
 574         struct adv76xx_state *state = to_state(sd);
 575
 576         return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
 577 }
 578
 579 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
 580 {
 581         return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
 582 }
 583
 584 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 585 {
 586         struct adv76xx_state *state = to_state(sd);
 587
 588         return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
 589 }
 590
 591 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 592 {
 593         return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
 594 }
 595
 596 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 597 {
 598         struct adv76xx_state *state = to_state(sd);
 599
 600         return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
 601 }
 602
 603 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 604 {
 605         struct adv76xx_state *state = to_state(sd);
 606
 607         return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
 608 }
 609
 610 #define ADV76XX_REG(page, offset)       (((page) << 8) | (offset))
 611 #define ADV76XX_REG_SEQ_TERM            0xffff
 612
 613 #ifdef CONFIG_VIDEO_ADV_DEBUG
 614 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
 615 {
 616         struct adv76xx_state *state = to_state(sd);
 617         unsigned int page = reg >> 8;
 618         unsigned int val;
 619         int err;
 620
 621         if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
 622                 return -EINVAL;
 623
 624         reg &= 0xff;
 625         err = regmap_read(state->regmap[page], reg, &val);
 626
 627         return err ? err : val;
 628 }
 629 #endif
 630
 631 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
 632 {
 633         struct adv76xx_state *state = to_state(sd);
 634         unsigned int page = reg >> 8;
 635
 636         if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
 637                 return -EINVAL;
 638
 639         reg &= 0xff;
 640
 641         return regmap_write(state->regmap[page], reg, val);
 642 }
 643
 644 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
 645                                   const struct adv76xx_reg_seq *reg_seq)
 646 {
 647         unsigned int i;
 648
 649         for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
 650                 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
 651 }
 652
 653 /* -----------------------------------------------------------------------------
 654  * Format helpers
 655  */
 656
 657 static const struct adv76xx_format_info adv7604_formats[] = {
 658         { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
 659           ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
 660         { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
 661           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 662         { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
 663           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 664         { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
 665           ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
 666         { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
 667           ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
 668         { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
 669           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 670         { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
 671           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 672         { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
 673           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 674         { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
 675           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 676         { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
 677           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 678         { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
 679           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 680         { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
 681           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 682         { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
 683           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 684         { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
 685           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 686         { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
 687           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 688         { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
 689           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 690         { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
 691           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 692         { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
 693           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 694         { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
 695           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 696 };
 697
 698 static const struct adv76xx_format_info adv7611_formats[] = {
 699         { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
 700           ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
 701         { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
 702           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 703         { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
 704           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 705         { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
 706           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 707         { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
 708           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
 709         { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
 710           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 711         { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
 712           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 713         { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
 714           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 715         { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
 716           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 717         { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
 718           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 719         { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
 720           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 721         { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
 722           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 723         { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
 724           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
 725 };
 726
 727 static const struct adv76xx_format_info adv7612_formats[] = {
 728         { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
 729           ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
 730         { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
 731           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 732         { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
 733           ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
 734         { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
 735           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 736         { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
 737           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 738         { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
 739           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 740         { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
 741           ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
 742 };
 743
 744 static const struct adv76xx_format_info *
 745 adv76xx_format_info(struct adv76xx_state *state, u32 code)
 746 {
 747         unsigned int i;
 748
 749         for (i = 0; i < state->info->nformats; ++i) {
 750                 if (state->info->formats[i].code == code)
 751                         return &state->info->formats[i];
 752         }
 753
 754         return NULL;
 755 }
 756
 757 /* ----------------------------------------------------------------------- */
 758
 759 static inline bool is_analog_input(struct v4l2_subdev *sd)
 760 {
 761         struct adv76xx_state *state = to_state(sd);
 762
 763         return state->selected_input == ADV7604_PAD_VGA_RGB ||
 764                state->selected_input == ADV7604_PAD_VGA_COMP;
 765 }
 766
 767 static inline bool is_digital_input(struct v4l2_subdev *sd)
 768 {
 769         struct adv76xx_state *state = to_state(sd);
 770
 771         return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
 772                state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
 773                state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
 774                state->selected_input == ADV7604_PAD_HDMI_PORT_D;
 775 }
 776
 777 static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
 778         .type = V4L2_DV_BT_656_1120,
 779         /* keep this initialization for compatibility with GCC < 4.4.6 */
 780         .reserved = { 0 },
 781         V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
 782                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 783                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 784                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 785                         V4L2_DV_BT_CAP_CUSTOM)
 786 };
 787
 788 static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
 789         .type = V4L2_DV_BT_656_1120,
 790         /* keep this initialization for compatibility with GCC < 4.4.6 */
 791         .reserved = { 0 },
 792         V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
 793                 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 794                         V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 795                 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 796                         V4L2_DV_BT_CAP_CUSTOM)
 797 };
 798
 799 /*
 800  * Return the DV timings capabilities for the requested sink pad. As a special
 801  * case, pad value -1 returns the capabilities for the currently selected input.
 802  */
 803 static const struct v4l2_dv_timings_cap *
 804 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad)
 805 {
 806         if (pad == -1) {
 807                 struct adv76xx_state *state = to_state(sd);
 808
 809                 pad = state->selected_input;
 810         }
 811
 812         switch (pad) {
 813         case ADV76XX_PAD_HDMI_PORT_A:
 814         case ADV7604_PAD_HDMI_PORT_B:
 815         case ADV7604_PAD_HDMI_PORT_C:
 816         case ADV7604_PAD_HDMI_PORT_D:
 817                 return &adv76xx_timings_cap_digital;
 818
 819         case ADV7604_PAD_VGA_RGB:
 820         case ADV7604_PAD_VGA_COMP:
 821         default:
 822                 return &adv7604_timings_cap_analog;
 823         }
 824 }
 825
 826
 827 /* ----------------------------------------------------------------------- */
 828
 829 #ifdef CONFIG_VIDEO_ADV_DEBUG
 830 static void adv76xx_inv_register(struct v4l2_subdev *sd)
 831 {
 832         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 833         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 834         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 835         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 836         v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
 837         v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
 838         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 839         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 840         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 841         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 842         v4l2_info(sd, "0xa00-0xaff: Test Map\n");
 843         v4l2_info(sd, "0xb00-0xbff: CP Map\n");
 844         v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
 845 }
 846
 847 static int adv76xx_g_register(struct v4l2_subdev *sd,
 848                                         struct v4l2_dbg_register *reg)
 849 {
 850         int ret;
 851
 852         ret = adv76xx_read_reg(sd, reg->reg);
 853         if (ret < 0) {
 854                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 855                 adv76xx_inv_register(sd);
 856                 return ret;
 857         }
 858
 859         reg->size = 1;
 860         reg->val = ret;
 861
 862         return 0;
 863 }
 864
 865 static int adv76xx_s_register(struct v4l2_subdev *sd,
 866                                         const struct v4l2_dbg_register *reg)
 867 {
 868         int ret;
 869
 870         ret = adv76xx_write_reg(sd, reg->reg, reg->val);
 871         if (ret < 0) {
 872                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 873                 adv76xx_inv_register(sd);
 874                 return ret;
 875         }
 876
 877         return 0;
 878 }
 879 #endif
 880
 881 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
 882 {
 883         u8 value = io_read(sd, 0x6f);
 884
 885         return ((value & 0x10) >> 4)
 886              | ((value & 0x08) >> 2)
 887              | ((value & 0x04) << 0)
 888              | ((value & 0x02) << 2);
 889 }
 890
 891 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
 892 {
 893         u8 value = io_read(sd, 0x6f);
 894
 895         return value & 1;
 896 }
 897
 898 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
 899 {
 900         /*  Reads CABLE_DET_A_RAW. For input B support, need to
 901          *  account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW)
 902          */
 903         u8 value = io_read(sd, 0x6f);
 904
 905         return value & 1;
 906 }
 907
 908 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 909 {
 910         struct adv76xx_state *state = to_state(sd);
 911         const struct adv76xx_chip_info *info = state->info;
 912         u16 cable_det = info->read_cable_det(sd);
 913
 914         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
 915 }
 916
 917 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 918                 u8 prim_mode,
 919                 const struct adv76xx_video_standards *predef_vid_timings,
 920                 const struct v4l2_dv_timings *timings)
 921 {
 922         int i;
 923
 924         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 925                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 926                                 is_digital_input(sd) ? 250000 : 1000000, false))
 927                         continue;
 928                 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
 929                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
 930                                 prim_mode); /* v_freq and prim mode */
 931                 return 0;
 932         }
 933
 934         return -1;
 935 }
 936
 937 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 938                 struct v4l2_dv_timings *timings)
 939 {
 940         struct adv76xx_state *state = to_state(sd);
 941         int err;
 942
 943         v4l2_dbg(1, debug, sd, "%s", __func__);
 944
 945         if (adv76xx_has_afe(state)) {
 946                 /* reset to default values */
 947                 io_write(sd, 0x16, 0x43);
 948                 io_write(sd, 0x17, 0x5a);
 949         }
 950         /* disable embedded syncs for auto graphics mode */
 951         cp_write_clr_set(sd, 0x81, 0x10, 0x00);
 952         cp_write(sd, 0x8f, 0x00);
 953         cp_write(sd, 0x90, 0x00);
 954         cp_write(sd, 0xa2, 0x00);
 955         cp_write(sd, 0xa3, 0x00);
 956         cp_write(sd, 0xa4, 0x00);
 957         cp_write(sd, 0xa5, 0x00);
 958         cp_write(sd, 0xa6, 0x00);
 959         cp_write(sd, 0xa7, 0x00);
 960         cp_write(sd, 0xab, 0x00);
 961         cp_write(sd, 0xac, 0x00);
 962
 963         if (is_analog_input(sd)) {
 964                 err = find_and_set_predefined_video_timings(sd,
 965                                 0x01, adv7604_prim_mode_comp, timings);
 966                 if (err)
 967                         err = find_and_set_predefined_video_timings(sd,
 968                                         0x02, adv7604_prim_mode_gr, timings);
 969         } else if (is_digital_input(sd)) {
 970                 err = find_and_set_predefined_video_timings(sd,
 971                                 0x05, adv76xx_prim_mode_hdmi_comp, timings);
 972                 if (err)
 973                         err = find_and_set_predefined_video_timings(sd,
 974                                         0x06, adv76xx_prim_mode_hdmi_gr, timings);
 975         } else {
 976                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 977                                 __func__, state->selected_input);
 978                 err = -1;
 979         }
 980
 981
 982         return err;
 983 }
 984
 985 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 986                 const struct v4l2_bt_timings *bt)
 987 {
 988         struct adv76xx_state *state = to_state(sd);
 989         u32 width = htotal(bt);
 990         u32 height = vtotal(bt);
 991         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 992         u16 cp_start_eav = width - bt->hfrontporch;
 993         u16 cp_start_vbi = height - bt->vfrontporch;
 994         u16 cp_end_vbi = bt->vsync + bt->vbackporch;
 995         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 996                 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 997         const u8 pll[2] = {
 998                 0xc0 | ((width >> 8) & 0x1f),
 999                 width & 0xff
1000         };
1001
1002         v4l2_dbg(2, debug, sd, "%s\n", __func__);
1003
1004         if (is_analog_input(sd)) {
1005                 /* auto graphics */
1006                 io_write(sd, 0x00, 0x07); /* video std */
1007                 io_write(sd, 0x01, 0x02); /* prim mode */
1008                 /* enable embedded syncs for auto graphics mode */
1009                 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
1010
1011                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1012                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1013                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1014                 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
1015                                         0x16, pll, 2))
1016                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1017
1018                 /* active video - horizontal timing */
1019                 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
1020                 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
1021                                    ((cp_start_eav >> 8) & 0x0f));
1022                 cp_write(sd, 0xa4, cp_start_eav & 0xff);
1023
1024                 /* active video - vertical timing */
1025                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1026                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1027                                    ((cp_end_vbi >> 8) & 0xf));
1028                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1029         } else if (is_digital_input(sd)) {
1030                 /* set default prim_mode/vid_std for HDMI
1031                    according to [REF_03, c. 4.2] */
1032                 io_write(sd, 0x00, 0x02); /* video std */
1033                 io_write(sd, 0x01, 0x06); /* prim mode */
1034         } else {
1035                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1036                                 __func__, state->selected_input);
1037         }
1038
1039         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1040         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1041         cp_write(sd, 0xab, (height >> 4) & 0xff);
1042         cp_write(sd, 0xac, (height & 0x0f) << 4);
1043 }
1044
1045 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1046 {
1047         struct adv76xx_state *state = to_state(sd);
1048         u8 offset_buf[4];
1049
1050         if (auto_offset) {
1051                 offset_a = 0x3ff;
1052                 offset_b = 0x3ff;
1053                 offset_c = 0x3ff;
1054         }
1055
1056         v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1057                         __func__, auto_offset ? "Auto" : "Manual",
1058                         offset_a, offset_b, offset_c);
1059
1060         offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1061         offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1062         offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1063         offset_buf[3] = offset_c & 0x0ff;
1064
1065         /* Registers must be written in this order with no i2c access in between */
1066         if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1067                         0x77, offset_buf, 4))
1068                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1069 }
1070
1071 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1072 {
1073         struct adv76xx_state *state = to_state(sd);
1074         u8 gain_buf[4];
1075         u8 gain_man = 1;
1076         u8 agc_mode_man = 1;
1077
1078         if (auto_gain) {
1079                 gain_man = 0;
1080                 agc_mode_man = 0;
1081                 gain_a = 0x100;
1082                 gain_b = 0x100;
1083                 gain_c = 0x100;
1084         }
1085
1086         v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1087                         __func__, auto_gain ? "Auto" : "Manual",
1088                         gain_a, gain_b, gain_c);
1089
1090         gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1091         gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1092         gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1093         gain_buf[3] = ((gain_c & 0x0ff));
1094
1095         /* Registers must be written in this order with no i2c access in between */
1096         if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1097                              0x73, gain_buf, 4))
1098                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1099 }
1100
1101 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1102 {
1103         struct adv76xx_state *state = to_state(sd);
1104         bool rgb_output = io_read(sd, 0x02) & 0x02;
1105         bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1106         u8 y = HDMI_COLORSPACE_RGB;
1107
1108         if (hdmi_signal && (io_read(sd, 0x60) & 1))
1109                 y = infoframe_read(sd, 0x01) >> 5;
1110
1111         v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1112                         __func__, state->rgb_quantization_range,
1113                         rgb_output, hdmi_signal);
1114
1115         adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1116         adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1117         io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1118
1119         switch (state->rgb_quantization_range) {
1120         case V4L2_DV_RGB_RANGE_AUTO:
1121                 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1122                         /* Receiving analog RGB signal
1123                          * Set RGB full range (0-255) */
1124                         io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1125                         break;
1126                 }
1127
1128                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1129                         /* Receiving analog YPbPr signal
1130                          * Set automode */
1131                         io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1132                         break;
1133                 }
1134
1135                 if (hdmi_signal) {
1136                         /* Receiving HDMI signal
1137                          * Set automode */
1138                         io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1139                         break;
1140                 }
1141
1142                 /* Receiving DVI-D signal
1143                  * ADV7604 selects RGB limited range regardless of
1144                  * input format (CE/IT) in automatic mode */
1145                 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1146                         /* RGB limited range (16-235) */
1147                         io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1148                 } else {
1149                         /* RGB full range (0-255) */
1150                         io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1151
1152                         if (is_digital_input(sd) && rgb_output) {
1153                                 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1154                         } else {
1155                                 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1156                                 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1157                         }
1158                 }
1159                 break;
1160         case V4L2_DV_RGB_RANGE_LIMITED:
1161                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1162                         /* YCrCb limited range (16-235) */
1163                         io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1164                         break;
1165                 }
1166
1167                 if (y != HDMI_COLORSPACE_RGB)
1168                         break;
1169
1170                 /* RGB limited range (16-235) */
1171                 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1172
1173                 break;
1174         case V4L2_DV_RGB_RANGE_FULL:
1175                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1176                         /* YCrCb full range (0-255) */
1177                         io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1178                         break;
1179                 }
1180
1181                 if (y != HDMI_COLORSPACE_RGB)
1182                         break;
1183
1184                 /* RGB full range (0-255) */
1185                 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1186
1187                 if (is_analog_input(sd) || hdmi_signal)
1188                         break;
1189
1190                 /* Adjust gain/offset for DVI-D signals only */
1191                 if (rgb_output) {
1192                         adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1193                 } else {
1194                         adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1195                         adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1196                 }
1197                 break;
1198         }
1199 }
1200
1201 static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1202 {
1203         struct v4l2_subdev *sd =
1204                 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1205
1206         struct adv76xx_state *state = to_state(sd);
1207
1208         switch (ctrl->id) {
1209         case V4L2_CID_BRIGHTNESS:
1210                 cp_write(sd, 0x3c, ctrl->val);
1211                 return 0;
1212         case V4L2_CID_CONTRAST:
1213                 cp_write(sd, 0x3a, ctrl->val);
1214                 return 0;
1215         case V4L2_CID_SATURATION:
1216                 cp_write(sd, 0x3b, ctrl->val);
1217                 return 0;
1218         case V4L2_CID_HUE:
1219                 cp_write(sd, 0x3d, ctrl->val);
1220                 return 0;
1221         case  V4L2_CID_DV_RX_RGB_RANGE:
1222                 state->rgb_quantization_range = ctrl->val;
1223                 set_rgb_quantization_range(sd);
1224                 return 0;
1225         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1226                 if (!adv76xx_has_afe(state))
1227                         return -EINVAL;
1228                 /* Set the analog sampling phase. This is needed to find the
1229                    best sampling phase for analog video: an application or
1230                    driver has to try a number of phases and analyze the picture
1231                    quality before settling on the best performing phase. */
1232                 afe_write(sd, 0xc8, ctrl->val);
1233                 return 0;
1234         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1235                 /* Use the default blue color for free running mode,
1236                    or supply your own. */
1237                 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1238                 return 0;
1239         case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1240                 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1241                 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1242                 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1243                 return 0;
1244         }
1245         return -EINVAL;
1246 }
1247
1248 static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1249 {
1250         struct v4l2_subdev *sd =
1251                 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1252
1253         if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1254                 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1255                 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1256                         ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1257                 return 0;
1258         }
1259         return -EINVAL;
1260 }
1261
1262 /* ----------------------------------------------------------------------- */
1263
1264 static inline bool no_power(struct v4l2_subdev *sd)
1265 {
1266         /* Entire chip or CP powered off */
1267         return io_read(sd, 0x0c) & 0x24;
1268 }
1269
1270 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1271 {
1272         struct adv76xx_state *state = to_state(sd);
1273
1274         return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1275 }
1276
1277 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1278 {
1279         struct adv76xx_state *state = to_state(sd);
1280         const struct adv76xx_chip_info *info = state->info;
1281
1282         return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1283 }
1284
1285 static inline bool is_hdmi(struct v4l2_subdev *sd)
1286 {
1287         return hdmi_read(sd, 0x05) & 0x80;
1288 }
1289
1290 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1291 {
1292         struct adv76xx_state *state = to_state(sd);
1293
1294         /*
1295          * Chips without a AFE don't expose registers for the SSPD, so just assume
1296          * that we have a lock.
1297          */
1298         if (adv76xx_has_afe(state))
1299                 return false;
1300
1301         /* TODO channel 2 */
1302         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1303 }
1304
1305 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1306 {
1307         /* TODO channel 2 */
1308         return !(cp_read(sd, 0xb1) & 0x80);
1309 }
1310
1311 static inline bool no_signal(struct v4l2_subdev *sd)
1312 {
1313         bool ret;
1314
1315         ret = no_power(sd);
1316
1317         ret |= no_lock_stdi(sd);
1318         ret |= no_lock_sspd(sd);
1319
1320         if (is_digital_input(sd)) {
1321                 ret |= no_lock_tmds(sd);
1322                 ret |= no_signal_tmds(sd);
1323         }
1324
1325         return ret;
1326 }
1327
1328 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1329 {
1330         struct adv76xx_state *state = to_state(sd);
1331
1332         if (!adv76xx_has_afe(state))
1333                 return false;
1334
1335         /* CP has detected a non standard number of lines on the incoming
1336            video compared to what it is configured to receive by s_dv_timings */
1337         return io_read(sd, 0x12) & 0x01;
1338 }
1339
1340 static inline bool in_free_run(struct v4l2_subdev *sd)
1341 {
1342         return cp_read(sd, 0xff) & 0x10;
1343 }
1344
1345 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1346 {
1347         *status = 0;
1348         *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1349         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1350         if (!in_free_run(sd) && no_lock_cp(sd))
1351                 *status |= is_digital_input(sd) ?
1352                            V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1353
1354         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1355
1356         return 0;
1357 }
1358
1359 /* ----------------------------------------------------------------------- */
1360
1361 struct stdi_readback {
1362         u16 bl, lcf, lcvs;
1363         u8 hs_pol, vs_pol;
1364         bool interlaced;
1365 };
1366
1367 static int stdi2dv_timings(struct v4l2_subdev *sd,
1368                 struct stdi_readback *stdi,
1369                 struct v4l2_dv_timings *timings)
1370 {
1371         struct adv76xx_state *state = to_state(sd);
1372         u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1373         u32 pix_clk;
1374         int i;
1375
1376         for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1377                 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1378
1379                 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1380                                            adv76xx_get_dv_timings_cap(sd, -1),
1381                                            adv76xx_check_dv_timings, NULL))
1382                         continue;
1383                 if (vtotal(bt) != stdi->lcf + 1)
1384                         continue;
1385                 if (bt->vsync != stdi->lcvs)
1386                         continue;
1387
1388                 pix_clk = hfreq * htotal(bt);
1389
1390                 if ((pix_clk < bt->pixelclock + 1000000) &&
1391                     (pix_clk > bt->pixelclock - 1000000)) {
1392                         *timings = v4l2_dv_timings_presets[i];
1393                         return 0;
1394                 }
1395         }
1396
1397         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1398                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1399                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1400                         false, timings))
1401                 return 0;
1402         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1403                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1404                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1405                         false, state->aspect_ratio, timings))
1406                 return 0;
1407
1408         v4l2_dbg(2, debug, sd,
1409                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1410                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1411                 stdi->hs_pol, stdi->vs_pol);
1412         return -1;
1413 }
1414
1415
1416 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1417 {
1418         struct adv76xx_state *state = to_state(sd);
1419         const struct adv76xx_chip_info *info = state->info;
1420         u8 polarity;
1421
1422         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1423                 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1424                 return -1;
1425         }
1426
1427         /* read STDI */
1428         stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1429         stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1430         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1431         stdi->interlaced = io_read(sd, 0x12) & 0x10;
1432
1433         if (adv76xx_has_afe(state)) {
1434                 /* read SSPD */
1435                 polarity = cp_read(sd, 0xb5);
1436                 if ((polarity & 0x03) == 0x01) {
1437                         stdi->hs_pol = polarity & 0x10
1438                                      ? (polarity & 0x08 ? '+' : '-') : 'x';
1439                         stdi->vs_pol = polarity & 0x40
1440                                      ? (polarity & 0x20 ? '+' : '-') : 'x';
1441                 } else {
1442                         stdi->hs_pol = 'x';
1443                         stdi->vs_pol = 'x';
1444                 }
1445         } else {
1446                 polarity = hdmi_read(sd, 0x05);
1447                 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1448                 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1449         }
1450
1451         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1452                 v4l2_dbg(2, debug, sd,
1453                         "%s: signal lost during readout of STDI/SSPD\n", __func__);
1454                 return -1;
1455         }
1456
1457         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1458                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1459                 memset(stdi, 0, sizeof(struct stdi_readback));
1460                 return -1;
1461         }
1462
1463         v4l2_dbg(2, debug, sd,
1464                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1465                 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1466                 stdi->hs_pol, stdi->vs_pol,
1467                 stdi->interlaced ? "interlaced" : "progressive");
1468
1469         return 0;
1470 }
1471
1472 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1473                         struct v4l2_enum_dv_timings *timings)
1474 {
1475         struct adv76xx_state *state = to_state(sd);
1476
1477         if (timings->pad >= state->source_pad)
1478                 return -EINVAL;
1479
1480         return v4l2_enum_dv_timings_cap(timings,
1481                 adv76xx_get_dv_timings_cap(sd, timings->pad),
1482                 adv76xx_check_dv_timings, NULL);
1483 }
1484
1485 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1486                         struct v4l2_dv_timings_cap *cap)
1487 {
1488         struct adv76xx_state *state = to_state(sd);
1489         unsigned int pad = cap->pad;
1490
1491         if (cap->pad >= state->source_pad)
1492                 return -EINVAL;
1493
1494         *cap = *adv76xx_get_dv_timings_cap(sd, pad);
1495         cap->pad = pad;
1496
1497         return 0;
1498 }
1499
1500 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1501    if the format is listed in adv76xx_timings[] */
1502 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1503                 struct v4l2_dv_timings *timings)
1504 {
1505         v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1),
1506                                  is_digital_input(sd) ? 250000 : 1000000,
1507                                  adv76xx_check_dv_timings, NULL);
1508 }
1509
1510 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1511 {
1512         unsigned int freq;
1513         int a, b;
1514
1515         a = hdmi_read(sd, 0x06);
1516         b = hdmi_read(sd, 0x3b);
1517         if (a < 0 || b < 0)
1518                 return 0;
1519         freq =  a * 1000000 + ((b & 0x30) >> 4) * 250000;
1520
1521         if (is_hdmi(sd)) {
1522                 /* adjust for deep color mode */
1523                 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1524
1525                 freq = freq * 8 / bits_per_channel;
1526         }
1527
1528         return freq;
1529 }
1530
1531 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1532 {
1533         int a, b;
1534
1535         a = hdmi_read(sd, 0x51);
1536         b = hdmi_read(sd, 0x52);
1537         if (a < 0 || b < 0)
1538                 return 0;
1539         return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1540 }
1541
1542 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1543                         struct v4l2_dv_timings *timings)
1544 {
1545         struct adv76xx_state *state = to_state(sd);
1546         const struct adv76xx_chip_info *info = state->info;
1547         struct v4l2_bt_timings *bt = &timings->bt;
1548         struct stdi_readback stdi;
1549
1550         if (!timings)
1551                 return -EINVAL;
1552
1553         memset(timings, 0, sizeof(struct v4l2_dv_timings));
1554
1555         if (no_signal(sd)) {
1556                 state->restart_stdi_once = true;
1557                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1558                 return -ENOLINK;
1559         }
1560
1561         /* read STDI */
1562         if (read_stdi(sd, &stdi)) {
1563                 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1564                 return -ENOLINK;
1565         }
1566         bt->interlaced = stdi.interlaced ?
1567                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1568
1569         if (is_digital_input(sd)) {
1570                 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1571                 u8 vic = 0;
1572                 u32 w, h;
1573
1574                 w = hdmi_read16(sd, 0x07, info->linewidth_mask);
1575                 h = hdmi_read16(sd, 0x09, info->field0_height_mask);
1576
1577                 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1578                         vic = infoframe_read(sd, 0x04);
1579
1580                 if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) &&
1581                     bt->width == w && bt->height == h)
1582                         goto found;
1583
1584                 timings->type = V4L2_DV_BT_656_1120;
1585
1586                 bt->width = w;
1587                 bt->height = h;
1588                 bt->pixelclock = info->read_hdmi_pixelclock(sd);
1589                 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1590                 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1591                 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1592                 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1593                         info->field0_vfrontporch_mask) / 2;
1594                 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1595                 bt->vbackporch = hdmi_read16(sd, 0x32,
1596                         info->field0_vbackporch_mask) / 2;
1597                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1598                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1599                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1600                         bt->height += hdmi_read16(sd, 0x0b,
1601                                 info->field1_height_mask);
1602                         bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1603                                 info->field1_vfrontporch_mask) / 2;
1604                         bt->il_vsync = hdmi_read16(sd, 0x30,
1605                                 info->field1_vsync_mask) / 2;
1606                         bt->il_vbackporch = hdmi_read16(sd, 0x34,
1607                                 info->field1_vbackporch_mask) / 2;
1608                 }
1609                 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1610         } else {
1611                 /* find format
1612                  * Since LCVS values are inaccurate [REF_03, p. 275-276],
1613                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1614                  */
1615                 if (!stdi2dv_timings(sd, &stdi, timings))
1616                         goto found;
1617                 stdi.lcvs += 1;
1618                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1619                 if (!stdi2dv_timings(sd, &stdi, timings))
1620                         goto found;
1621                 stdi.lcvs -= 2;
1622                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1623                 if (stdi2dv_timings(sd, &stdi, timings)) {
1624                         /*
1625                          * The STDI block may measure wrong values, especially
1626                          * for lcvs and lcf. If the driver can not find any
1627                          * valid timing, the STDI block is restarted to measure
1628                          * the video timings again. The function will return an
1629                          * error, but the restart of STDI will generate a new
1630                          * STDI interrupt and the format detection process will
1631                          * restart.
1632                          */
1633                         if (state->restart_stdi_once) {
1634                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1635                                 /* TODO restart STDI for Sync Channel 2 */
1636                                 /* enter one-shot mode */
1637                                 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1638                                 /* trigger STDI restart */
1639                                 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1640                                 /* reset to continuous mode */
1641                                 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1642                                 state->restart_stdi_once = false;
1643                                 return -ENOLINK;
1644                         }
1645                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1646                         return -ERANGE;
1647                 }
1648                 state->restart_stdi_once = true;
1649         }
1650 found:
1651
1652         if (no_signal(sd)) {
1653                 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1654                 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1655                 return -ENOLINK;
1656         }
1657
1658         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1659                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1660                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1661                                 __func__, (u32)bt->pixelclock);
1662                 return -ERANGE;
1663         }
1664
1665         if (debug > 1)
1666                 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1667                                       timings, true);
1668
1669         return 0;
1670 }
1671
1672 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1673                 struct v4l2_dv_timings *timings)
1674 {
1675         struct adv76xx_state *state = to_state(sd);
1676         struct v4l2_bt_timings *bt;
1677         int err;
1678
1679         if (!timings)
1680                 return -EINVAL;
1681
1682         if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1683                 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1684                 return 0;
1685         }
1686
1687         bt = &timings->bt;
1688
1689         if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1),
1690                                    adv76xx_check_dv_timings, NULL))
1691                 return -ERANGE;
1692
1693         adv76xx_fill_optional_dv_timings_fields(sd, timings);
1694
1695         state->timings = *timings;
1696
1697         cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1698
1699         /* Use prim_mode and vid_std when available */
1700         err = configure_predefined_video_timings(sd, timings);
1701         if (err) {
1702                 /* custom settings when the video format
1703                  does not have prim_mode/vid_std */
1704                 configure_custom_video_timings(sd, bt);
1705         }
1706
1707         set_rgb_quantization_range(sd);
1708
1709         if (debug > 1)
1710                 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1711                                       timings, true);
1712         return 0;
1713 }
1714
1715 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1716                 struct v4l2_dv_timings *timings)
1717 {
1718         struct adv76xx_state *state = to_state(sd);
1719
1720         *timings = state->timings;
1721         return 0;
1722 }
1723
1724 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1725 {
1726         hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1727 }
1728
1729 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1730 {
1731         hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1732 }
1733
1734 static void enable_input(struct v4l2_subdev *sd)
1735 {
1736         struct adv76xx_state *state = to_state(sd);
1737
1738         if (is_analog_input(sd)) {
1739                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1740         } else if (is_digital_input(sd)) {
1741                 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1742                 state->info->set_termination(sd, true);
1743                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1744                 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1745         } else {
1746                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1747                                 __func__, state->selected_input);
1748         }
1749 }
1750
1751 static void disable_input(struct v4l2_subdev *sd)
1752 {
1753         struct adv76xx_state *state = to_state(sd);
1754
1755         hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1756         msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1757         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1758         state->info->set_termination(sd, false);
1759 }
1760
1761 static void select_input(struct v4l2_subdev *sd)
1762 {
1763         struct adv76xx_state *state = to_state(sd);
1764         const struct adv76xx_chip_info *info = state->info;
1765
1766         if (is_analog_input(sd)) {
1767                 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1768
1769                 afe_write(sd, 0x00, 0x08); /* power up ADC */
1770                 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1771                 afe_write(sd, 0xc8, 0x00); /* phase control */
1772         } else if (is_digital_input(sd)) {
1773                 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1774
1775                 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1776
1777                 if (adv76xx_has_afe(state)) {
1778                         afe_write(sd, 0x00, 0xff); /* power down ADC */
1779                         afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1780                         afe_write(sd, 0xc8, 0x40); /* phase control */
1781                 }
1782
1783                 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1784                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1785                 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1786         } else {
1787                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1788                                 __func__, state->selected_input);
1789         }
1790 }
1791
1792 static int adv76xx_s_routing(struct v4l2_subdev *sd,
1793                 u32 input, u32 output, u32 config)
1794 {
1795         struct adv76xx_state *state = to_state(sd);
1796
1797         v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1798                         __func__, input, state->selected_input);
1799
1800         if (input == state->selected_input)
1801                 return 0;
1802
1803         if (input > state->info->max_port)
1804                 return -EINVAL;
1805
1806         state->selected_input = input;
1807
1808         disable_input(sd);
1809         select_input(sd);
1810         enable_input(sd);
1811
1812         v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1813
1814         return 0;
1815 }
1816
1817 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1818                                   struct v4l2_subdev_pad_config *cfg,
1819                                   struct v4l2_subdev_mbus_code_enum *code)
1820 {
1821         struct adv76xx_state *state = to_state(sd);
1822
1823         if (code->index >= state->info->nformats)
1824                 return -EINVAL;
1825
1826         code->code = state->info->formats[code->index].code;
1827
1828         return 0;
1829 }
1830
1831 static void adv76xx_fill_format(struct adv76xx_state *state,
1832                                 struct v4l2_mbus_framefmt *format)
1833 {
1834         memset(format, 0, sizeof(*format));
1835
1836         format->width = state->timings.bt.width;
1837         format->height = state->timings.bt.height;
1838         format->field = V4L2_FIELD_NONE;
1839         format->colorspace = V4L2_COLORSPACE_SRGB;
1840
1841         if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1842                 format->colorspace = (state->timings.bt.height <= 576) ?
1843                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1844 }
1845
1846 /*
1847  * Compute the op_ch_sel value required to obtain on the bus the component order
1848  * corresponding to the selected format taking into account bus reordering
1849  * applied by the board at the output of the device.
1850  *
1851  * The following table gives the op_ch_value from the format component order
1852  * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1853  * adv76xx_bus_order value in row).
1854  *
1855  *           |  GBR(0)  GRB(1)  BGR(2)  RGB(3)  BRG(4)  RBG(5)
1856  * ----------+-------------------------------------------------
1857  * RGB (NOP) |  GBR     GRB     BGR     RGB     BRG     RBG
1858  * GRB (1-2) |  BGR     RGB     GBR     GRB     RBG     BRG
1859  * RBG (2-3) |  GRB     GBR     BRG     RBG     BGR     RGB
1860  * BGR (1-3) |  RBG     BRG     RGB     BGR     GRB     GBR
1861  * BRG (ROR) |  BRG     RBG     GRB     GBR     RGB     BGR
1862  * GBR (ROL) |  RGB     BGR     RBG     BRG     GBR     GRB
1863  */
1864 static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1865 {
1866 #define _SEL(a,b,c,d,e,f)       { \
1867         ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1868         ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1869 #define _BUS(x)                 [ADV7604_BUS_ORDER_##x]
1870
1871         static const unsigned int op_ch_sel[6][6] = {
1872                 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1873                 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1874                 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1875                 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1876                 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1877                 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1878         };
1879
1880         return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1881 }
1882
1883 static void adv76xx_setup_format(struct adv76xx_state *state)
1884 {
1885         struct v4l2_subdev *sd = &state->sd;
1886
1887         io_write_clr_set(sd, 0x02, 0x02,
1888                         state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1889         io_write(sd, 0x03, state->format->op_format_sel |
1890                  state->pdata.op_format_mode_sel);
1891         io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1892         io_write_clr_set(sd, 0x05, 0x01,
1893                         state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1894         set_rgb_quantization_range(sd);
1895 }
1896
1897 static int adv76xx_get_format(struct v4l2_subdev *sd,
1898                               struct v4l2_subdev_pad_config *cfg,
1899                               struct v4l2_subdev_format *format)
1900 {
1901         struct adv76xx_state *state = to_state(sd);
1902
1903         if (format->pad != state->source_pad)
1904                 return -EINVAL;
1905
1906         adv76xx_fill_format(state, &format->format);
1907
1908         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1909                 struct v4l2_mbus_framefmt *fmt;
1910
1911                 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1912                 format->format.code = fmt->code;
1913         } else {
1914                 format->format.code = state->format->code;
1915         }
1916
1917         return 0;
1918 }
1919
1920 static int adv76xx_get_selection(struct v4l2_subdev *sd,
1921                                  struct v4l2_subdev_pad_config *cfg,
1922                                  struct v4l2_subdev_selection *sel)
1923 {
1924         struct adv76xx_state *state = to_state(sd);
1925
1926         if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1927                 return -EINVAL;
1928         /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
1929         if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
1930                 return -EINVAL;
1931
1932         sel->r.left     = 0;
1933         sel->r.top      = 0;
1934         sel->r.width    = state->timings.bt.width;
1935         sel->r.height   = state->timings.bt.height;
1936
1937         return 0;
1938 }
1939
1940 static int adv76xx_set_format(struct v4l2_subdev *sd,
1941                               struct v4l2_subdev_pad_config *cfg,
1942                               struct v4l2_subdev_format *format)
1943 {
1944         struct adv76xx_state *state = to_state(sd);
1945         const struct adv76xx_format_info *info;
1946
1947         if (format->pad != state->source_pad)
1948                 return -EINVAL;
1949
1950         info = adv76xx_format_info(state, format->format.code);
1951         if (info == NULL)
1952                 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1953
1954         adv76xx_fill_format(state, &format->format);
1955         format->format.code = info->code;
1956
1957         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1958                 struct v4l2_mbus_framefmt *fmt;
1959
1960                 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
1961                 fmt->code = format->format.code;
1962         } else {
1963                 state->format = info;
1964                 adv76xx_setup_format(state);
1965         }
1966
1967         return 0;
1968 }
1969
1970 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
1971 static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
1972 {
1973         struct adv76xx_state *state = to_state(sd);
1974
1975         if ((cec_read(sd, 0x11) & 0x01) == 0) {
1976                 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
1977                 return;
1978         }
1979
1980         if (tx_raw_status & 0x02) {
1981                 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
1982                          __func__);
1983                 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
1984                                   1, 0, 0, 0);
1985         }
1986         if (tx_raw_status & 0x04) {
1987                 u8 status;
1988                 u8 nack_cnt;
1989                 u8 low_drive_cnt;
1990
1991                 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
1992                 /*
1993                  * We set this status bit since this hardware performs
1994                  * retransmissions.
1995                  */
1996                 status = CEC_TX_STATUS_MAX_RETRIES;
1997                 nack_cnt = cec_read(sd, 0x14) & 0xf;
1998                 if (nack_cnt)
1999                         status |= CEC_TX_STATUS_NACK;
2000                 low_drive_cnt = cec_read(sd, 0x14) >> 4;
2001                 if (low_drive_cnt)
2002                         status |= CEC_TX_STATUS_LOW_DRIVE;
2003                 cec_transmit_done(state->cec_adap, status,
2004                                   0, nack_cnt, low_drive_cnt, 0);
2005                 return;
2006         }
2007         if (tx_raw_status & 0x01) {
2008                 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2009                 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
2010                 return;
2011         }
2012 }
2013
2014 static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled)
2015 {
2016         struct adv76xx_state *state = to_state(sd);
2017         u8 cec_irq;
2018
2019         /* cec controller */
2020         cec_irq = io_read(sd, 0x4d) & 0x0f;
2021         if (!cec_irq)
2022                 return;
2023
2024         v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2025         adv76xx_cec_tx_raw_status(sd, cec_irq);
2026         if (cec_irq & 0x08) {
2027                 struct cec_msg msg;
2028
2029                 msg.len = cec_read(sd, 0x25) & 0x1f;
2030                 if (msg.len > 16)
2031                         msg.len = 16;
2032
2033                 if (msg.len) {
2034                         u8 i;
2035
2036                         for (i = 0; i < msg.len; i++)
2037                                 msg.msg[i] = cec_read(sd, i + 0x15);
2038                         cec_write(sd, 0x26, 0x01); /* re-enable rx */
2039                         cec_received_msg(state->cec_adap, &msg);
2040                 }
2041         }
2042
2043         /* note: the bit order is swapped between 0x4d and 0x4e */
2044         cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) |
2045                   ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3);
2046         io_write(sd, 0x4e, cec_irq);
2047
2048         if (handled)
2049                 *handled = true;
2050 }
2051
2052 static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable)
2053 {
2054         struct adv76xx_state *state = cec_get_drvdata(adap);
2055         struct v4l2_subdev *sd = &state->sd;
2056
2057         if (!state->cec_enabled_adap && enable) {
2058                 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2059                 cec_write(sd, 0x2c, 0x01);      /* cec soft reset */
2060                 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2061                 /* enabled irqs: */
2062                 /* tx: ready */
2063                 /* tx: arbitration lost */
2064                 /* tx: retry timeout */
2065                 /* rx: ready */
2066                 io_write_clr_set(sd, 0x50, 0x0f, 0x0f);
2067                 cec_write(sd, 0x26, 0x01);            /* enable rx */
2068         } else if (state->cec_enabled_adap && !enable) {
2069                 /* disable cec interrupts */
2070                 io_write_clr_set(sd, 0x50, 0x0f, 0x00);
2071                 /* disable address mask 1-3 */
2072                 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2073                 /* power down cec section */
2074                 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2075                 state->cec_valid_addrs = 0;
2076         }
2077         state->cec_enabled_adap = enable;
2078         adv76xx_s_detect_tx_5v_ctrl(sd);
2079         return 0;
2080 }
2081
2082 static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2083 {
2084         struct adv76xx_state *state = cec_get_drvdata(adap);
2085         struct v4l2_subdev *sd = &state->sd;
2086         unsigned int i, free_idx = ADV76XX_MAX_ADDRS;
2087
2088         if (!state->cec_enabled_adap)
2089                 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2090
2091         if (addr == CEC_LOG_ADDR_INVALID) {
2092                 cec_write_clr_set(sd, 0x27, 0x70, 0);
2093                 state->cec_valid_addrs = 0;
2094                 return 0;
2095         }
2096
2097         for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2098                 bool is_valid = state->cec_valid_addrs & (1 << i);
2099
2100                 if (free_idx == ADV76XX_MAX_ADDRS && !is_valid)
2101                         free_idx = i;
2102                 if (is_valid && state->cec_addr[i] == addr)
2103                         return 0;
2104         }
2105         if (i == ADV76XX_MAX_ADDRS) {
2106                 i = free_idx;
2107                 if (i == ADV76XX_MAX_ADDRS)
2108                         return -ENXIO;
2109         }
2110         state->cec_addr[i] = addr;
2111         state->cec_valid_addrs |= 1 << i;
2112
2113         switch (i) {
2114         case 0:
2115                 /* enable address mask 0 */
2116                 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2117                 /* set address for mask 0 */
2118                 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2119                 break;
2120         case 1:
2121                 /* enable address mask 1 */
2122                 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2123                 /* set address for mask 1 */
2124                 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2125                 break;
2126         case 2:
2127                 /* enable address mask 2 */
2128                 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2129                 /* set address for mask 1 */
2130                 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2131                 break;
2132         }
2133         return 0;
2134 }
2135
2136 static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2137                                      u32 signal_free_time, struct cec_msg *msg)
2138 {
2139         struct adv76xx_state *state = cec_get_drvdata(adap);
2140         struct v4l2_subdev *sd = &state->sd;
2141         u8 len = msg->len;
2142         unsigned int i;
2143
2144         /*
2145          * The number of retries is the number of attempts - 1, but retry
2146          * at least once. It's not clear if a value of 0 is allowed, so
2147          * let's do at least one retry.
2148          */
2149         cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2150
2151         if (len > 16) {
2152                 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2153                 return -EINVAL;
2154         }
2155
2156         /* write data */
2157         for (i = 0; i < len; i++)
2158                 cec_write(sd, i, msg->msg[i]);
2159
2160         /* set length (data + header) */
2161         cec_write(sd, 0x10, len);
2162         /* start transmit, enable tx */
2163         cec_write(sd, 0x11, 0x01);
2164         return 0;
2165 }
2166
2167 static const struct cec_adap_ops adv76xx_cec_adap_ops = {
2168         .adap_enable = adv76xx_cec_adap_enable,
2169         .adap_log_addr = adv76xx_cec_adap_log_addr,
2170         .adap_transmit = adv76xx_cec_adap_transmit,
2171 };
2172 #endif
2173
2174 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2175 {
2176         struct adv76xx_state *state = to_state(sd);
2177         const struct adv76xx_chip_info *info = state->info;
2178         const u8 irq_reg_0x43 = io_read(sd, 0x43);
2179         const u8 irq_reg_0x6b = io_read(sd, 0x6b);
2180         const u8 irq_reg_0x70 = io_read(sd, 0x70);
2181         u8 fmt_change_digital;
2182         u8 fmt_change;
2183         u8 tx_5v;
2184
2185         if (irq_reg_0x43)
2186                 io_write(sd, 0x44, irq_reg_0x43);
2187         if (irq_reg_0x70)
2188                 io_write(sd, 0x71, irq_reg_0x70);
2189         if (irq_reg_0x6b)
2190                 io_write(sd, 0x6c, irq_reg_0x6b);
2191
2192         v4l2_dbg(2, debug, sd, "%s: ", __func__);
2193
2194         /* format change */
2195         fmt_change = irq_reg_0x43 & 0x98;
2196         fmt_change_digital = is_digital_input(sd)
2197                            ? irq_reg_0x6b & info->fmt_change_digital_mask
2198                            : 0;
2199
2200         if (fmt_change || fmt_change_digital) {
2201                 v4l2_dbg(1, debug, sd,
2202                         "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
2203                         __func__, fmt_change, fmt_change_digital);
2204
2205                 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
2206
2207                 if (handled)
2208                         *handled = true;
2209         }
2210         /* HDMI/DVI mode */
2211         if (irq_reg_0x6b & 0x01) {
2212                 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2213                         (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
2214                 set_rgb_quantization_range(sd);
2215                 if (handled)
2216                         *handled = true;
2217         }
2218
2219 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
2220         /* cec */
2221         adv76xx_cec_isr(sd, handled);
2222 #endif
2223
2224         /* tx 5v detect */
2225         tx_5v = irq_reg_0x70 & info->cable_det_mask;
2226         if (tx_5v) {
2227                 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
2228                 adv76xx_s_detect_tx_5v_ctrl(sd);
2229                 if (handled)
2230                         *handled = true;
2231         }
2232         return 0;
2233 }
2234
2235 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2236 {
2237         struct adv76xx_state *state = to_state(sd);
2238         u8 *data = NULL;
2239
2240         memset(edid->reserved, 0, sizeof(edid->reserved));
2241
2242         switch (edid->pad) {
2243         case ADV76XX_PAD_HDMI_PORT_A:
2244         case ADV7604_PAD_HDMI_PORT_B:
2245         case ADV7604_PAD_HDMI_PORT_C:
2246         case ADV7604_PAD_HDMI_PORT_D:
2247                 if (state->edid.present & (1 << edid->pad))
2248                         data = state->edid.edid;
2249                 break;
2250         default:
2251                 return -EINVAL;
2252         }
2253
2254         if (edid->start_block == 0 && edid->blocks == 0) {
2255                 edid->blocks = data ? state->edid.blocks : 0;
2256                 return 0;
2257         }
2258
2259         if (data == NULL)
2260                 return -ENODATA;
2261
2262         if (edid->start_block >= state->edid.blocks)
2263                 return -EINVAL;
2264
2265         if (edid->start_block + edid->blocks > state->edid.blocks)
2266                 edid->blocks = state->edid.blocks - edid->start_block;
2267
2268         memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2269
2270         return 0;
2271 }
2272
2273 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2274 {
2275         struct adv76xx_state *state = to_state(sd);
2276         const struct adv76xx_chip_info *info = state->info;
2277         unsigned int spa_loc;
2278         u16 pa;
2279         int err;
2280         int i;
2281
2282         memset(edid->reserved, 0, sizeof(edid->reserved));
2283
2284         if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2285                 return -EINVAL;
2286         if (edid->start_block != 0)
2287                 return -EINVAL;
2288         if (edid->blocks == 0) {
2289                 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2290                 state->edid.present &= ~(1 << edid->pad);
2291                 adv76xx_set_hpd(state, state->edid.present);
2292                 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2293
2294                 /* Fall back to a 16:9 aspect ratio */
2295                 state->aspect_ratio.numerator = 16;
2296                 state->aspect_ratio.denominator = 9;
2297
2298                 if (!state->edid.present) {
2299                         state->edid.blocks = 0;
2300                         cec_phys_addr_invalidate(state->cec_adap);
2301                 }
2302
2303                 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2304                                 __func__, edid->pad, state->edid.present);
2305                 return 0;
2306         }
2307         if (edid->blocks > 2) {
2308                 edid->blocks = 2;
2309                 return -E2BIG;
2310         }
2311         pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc);
2312         err = cec_phys_addr_validate(pa, &pa, NULL);
2313         if (err)
2314                 return err;
2315
2316         v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2317                         __func__, edid->pad, state->edid.present);
2318
2319         /* Disable hotplug and I2C access to EDID RAM from DDC port */
2320         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2321         adv76xx_set_hpd(state, 0);
2322         rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2323
2324         /*
2325          * Return an error if no location of the source physical address
2326          * was found.
2327          */
2328         if (spa_loc == 0)
2329                 return -EINVAL;
2330
2331         switch (edid->pad) {
2332         case ADV76XX_PAD_HDMI_PORT_A:
2333                 state->spa_port_a[0] = edid->edid[spa_loc];
2334                 state->spa_port_a[1] = edid->edid[spa_loc + 1];
2335                 break;
2336         case ADV7604_PAD_HDMI_PORT_B:
2337                 rep_write(sd, 0x70, edid->edid[spa_loc]);
2338                 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
2339                 break;
2340         case ADV7604_PAD_HDMI_PORT_C:
2341                 rep_write(sd, 0x72, edid->edid[spa_loc]);
2342                 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
2343                 break;
2344         case ADV7604_PAD_HDMI_PORT_D:
2345                 rep_write(sd, 0x74, edid->edid[spa_loc]);
2346                 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
2347                 break;
2348         default:
2349                 return -EINVAL;
2350         }
2351
2352         if (info->type == ADV7604) {
2353                 rep_write(sd, 0x76, spa_loc & 0xff);
2354                 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
2355         } else {
2356                 /* ADV7612 Software Manual Rev. A, p. 15 */
2357                 rep_write(sd, 0x70, spa_loc & 0xff);
2358                 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
2359         }
2360
2361         edid->edid[spa_loc] = state->spa_port_a[0];
2362         edid->edid[spa_loc + 1] = state->spa_port_a[1];
2363
2364         memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2365         state->edid.blocks = edid->blocks;
2366         state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2367                         edid->edid[0x16]);
2368         state->edid.present |= 1 << edid->pad;
2369
2370         err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2371         if (err < 0) {
2372                 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2373                 return err;
2374         }
2375
2376         /* adv76xx calculates the checksums and enables I2C access to internal
2377            EDID RAM from DDC port. */
2378         rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2379
2380         for (i = 0; i < 1000; i++) {
2381                 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2382                         break;
2383                 mdelay(1);
2384         }
2385         if (i == 1000) {
2386                 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2387                 return -EIO;
2388         }
2389         cec_s_phys_addr(state->cec_adap, pa, false);
2390
2391         /* enable hotplug after 100 ms */
2392         schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
2393         return 0;
2394 }
2395
2396 /*********** avi info frame CEA-861-E **************/
2397
2398 static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2399         { "AVI", 0x01, 0xe0, 0x00 },
2400         { "Audio", 0x02, 0xe3, 0x1c },
2401         { "SDP", 0x04, 0xe6, 0x2a },
2402         { "Vendor", 0x10, 0xec, 0x54 }
2403 };
2404
2405 static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2406                                   union hdmi_infoframe *frame)
2407 {
2408         uint8_t buffer[32];
2409         u8 len;
2410         int i;
2411
2412         if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2413                 v4l2_info(sd, "%s infoframe not received\n",
2414                           adv76xx_cri[index].desc);
2415                 return -ENOENT;
2416         }
2417
2418         for (i = 0; i < 3; i++)
2419                 buffer[i] = infoframe_read(sd,
2420                                            adv76xx_cri[index].head_addr + i);
2421
2422         len = buffer[2] + 1;
2423
2424         if (len + 3 > sizeof(buffer)) {
2425                 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2426                          adv76xx_cri[index].desc, len);
2427                 return -ENOENT;
2428         }
2429
2430         for (i = 0; i < len; i++)
2431                 buffer[i + 3] = infoframe_read(sd,
2432                                        adv76xx_cri[index].payload_addr + i);
2433
2434         if (hdmi_infoframe_unpack(frame, buffer) < 0) {
2435                 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2436                          adv76xx_cri[index].desc);
2437                 return -ENOENT;
2438         }
2439         return 0;
2440 }
2441
2442 static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2443 {
2444         int i;
2445
2446         if (!is_hdmi(sd)) {
2447                 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2448                 return;
2449         }
2450
2451         for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2452                 union hdmi_infoframe frame;
2453                 struct i2c_client *client = v4l2_get_subdevdata(sd);
2454
2455                 if (adv76xx_read_infoframe(sd, i, &frame))
2456                         return;
2457                 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2458         }
2459 }
2460
2461 static int adv76xx_log_status(struct v4l2_subdev *sd)
2462 {
2463         struct adv76xx_state *state = to_state(sd);
2464         const struct adv76xx_chip_info *info = state->info;
2465         struct v4l2_dv_timings timings;
2466         struct stdi_readback stdi;
2467         u8 reg_io_0x02 = io_read(sd, 0x02);
2468         u8 edid_enabled;
2469         u8 cable_det;
2470
2471         static const char * const csc_coeff_sel_rb[16] = {
2472                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2473                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2474                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2475                 "reserved", "reserved", "reserved", "reserved", "manual"
2476         };
2477         static const char * const input_color_space_txt[16] = {
2478                 "RGB limited range (16-235)", "RGB full range (0-255)",
2479                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2480                 "xvYCC Bt.601", "xvYCC Bt.709",
2481                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2482                 "invalid", "invalid", "invalid", "invalid", "invalid",
2483                 "invalid", "invalid", "automatic"
2484         };
2485         static const char * const hdmi_color_space_txt[16] = {
2486                 "RGB limited range (16-235)", "RGB full range (0-255)",
2487                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2488                 "xvYCC Bt.601", "xvYCC Bt.709",
2489                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2490                 "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid",
2491                 "invalid", "invalid", "invalid"
2492         };
2493         static const char * const rgb_quantization_range_txt[] = {
2494                 "Automatic",
2495                 "RGB limited range (16-235)",
2496                 "RGB full range (0-255)",
2497         };
2498         static const char * const deep_color_mode_txt[4] = {
2499                 "8-bits per channel",
2500                 "10-bits per channel",
2501                 "12-bits per channel",
2502                 "16-bits per channel (not supported)"
2503         };
2504
2505         v4l2_info(sd, "-----Chip status-----\n");
2506         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2507         edid_enabled = rep_read(sd, info->edid_status_reg);
2508         v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2509                         ((edid_enabled & 0x01) ? "Yes" : "No"),
2510                         ((edid_enabled & 0x02) ? "Yes" : "No"),
2511                         ((edid_enabled & 0x04) ? "Yes" : "No"),
2512                         ((edid_enabled & 0x08) ? "Yes" : "No"));
2513         v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2514                         "enabled" : "disabled");
2515         if (state->cec_enabled_adap) {
2516                 int i;
2517
2518                 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2519                         bool is_valid = state->cec_valid_addrs & (1 << i);
2520
2521                         if (is_valid)
2522                                 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2523                                           state->cec_addr[i]);
2524                 }
2525         }
2526
2527         v4l2_info(sd, "-----Signal status-----\n");
2528         cable_det = info->read_cable_det(sd);
2529         v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2530                         ((cable_det & 0x01) ? "Yes" : "No"),
2531                         ((cable_det & 0x02) ? "Yes" : "No"),
2532                         ((cable_det & 0x04) ? "Yes" : "No"),
2533                         ((cable_det & 0x08) ? "Yes" : "No"));
2534         v4l2_info(sd, "TMDS signal detected: %s\n",
2535                         no_signal_tmds(sd) ? "false" : "true");
2536         v4l2_info(sd, "TMDS signal locked: %s\n",
2537                         no_lock_tmds(sd) ? "false" : "true");
2538         v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2539         v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2540         v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2541         v4l2_info(sd, "CP free run: %s\n",
2542                         (in_free_run(sd)) ? "on" : "off");
2543         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2544                         io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2545                         (io_read(sd, 0x01) & 0x70) >> 4);
2546
2547         v4l2_info(sd, "-----Video Timings-----\n");
2548         if (read_stdi(sd, &stdi))
2549                 v4l2_info(sd, "STDI: not locked\n");
2550         else
2551                 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2552                                 stdi.lcf, stdi.bl, stdi.lcvs,
2553                                 stdi.interlaced ? "interlaced" : "progressive",
2554                                 stdi.hs_pol, stdi.vs_pol);
2555         if (adv76xx_query_dv_timings(sd, &timings))
2556                 v4l2_info(sd, "No video detected\n");
2557         else
2558                 v4l2_print_dv_timings(sd->name, "Detected format: ",
2559                                       &timings, true);
2560         v4l2_print_dv_timings(sd->name, "Configured format: ",
2561                               &state->timings, true);
2562
2563         if (no_signal(sd))
2564                 return 0;
2565
2566         v4l2_info(sd, "-----Color space-----\n");
2567         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2568                         rgb_quantization_range_txt[state->rgb_quantization_range]);
2569         v4l2_info(sd, "Input color space: %s\n",
2570                         input_color_space_txt[reg_io_0x02 >> 4]);
2571         v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2572                         (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2573                         (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2574                                 "(16-235)" : "(0-255)",
2575                         (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2576         v4l2_info(sd, "Color space conversion: %s\n",
2577                         csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2578
2579         if (!is_digital_input(sd))
2580                 return 0;
2581
2582         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2583         v4l2_info(sd, "Digital video port selected: %c\n",
2584                         (hdmi_read(sd, 0x00) & 0x03) + 'A');
2585         v4l2_info(sd, "HDCP encrypted content: %s\n",
2586                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2587         v4l2_info(sd, "HDCP keys read: %s%s\n",
2588                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2589                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2590         if (is_hdmi(sd)) {
2591                 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2592                 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2593                 bool audio_mute = io_read(sd, 0x65) & 0x40;
2594
2595                 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2596                                 audio_pll_locked ? "locked" : "not locked",
2597                                 audio_sample_packet_detect ? "detected" : "not detected",
2598                                 audio_mute ? "muted" : "enabled");
2599                 if (audio_pll_locked && audio_sample_packet_detect) {
2600                         v4l2_info(sd, "Audio format: %s\n",
2601                                         (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2602                 }
2603                 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2604                                 (hdmi_read(sd, 0x5c) << 8) +
2605                                 (hdmi_read(sd, 0x5d) & 0xf0));
2606                 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2607                                 (hdmi_read(sd, 0x5e) << 8) +
2608                                 hdmi_read(sd, 0x5f));
2609                 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2610
2611                 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2612                 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
2613
2614                 adv76xx_log_infoframes(sd);
2615         }
2616
2617         return 0;
2618 }
2619
2620 static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
2621                                    struct v4l2_fh *fh,
2622                                    struct v4l2_event_subscription *sub)
2623 {
2624         switch (sub->type) {
2625         case V4L2_EVENT_SOURCE_CHANGE:
2626                 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2627         case V4L2_EVENT_CTRL:
2628                 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2629         default:
2630                 return -EINVAL;
2631         }
2632 }
2633
2634 static int adv76xx_registered(struct v4l2_subdev *sd)
2635 {
2636         struct adv76xx_state *state = to_state(sd);
2637         struct i2c_client *client = v4l2_get_subdevdata(sd);
2638         int err;
2639
2640         err = cec_register_adapter(state->cec_adap, &client->dev);
2641         if (err)
2642                 cec_delete_adapter(state->cec_adap);
2643         return err;
2644 }
2645
2646 static void adv76xx_unregistered(struct v4l2_subdev *sd)
2647 {
2648         struct adv76xx_state *state = to_state(sd);
2649
2650         cec_unregister_adapter(state->cec_adap);
2651 }
2652
2653 /* ----------------------------------------------------------------------- */
2654
2655 static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2656         .s_ctrl = adv76xx_s_ctrl,
2657         .g_volatile_ctrl = adv76xx_g_volatile_ctrl,
2658 };
2659
2660 static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2661         .log_status = adv76xx_log_status,
2662         .interrupt_service_routine = adv76xx_isr,
2663         .subscribe_event = adv76xx_subscribe_event,
2664         .unsubscribe_event = v4l2_event_subdev_unsubscribe,
2665 #ifdef CONFIG_VIDEO_ADV_DEBUG
2666         .g_register = adv76xx_g_register,
2667         .s_register = adv76xx_s_register,
2668 #endif
2669 };
2670
2671 static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2672         .s_routing = adv76xx_s_routing,
2673         .g_input_status = adv76xx_g_input_status,
2674         .s_dv_timings = adv76xx_s_dv_timings,
2675         .g_dv_timings = adv76xx_g_dv_timings,
2676         .query_dv_timings = adv76xx_query_dv_timings,
2677 };
2678
2679 static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2680         .enum_mbus_code = adv76xx_enum_mbus_code,
2681         .get_selection = adv76xx_get_selection,
2682         .get_fmt = adv76xx_get_format,
2683         .set_fmt = adv76xx_set_format,
2684         .get_edid = adv76xx_get_edid,
2685         .set_edid = adv76xx_set_edid,
2686         .dv_timings_cap = adv76xx_dv_timings_cap,
2687         .enum_dv_timings = adv76xx_enum_dv_timings,
2688 };
2689
2690 static const struct v4l2_subdev_ops adv76xx_ops = {
2691         .core = &adv76xx_core_ops,
2692         .video = &adv76xx_video_ops,
2693         .pad = &adv76xx_pad_ops,
2694 };
2695
2696 static const struct v4l2_subdev_internal_ops adv76xx_int_ops = {
2697         .registered = adv76xx_registered,
2698         .unregistered = adv76xx_unregistered,
2699 };
2700
2701 /* -------------------------- custom ctrls ---------------------------------- */
2702
2703 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2704         .ops = &adv76xx_ctrl_ops,
2705         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2706         .name = "Analog Sampling Phase",
2707         .type = V4L2_CTRL_TYPE_INTEGER,
2708         .min = 0,
2709         .max = 0x1f,
2710         .step = 1,
2711         .def = 0,
2712 };
2713
2714 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2715         .ops = &adv76xx_ctrl_ops,
2716         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2717         .name = "Free Running Color, Manual",
2718         .type = V4L2_CTRL_TYPE_BOOLEAN,
2719         .min = false,
2720         .max = true,
2721         .step = 1,
2722         .def = false,
2723 };
2724
2725 static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2726         .ops = &adv76xx_ctrl_ops,
2727         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2728         .name = "Free Running Color",
2729         .type = V4L2_CTRL_TYPE_INTEGER,
2730         .min = 0x0,
2731         .max = 0xffffff,
2732         .step = 0x1,
2733         .def = 0x0,
2734 };
2735
2736 /* ----------------------------------------------------------------------- */
2737
2738 static int adv76xx_core_init(struct v4l2_subdev *sd)
2739 {
2740         struct adv76xx_state *state = to_state(sd);
2741         const struct adv76xx_chip_info *info = state->info;
2742         struct adv76xx_platform_data *pdata = &state->pdata;
2743
2744         hdmi_write(sd, 0x48,
2745                 (pdata->disable_pwrdnb ? 0x80 : 0) |
2746                 (pdata->disable_cable_det_rst ? 0x40 : 0));
2747
2748         disable_input(sd);
2749
2750         if (pdata->default_input >= 0 &&
2751             pdata->default_input < state->source_pad) {
2752                 state->selected_input = pdata->default_input;
2753                 select_input(sd);
2754                 enable_input(sd);
2755         }
2756
2757         /* power */
2758         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2759         io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
2760         cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */
2761
2762         /* video format */
2763         io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3);
2764         io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2765                         pdata->insert_av_codes << 2 |
2766                         pdata->replicate_av_codes << 1);
2767         adv76xx_setup_format(state);
2768
2769         cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
2770
2771         /* VS, HS polarities */
2772         io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2773                  pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2774
2775         /* Adjust drive strength */
2776         io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2777                                 pdata->dr_str_clk << 2 |
2778                                 pdata->dr_str_sync);
2779
2780         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2781         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2782         cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
2783                                       ADI recommended setting [REF_01, c. 2.3.3] */
2784         cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
2785                                       ADI recommended setting [REF_01, c. 2.3.3] */
2786         cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2787                                      for digital formats */
2788
2789         /* HDMI audio */
2790         hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2791         hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2792         hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2793
2794         /* TODO from platform data */
2795         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2796
2797         if (adv76xx_has_afe(state)) {
2798                 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2799                 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2800         }
2801
2802         /* interrupts */
2803         io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2804         io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2805         io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2806         io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2807         info->setup_irqs(sd);
2808
2809         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2810 }
2811
2812 static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2813 {
2814         io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2815 }
2816
2817 static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2818 {
2819         io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2820 }
2821
2822 static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2823 {
2824         io_write(sd, 0x41, 0xd0); /* disable INT2 */
2825 }
2826
2827 static void adv76xx_unregister_clients(struct adv76xx_state *state)
2828 {
2829         unsigned int i;
2830
2831         for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2832                 if (state->i2c_clients[i])
2833                         i2c_unregister_device(state->i2c_clients[i]);
2834         }
2835 }
2836
2837 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2838                                                         u8 addr, u8 io_reg)
2839 {
2840         struct i2c_client *client = v4l2_get_subdevdata(sd);
2841
2842         if (addr)
2843                 io_write(sd, io_reg, addr << 1);
2844         return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2845 }
2846
2847 static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2848         /* reset ADI recommended settings for HDMI: */
2849         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2850         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2851         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2852         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2853         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2854         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2855         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2856         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2857         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2858         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2859         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2860         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2861         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2862
2863         /* set ADI recommended settings for digitizer */
2864         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2865         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2866         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2867         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2868         { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2869         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2870
2871         { ADV76XX_REG_SEQ_TERM, 0 },
2872 };
2873
2874 static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2875         /* set ADI recommended settings for HDMI: */
2876         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2877         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2878         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2879         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2880         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2881         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2882         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2883         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2884         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2885         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2886         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2887         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2888
2889         /* reset ADI recommended settings for digitizer */
2890         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2891         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2892         { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2893
2894         { ADV76XX_REG_SEQ_TERM, 0 },
2895 };
2896
2897 static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
2898         /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2899         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2900         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2901         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2902         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2903         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2904         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2905         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2906         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2907         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2908         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2909         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2910
2911         { ADV76XX_REG_SEQ_TERM, 0 },
2912 };
2913
2914 static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
2915         { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2916         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2917         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2918         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2919         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2920         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2921         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2922         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2923         { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2924         { ADV76XX_REG_SEQ_TERM, 0 },
2925 };
2926
2927 static const struct adv76xx_chip_info adv76xx_chip_info[] = {
2928         [ADV7604] = {
2929                 .type = ADV7604,
2930                 .has_afe = true,
2931                 .max_port = ADV7604_PAD_VGA_COMP,
2932                 .num_dv_ports = 4,
2933                 .edid_enable_reg = 0x77,
2934                 .edid_status_reg = 0x7d,
2935                 .lcf_reg = 0xb3,
2936                 .tdms_lock_mask = 0xe0,
2937                 .cable_det_mask = 0x1e,
2938                 .fmt_change_digital_mask = 0xc1,
2939                 .cp_csc = 0xfc,
2940                 .formats = adv7604_formats,
2941                 .nformats = ARRAY_SIZE(adv7604_formats),
2942                 .set_termination = adv7604_set_termination,
2943                 .setup_irqs = adv7604_setup_irqs,
2944                 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2945                 .read_cable_det = adv7604_read_cable_det,
2946                 .recommended_settings = {
2947                     [0] = adv7604_recommended_settings_afe,
2948                     [1] = adv7604_recommended_settings_hdmi,
2949                 },
2950                 .num_recommended_settings = {
2951                     [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2952                     [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2953                 },
2954                 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2955                         BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
2956                         BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
2957                         BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2958                         BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2959                         BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
2960                         BIT(ADV7604_PAGE_VDP),
2961                 .linewidth_mask = 0xfff,
2962                 .field0_height_mask = 0xfff,
2963                 .field1_height_mask = 0xfff,
2964                 .hfrontporch_mask = 0x3ff,
2965                 .hsync_mask = 0x3ff,
2966                 .hbackporch_mask = 0x3ff,
2967                 .field0_vfrontporch_mask = 0x1fff,
2968                 .field0_vsync_mask = 0x1fff,
2969                 .field0_vbackporch_mask = 0x1fff,
2970                 .field1_vfrontporch_mask = 0x1fff,
2971                 .field1_vsync_mask = 0x1fff,
2972                 .field1_vbackporch_mask = 0x1fff,
2973         },
2974         [ADV7611] = {
2975                 .type = ADV7611,
2976                 .has_afe = false,
2977                 .max_port = ADV76XX_PAD_HDMI_PORT_A,
2978                 .num_dv_ports = 1,
2979                 .edid_enable_reg = 0x74,
2980                 .edid_status_reg = 0x76,
2981                 .lcf_reg = 0xa3,
2982                 .tdms_lock_mask = 0x43,
2983                 .cable_det_mask = 0x01,
2984                 .fmt_change_digital_mask = 0x03,
2985                 .cp_csc = 0xf4,
2986                 .formats = adv7611_formats,
2987                 .nformats = ARRAY_SIZE(adv7611_formats),
2988                 .set_termination = adv7611_set_termination,
2989                 .setup_irqs = adv7611_setup_irqs,
2990                 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2991                 .read_cable_det = adv7611_read_cable_det,
2992                 .recommended_settings = {
2993                     [1] = adv7611_recommended_settings_hdmi,
2994                 },
2995                 .num_recommended_settings = {
2996                     [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2997                 },
2998                 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2999                         BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3000                         BIT(ADV76XX_PAGE_REP) |  BIT(ADV76XX_PAGE_EDID) |
3001                         BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3002                 .linewidth_mask = 0x1fff,
3003                 .field0_height_mask = 0x1fff,
3004                 .field1_height_mask = 0x1fff,
3005                 .hfrontporch_mask = 0x1fff,
3006                 .hsync_mask = 0x1fff,
3007                 .hbackporch_mask = 0x1fff,
3008                 .field0_vfrontporch_mask = 0x3fff,
3009                 .field0_vsync_mask = 0x3fff,
3010                 .field0_vbackporch_mask = 0x3fff,
3011                 .field1_vfrontporch_mask = 0x3fff,
3012                 .field1_vsync_mask = 0x3fff,
3013                 .field1_vbackporch_mask = 0x3fff,
3014         },
3015         [ADV7612] = {
3016                 .type = ADV7612,
3017                 .has_afe = false,
3018                 .max_port = ADV76XX_PAD_HDMI_PORT_A,    /* B not supported */
3019                 .num_dv_ports = 1,                      /* normally 2 */
3020                 .edid_enable_reg = 0x74,
3021                 .edid_status_reg = 0x76,
3022                 .lcf_reg = 0xa3,
3023                 .tdms_lock_mask = 0x43,
3024                 .cable_det_mask = 0x01,
3025                 .fmt_change_digital_mask = 0x03,
3026                 .cp_csc = 0xf4,
3027                 .formats = adv7612_formats,
3028                 .nformats = ARRAY_SIZE(adv7612_formats),
3029                 .set_termination = adv7611_set_termination,
3030                 .setup_irqs = adv7612_setup_irqs,
3031                 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3032                 .read_cable_det = adv7612_read_cable_det,
3033                 .recommended_settings = {
3034                     [1] = adv7612_recommended_settings_hdmi,
3035                 },
3036                 .num_recommended_settings = {
3037                     [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
3038                 },
3039                 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3040                         BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3041                         BIT(ADV76XX_PAGE_REP) |  BIT(ADV76XX_PAGE_EDID) |
3042                         BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3043                 .linewidth_mask = 0x1fff,
3044                 .field0_height_mask = 0x1fff,
3045                 .field1_height_mask = 0x1fff,
3046                 .hfrontporch_mask = 0x1fff,
3047                 .hsync_mask = 0x1fff,
3048                 .hbackporch_mask = 0x1fff,
3049                 .field0_vfrontporch_mask = 0x3fff,
3050                 .field0_vsync_mask = 0x3fff,
3051                 .field0_vbackporch_mask = 0x3fff,
3052                 .field1_vfrontporch_mask = 0x3fff,
3053                 .field1_vsync_mask = 0x3fff,
3054                 .field1_vbackporch_mask = 0x3fff,
3055         },
3056 };
3057
3058 static const struct i2c_device_id adv76xx_i2c_id[] = {
3059         { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
3060         { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
3061         { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
3062         { }
3063 };
3064 MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
3065
3066 static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
3067         { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
3068         { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
3069         { }
3070 };
3071 MODULE_DEVICE_TABLE(of, adv76xx_of_id);
3072
3073 static int adv76xx_parse_dt(struct adv76xx_state *state)
3074 {
3075         struct v4l2_fwnode_endpoint bus_cfg;
3076         struct device_node *endpoint;
3077         struct device_node *np;
3078         unsigned int flags;
3079         int ret;
3080         u32 v;
3081
3082         np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
3083
3084         /* Parse the endpoint. */
3085         endpoint = of_graph_get_next_endpoint(np, NULL);
3086         if (!endpoint)
3087                 return -EINVAL;
3088
3089         ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg);
3090         if (ret) {
3091                 of_node_put(endpoint);
3092                 return ret;
3093         }
3094
3095         of_node_put(endpoint);
3096
3097         if (!of_property_read_u32(np, "default-input", &v))
3098                 state->pdata.default_input = v;
3099         else
3100                 state->pdata.default_input = -1;
3101
3102         flags = bus_cfg.bus.parallel.flags;
3103
3104         if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
3105                 state->pdata.inv_hs_pol = 1;
3106
3107         if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
3108                 state->pdata.inv_vs_pol = 1;
3109
3110         if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
3111                 state->pdata.inv_llc_pol = 1;
3112
3113         if (bus_cfg.bus_type == V4L2_MBUS_BT656)
3114                 state->pdata.insert_av_codes = 1;
3115
3116         /* Disable the interrupt for now as no DT-based board uses it. */
3117         state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
3118
3119         /* Use the default I2C addresses. */
3120         state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
3121         state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
3122         state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
3123         state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
3124         state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
3125         state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
3126         state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
3127         state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
3128         state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
3129         state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
3130         state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
3131         state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
3132
3133         /* Hardcode the remaining platform data fields. */
3134         state->pdata.disable_pwrdnb = 0;
3135         state->pdata.disable_cable_det_rst = 0;
3136         state->pdata.blank_data = 1;
3137         state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
3138         state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
3139         state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH;
3140         state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH;
3141         state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH;
3142
3143         return 0;
3144 }
3145
3146 static const struct regmap_config adv76xx_regmap_cnf[] = {
3147         {
3148                 .name                   = "io",
3149                 .reg_bits               = 8,
3150                 .val_bits               = 8,
3151
3152                 .max_register           = 0xff,
3153                 .cache_type             = REGCACHE_NONE,
3154         },
3155         {
3156                 .name                   = "avlink",
3157                 .reg_bits               = 8,
3158                 .val_bits               = 8,
3159
3160                 .max_register           = 0xff,
3161                 .cache_type             = REGCACHE_NONE,
3162         },
3163         {
3164                 .name                   = "cec",
3165                 .reg_bits               = 8,
3166                 .val_bits               = 8,
3167
3168                 .max_register           = 0xff,
3169                 .cache_type             = REGCACHE_NONE,
3170         },
3171         {
3172                 .name                   = "infoframe",
3173                 .reg_bits               = 8,
3174                 .val_bits               = 8,
3175
3176                 .max_register           = 0xff,
3177                 .cache_type             = REGCACHE_NONE,
3178         },
3179         {
3180                 .name                   = "esdp",
3181                 .reg_bits               = 8,
3182                 .val_bits               = 8,
3183
3184                 .max_register           = 0xff,
3185                 .cache_type             = REGCACHE_NONE,
3186         },
3187         {
3188                 .name                   = "epp",
3189                 .reg_bits               = 8,
3190                 .val_bits               = 8,
3191
3192                 .max_register           = 0xff,
3193                 .cache_type             = REGCACHE_NONE,
3194         },
3195         {
3196                 .name                   = "afe",
3197                 .reg_bits               = 8,
3198                 .val_bits               = 8,
3199
3200                 .max_register           = 0xff,
3201                 .cache_type             = REGCACHE_NONE,
3202         },
3203         {
3204                 .name                   = "rep",
3205                 .reg_bits               = 8,
3206                 .val_bits               = 8,
3207
3208                 .max_register           = 0xff,
3209                 .cache_type             = REGCACHE_NONE,
3210         },
3211         {
3212                 .name                   = "edid",
3213                 .reg_bits               = 8,
3214                 .val_bits               = 8,
3215
3216                 .max_register           = 0xff,
3217                 .cache_type             = REGCACHE_NONE,
3218         },
3219
3220         {
3221                 .name                   = "hdmi",
3222                 .reg_bits               = 8,
3223                 .val_bits               = 8,
3224
3225                 .max_register           = 0xff,
3226                 .cache_type             = REGCACHE_NONE,
3227         },
3228         {
3229                 .name                   = "test",
3230                 .reg_bits               = 8,
3231                 .val_bits               = 8,
3232
3233                 .max_register           = 0xff,
3234                 .cache_type             = REGCACHE_NONE,
3235         },
3236         {
3237                 .name                   = "cp",
3238                 .reg_bits               = 8,
3239                 .val_bits               = 8,
3240
3241                 .max_register           = 0xff,
3242                 .cache_type             = REGCACHE_NONE,
3243         },
3244         {
3245                 .name                   = "vdp",
3246                 .reg_bits               = 8,
3247                 .val_bits               = 8,
3248
3249                 .max_register           = 0xff,
3250                 .cache_type             = REGCACHE_NONE,
3251         },
3252 };
3253
3254 static int configure_regmap(struct adv76xx_state *state, int region)
3255 {
3256         int err;
3257
3258         if (!state->i2c_clients[region])
3259                 return -ENODEV;
3260
3261         state->regmap[region] =
3262                 devm_regmap_init_i2c(state->i2c_clients[region],
3263                                      &adv76xx_regmap_cnf[region]);
3264
3265         if (IS_ERR(state->regmap[region])) {
3266                 err = PTR_ERR(state->regmap[region]);
3267                 v4l_err(state->i2c_clients[region],
3268                         "Error initializing regmap %d with error %d\n",
3269                         region, err);
3270                 return -EINVAL;
3271         }
3272
3273         return 0;
3274 }
3275
3276 static int configure_regmaps(struct adv76xx_state *state)
3277 {
3278         int i, err;
3279
3280         for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
3281                 err = configure_regmap(state, i);
3282                 if (err && (err != -ENODEV))
3283                         return err;
3284         }
3285         return 0;
3286 }
3287
3288 static void adv76xx_reset(struct adv76xx_state *state)
3289 {
3290         if (state->reset_gpio) {
3291                 /* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */
3292                 gpiod_set_value_cansleep(state->reset_gpio, 0);
3293                 usleep_range(5000, 10000);
3294                 gpiod_set_value_cansleep(state->reset_gpio, 1);
3295                 /* It is recommended to wait 5 ms after the low pulse before */
3296                 /* an I2C write is performed to the ADV76XX. */
3297                 usleep_range(5000, 10000);
3298         }
3299 }
3300
3301 static int adv76xx_probe(struct i2c_client *client,
3302                          const struct i2c_device_id *id)
3303 {
3304         static const struct v4l2_dv_timings cea640x480 =
3305                 V4L2_DV_BT_CEA_640X480P59_94;
3306         struct adv76xx_state *state;
3307         struct v4l2_ctrl_handler *hdl;
3308         struct v4l2_ctrl *ctrl;
3309         struct v4l2_subdev *sd;
3310         unsigned int i;
3311         unsigned int val, val2;
3312         int err;
3313
3314         /* Check if the adapter supports the needed features */
3315         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3316                 return -EIO;
3317         v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
3318                         client->addr << 1);
3319
3320         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3321         if (!state) {
3322                 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
3323                 return -ENOMEM;
3324         }
3325
3326         state->i2c_clients[ADV76XX_PAGE_IO] = client;
3327
3328         /* initialize variables */
3329         state->restart_stdi_once = true;
3330         state->selected_input = ~0;
3331
3332         if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3333                 const struct of_device_id *oid;
3334
3335                 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
3336                 state->info = oid->data;
3337
3338                 err = adv76xx_parse_dt(state);
3339                 if (err < 0) {
3340                         v4l_err(client, "DT parsing error\n");
3341                         return err;
3342                 }
3343         } else if (client->dev.platform_data) {
3344                 struct adv76xx_platform_data *pdata = client->dev.platform_data;
3345
3346                 state->info = (const struct adv76xx_chip_info *)id->driver_data;
3347                 state->pdata = *pdata;
3348         } else {
3349                 v4l_err(client, "No platform data!\n");
3350                 return -ENODEV;
3351         }
3352
3353         /* Request GPIOs. */
3354         for (i = 0; i < state->info->num_dv_ports; ++i) {
3355                 state->hpd_gpio[i] =
3356                         devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3357                                                       GPIOD_OUT_LOW);
3358                 if (IS_ERR(state->hpd_gpio[i]))
3359                         return PTR_ERR(state->hpd_gpio[i]);
3360
3361                 if (state->hpd_gpio[i])
3362                         v4l_info(client, "Handling HPD %u GPIO\n", i);
3363         }
3364         state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3365                                                                 GPIOD_OUT_HIGH);
3366         if (IS_ERR(state->reset_gpio))
3367                 return PTR_ERR(state->reset_gpio);
3368
3369         adv76xx_reset(state);
3370
3371         state->timings = cea640x480;
3372         state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3373
3374         sd = &state->sd;
3375         v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
3376         snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3377                 id->name, i2c_adapter_id(client->adapter),
3378                 client->addr);
3379         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3380         sd->internal_ops = &adv76xx_int_ops;
3381
3382         /* Configure IO Regmap region */
3383         err = configure_regmap(state, ADV76XX_PAGE_IO);
3384
3385         if (err) {
3386                 v4l2_err(sd, "Error configuring IO regmap region\n");
3387                 return -ENODEV;
3388         }
3389
3390         /*
3391          * Verify that the chip is present. On ADV7604 the RD_INFO register only
3392          * identifies the revision, while on ADV7611 it identifies the model as
3393          * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
3394          */
3395         switch (state->info->type) {
3396         case ADV7604:
3397                 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3398                 if (err) {
3399                         v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3400                         return -ENODEV;
3401                 }
3402                 if (val != 0x68) {
3403                         v4l2_err(sd, "not an adv7604 on address 0x%x\n",
3404                                         client->addr << 1);
3405                         return -ENODEV;
3406                 }
3407                 break;
3408         case ADV7611:
3409         case ADV7612:
3410                 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3411                                 0xea,
3412                                 &val);
3413                 if (err) {
3414                         v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3415                         return -ENODEV;
3416                 }
3417                 val2 = val << 8;
3418                 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3419                             0xeb,
3420                             &val);
3421                 if (err) {
3422                         v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3423                         return -ENODEV;
3424                 }
3425                 val |= val2;
3426                 if ((state->info->type == ADV7611 && val != 0x2051) ||
3427                         (state->info->type == ADV7612 && val != 0x2041)) {
3428                         v4l2_err(sd, "not an adv761x on address 0x%x\n",
3429                                         client->addr << 1);
3430                         return -ENODEV;
3431                 }
3432                 break;
3433         }
3434
3435         /* control handlers */
3436         hdl = &state->hdl;
3437         v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
3438
3439         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3440                         V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3441         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3442                         V4L2_CID_CONTRAST, 0, 255, 1, 128);
3443         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3444                         V4L2_CID_SATURATION, 0, 255, 1, 128);
3445         v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3446                         V4L2_CID_HUE, 0, 128, 1, 0);
3447         ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3448                         V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3449                         0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3450         if (ctrl)
3451                 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3452
3453         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3454                         V4L2_CID_DV_RX_POWER_PRESENT, 0,
3455                         (1 << state->info->num_dv_ports) - 1, 0, 0);
3456         state->rgb_quantization_range_ctrl =
3457                 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3458                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3459                         0, V4L2_DV_RGB_RANGE_AUTO);
3460
3461         /* custom controls */
3462         if (adv76xx_has_afe(state))
3463                 state->analog_sampling_phase_ctrl =
3464                         v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
3465         state->free_run_color_manual_ctrl =
3466                 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
3467         state->free_run_color_ctrl =
3468                 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
3469
3470         sd->ctrl_handler = hdl;
3471         if (hdl->error) {
3472                 err = hdl->error;
3473                 goto err_hdl;
3474         }
3475         if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
3476                 err = -ENODEV;
3477                 goto err_hdl;
3478         }
3479
3480         for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
3481                 if (!(BIT(i) & state->info->page_mask))
3482                         continue;
3483
3484                 state->i2c_clients[i] =
3485                         adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
3486                                              0xf2 + i);
3487                 if (state->i2c_clients[i] == NULL) {
3488                         err = -ENOMEM;
3489                         v4l2_err(sd, "failed to create i2c client %u\n", i);
3490                         goto err_i2c;
3491                 }
3492         }
3493
3494         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3495                         adv76xx_delayed_work_enable_hotplug);
3496
3497         state->source_pad = state->info->num_dv_ports
3498                           + (state->info->has_afe ? 2 : 0);
3499         for (i = 0; i < state->source_pad; ++i)
3500                 state->pads[i].flags = MEDIA_PAD_FL_SINK;
3501         state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3502
3503         err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
3504                                 state->pads);
3505         if (err)
3506                 goto err_work_queues;
3507
3508         /* Configure regmaps */
3509         err = configure_regmaps(state);
3510         if (err)
3511                 goto err_entity;
3512
3513         err = adv76xx_core_init(sd);
3514         if (err)
3515                 goto err_entity;
3516
3517 #if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
3518         state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops,
3519                 state, dev_name(&client->dev),
3520                 CEC_CAP_DEFAULTS, ADV76XX_MAX_ADDRS);
3521         err = PTR_ERR_OR_ZERO(state->cec_adap);
3522         if (err)
3523                 goto err_entity;
3524 #endif
3525
3526         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3527                         client->addr << 1, client->adapter->name);
3528
3529         err = v4l2_async_register_subdev(sd);
3530         if (err)
3531                 goto err_entity;
3532
3533         return 0;
3534
3535 err_entity:
3536         media_entity_cleanup(&sd->entity);
3537 err_work_queues:
3538         cancel_delayed_work(&state->delayed_work_enable_hotplug);
3539 err_i2c:
3540         adv76xx_unregister_clients(state);
3541 err_hdl:
3542         v4l2_ctrl_handler_free(hdl);
3543         return err;
3544 }
3545
3546 /* ----------------------------------------------------------------------- */
3547
3548 static int adv76xx_remove(struct i2c_client *client)
3549 {
3550         struct v4l2_subdev *sd = i2c_get_clientdata(client);
3551         struct adv76xx_state *state = to_state(sd);
3552
3553         /* disable interrupts */
3554         io_write(sd, 0x40, 0);
3555         io_write(sd, 0x41, 0);
3556         io_write(sd, 0x46, 0);
3557         io_write(sd, 0x6e, 0);
3558         io_write(sd, 0x73, 0);
3559
3560         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
3561         v4l2_async_unregister_subdev(sd);
3562         media_entity_cleanup(&sd->entity);
3563         adv76xx_unregister_clients(to_state(sd));
3564         v4l2_ctrl_handler_free(sd->ctrl_handler);
3565         return 0;
3566 }
3567
3568 /* ----------------------------------------------------------------------- */
3569
3570 static struct i2c_driver adv76xx_driver = {
3571         .driver = {
3572                 .name = "adv7604",
3573                 .of_match_table = of_match_ptr(adv76xx_of_id),
3574         },
3575         .probe = adv76xx_probe,
3576         .remove = adv76xx_remove,
3577         .id_table = adv76xx_i2c_id,
3578 };
3579
3580 module_i2c_driver(adv76xx_driver);