2 * Analog Devices AD9389B/AD9889B video encoder driver
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * References (c = chapter, p = page):
22 * REF_01 - Analog Devices, Programming Guide, AD9889B/AD9389B,
23 * HDMI Transitter, Rev. A, October 2010
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/slab.h>
29 #include <linux/i2c.h>
30 #include <linux/delay.h>
31 #include <linux/videodev2.h>
32 #include <linux/workqueue.h>
33 #include <linux/v4l2-dv-timings.h>
34 #include <media/v4l2-device.h>
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-dv-timings.h>
37 #include <media/v4l2-ctrls.h>
38 #include <media/i2c/ad9389b.h>
41 module_param(debug, int, 0644);
42 MODULE_PARM_DESC(debug, "debug level (0-2)");
44 MODULE_DESCRIPTION("Analog Devices AD9389B/AD9889B video encoder driver");
45 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
46 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
47 MODULE_LICENSE("GPL");
49 #define MASK_AD9389B_EDID_RDY_INT 0x04
50 #define MASK_AD9389B_MSEN_INT 0x40
51 #define MASK_AD9389B_HPD_INT 0x80
53 #define MASK_AD9389B_HPD_DETECT 0x40
54 #define MASK_AD9389B_MSEN_DETECT 0x20
55 #define MASK_AD9389B_EDID_RDY 0x10
57 #define EDID_MAX_RETRIES (8)
58 #define EDID_DELAY 250
59 #define EDID_MAX_SEGM 8
62 **********************************************************************
64 * Arrays with configuration parameters for the AD9389B
66 **********************************************************************
69 struct ad9389b_state_edid {
70 /* total number of blocks */
72 /* Number of segments read */
74 u8 data[EDID_MAX_SEGM * 256];
75 /* Number of EDID read retries left */
76 unsigned read_retries;
79 struct ad9389b_state {
80 struct ad9389b_platform_data pdata;
81 struct v4l2_subdev sd;
83 struct v4l2_ctrl_handler hdl;
85 /* Is the ad9389b powered on? */
87 /* Did we receive hotplug and rx-sense signals? */
89 /* timings from s_dv_timings */
90 struct v4l2_dv_timings dv_timings;
92 struct v4l2_ctrl *hdmi_mode_ctrl;
93 struct v4l2_ctrl *hotplug_ctrl;
94 struct v4l2_ctrl *rx_sense_ctrl;
95 struct v4l2_ctrl *have_edid0_ctrl;
96 struct v4l2_ctrl *rgb_quantization_range_ctrl;
97 struct i2c_client *edid_i2c_client;
98 struct ad9389b_state_edid edid;
99 /* Running counter of the number of detected EDIDs (for debugging) */
100 unsigned edid_detect_counter;
101 struct delayed_work edid_handler; /* work entry */
104 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd);
105 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd);
106 static void ad9389b_setup(struct v4l2_subdev *sd);
107 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
108 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
110 static inline struct ad9389b_state *get_ad9389b_state(struct v4l2_subdev *sd)
112 return container_of(sd, struct ad9389b_state, sd);
115 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
117 return &container_of(ctrl->handler, struct ad9389b_state, hdl)->sd;
120 /* ------------------------ I2C ----------------------------------------------- */
122 static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
124 struct i2c_client *client = v4l2_get_subdevdata(sd);
126 return i2c_smbus_read_byte_data(client, reg);
129 static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
131 struct i2c_client *client = v4l2_get_subdevdata(sd);
135 for (i = 0; i < 3; i++) {
136 ret = i2c_smbus_write_byte_data(client, reg, val);
140 v4l2_err(sd, "%s: failed reg 0x%x, val 0x%x\n", __func__, reg, val);
144 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
145 and then the value-mask (to be OR-ed). */
146 static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg,
147 u8 clr_mask, u8 val_mask)
149 ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
152 static void ad9389b_edid_rd(struct v4l2_subdev *sd, u16 len, u8 *buf)
154 struct ad9389b_state *state = get_ad9389b_state(sd);
157 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
159 for (i = 0; i < len; i++)
160 buf[i] = i2c_smbus_read_byte_data(state->edid_i2c_client, i);
163 static inline bool ad9389b_have_hotplug(struct v4l2_subdev *sd)
165 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
168 static inline bool ad9389b_have_rx_sense(struct v4l2_subdev *sd)
170 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
173 static void ad9389b_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
175 ad9389b_wr_and_or(sd, 0x17, 0xe7, (mode & 0x3)<<3);
176 ad9389b_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
179 static void ad9389b_csc_coeff(struct v4l2_subdev *sd,
180 u16 A1, u16 A2, u16 A3, u16 A4,
181 u16 B1, u16 B2, u16 B3, u16 B4,
182 u16 C1, u16 C2, u16 C3, u16 C4)
185 ad9389b_wr_and_or(sd, 0x18, 0xe0, A1>>8);
186 ad9389b_wr(sd, 0x19, A1);
187 ad9389b_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
188 ad9389b_wr(sd, 0x1B, A2);
189 ad9389b_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
190 ad9389b_wr(sd, 0x1d, A3);
191 ad9389b_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
192 ad9389b_wr(sd, 0x1f, A4);
195 ad9389b_wr_and_or(sd, 0x20, 0xe0, B1>>8);
196 ad9389b_wr(sd, 0x21, B1);
197 ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8);
198 ad9389b_wr(sd, 0x23, B2);
199 ad9389b_wr_and_or(sd, 0x24, 0xe0, B3>>8);
200 ad9389b_wr(sd, 0x25, B3);
201 ad9389b_wr_and_or(sd, 0x26, 0xe0, B4>>8);
202 ad9389b_wr(sd, 0x27, B4);
205 ad9389b_wr_and_or(sd, 0x28, 0xe0, C1>>8);
206 ad9389b_wr(sd, 0x29, C1);
207 ad9389b_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
208 ad9389b_wr(sd, 0x2B, C2);
209 ad9389b_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
210 ad9389b_wr(sd, 0x2D, C3);
211 ad9389b_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
212 ad9389b_wr(sd, 0x2F, C4);
215 static void ad9389b_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
220 ad9389b_csc_conversion_mode(sd, csc_mode);
221 ad9389b_csc_coeff(sd,
224 0, 0, 4096-564, 256);
226 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x1);
227 /* AVI infoframe: Limited range RGB (16-235) */
228 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x02);
231 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x0);
232 /* AVI infoframe: Full range RGB (0-255) */
233 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x04);
237 static void ad9389b_set_IT_content_AVI_InfoFrame(struct v4l2_subdev *sd)
239 struct ad9389b_state *state = get_ad9389b_state(sd);
241 if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
242 /* CE format, not IT */
243 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x00);
246 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x40);
250 static int ad9389b_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
252 struct ad9389b_state *state = get_ad9389b_state(sd);
255 case V4L2_DV_RGB_RANGE_AUTO:
257 if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
258 /* CE format, RGB limited range (16-235) */
259 ad9389b_csc_rgb_full2limit(sd, true);
261 /* not CE format, RGB full range (0-255) */
262 ad9389b_csc_rgb_full2limit(sd, false);
265 case V4L2_DV_RGB_RANGE_LIMITED:
266 /* RGB limited range (16-235) */
267 ad9389b_csc_rgb_full2limit(sd, true);
269 case V4L2_DV_RGB_RANGE_FULL:
270 /* RGB full range (0-255) */
271 ad9389b_csc_rgb_full2limit(sd, false);
279 static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)
283 /* Workaround for TMDS PLL problem
284 * The TMDS PLL in AD9389b change gear when the chip is heated above a
285 * certain temperature. The output is disabled when the PLL change gear
286 * so the monitor has to lock on the signal again. A workaround for
287 * this is to use the manual PLL gears. This is a solution from Analog
288 * Devices that is not documented in the datasheets.
289 * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear
291 * The pixel frequency ranges are based on readout of the gear the
292 * automatic gearing selects for different pixel clocks
293 * (read from 0x9e [3:1]).
296 if (pixelclock > 140000000)
297 gear = 0xc0; /* 4th gear */
298 else if (pixelclock > 117000000)
299 gear = 0xb0; /* 3rd gear */
300 else if (pixelclock > 87000000)
301 gear = 0xa0; /* 2nd gear */
302 else if (pixelclock > 60000000)
303 gear = 0x90; /* 1st gear */
305 gear = 0x80; /* 0th gear */
307 ad9389b_wr_and_or(sd, 0x98, 0x0f, gear);
310 /* ------------------------------ CTRL OPS ------------------------------ */
312 static int ad9389b_s_ctrl(struct v4l2_ctrl *ctrl)
314 struct v4l2_subdev *sd = to_sd(ctrl);
315 struct ad9389b_state *state = get_ad9389b_state(sd);
317 v4l2_dbg(1, debug, sd,
318 "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
320 if (state->hdmi_mode_ctrl == ctrl) {
321 /* Set HDMI or DVI-D */
322 ad9389b_wr_and_or(sd, 0xaf, 0xfd,
323 ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
326 if (state->rgb_quantization_range_ctrl == ctrl)
327 return ad9389b_set_rgb_quantization_mode(sd, ctrl);
331 static const struct v4l2_ctrl_ops ad9389b_ctrl_ops = {
332 .s_ctrl = ad9389b_s_ctrl,
335 /* ---------------------------- CORE OPS ------------------------------------------- */
337 #ifdef CONFIG_VIDEO_ADV_DEBUG
338 static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
340 reg->val = ad9389b_rd(sd, reg->reg & 0xff);
345 static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
347 ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff);
352 static int ad9389b_log_status(struct v4l2_subdev *sd)
354 struct ad9389b_state *state = get_ad9389b_state(sd);
355 struct ad9389b_state_edid *edid = &state->edid;
357 static const char * const states[] = {
363 "initializing HDCP repeater",
364 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
366 static const char * const errors[] = {
373 "max repeater cascade exceeded",
376 "9", "A", "B", "C", "D", "E", "F"
381 v4l2_info(sd, "chip revision %d\n", state->chip_revision);
382 v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
383 v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
384 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
386 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
388 edid->segments ? "found" : "no", edid->blocks);
389 v4l2_info(sd, "%s output %s\n",
390 (ad9389b_rd(sd, 0xaf) & 0x02) ?
392 (ad9389b_rd(sd, 0xa1) & 0x3c) ?
393 "disabled" : "enabled");
394 v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
395 "encrypted" : "no encryption");
396 v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
397 states[ad9389b_rd(sd, 0xc8) & 0xf],
398 errors[ad9389b_rd(sd, 0xc8) >> 4],
399 state->edid_detect_counter,
400 ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
401 manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
402 v4l2_info(sd, "ad9389b: RGB quantization: %s range\n",
403 ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
404 v4l2_info(sd, "ad9389b: %s gear %d\n",
405 manual_gear ? "manual" : "automatic",
406 manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
407 ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
408 if (ad9389b_rd(sd, 0xaf) & 0x02) {
410 u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
411 u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
412 ad9389b_rd(sd, 0x02) << 8 |
413 ad9389b_rd(sd, 0x03);
414 u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
415 u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
419 CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
420 ad9389b_rd(sd, 0x08) << 8 |
421 ad9389b_rd(sd, 0x09);
423 CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
424 ad9389b_rd(sd, 0x05) << 8 |
425 ad9389b_rd(sd, 0x06);
426 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
427 ad9389b_rd(sd, 0x02) << 8 |
428 ad9389b_rd(sd, 0x03);
430 v4l2_info(sd, "ad9389b: CTS %s mode: N %d, CTS %d\n",
431 manual_cts ? "manual" : "automatic", N, CTS);
433 v4l2_info(sd, "ad9389b: VIC: detected %d, sent %d\n",
434 vic_detect, vic_sent);
436 if (state->dv_timings.type == V4L2_DV_BT_656_1120)
437 v4l2_print_dv_timings(sd->name, "timings: ",
438 &state->dv_timings, false);
440 v4l2_info(sd, "no timings set\n");
444 /* Power up/down ad9389b */
445 static int ad9389b_s_power(struct v4l2_subdev *sd, int on)
447 struct ad9389b_state *state = get_ad9389b_state(sd);
448 struct ad9389b_platform_data *pdata = &state->pdata;
449 const int retries = 20;
452 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
454 state->power_on = on;
458 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
463 /* The ad9389b does not always come up immediately.
464 Retry multiple times. */
465 for (i = 0; i < retries; i++) {
466 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x0);
467 if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
469 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
473 v4l2_dbg(1, debug, sd, "failed to powerup the ad9389b\n");
474 ad9389b_s_power(sd, 0);
478 v4l2_dbg(1, debug, sd,
479 "needed %d retries to powerup the ad9389b\n", i);
481 /* Select chip: AD9389B */
482 ad9389b_wr_and_or(sd, 0xba, 0xef, 0x10);
484 /* Reserved registers that must be set according to REF_01 p. 11*/
485 ad9389b_wr_and_or(sd, 0x98, 0xf0, 0x07);
486 ad9389b_wr(sd, 0x9c, 0x38);
487 ad9389b_wr_and_or(sd, 0x9d, 0xfc, 0x01);
489 /* Differential output drive strength */
490 if (pdata->diff_data_drive_strength > 0)
491 ad9389b_wr(sd, 0xa2, pdata->diff_data_drive_strength);
493 ad9389b_wr(sd, 0xa2, 0x87);
495 if (pdata->diff_clk_drive_strength > 0)
496 ad9389b_wr(sd, 0xa3, pdata->diff_clk_drive_strength);
498 ad9389b_wr(sd, 0xa3, 0x87);
500 ad9389b_wr(sd, 0x0a, 0x01);
501 ad9389b_wr(sd, 0xbb, 0xff);
503 /* Set number of attempts to read the EDID */
504 ad9389b_wr(sd, 0xc9, 0xf);
508 /* Enable interrupts */
509 static void ad9389b_set_isr(struct v4l2_subdev *sd, bool enable)
511 u8 irqs = MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT;
515 /* The datasheet says that the EDID ready interrupt should be
516 disabled if there is no hotplug. */
519 else if (ad9389b_have_hotplug(sd))
520 irqs |= MASK_AD9389B_EDID_RDY_INT;
523 * This i2c write can fail (approx. 1 in 1000 writes). But it
524 * is essential that this register is correct, so retry it
527 * Note that the i2c write does not report an error, but the readback
528 * clearly shows the wrong value.
531 ad9389b_wr(sd, 0x94, irqs);
532 irqs_rd = ad9389b_rd(sd, 0x94);
533 } while (retries-- && irqs_rd != irqs);
536 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
539 /* Interrupt handler */
540 static int ad9389b_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
544 /* disable interrupts to prevent a race condition */
545 ad9389b_set_isr(sd, false);
546 irq_status = ad9389b_rd(sd, 0x96);
547 /* clear detected interrupts */
548 ad9389b_wr(sd, 0x96, irq_status);
549 /* enable interrupts */
550 ad9389b_set_isr(sd, true);
552 v4l2_dbg(1, debug, sd, "%s: irq_status 0x%x\n", __func__, irq_status);
554 if (irq_status & (MASK_AD9389B_HPD_INT))
555 ad9389b_check_monitor_present_status(sd);
556 if (irq_status & MASK_AD9389B_EDID_RDY_INT)
557 ad9389b_check_edid_status(sd);
563 static const struct v4l2_subdev_core_ops ad9389b_core_ops = {
564 .log_status = ad9389b_log_status,
565 #ifdef CONFIG_VIDEO_ADV_DEBUG
566 .g_register = ad9389b_g_register,
567 .s_register = ad9389b_s_register,
569 .s_power = ad9389b_s_power,
570 .interrupt_service_routine = ad9389b_isr,
573 /* ------------------------------ VIDEO OPS ------------------------------ */
575 /* Enable/disable ad9389b output */
576 static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
578 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
580 ad9389b_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
582 ad9389b_check_monitor_present_status(sd);
584 ad9389b_s_power(sd, 0);
589 static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
590 .type = V4L2_DV_BT_656_1120,
591 /* keep this initialization for compatibility with GCC < 4.4.6 */
593 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
594 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
595 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
596 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
597 V4L2_DV_BT_CAP_CUSTOM)
600 static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
601 struct v4l2_dv_timings *timings)
603 struct ad9389b_state *state = get_ad9389b_state(sd);
605 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
607 /* quick sanity check */
608 if (!v4l2_valid_dv_timings(timings, &ad9389b_timings_cap, NULL, NULL))
611 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
612 if the format is one of the CEA or DMT timings. */
613 v4l2_find_dv_timings_cap(timings, &ad9389b_timings_cap, 0, NULL, NULL);
615 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
618 state->dv_timings = *timings;
620 /* update quantization range based on new dv_timings */
621 ad9389b_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
623 /* update PLL gear based on new dv_timings */
624 if (state->pdata.tmds_pll_gear == AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC)
625 ad9389b_set_manual_pll_gear(sd, (u32)timings->bt.pixelclock);
627 /* update AVI infoframe */
628 ad9389b_set_IT_content_AVI_InfoFrame(sd);
633 static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
634 struct v4l2_dv_timings *timings)
636 struct ad9389b_state *state = get_ad9389b_state(sd);
638 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
643 *timings = state->dv_timings;
648 static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
649 struct v4l2_enum_dv_timings *timings)
651 if (timings->pad != 0)
654 return v4l2_enum_dv_timings_cap(timings, &ad9389b_timings_cap,
658 static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
659 struct v4l2_dv_timings_cap *cap)
664 *cap = ad9389b_timings_cap;
668 static const struct v4l2_subdev_video_ops ad9389b_video_ops = {
669 .s_stream = ad9389b_s_stream,
670 .s_dv_timings = ad9389b_s_dv_timings,
671 .g_dv_timings = ad9389b_g_dv_timings,
674 /* ------------------------------ PAD OPS ------------------------------ */
676 static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
678 struct ad9389b_state *state = get_ad9389b_state(sd);
682 if (edid->blocks == 0 || edid->blocks > 256)
684 if (!state->edid.segments) {
685 v4l2_dbg(1, debug, sd, "EDID segment 0 not found\n");
688 if (edid->start_block >= state->edid.segments * 2)
690 if (edid->blocks + edid->start_block >= state->edid.segments * 2)
691 edid->blocks = state->edid.segments * 2 - edid->start_block;
692 memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
697 static const struct v4l2_subdev_pad_ops ad9389b_pad_ops = {
698 .get_edid = ad9389b_get_edid,
699 .enum_dv_timings = ad9389b_enum_dv_timings,
700 .dv_timings_cap = ad9389b_dv_timings_cap,
703 /* ------------------------------ AUDIO OPS ------------------------------ */
705 static int ad9389b_s_audio_stream(struct v4l2_subdev *sd, int enable)
707 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
710 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x80);
712 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x40);
717 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
722 case 32000: N = 4096; break;
723 case 44100: N = 6272; break;
724 case 48000: N = 6144; break;
725 case 88200: N = 12544; break;
726 case 96000: N = 12288; break;
727 case 176400: N = 25088; break;
728 case 192000: N = 24576; break;
733 /* Set N (used with CTS to regenerate the audio clock) */
734 ad9389b_wr(sd, 0x01, (N >> 16) & 0xf);
735 ad9389b_wr(sd, 0x02, (N >> 8) & 0xff);
736 ad9389b_wr(sd, 0x03, N & 0xff);
741 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
746 case 32000: i2s_sf = 0x30; break;
747 case 44100: i2s_sf = 0x00; break;
748 case 48000: i2s_sf = 0x20; break;
749 case 88200: i2s_sf = 0x80; break;
750 case 96000: i2s_sf = 0xa0; break;
751 case 176400: i2s_sf = 0xc0; break;
752 case 192000: i2s_sf = 0xe0; break;
757 /* Set sampling frequency for I2S audio to 48 kHz */
758 ad9389b_wr_and_or(sd, 0x15, 0xf, i2s_sf);
763 static int ad9389b_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
765 /* TODO based on input/output/config */
766 /* TODO See datasheet "Programmers guide" p. 39-40 */
768 /* Only 2 channels in use for application */
769 ad9389b_wr_and_or(sd, 0x50, 0x1f, 0x20);
770 /* Speaker mapping */
771 ad9389b_wr(sd, 0x51, 0x00);
773 /* TODO Where should this be placed? */
774 /* 16 bit audio word length */
775 ad9389b_wr_and_or(sd, 0x14, 0xf0, 0x02);
780 static const struct v4l2_subdev_audio_ops ad9389b_audio_ops = {
781 .s_stream = ad9389b_s_audio_stream,
782 .s_clock_freq = ad9389b_s_clock_freq,
783 .s_i2s_clock_freq = ad9389b_s_i2s_clock_freq,
784 .s_routing = ad9389b_s_routing,
787 /* --------------------- SUBDEV OPS --------------------------------------- */
789 static const struct v4l2_subdev_ops ad9389b_ops = {
790 .core = &ad9389b_core_ops,
791 .video = &ad9389b_video_ops,
792 .audio = &ad9389b_audio_ops,
793 .pad = &ad9389b_pad_ops,
796 /* ----------------------------------------------------------------------- */
797 static void ad9389b_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd,
798 int segment, u8 *buf)
805 v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
806 for (i = 0; i < 256; i += 16) {
811 v4l2_dbg(lvl, debug, sd, "\n");
812 for (j = i; j < i + 16; j++) {
813 sprintf(bp, "0x%02x, ", buf[j]);
817 v4l2_dbg(lvl, debug, sd, "%s\n", b);
821 static void ad9389b_edid_handler(struct work_struct *work)
823 struct delayed_work *dwork = to_delayed_work(work);
824 struct ad9389b_state *state =
825 container_of(dwork, struct ad9389b_state, edid_handler);
826 struct v4l2_subdev *sd = &state->sd;
827 struct ad9389b_edid_detect ed;
829 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
831 if (ad9389b_check_edid_status(sd)) {
832 /* Return if we received the EDID. */
836 if (ad9389b_have_hotplug(sd)) {
837 /* We must retry reading the EDID several times, it is possible
838 * that initially the EDID couldn't be read due to i2c errors
839 * (DVI connectors are particularly prone to this problem). */
840 if (state->edid.read_retries) {
841 state->edid.read_retries--;
842 v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
843 ad9389b_s_power(sd, false);
844 ad9389b_s_power(sd, true);
845 schedule_delayed_work(&state->edid_handler, EDID_DELAY);
850 /* We failed to read the EDID, so send an event for this. */
852 ed.segment = ad9389b_rd(sd, 0xc4);
853 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
854 v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
857 static void ad9389b_audio_setup(struct v4l2_subdev *sd)
859 v4l2_dbg(1, debug, sd, "%s\n", __func__);
861 ad9389b_s_i2s_clock_freq(sd, 48000);
862 ad9389b_s_clock_freq(sd, 48000);
863 ad9389b_s_routing(sd, 0, 0, 0);
866 /* Initial setup of AD9389b */
868 /* Configure hdmi transmitter. */
869 static void ad9389b_setup(struct v4l2_subdev *sd)
871 struct ad9389b_state *state = get_ad9389b_state(sd);
873 v4l2_dbg(1, debug, sd, "%s\n", __func__);
875 /* Input format: RGB 4:4:4 */
876 ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);
877 /* Output format: RGB 4:4:4 */
878 ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);
879 /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion,
880 Aspect ratio: 16:9 */
881 ad9389b_wr_and_or(sd, 0x17, 0xf9, 0x06);
882 /* Output format: RGB 4:4:4, Active Format Information is valid. */
883 ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);
885 ad9389b_wr_and_or(sd, 0x46, 0x3f, 0x80);
886 /* Setup video format */
887 ad9389b_wr(sd, 0x3c, 0x0);
888 /* Active format aspect ratio: same as picure. */
889 ad9389b_wr(sd, 0x47, 0x80);
891 ad9389b_wr_and_or(sd, 0xaf, 0xef, 0x0);
892 /* Positive clk edge capture for input video clock */
893 ad9389b_wr_and_or(sd, 0xba, 0x1f, 0x60);
895 ad9389b_audio_setup(sd);
897 v4l2_ctrl_handler_setup(&state->hdl);
899 ad9389b_set_IT_content_AVI_InfoFrame(sd);
902 static void ad9389b_notify_monitor_detect(struct v4l2_subdev *sd)
904 struct ad9389b_monitor_detect mdt;
905 struct ad9389b_state *state = get_ad9389b_state(sd);
907 mdt.present = state->have_monitor;
908 v4l2_subdev_notify(sd, AD9389B_MONITOR_DETECT, (void *)&mdt);
911 static void ad9389b_update_monitor_present_status(struct v4l2_subdev *sd)
913 struct ad9389b_state *state = get_ad9389b_state(sd);
914 /* read hotplug and rx-sense state */
915 u8 status = ad9389b_rd(sd, 0x42);
917 v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
920 status & MASK_AD9389B_HPD_DETECT ? ", hotplug" : "",
921 status & MASK_AD9389B_MSEN_DETECT ? ", rx-sense" : "");
923 if (status & MASK_AD9389B_HPD_DETECT) {
924 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
925 state->have_monitor = true;
926 if (!ad9389b_s_power(sd, true)) {
927 v4l2_dbg(1, debug, sd,
928 "%s: monitor detected, powerup failed\n", __func__);
932 ad9389b_notify_monitor_detect(sd);
933 state->edid.read_retries = EDID_MAX_RETRIES;
934 schedule_delayed_work(&state->edid_handler, EDID_DELAY);
935 } else if (!(status & MASK_AD9389B_HPD_DETECT)) {
936 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
937 state->have_monitor = false;
938 ad9389b_notify_monitor_detect(sd);
939 ad9389b_s_power(sd, false);
940 memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
943 /* update read only ctrls */
944 v4l2_ctrl_s_ctrl(state->hotplug_ctrl, ad9389b_have_hotplug(sd) ? 0x1 : 0x0);
945 v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, ad9389b_have_rx_sense(sd) ? 0x1 : 0x0);
946 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
948 /* update with setting from ctrls */
949 ad9389b_s_ctrl(state->rgb_quantization_range_ctrl);
950 ad9389b_s_ctrl(state->hdmi_mode_ctrl);
953 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd)
955 struct ad9389b_state *state = get_ad9389b_state(sd);
958 ad9389b_update_monitor_present_status(sd);
961 * Rapid toggling of the hotplug may leave the chip powered off,
962 * even if we think it is on. In that case reset and power up again.
964 while (state->power_on && (ad9389b_rd(sd, 0x41) & 0x40)) {
966 v4l2_err(sd, "retried %d times, give up\n", retry);
969 v4l2_dbg(1, debug, sd, "%s: reset and re-check status (%d)\n", __func__, retry);
970 ad9389b_notify_monitor_detect(sd);
971 cancel_delayed_work_sync(&state->edid_handler);
972 memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
973 ad9389b_s_power(sd, false);
974 ad9389b_update_monitor_present_status(sd);
978 static bool edid_block_verify_crc(u8 *edid_block)
983 for (i = 0; i < 128; i++)
984 sum += edid_block[i];
988 static bool edid_verify_crc(struct v4l2_subdev *sd, u32 segment)
990 struct ad9389b_state *state = get_ad9389b_state(sd);
991 u32 blocks = state->edid.blocks;
992 u8 *data = state->edid.data;
994 if (edid_block_verify_crc(&data[segment * 256])) {
995 if ((segment + 1) * 2 <= blocks)
996 return edid_block_verify_crc(&data[segment * 256 + 128]);
1002 static bool edid_verify_header(struct v4l2_subdev *sd, u32 segment)
1004 static const u8 hdmi_header[] = {
1005 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1007 struct ad9389b_state *state = get_ad9389b_state(sd);
1008 u8 *data = state->edid.data;
1014 for (i = 0; i < ARRAY_SIZE(hdmi_header); i++)
1015 if (data[i] != hdmi_header[i])
1021 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd)
1023 struct ad9389b_state *state = get_ad9389b_state(sd);
1024 struct ad9389b_edid_detect ed;
1026 u8 edidRdy = ad9389b_rd(sd, 0xc5);
1028 v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1029 __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1031 if (!(edidRdy & MASK_AD9389B_EDID_RDY))
1034 segment = ad9389b_rd(sd, 0xc4);
1035 if (segment >= EDID_MAX_SEGM) {
1036 v4l2_err(sd, "edid segment number too big\n");
1039 v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1040 ad9389b_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1041 ad9389b_dbg_dump_edid(2, debug, sd, segment,
1042 &state->edid.data[segment * 256]);
1044 state->edid.blocks = state->edid.data[0x7e] + 1;
1045 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
1046 __func__, state->edid.blocks);
1048 if (!edid_verify_crc(sd, segment) ||
1049 !edid_verify_header(sd, segment)) {
1050 /* edid crc error, force reread of edid segment */
1051 v4l2_err(sd, "%s: edid crc or header error\n", __func__);
1052 ad9389b_s_power(sd, false);
1053 ad9389b_s_power(sd, true);
1056 /* one more segment read ok */
1057 state->edid.segments = segment + 1;
1058 if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1059 /* Request next EDID segment */
1060 v4l2_dbg(1, debug, sd, "%s: request segment %d\n",
1061 __func__, state->edid.segments);
1062 ad9389b_wr(sd, 0xc9, 0xf);
1063 ad9389b_wr(sd, 0xc4, state->edid.segments);
1064 state->edid.read_retries = EDID_MAX_RETRIES;
1065 schedule_delayed_work(&state->edid_handler, EDID_DELAY);
1069 /* report when we have all segments but report only for segment 0 */
1072 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
1073 state->edid_detect_counter++;
1074 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1078 /* ----------------------------------------------------------------------- */
1080 static void ad9389b_init_setup(struct v4l2_subdev *sd)
1082 struct ad9389b_state *state = get_ad9389b_state(sd);
1083 struct ad9389b_state_edid *edid = &state->edid;
1085 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1087 /* clear all interrupts */
1088 ad9389b_wr(sd, 0x96, 0xff);
1090 memset(edid, 0, sizeof(struct ad9389b_state_edid));
1091 state->have_monitor = false;
1092 ad9389b_set_isr(sd, false);
1095 static int ad9389b_probe(struct i2c_client *client, const struct i2c_device_id *id)
1097 const struct v4l2_dv_timings dv1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
1098 struct ad9389b_state *state;
1099 struct ad9389b_platform_data *pdata = client->dev.platform_data;
1100 struct v4l2_ctrl_handler *hdl;
1101 struct v4l2_subdev *sd;
1104 /* Check if the adapter supports the needed features */
1105 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1108 v4l_dbg(1, debug, client, "detecting ad9389b client on address 0x%x\n",
1111 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1116 if (pdata == NULL) {
1117 v4l_err(client, "No platform data!\n");
1120 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1123 v4l2_i2c_subdev_init(sd, client, &ad9389b_ops);
1124 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1127 v4l2_ctrl_handler_init(hdl, 5);
1129 state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1130 V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1131 0, V4L2_DV_TX_MODE_DVI_D);
1132 state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1133 V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1134 state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1135 V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1136 state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1137 V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1138 state->rgb_quantization_range_ctrl =
1139 v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1140 V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1141 0, V4L2_DV_RGB_RANGE_AUTO);
1142 sd->ctrl_handler = hdl;
1148 state->pad.flags = MEDIA_PAD_FL_SINK;
1149 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
1153 state->chip_revision = ad9389b_rd(sd, 0x0);
1154 if (state->chip_revision != 2) {
1155 v4l2_err(sd, "chip_revision %d != 2\n", state->chip_revision);
1159 v4l2_dbg(1, debug, sd, "reg 0x41 0x%x, chip version (reg 0x00) 0x%x\n",
1160 ad9389b_rd(sd, 0x41), state->chip_revision);
1162 state->edid_i2c_client = i2c_new_dummy(client->adapter, (0x7e>>1));
1163 if (state->edid_i2c_client == NULL) {
1164 v4l2_err(sd, "failed to register edid i2c client\n");
1169 INIT_DELAYED_WORK(&state->edid_handler, ad9389b_edid_handler);
1170 state->dv_timings = dv1080p60;
1172 ad9389b_init_setup(sd);
1173 ad9389b_set_isr(sd, true);
1175 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1176 client->addr << 1, client->adapter->name);
1180 media_entity_cleanup(&sd->entity);
1182 v4l2_ctrl_handler_free(&state->hdl);
1186 /* ----------------------------------------------------------------------- */
1188 static int ad9389b_remove(struct i2c_client *client)
1190 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1191 struct ad9389b_state *state = get_ad9389b_state(sd);
1193 state->chip_revision = -1;
1195 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1196 client->addr << 1, client->adapter->name);
1198 ad9389b_s_stream(sd, false);
1199 ad9389b_s_audio_stream(sd, false);
1200 ad9389b_init_setup(sd);
1201 cancel_delayed_work_sync(&state->edid_handler);
1202 i2c_unregister_device(state->edid_i2c_client);
1203 v4l2_device_unregister_subdev(sd);
1204 media_entity_cleanup(&sd->entity);
1205 v4l2_ctrl_handler_free(sd->ctrl_handler);
1209 /* ----------------------------------------------------------------------- */
1211 static const struct i2c_device_id ad9389b_id[] = {
1216 MODULE_DEVICE_TABLE(i2c, ad9389b_id);
1218 static struct i2c_driver ad9389b_driver = {
1222 .probe = ad9389b_probe,
1223 .remove = ad9389b_remove,
1224 .id_table = ad9389b_id,
1227 module_i2c_driver(ad9389b_driver);