drivers/media/dvb-frontends/tda1004x.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2   /*
   3      Driver for Philips tda1004xh OFDM Demodulator
   4
   5      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   6
   7
   8    */
   9 /*(DEBLOBBED)*/
  10
  11 #include <linux/init.h>
  12 #include <linux/module.h>
  13 #include <linux/device.h>
  14 #include <linux/jiffies.h>
  15 #include <linux/string.h>
  16 #include <linux/slab.h>
  17
  18 #include <media/dvb_frontend.h>
  19 #include "tda1004x.h"
  20
  21 static int debug;
  22 #define dprintk(args...) \
  23         do { \
  24                 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
  25         } while (0)
  26
  27 #define TDA1004X_CHIPID          0x00
  28 #define TDA1004X_AUTO            0x01
  29 #define TDA1004X_IN_CONF1        0x02
  30 #define TDA1004X_IN_CONF2        0x03
  31 #define TDA1004X_OUT_CONF1       0x04
  32 #define TDA1004X_OUT_CONF2       0x05
  33 #define TDA1004X_STATUS_CD       0x06
  34 #define TDA1004X_CONFC4          0x07
  35 #define TDA1004X_DSSPARE2        0x0C
  36 #define TDA10045H_CODE_IN        0x0D
  37 #define TDA10045H_FWPAGE         0x0E
  38 #define TDA1004X_SCAN_CPT        0x10
  39 #define TDA1004X_DSP_CMD         0x11
  40 #define TDA1004X_DSP_ARG         0x12
  41 #define TDA1004X_DSP_DATA1       0x13
  42 #define TDA1004X_DSP_DATA2       0x14
  43 #define TDA1004X_CONFADC1        0x15
  44 #define TDA1004X_CONFC1          0x16
  45 #define TDA10045H_S_AGC          0x1a
  46 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  47 #define TDA1004X_SNR             0x1c
  48 #define TDA1004X_CONF_TS1        0x1e
  49 #define TDA1004X_CONF_TS2        0x1f
  50 #define TDA1004X_CBER_RESET      0x20
  51 #define TDA1004X_CBER_MSB        0x21
  52 #define TDA1004X_CBER_LSB        0x22
  53 #define TDA1004X_CVBER_LUT       0x23
  54 #define TDA1004X_VBER_MSB        0x24
  55 #define TDA1004X_VBER_MID        0x25
  56 #define TDA1004X_VBER_LSB        0x26
  57 #define TDA1004X_UNCOR           0x27
  58
  59 #define TDA10045H_CONFPLL_P      0x2D
  60 #define TDA10045H_CONFPLL_M_MSB  0x2E
  61 #define TDA10045H_CONFPLL_M_LSB  0x2F
  62 #define TDA10045H_CONFPLL_N      0x30
  63
  64 #define TDA10046H_CONFPLL1       0x2D
  65 #define TDA10046H_CONFPLL2       0x2F
  66 #define TDA10046H_CONFPLL3       0x30
  67 #define TDA10046H_TIME_WREF1     0x31
  68 #define TDA10046H_TIME_WREF2     0x32
  69 #define TDA10046H_TIME_WREF3     0x33
  70 #define TDA10046H_TIME_WREF4     0x34
  71 #define TDA10046H_TIME_WREF5     0x35
  72
  73 #define TDA10045H_UNSURW_MSB     0x31
  74 #define TDA10045H_UNSURW_LSB     0x32
  75 #define TDA10045H_WREF_MSB       0x33
  76 #define TDA10045H_WREF_MID       0x34
  77 #define TDA10045H_WREF_LSB       0x35
  78 #define TDA10045H_MUXOUT         0x36
  79 #define TDA1004X_CONFADC2        0x37
  80
  81 #define TDA10045H_IOFFSET        0x38
  82
  83 #define TDA10046H_CONF_TRISTATE1 0x3B
  84 #define TDA10046H_CONF_TRISTATE2 0x3C
  85 #define TDA10046H_CONF_POLARITY  0x3D
  86 #define TDA10046H_FREQ_OFFSET    0x3E
  87 #define TDA10046H_GPIO_OUT_SEL   0x41
  88 #define TDA10046H_GPIO_SELECT    0x42
  89 #define TDA10046H_AGC_CONF       0x43
  90 #define TDA10046H_AGC_THR        0x44
  91 #define TDA10046H_AGC_RENORM     0x45
  92 #define TDA10046H_AGC_GAINS      0x46
  93 #define TDA10046H_AGC_TUN_MIN    0x47
  94 #define TDA10046H_AGC_TUN_MAX    0x48
  95 #define TDA10046H_AGC_IF_MIN     0x49
  96 #define TDA10046H_AGC_IF_MAX     0x4A
  97
  98 #define TDA10046H_FREQ_PHY2_MSB  0x4D
  99 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 100
 101 #define TDA10046H_CVBER_CTRL     0x4F
 102 #define TDA10046H_AGC_IF_LEVEL   0x52
 103 #define TDA10046H_CODE_CPT       0x57
 104 #define TDA10046H_CODE_IN        0x58
 105
 106
 107 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
 108 {
 109         int ret;
 110         u8 buf[] = { reg, data };
 111         struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
 112
 113         dprintk("%s: reg=0x%x, data=0x%x\n", __func__, reg, data);
 114
 115         msg.addr = state->config->demod_address;
 116         ret = i2c_transfer(state->i2c, &msg, 1);
 117
 118         if (ret != 1)
 119                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 120                         __func__, reg, data, ret);
 121
 122         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
 123                 reg, data, ret);
 124         return (ret != 1) ? -1 : 0;
 125 }
 126
 127 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
 128 {
 129         int ret;
 130         u8 b0[] = { reg };
 131         u8 b1[] = { 0 };
 132         struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
 133                                 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
 134
 135         dprintk("%s: reg=0x%x\n", __func__, reg);
 136
 137         msg[0].addr = state->config->demod_address;
 138         msg[1].addr = state->config->demod_address;
 139         ret = i2c_transfer(state->i2c, msg, 2);
 140
 141         if (ret != 2) {
 142                 dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg,
 143                         ret);
 144                 return -EINVAL;
 145         }
 146
 147         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
 148                 reg, b1[0], ret);
 149         return b1[0];
 150 }
 151
 152 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
 153 {
 154         int val;
 155         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __func__, reg,
 156                 mask, data);
 157
 158         // read a byte and check
 159         val = tda1004x_read_byte(state, reg);
 160         if (val < 0)
 161                 return val;
 162
 163         // mask if off
 164         val = val & ~mask;
 165         val |= data & 0xff;
 166
 167         // write it out again
 168         return tda1004x_write_byteI(state, reg, val);
 169 }
 170
 171 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
 172 {
 173         int i;
 174         int result;
 175
 176         dprintk("%s: reg=0x%x, len=0x%x\n", __func__, reg, len);
 177
 178         result = 0;
 179         for (i = 0; i < len; i++) {
 180                 result = tda1004x_write_byteI(state, reg + i, buf[i]);
 181                 if (result != 0)
 182                         break;
 183         }
 184
 185         return result;
 186 }
 187
 188 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
 189 {
 190         int result;
 191         dprintk("%s\n", __func__);
 192
 193         result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
 194         msleep(20);
 195         return result;
 196 }
 197
 198 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
 199 {
 200         dprintk("%s\n", __func__);
 201
 202         return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
 203 }
 204
 205 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
 206                                    u32 bandwidth)
 207 {
 208         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 209         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 210         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 211
 212         switch (bandwidth) {
 213         case 6000000:
 214                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 215                 break;
 216
 217         case 7000000:
 218                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 219                 break;
 220
 221         case 8000000:
 222                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 223                 break;
 224
 225         default:
 226                 return -EINVAL;
 227         }
 228
 229         tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
 230
 231         return 0;
 232 }
 233
 234 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
 235                                    u32 bandwidth)
 236 {
 237         static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
 238         static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
 239         static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
 240
 241         static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
 242         static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
 243         static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
 244         int tda10046_clk53m;
 245
 246         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 247             (state->config->if_freq == TDA10046_FREQ_052))
 248                 tda10046_clk53m = 0;
 249         else
 250                 tda10046_clk53m = 1;
 251         switch (bandwidth) {
 252         case 6000000:
 253                 if (tda10046_clk53m)
 254                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
 255                                                   sizeof(bandwidth_6mhz_53M));
 256                 else
 257                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
 258                                                   sizeof(bandwidth_6mhz_48M));
 259                 if (state->config->if_freq == TDA10046_FREQ_045) {
 260                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
 261                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
 262                 }
 263                 break;
 264
 265         case 7000000:
 266                 if (tda10046_clk53m)
 267                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
 268                                                   sizeof(bandwidth_7mhz_53M));
 269                 else
 270                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
 271                                                   sizeof(bandwidth_7mhz_48M));
 272                 if (state->config->if_freq == TDA10046_FREQ_045) {
 273                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 274                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 275                 }
 276                 break;
 277
 278         case 8000000:
 279                 if (tda10046_clk53m)
 280                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
 281                                                   sizeof(bandwidth_8mhz_53M));
 282                 else
 283                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
 284                                                   sizeof(bandwidth_8mhz_48M));
 285                 if (state->config->if_freq == TDA10046_FREQ_045) {
 286                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 287                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
 288                 }
 289                 break;
 290
 291         default:
 292                 return -EINVAL;
 293         }
 294
 295         return 0;
 296 }
 297
 298 static int tda1004x_do_upload(struct tda1004x_state *state,
 299                               const unsigned char *mem, unsigned int len,
 300                               u8 dspCodeCounterReg, u8 dspCodeInReg)
 301 {
 302         u8 buf[65];
 303         struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
 304         int tx_size;
 305         int pos = 0;
 306
 307         /* clear code counter */
 308         tda1004x_write_byteI(state, dspCodeCounterReg, 0);
 309         fw_msg.addr = state->config->demod_address;
 310
 311         i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT);
 312         buf[0] = dspCodeInReg;
 313         while (pos != len) {
 314                 // work out how much to send this time
 315                 tx_size = len - pos;
 316                 if (tx_size > 0x10)
 317                         tx_size = 0x10;
 318
 319                 // send the chunk
 320                 memcpy(buf + 1, mem + pos, tx_size);
 321                 fw_msg.len = tx_size + 1;
 322                 if (__i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
 323                         printk(KERN_ERR "tda1004x: Error during firmware upload\n");
 324                         i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
 325                         return -EIO;
 326                 }
 327                 pos += tx_size;
 328
 329                 dprintk("%s: fw_pos=0x%x\n", __func__, pos);
 330         }
 331         i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
 332
 333         /* give the DSP a chance to settle 03/10/05 Hac */
 334         msleep(100);
 335
 336         return 0;
 337 }
 338
 339 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
 340 {
 341         u8 data1, data2;
 342         unsigned long timeout;
 343
 344         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 345                 timeout = jiffies + 2 * HZ;
 346                 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
 347                         if (time_after(jiffies, timeout)) {
 348                                 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
 349                                 break;
 350                         }
 351                         msleep(1);
 352                 }
 353         } else
 354                 msleep(100);
 355
 356         // check upload was OK
 357         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 358         tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
 359
 360         data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
 361         data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
 362         if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
 363                 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
 364                 return -EIO;
 365         }
 366         printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
 367         return 0;
 368 }
 369
 370 static int tda10045_fwupload(struct dvb_frontend* fe)
 371 {
 372         struct tda1004x_state* state = fe->demodulator_priv;
 373         int ret;
 374         const struct firmware *fw;
 375
 376         /* don't re-upload unless necessary */
 377         if (tda1004x_check_upload_ok(state) == 0)
 378                 return 0;
 379
 380         /* request the firmware, this will block until someone uploads it */
 381         printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", "/*(DEBLOBBED)*/");
 382         ret = state->config->request_firmware(fe, &fw, "/*(DEBLOBBED)*/");
 383         if (ret) {
 384                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 385                 return ret;
 386         }
 387
 388         /* reset chip */
 389         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
 390         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 391         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 392         msleep(10);
 393
 394         /* set parameters */
 395         tda10045h_set_bandwidth(state, 8000000);
 396
 397         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
 398         release_firmware(fw);
 399         if (ret)
 400                 return ret;
 401         printk(KERN_INFO "tda1004x: firmware upload complete\n");
 402
 403         /* wait for DSP to initialise */
 404         /* DSPREADY doesn't seem to work on the TDA10045H */
 405         msleep(100);
 406
 407         return tda1004x_check_upload_ok(state);
 408 }
 409
 410 static void tda10046_init_plls(struct dvb_frontend* fe)
 411 {
 412         struct tda1004x_state* state = fe->demodulator_priv;
 413         int tda10046_clk53m;
 414
 415         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 416             (state->config->if_freq == TDA10046_FREQ_052))
 417                 tda10046_clk53m = 0;
 418         else
 419                 tda10046_clk53m = 1;
 420
 421         tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
 422         if(tda10046_clk53m) {
 423                 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
 424                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
 425         } else {
 426                 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
 427                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
 428         }
 429         if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
 430                 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __func__);
 431                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
 432         } else {
 433                 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __func__);
 434                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
 435         }
 436         if(tda10046_clk53m)
 437                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
 438         else
 439                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
 440         /* Note clock frequency is handled implicitly */
 441         switch (state->config->if_freq) {
 442         case TDA10046_FREQ_045:
 443                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 444                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 445                 break;
 446         case TDA10046_FREQ_052:
 447                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 448                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
 449                 break;
 450         case TDA10046_FREQ_3617:
 451                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 452                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
 453                 break;
 454         case TDA10046_FREQ_3613:
 455                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 456                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
 457                 break;
 458         }
 459         tda10046h_set_bandwidth(state, 8000000); /* default bandwidth 8 MHz */
 460         /* let the PLLs settle */
 461         msleep(120);
 462 }
 463
 464 static int tda10046_fwupload(struct dvb_frontend* fe)
 465 {
 466         struct tda1004x_state* state = fe->demodulator_priv;
 467         int ret, confc4;
 468         const struct firmware *fw;
 469
 470         /* reset + wake up chip */
 471         if (state->config->xtal_freq == TDA10046_XTAL_4M) {
 472                 confc4 = 0;
 473         } else {
 474                 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __func__);
 475                 confc4 = 0x80;
 476         }
 477         tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
 478
 479         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
 480         /* set GPIO 1 and 3 */
 481         if (state->config->gpio_config != TDA10046_GPTRI) {
 482                 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33);
 483                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f);
 484         }
 485         /* let the clocks recover from sleep */
 486         msleep(10);
 487
 488         /* The PLLs need to be reprogrammed after sleep */
 489         tda10046_init_plls(fe);
 490         tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0);
 491
 492         /* don't re-upload unless necessary */
 493         if (tda1004x_check_upload_ok(state) == 0)
 494                 return 0;
 495
 496         /*
 497            For i2c normal work, we need to slow down the bus speed.
 498            However, the slow down breaks the eeprom firmware load.
 499            So, use normal speed for eeprom booting and then restore the
 500            i2c speed after that. Tested with MSI TV @nyware A/D board,
 501            that comes with firmware version 29 inside their eeprom.
 502
 503            It should also be noticed that no other I2C transfer should
 504            be in course while booting from eeprom, otherwise, tda10046
 505            goes into an instable state. So, proper locking are needed
 506            at the i2c bus master.
 507          */
 508         printk(KERN_INFO "tda1004x: trying to boot from eeprom\n");
 509         tda1004x_write_byteI(state, TDA1004X_CONFC4, 4);
 510         msleep(300);
 511         tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
 512
 513         /* Checks if eeprom firmware went without troubles */
 514         if (tda1004x_check_upload_ok(state) == 0)
 515                 return 0;
 516
 517         /* eeprom firmware didn't work. Load one manually. */
 518
 519         if (state->config->request_firmware != NULL) {
 520                 /* request the firmware, this will block until someone uploads it */
 521                 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
 522                 ret = state->config->request_firmware(fe, &fw, "/*(DEBLOBBED)*/");
 523                 if (ret) {
 524                         /* remain compatible to old bug: try to load with tda10045 image name */
 525                         ret = state->config->request_firmware(fe, &fw, "/*(DEBLOBBED)*/");
 526                         if (ret) {
 527                                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 528                                 return ret;
 529                         } else {
 530                                 printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n",
 531                                                   "/*(DEBLOBBED)*/");
 532                         }
 533                 }
 534         } else {
 535                 printk(KERN_ERR "tda1004x: no request function defined, can't upload from file\n");
 536                 return -EIO;
 537         }
 538         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 539         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
 540         release_firmware(fw);
 541         return tda1004x_check_upload_ok(state);
 542 }
 543
 544 static int tda1004x_encode_fec(int fec)
 545 {
 546         // convert known FEC values
 547         switch (fec) {
 548         case FEC_1_2:
 549                 return 0;
 550         case FEC_2_3:
 551                 return 1;
 552         case FEC_3_4:
 553                 return 2;
 554         case FEC_5_6:
 555                 return 3;
 556         case FEC_7_8:
 557                 return 4;
 558         }
 559
 560         // unsupported
 561         return -EINVAL;
 562 }
 563
 564 static int tda1004x_decode_fec(int tdafec)
 565 {
 566         // convert known FEC values
 567         switch (tdafec) {
 568         case 0:
 569                 return FEC_1_2;
 570         case 1:
 571                 return FEC_2_3;
 572         case 2:
 573                 return FEC_3_4;
 574         case 3:
 575                 return FEC_5_6;
 576         case 4:
 577                 return FEC_7_8;
 578         }
 579
 580         // unsupported
 581         return -1;
 582 }
 583
 584 static int tda1004x_write(struct dvb_frontend* fe, const u8 buf[], int len)
 585 {
 586         struct tda1004x_state* state = fe->demodulator_priv;
 587
 588         if (len != 2)
 589                 return -EINVAL;
 590
 591         return tda1004x_write_byteI(state, buf[0], buf[1]);
 592 }
 593
 594 static int tda10045_init(struct dvb_frontend* fe)
 595 {
 596         struct tda1004x_state* state = fe->demodulator_priv;
 597
 598         dprintk("%s\n", __func__);
 599
 600         if (tda10045_fwupload(fe)) {
 601                 printk("tda1004x: firmware upload failed\n");
 602                 return -EIO;
 603         }
 604
 605         tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 606
 607         // tda setup
 608         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 609         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 610         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
 611         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 612         tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 613         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 614         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 615         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 616         tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 617         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 618         tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
 619
 620         tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
 621
 622         return 0;
 623 }
 624
 625 static int tda10046_init(struct dvb_frontend* fe)
 626 {
 627         struct tda1004x_state* state = fe->demodulator_priv;
 628         dprintk("%s\n", __func__);
 629
 630         if (tda10046_fwupload(fe)) {
 631                 printk("tda1004x: firmware upload failed\n");
 632                 return -EIO;
 633         }
 634
 635         // tda setup
 636         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 637         tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87);    // 100 ppm crystal, select HP stream
 638         tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88);      // enable pulse killer
 639
 640         switch (state->config->agc_config) {
 641         case TDA10046_AGC_DEFAULT:
 642                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
 643                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
 644                 break;
 645         case TDA10046_AGC_IFO_AUTO_NEG:
 646                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 647                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
 648                 break;
 649         case TDA10046_AGC_IFO_AUTO_POS:
 650                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 651                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00);  // set AGC polarities
 652                 break;
 653         case TDA10046_AGC_TDA827X:
 654                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02);   // AGC setup
 655                 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70);    // AGC Threshold
 656                 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
 657                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
 658                 break;
 659         }
 660         if (state->config->ts_mode == 0) {
 661                 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40);
 662                 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
 663         } else {
 664                 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80);
 665                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10,
 666                                                         state->config->invert_oclk << 4);
 667         }
 668         tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
 669         tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on
 670         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);    // }
 671         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 672         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);     // }
 673         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 674         tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
 675         tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
 676         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 677         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
 678         // tda1004x_write_mask(state, 0x50, 0x80, 0x80);         // handle out of guard echoes
 679
 680         return 0;
 681 }
 682
 683 static int tda1004x_set_fe(struct dvb_frontend *fe)
 684 {
 685         struct dtv_frontend_properties *fe_params = &fe->dtv_property_cache;
 686         struct tda1004x_state* state = fe->demodulator_priv;
 687         int tmp;
 688         int inversion;
 689
 690         dprintk("%s\n", __func__);
 691
 692         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 693                 // setup auto offset
 694                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
 695                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
 696                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
 697
 698                 // disable agc_conf[2]
 699                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
 700         }
 701
 702         // set frequency
 703         if (fe->ops.tuner_ops.set_params) {
 704                 fe->ops.tuner_ops.set_params(fe);
 705                 if (fe->ops.i2c_gate_ctrl)
 706                         fe->ops.i2c_gate_ctrl(fe, 0);
 707         }
 708
 709         // Hardcoded to use auto as much as possible on the TDA10045 as it
 710         // is very unreliable if AUTO mode is _not_ used.
 711         if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
 712                 fe_params->code_rate_HP = FEC_AUTO;
 713                 fe_params->guard_interval = GUARD_INTERVAL_AUTO;
 714                 fe_params->transmission_mode = TRANSMISSION_MODE_AUTO;
 715         }
 716
 717         // Set standard params.. or put them to auto
 718         if ((fe_params->code_rate_HP == FEC_AUTO) ||
 719                 (fe_params->code_rate_LP == FEC_AUTO) ||
 720                 (fe_params->modulation == QAM_AUTO) ||
 721                 (fe_params->hierarchy == HIERARCHY_AUTO)) {
 722                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1);        // enable auto
 723                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */
 724                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
 725                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
 726         } else {
 727                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0);        // disable auto
 728
 729                 // set HP FEC
 730                 tmp = tda1004x_encode_fec(fe_params->code_rate_HP);
 731                 if (tmp < 0)
 732                         return tmp;
 733                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
 734
 735                 // set LP FEC
 736                 tmp = tda1004x_encode_fec(fe_params->code_rate_LP);
 737                 if (tmp < 0)
 738                         return tmp;
 739                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 740
 741                 /* set modulation */
 742                 switch (fe_params->modulation) {
 743                 case QPSK:
 744                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
 745                         break;
 746
 747                 case QAM_16:
 748                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
 749                         break;
 750
 751                 case QAM_64:
 752                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
 753                         break;
 754
 755                 default:
 756                         return -EINVAL;
 757                 }
 758
 759                 // set hierarchy
 760                 switch (fe_params->hierarchy) {
 761                 case HIERARCHY_NONE:
 762                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 763                         break;
 764
 765                 case HIERARCHY_1:
 766                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 767                         break;
 768
 769                 case HIERARCHY_2:
 770                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 771                         break;
 772
 773                 case HIERARCHY_4:
 774                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 775                         break;
 776
 777                 default:
 778                         return -EINVAL;
 779                 }
 780         }
 781
 782         // set bandwidth
 783         switch (state->demod_type) {
 784         case TDA1004X_DEMOD_TDA10045:
 785                 tda10045h_set_bandwidth(state, fe_params->bandwidth_hz);
 786                 break;
 787
 788         case TDA1004X_DEMOD_TDA10046:
 789                 tda10046h_set_bandwidth(state, fe_params->bandwidth_hz);
 790                 break;
 791         }
 792
 793         // set inversion
 794         inversion = fe_params->inversion;
 795         if (state->config->invert)
 796                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 797         switch (inversion) {
 798         case INVERSION_OFF:
 799                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
 800                 break;
 801
 802         case INVERSION_ON:
 803                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
 804                 break;
 805
 806         default:
 807                 return -EINVAL;
 808         }
 809
 810         // set guard interval
 811         switch (fe_params->guard_interval) {
 812         case GUARD_INTERVAL_1_32:
 813                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 814                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 815                 break;
 816
 817         case GUARD_INTERVAL_1_16:
 818                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 819                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 820                 break;
 821
 822         case GUARD_INTERVAL_1_8:
 823                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 824                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 825                 break;
 826
 827         case GUARD_INTERVAL_1_4:
 828                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 829                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 830                 break;
 831
 832         case GUARD_INTERVAL_AUTO:
 833                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
 834                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 835                 break;
 836
 837         default:
 838                 return -EINVAL;
 839         }
 840
 841         // set transmission mode
 842         switch (fe_params->transmission_mode) {
 843         case TRANSMISSION_MODE_2K:
 844                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 845                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 846                 break;
 847
 848         case TRANSMISSION_MODE_8K:
 849                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 850                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 851                 break;
 852
 853         case TRANSMISSION_MODE_AUTO:
 854                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
 855                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
 856                 break;
 857
 858         default:
 859                 return -EINVAL;
 860         }
 861
 862         // start the lock
 863         switch (state->demod_type) {
 864         case TDA1004X_DEMOD_TDA10045:
 865                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 866                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 867                 break;
 868
 869         case TDA1004X_DEMOD_TDA10046:
 870                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
 871                 msleep(1);
 872                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
 873                 break;
 874         }
 875
 876         msleep(10);
 877
 878         return 0;
 879 }
 880
 881 static int tda1004x_get_fe(struct dvb_frontend *fe,
 882                            struct dtv_frontend_properties *fe_params)
 883 {
 884         struct tda1004x_state* state = fe->demodulator_priv;
 885         int status;
 886
 887         dprintk("%s\n", __func__);
 888
 889         status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
 890         if (status == -1)
 891                 return -EIO;
 892
 893         /* Only update the properties cache if device is locked */
 894         if (!(status & 8))
 895                 return 0;
 896
 897         // inversion status
 898         fe_params->inversion = INVERSION_OFF;
 899         if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
 900                 fe_params->inversion = INVERSION_ON;
 901         if (state->config->invert)
 902                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
 903
 904         // bandwidth
 905         switch (state->demod_type) {
 906         case TDA1004X_DEMOD_TDA10045:
 907                 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
 908                 case 0x14:
 909                         fe_params->bandwidth_hz = 8000000;
 910                         break;
 911                 case 0xdb:
 912                         fe_params->bandwidth_hz = 7000000;
 913                         break;
 914                 case 0x4f:
 915                         fe_params->bandwidth_hz = 6000000;
 916                         break;
 917                 }
 918                 break;
 919         case TDA1004X_DEMOD_TDA10046:
 920                 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
 921                 case 0x5c:
 922                 case 0x54:
 923                         fe_params->bandwidth_hz = 8000000;
 924                         break;
 925                 case 0x6a:
 926                 case 0x60:
 927                         fe_params->bandwidth_hz = 7000000;
 928                         break;
 929                 case 0x7b:
 930                 case 0x70:
 931                         fe_params->bandwidth_hz = 6000000;
 932                         break;
 933                 }
 934                 break;
 935         }
 936
 937         // FEC
 938         fe_params->code_rate_HP =
 939             tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
 940         fe_params->code_rate_LP =
 941             tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
 942
 943         /* modulation */
 944         switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
 945         case 0:
 946                 fe_params->modulation = QPSK;
 947                 break;
 948         case 1:
 949                 fe_params->modulation = QAM_16;
 950                 break;
 951         case 2:
 952                 fe_params->modulation = QAM_64;
 953                 break;
 954         }
 955
 956         // transmission mode
 957         fe_params->transmission_mode = TRANSMISSION_MODE_2K;
 958         if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
 959                 fe_params->transmission_mode = TRANSMISSION_MODE_8K;
 960
 961         // guard interval
 962         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
 963         case 0:
 964                 fe_params->guard_interval = GUARD_INTERVAL_1_32;
 965                 break;
 966         case 1:
 967                 fe_params->guard_interval = GUARD_INTERVAL_1_16;
 968                 break;
 969         case 2:
 970                 fe_params->guard_interval = GUARD_INTERVAL_1_8;
 971                 break;
 972         case 3:
 973                 fe_params->guard_interval = GUARD_INTERVAL_1_4;
 974                 break;
 975         }
 976
 977         // hierarchy
 978         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
 979         case 0:
 980                 fe_params->hierarchy = HIERARCHY_NONE;
 981                 break;
 982         case 1:
 983                 fe_params->hierarchy = HIERARCHY_1;
 984                 break;
 985         case 2:
 986                 fe_params->hierarchy = HIERARCHY_2;
 987                 break;
 988         case 3:
 989                 fe_params->hierarchy = HIERARCHY_4;
 990                 break;
 991         }
 992
 993         return 0;
 994 }
 995
 996 static int tda1004x_read_status(struct dvb_frontend *fe,
 997                                 enum fe_status *fe_status)
 998 {
 999         struct tda1004x_state* state = fe->demodulator_priv;
1000         int status;
1001         int cber;
1002         int vber;
1003
1004         dprintk("%s\n", __func__);
1005
1006         // read status
1007         status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
1008         if (status == -1)
1009                 return -EIO;
1010
1011         // decode
1012         *fe_status = 0;
1013         if (status & 4)
1014                 *fe_status |= FE_HAS_SIGNAL;
1015         if (status & 2)
1016                 *fe_status |= FE_HAS_CARRIER;
1017         if (status & 8)
1018                 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1019
1020         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1021         // is getting anything valid
1022         if (!(*fe_status & FE_HAS_VITERBI)) {
1023                 // read the CBER
1024                 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1025                 if (cber == -1)
1026                         return -EIO;
1027                 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1028                 if (status == -1)
1029                         return -EIO;
1030                 cber |= (status << 8);
1031                 // The address 0x20 should be read to cope with a TDA10046 bug
1032                 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1033
1034                 if (cber != 65535)
1035                         *fe_status |= FE_HAS_VITERBI;
1036         }
1037
1038         // if we DO have some valid VITERBI output, but don't already have SYNC
1039         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1040         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1041                 // read the VBER
1042                 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1043                 if (vber == -1)
1044                         return -EIO;
1045                 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1046                 if (status == -1)
1047                         return -EIO;
1048                 vber |= (status << 8);
1049                 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1050                 if (status == -1)
1051                         return -EIO;
1052                 vber |= (status & 0x0f) << 16;
1053                 // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1054                 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1055
1056                 // if RS has passed some valid TS packets, then we must be
1057                 // getting some SYNC bytes
1058                 if (vber < 16632)
1059                         *fe_status |= FE_HAS_SYNC;
1060         }
1061
1062         // success
1063         dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
1064         return 0;
1065 }
1066
1067 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1068 {
1069         struct tda1004x_state* state = fe->demodulator_priv;
1070         int tmp;
1071         int reg = 0;
1072
1073         dprintk("%s\n", __func__);
1074
1075         // determine the register to use
1076         switch (state->demod_type) {
1077         case TDA1004X_DEMOD_TDA10045:
1078                 reg = TDA10045H_S_AGC;
1079                 break;
1080
1081         case TDA1004X_DEMOD_TDA10046:
1082                 reg = TDA10046H_AGC_IF_LEVEL;
1083                 break;
1084         }
1085
1086         // read it
1087         tmp = tda1004x_read_byte(state, reg);
1088         if (tmp < 0)
1089                 return -EIO;
1090
1091         *signal = (tmp << 8) | tmp;
1092         dprintk("%s: signal=0x%x\n", __func__, *signal);
1093         return 0;
1094 }
1095
1096 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1097 {
1098         struct tda1004x_state* state = fe->demodulator_priv;
1099         int tmp;
1100
1101         dprintk("%s\n", __func__);
1102
1103         // read it
1104         tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1105         if (tmp < 0)
1106                 return -EIO;
1107         tmp = 255 - tmp;
1108
1109         *snr = ((tmp << 8) | tmp);
1110         dprintk("%s: snr=0x%x\n", __func__, *snr);
1111         return 0;
1112 }
1113
1114 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1115 {
1116         struct tda1004x_state* state = fe->demodulator_priv;
1117         int tmp;
1118         int tmp2;
1119         int counter;
1120
1121         dprintk("%s\n", __func__);
1122
1123         // read the UCBLOCKS and reset
1124         counter = 0;
1125         tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1126         if (tmp < 0)
1127                 return -EIO;
1128         tmp &= 0x7f;
1129         while (counter++ < 5) {
1130                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1131                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1132                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1133
1134                 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1135                 if (tmp2 < 0)
1136                         return -EIO;
1137                 tmp2 &= 0x7f;
1138                 if ((tmp2 < tmp) || (tmp2 == 0))
1139                         break;
1140         }
1141
1142         if (tmp != 0x7f)
1143                 *ucblocks = tmp;
1144         else
1145                 *ucblocks = 0xffffffff;
1146
1147         dprintk("%s: ucblocks=0x%x\n", __func__, *ucblocks);
1148         return 0;
1149 }
1150
1151 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1152 {
1153         struct tda1004x_state* state = fe->demodulator_priv;
1154         int tmp;
1155
1156         dprintk("%s\n", __func__);
1157
1158         // read it in
1159         tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1160         if (tmp < 0)
1161                 return -EIO;
1162         *ber = tmp << 1;
1163         tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1164         if (tmp < 0)
1165                 return -EIO;
1166         *ber |= (tmp << 9);
1167         // The address 0x20 should be read to cope with a TDA10046 bug
1168         tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1169
1170         dprintk("%s: ber=0x%x\n", __func__, *ber);
1171         return 0;
1172 }
1173
1174 static int tda1004x_sleep(struct dvb_frontend* fe)
1175 {
1176         struct tda1004x_state* state = fe->demodulator_priv;
1177         int gpio_conf;
1178
1179         switch (state->demod_type) {
1180         case TDA1004X_DEMOD_TDA10045:
1181                 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1182                 break;
1183
1184         case TDA1004X_DEMOD_TDA10046:
1185                 /* set outputs to tristate */
1186                 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1187                 /* invert GPIO 1 and 3 if desired*/
1188                 gpio_conf = state->config->gpio_config;
1189                 if (gpio_conf >= TDA10046_GP00_I)
1190                         tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f,
1191                                                         (gpio_conf & 0x0f) ^ 0x0a);
1192
1193                 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0);
1194                 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1195                 break;
1196         }
1197
1198         return 0;
1199 }
1200
1201 static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
1202 {
1203         struct tda1004x_state* state = fe->demodulator_priv;
1204
1205         if (enable) {
1206                 return tda1004x_enable_tuner_i2c(state);
1207         } else {
1208                 return tda1004x_disable_tuner_i2c(state);
1209         }
1210 }
1211
1212 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1213 {
1214         fesettings->min_delay_ms = 800;
1215         /* Drift compensation makes no sense for DVB-T */
1216         fesettings->step_size = 0;
1217         fesettings->max_drift = 0;
1218         return 0;
1219 }
1220
1221 static void tda1004x_release(struct dvb_frontend* fe)
1222 {
1223         struct tda1004x_state *state = fe->demodulator_priv;
1224         kfree(state);
1225 }
1226
1227 static const struct dvb_frontend_ops tda10045_ops = {
1228         .delsys = { SYS_DVBT },
1229         .info = {
1230                 .name = "Philips TDA10045H DVB-T",
1231                 .frequency_min_hz =  51 * MHz,
1232                 .frequency_max_hz = 858 * MHz,
1233                 .frequency_stepsize_hz = 166667,
1234                 .caps =
1235                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1236                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1237                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1238                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1239         },
1240
1241         .release = tda1004x_release,
1242
1243         .init = tda10045_init,
1244         .sleep = tda1004x_sleep,
1245         .write = tda1004x_write,
1246         .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1247
1248         .set_frontend = tda1004x_set_fe,
1249         .get_frontend = tda1004x_get_fe,
1250         .get_tune_settings = tda1004x_get_tune_settings,
1251
1252         .read_status = tda1004x_read_status,
1253         .read_ber = tda1004x_read_ber,
1254         .read_signal_strength = tda1004x_read_signal_strength,
1255         .read_snr = tda1004x_read_snr,
1256         .read_ucblocks = tda1004x_read_ucblocks,
1257 };
1258
1259 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1260                                      struct i2c_adapter* i2c)
1261 {
1262         struct tda1004x_state *state;
1263         int id;
1264
1265         /* allocate memory for the internal state */
1266         state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1267         if (!state) {
1268                 printk(KERN_ERR "Can't allocate memory for tda10045 state\n");
1269                 return NULL;
1270         }
1271
1272         /* setup the state */
1273         state->config = config;
1274         state->i2c = i2c;
1275         state->demod_type = TDA1004X_DEMOD_TDA10045;
1276
1277         /* check if the demod is there */
1278         id = tda1004x_read_byte(state, TDA1004X_CHIPID);
1279         if (id < 0) {
1280                 printk(KERN_ERR "tda10045: chip is not answering. Giving up.\n");
1281                 kfree(state);
1282                 return NULL;
1283         }
1284
1285         if (id != 0x25) {
1286                 printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
1287                 kfree(state);
1288                 return NULL;
1289         }
1290
1291         /* create dvb_frontend */
1292         memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1293         state->frontend.demodulator_priv = state;
1294         return &state->frontend;
1295 }
1296
1297 static const struct dvb_frontend_ops tda10046_ops = {
1298         .delsys = { SYS_DVBT },
1299         .info = {
1300                 .name = "Philips TDA10046H DVB-T",
1301                 .frequency_min_hz =  51 * MHz,
1302                 .frequency_max_hz = 858 * MHz,
1303                 .frequency_stepsize_hz = 166667,
1304                 .caps =
1305                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1306                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1307                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1308                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1309         },
1310
1311         .release = tda1004x_release,
1312
1313         .init = tda10046_init,
1314         .sleep = tda1004x_sleep,
1315         .write = tda1004x_write,
1316         .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1317
1318         .set_frontend = tda1004x_set_fe,
1319         .get_frontend = tda1004x_get_fe,
1320         .get_tune_settings = tda1004x_get_tune_settings,
1321
1322         .read_status = tda1004x_read_status,
1323         .read_ber = tda1004x_read_ber,
1324         .read_signal_strength = tda1004x_read_signal_strength,
1325         .read_snr = tda1004x_read_snr,
1326         .read_ucblocks = tda1004x_read_ucblocks,
1327 };
1328
1329 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1330                                      struct i2c_adapter* i2c)
1331 {
1332         struct tda1004x_state *state;
1333         int id;
1334
1335         /* allocate memory for the internal state */
1336         state = kzalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1337         if (!state) {
1338                 printk(KERN_ERR "Can't allocate memory for tda10046 state\n");
1339                 return NULL;
1340         }
1341
1342         /* setup the state */
1343         state->config = config;
1344         state->i2c = i2c;
1345         state->demod_type = TDA1004X_DEMOD_TDA10046;
1346
1347         /* check if the demod is there */
1348         id = tda1004x_read_byte(state, TDA1004X_CHIPID);
1349         if (id < 0) {
1350                 printk(KERN_ERR "tda10046: chip is not answering. Giving up.\n");
1351                 kfree(state);
1352                 return NULL;
1353         }
1354         if (id != 0x46) {
1355                 printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
1356                 kfree(state);
1357                 return NULL;
1358         }
1359
1360         /* create dvb_frontend */
1361         memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1362         state->frontend.demodulator_priv = state;
1363         return &state->frontend;
1364 }
1365
1366 module_param(debug, int, 0644);
1367 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1368
1369 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1370 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1371 MODULE_LICENSE("GPL");
1372
1373 EXPORT_SYMBOL(tda10045_attach);
1374 EXPORT_SYMBOL(tda10046_attach);