4 * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
6 * Copyright (C) ST Microelectronics.
7 * Copyright (C) 2010,2011 NetUP Inc.
8 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/string.h>
25 #include <linux/slab.h>
26 #include <linux/i2c.h>
31 #include "stv0367_defs.h"
32 #include "stv0367_regs.h"
33 #include "stv0367_priv.h"
35 /* Max transfer size done by I2C transfer functions */
36 #define MAX_XFER_SIZE 64
39 module_param_named(debug, stvdebug, int, 0644);
42 module_param_named(i2c_debug, i2cdebug, int, 0644);
44 #define dprintk(args...) \
47 printk(KERN_DEBUG args); \
51 enum active_demod_state { demod_none, demod_ter, demod_cab };
53 struct stv0367cab_state {
54 enum stv0367_cab_signal_type state;
60 int locked; /* channel found */
61 u32 freq_khz; /* found frequency (in kHz) */
62 u32 symbol_rate; /* found symbol rate (in Bds) */
63 enum fe_spectral_inversion spect_inv; /* Spectrum Inversion */
64 u32 qamfec_status_reg; /* status reg to poll for FEC Lock */
67 struct stv0367ter_state {
69 enum stv0367_ter_signal_type state;
70 enum stv0367_ter_if_iq_mode if_iq_mode;
71 enum stv0367_ter_mode mode;/* mode 2K or 8K */
72 enum fe_guard_interval guard;
73 enum stv0367_ter_hierarchy hierarchy;
75 enum fe_spectral_inversion sense; /* current search spectrum */
76 u8 force; /* force mode/guard */
77 u8 bw; /* channel width 6, 7 or 8 in MHz */
78 u8 pBW; /* channel width used during previous lock */
82 s8 echo_pos; /* echo position */
88 struct stv0367_state {
89 struct dvb_frontend fe;
90 struct i2c_adapter *i2c;
92 const struct stv0367_config *config;
95 struct stv0367cab_state *cab_state;
97 struct stv0367ter_state *ter_state;
98 /* flags for operation control */
101 u8 reinit_on_setfrontend;
103 enum active_demod_state activedemod;
106 #define RF_LOOKUP_TABLE_SIZE 31
107 #define RF_LOOKUP_TABLE2_SIZE 16
108 /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
109 static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
111 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
112 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
113 76, 77, 78, 80, 83, 85, 88,
115 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
116 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
117 49, 50, 52, 53, 54, 55, 56,
120 /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
121 static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
123 28, 29, 31, 32, 34, 35, 36, 37,
124 38, 39, 40, 41, 42, 43, 44, 45,
126 57, 58, 59, 60, 61, 62, 63, 64,
127 65, 66, 67, 68, 69, 70, 71, 72,
132 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
134 u8 buf[MAX_XFER_SIZE];
135 struct i2c_msg msg = {
136 .addr = state->config->demod_address,
143 if (2 + len > sizeof(buf)) {
145 "%s: i2c wr reg=%04x: len=%d is too big!\n",
146 KBUILD_MODNAME, reg, len);
153 memcpy(buf + 2, data, len);
156 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
157 state->config->demod_address, reg, buf[2]);
159 ret = i2c_transfer(state->i2c, &msg, 1);
161 printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n",
162 __func__, state->config->demod_address, reg, buf[2]);
164 return (ret != 1) ? -EREMOTEIO : 0;
167 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
169 u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
171 return stv0367_writeregs(state, reg, &tmp, 1);
174 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
178 struct i2c_msg msg[] = {
180 .addr = state->config->demod_address,
185 .addr = state->config->demod_address,
196 ret = i2c_transfer(state->i2c, msg, 2);
198 printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n",
199 __func__, state->config->demod_address, reg, b1[0]);
202 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
203 state->config->demod_address, reg, b1[0]);
208 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
210 u8 position = 0, i = 0;
212 (*mask) = label & 0xff;
214 while ((position == 0) && (i < 8)) {
215 position = ((*mask) >> i) & 0x01;
222 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
226 reg = stv0367_readreg(state, (label >> 16) & 0xffff);
227 extract_mask_pos(label, &mask, &pos);
229 val = mask & (val << pos);
231 reg = (reg & (~mask)) | val;
232 stv0367_writereg(state, (label >> 16) & 0xffff, reg);
236 static void stv0367_setbits(u8 *reg, u32 label, u8 val)
240 extract_mask_pos(label, &mask, &pos);
242 val = mask & (val << pos);
244 (*reg) = ((*reg) & (~mask)) | val;
247 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
252 extract_mask_pos(label, &mask, &pos);
254 val = stv0367_readreg(state, label >> 16);
255 val = (val & mask) >> pos;
260 #if 0 /* Currently, unused */
261 static u8 stv0367_getbits(u8 reg, u32 label)
265 extract_mask_pos(label, &mask, &pos);
267 return (reg & mask) >> pos;
271 static void stv0367_write_table(struct stv0367_state *state,
272 const struct st_register *deftab)
279 stv0367_writereg(state, deftab[i].addr, deftab[i].value);
284 static void stv0367_pll_setup(struct stv0367_state *state,
285 u32 icspeed, u32 xtal)
287 /* note on regs: R367TER_* and R367CAB_* defines each point to
288 * 0xf0d8, so just use R367TER_ for both cases
292 case STV0367_ICSPEED_58000:
296 dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n");
297 /* PLLMDIV: 27, PLLNDIV: 232 */
298 stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
299 stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
304 case STV0367_ICSPEED_53125:
306 /* set internal freq to 53.125MHz */
308 stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
309 stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
312 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
313 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
317 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
318 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
319 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
322 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
323 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
328 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
331 static int stv0367_get_if_khz(struct stv0367_state *state, u32 *ifkhz)
333 if (state->auto_if_khz && state->fe.ops.tuner_ops.get_if_frequency) {
334 state->fe.ops.tuner_ops.get_if_frequency(&state->fe, ifkhz);
335 *ifkhz = *ifkhz / 1000; /* hz -> khz */
337 *ifkhz = state->config->if_khz;
342 static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
344 struct stv0367_state *state = fe->demodulator_priv;
345 u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
347 dprintk("%s:\n", __func__);
350 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
351 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
353 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
354 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
357 stv0367_writereg(state, R367TER_I2CRPT, tmp);
362 static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
364 struct dvb_frontend_ops *frontend_ops = &fe->ops;
365 struct dvb_tuner_ops *tuner_ops = &frontend_ops->tuner_ops;
369 dprintk("%s:\n", __func__);
371 if (tuner_ops->get_frequency) {
372 err = tuner_ops->get_frequency(fe, &freq);
374 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
378 dprintk("%s: frequency=%d\n", __func__, freq);
386 static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
388 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
389 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
390 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
391 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
392 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
393 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
395 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
396 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
397 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
398 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
399 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
400 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
402 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
403 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
404 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
405 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
406 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
407 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
411 static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
413 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
414 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
415 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
416 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
417 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
418 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
420 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
421 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
422 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
423 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
424 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
425 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
427 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
428 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
429 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
430 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
431 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
432 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
436 static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
438 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
439 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
440 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
441 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
442 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
443 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
445 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
446 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
447 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
448 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
449 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
450 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
453 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
454 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
455 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
456 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
457 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
458 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
462 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
464 u32 mclk_Hz = 0; /* master clock frequency (Hz) */
467 dprintk("%s:\n", __func__);
469 if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
470 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
474 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
478 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
482 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
484 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
485 n, m, p, mclk_Hz, ExtClk_Hz);
489 dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
494 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
495 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
499 dprintk("%s:\n", __func__);
501 freq = stv0367ter_get_mclk(state, DemodXtal);
503 if (freq == 53125000)
504 k = 1; /* equivalent to Xtal 25M on 362*/
505 else if (freq == 54000000)
506 k = 0; /* equivalent to Xtal 27M on 362*/
507 else if (freq == 52500000)
508 k = 2; /* equivalent to Xtal 30M on 362*/
512 for (i = 1; i <= 6; i++) {
513 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
515 for (j = 1; j <= 5; j++) {
516 stv0367_writereg(state,
517 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
518 MSB(CellsCoeffs[k][i-1][j-1]));
519 stv0367_writereg(state,
520 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
521 LSB(CellsCoeffs[k][i-1][j-1]));
529 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
531 dprintk("%s:\n", __func__);
533 stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
536 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
537 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
538 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
541 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
542 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
543 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
546 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
547 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
548 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
551 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
552 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
553 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
557 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
560 dprintk("%s:\n", __func__);
562 stv0367_writebits(state, F367TER_NRST_IIR, 0);
566 if (!stv0367ter_filt_coeff_init(state,
567 CellsCoeffs_6MHz_367cofdm,
572 if (!stv0367ter_filt_coeff_init(state,
573 CellsCoeffs_7MHz_367cofdm,
578 if (!stv0367ter_filt_coeff_init(state,
579 CellsCoeffs_8MHz_367cofdm,
587 stv0367_writebits(state, F367TER_NRST_IIR, 1);
592 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
597 dprintk("%s:\n", __func__);
599 com_n = stv0367_readbits(state, F367TER_COM_N);
601 stv0367_writebits(state, F367TER_COM_N, 0x07);
603 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
604 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
606 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
607 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
609 stv0367_writebits(state, F367TER_COM_N, com_n);
613 static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
618 local_tempo = tempo1;
621 local_tempo = tempo2;
625 local_tempo = tempo3;
631 /* msleep(local_tempo); */
636 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
639 unsigned short int SYR_var;
642 dprintk("%s:\n", __func__);
644 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
646 while ((!SYR_var) && (wd > 0)) {
647 usleep_range(2000, 3000);
649 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
653 SYRStatus = FE_TER_NOSYMBOL;
655 SYRStatus = FE_TER_SYMBOLOK;
657 dprintk("stv0367ter_check_syr SYRStatus %s\n",
658 SYR_var == 0 ? "No Symbol" : "OK");
664 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
668 s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
671 dprintk("%s:\n", __func__);
687 CPAMPMin = 0xffff; /*drives to NOCPAMP */
691 dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
693 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
694 while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
695 usleep_range(1000, 2000);
697 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
698 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
700 dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
701 if (CPAMPvalue < CPAMPMin) {
702 CPAMPStatus = FE_TER_NOCPAMP;
703 dprintk("%s: CPAMP failed\n", __func__);
705 dprintk("%s: CPAMP OK !\n", __func__);
706 CPAMPStatus = FE_TER_CPAMPOK;
712 static enum stv0367_ter_signal_type
713 stv0367ter_lock_algo(struct stv0367_state *state)
715 enum stv0367_ter_signal_type ret_flag;
717 u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
720 dprintk("%s:\n", __func__);
727 ret_flag = FE_TER_LOCKOK;
729 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
731 if (state->config->if_iq_mode != 0)
732 stv0367_writebits(state, F367TER_COM_N, 0x07);
734 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
735 stv0367_writebits(state, F367TER_MODE, 0);
736 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
737 usleep_range(5000, 10000);
739 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
742 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
743 return FE_TER_NOSYMBOL;
745 if chip locked on wrong mode first try,
746 it must lock correctly second try */
747 mode = stv0367_readbits(state, F367TER_SYR_MODE);
748 if (stv0367ter_check_cpamp(state, mode) ==
751 ret_flag = FE_TER_NOCPAMP;
757 } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
759 tmp = stv0367_readreg(state, R367TER_SYR_STAT);
760 tmp2 = stv0367_readreg(state, R367TER_STATUS);
761 dprintk("state=%p\n", state);
762 dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
765 tmp = stv0367_readreg(state, R367TER_PRVIT);
766 tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
767 dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
769 tmp = stv0367_readreg(state, R367TER_GAIN_SRC1);
770 dprintk("GAIN_SRC1=0x%x\n", tmp);
772 if ((mode != 0) && (mode != 1) && (mode != 2))
775 /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
777 /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
778 and set channel predictor in automatic */
784 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
785 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
789 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
790 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
798 /*reset fec an reedsolo FOR 367 only*/
799 stv0367_writebits(state, F367TER_RST_SFEC, 1);
800 stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
801 usleep_range(1000, 2000);
802 stv0367_writebits(state, F367TER_RST_SFEC, 0);
803 stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
805 u_var1 = stv0367_readbits(state, F367TER_LK);
806 u_var2 = stv0367_readbits(state, F367TER_PRF);
807 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
808 /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
810 wd = stv0367ter_duration(mode, 125, 500, 250);
811 tempo = stv0367ter_duration(mode, 4, 16, 8);
813 /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */
814 while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
815 usleep_range(1000 * tempo, 1000 * (tempo + 1));
817 u_var1 = stv0367_readbits(state, F367TER_LK);
818 u_var2 = stv0367_readbits(state, F367TER_PRF);
819 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
820 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
824 return FE_TER_NOLOCK;
828 return FE_TER_NOPRFOUND;
833 guard = stv0367_readbits(state, F367TER_SYR_GUARD);
834 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
838 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
839 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
840 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
844 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
845 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
846 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
853 /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
854 if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
856 (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
857 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
858 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
859 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
861 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
863 wd = stv0367ter_duration(mode, 125, 500, 250);
864 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
866 while ((!u_var4) && (wd >= 0)) {
867 usleep_range(1000 * tempo, 1000 * (tempo + 1));
869 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
873 return FE_TER_NOLOCK;
875 /* for 367 leave COM_N at 0x7 for IQ_mode*/
876 /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
878 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
879 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
880 ChipWaitOrAbort(state,1);
884 stv0367_writebits(state,F367TER_COM_N,0x17);
887 stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
889 dprintk("FE_TER_LOCKOK !!!\n");
891 return FE_TER_LOCKOK;
895 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
896 enum stv0367_ts_mode PathTS)
899 dprintk("%s:\n", __func__);
904 stv0367_writebits(state, F367TER_TS_DIS, 0);
907 /*for removing warning :default we can assume in parallel mode*/
908 case STV0367_PARALLEL_PUNCT_CLOCK:
909 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
910 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
912 case STV0367_SERIAL_PUNCT_CLOCK:
913 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
914 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
919 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
920 enum stv0367_clk_pol clock)
923 dprintk("%s:\n", __func__);
929 case STV0367_RISINGEDGE_CLOCK:
930 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
932 case STV0367_FALLINGEDGE_CLOCK:
933 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
935 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
937 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
943 static void stv0367ter_core_sw(struct stv0367_state *state)
946 dprintk("%s:\n", __func__);
948 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
949 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
953 static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
955 struct stv0367_state *state = fe->demodulator_priv;
957 dprintk("%s:\n", __func__);
960 stv0367_writebits(state, F367TER_STDBY, 1);
961 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
962 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
964 stv0367_writebits(state, F367TER_STDBY, 0);
965 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
966 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
972 static int stv0367ter_sleep(struct dvb_frontend *fe)
974 return stv0367ter_standby(fe, 1);
977 static int stv0367ter_init(struct dvb_frontend *fe)
979 struct stv0367_state *state = fe->demodulator_priv;
980 struct stv0367ter_state *ter_state = state->ter_state;
982 dprintk("%s:\n", __func__);
986 stv0367_write_table(state,
987 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
989 stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
991 stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
992 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
994 /*Set TS1 and TS2 to serial or parallel mode */
995 stv0367ter_set_ts_mode(state, state->config->ts_mode);
996 stv0367ter_set_clk_pol(state, state->config->clk_pol);
998 state->chip_id = stv0367_readreg(state, R367TER_ID);
999 ter_state->first_lock = 0;
1000 ter_state->unlock_counter = 2;
1005 static int stv0367ter_algo(struct dvb_frontend *fe)
1007 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1008 struct stv0367_state *state = fe->demodulator_priv;
1009 struct stv0367ter_state *ter_state = state->ter_state;
1010 int offset = 0, tempo = 0;
1012 u8 /*constell,*/ counter;
1014 s32 timing_offset = 0;
1015 u32 trl_nomrate = 0, InternalFreq = 0, temp = 0, ifkhz = 0;
1017 dprintk("%s:\n", __func__);
1019 stv0367_get_if_khz(state, &ifkhz);
1021 ter_state->frequency = p->frequency;
1022 ter_state->force = FE_TER_FORCENONE
1023 + stv0367_readbits(state, F367TER_FORCE) * 2;
1024 ter_state->if_iq_mode = state->config->if_iq_mode;
1025 switch (state->config->if_iq_mode) {
1026 case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */
1027 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1028 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1029 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1030 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1032 case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */
1033 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1034 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1035 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1036 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1038 case FE_TER_IQ_TUNER: /* IQ mode */
1039 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1040 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1041 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1044 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1048 usleep_range(5000, 7000);
1050 switch (p->inversion) {
1051 case INVERSION_AUTO:
1053 dprintk("%s: inversion AUTO\n", __func__);
1054 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1055 stv0367_writebits(state, F367TER_IQ_INVERT,
1058 stv0367_writebits(state, F367TER_INV_SPECTR,
1064 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1065 stv0367_writebits(state, F367TER_IQ_INVERT,
1068 stv0367_writebits(state, F367TER_INV_SPECTR,
1074 if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1075 (ter_state->pBW != ter_state->bw)) {
1076 stv0367ter_agc_iir_lock_detect_set(state);
1078 /*set fine agc target to 180 for LPIF or IQ mode*/
1079 /* set Q_AGCTarget */
1080 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1081 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1082 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1084 /* set Q_AGCTarget */
1085 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1086 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1087 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1089 if (!stv0367_iir_filt_init(state, ter_state->bw,
1090 state->config->xtal))
1092 /*set IIR filter once for 6,7 or 8MHz BW*/
1093 ter_state->pBW = ter_state->bw;
1095 stv0367ter_agc_iir_rst(state);
1098 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1099 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1101 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1103 InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1105 ((((ter_state->bw * 64 * (1 << 15) * 100)
1106 / (InternalFreq)) * 10) / 7);
1108 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1110 stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1111 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1113 temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1114 stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1115 stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1116 temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1117 stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1118 stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1119 temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1120 stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1123 ((InternalFreq - ifkhz) * (1 << 16) / (InternalFreq));
1125 dprintk("DEROT temp=0x%x\n", temp);
1126 stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1127 stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1129 ter_state->echo_pos = 0;
1130 ter_state->ucblocks = 0; /* liplianin */
1131 ter_state->pBER = 0; /* liplianin */
1132 stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1134 if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1137 ter_state->state = FE_TER_LOCKOK;
1139 ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1140 ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1142 ter_state->first_lock = 1; /* we know sense now :) */
1144 ter_state->agc_val =
1145 (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1146 (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1147 stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1148 (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1150 /* Carrier offset calculation */
1151 stv0367_writebits(state, F367TER_FREEZE, 1);
1152 offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1153 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1154 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1155 stv0367_writebits(state, F367TER_FREEZE, 0);
1156 if (offset > 8388607)
1159 offset = offset * 2 / 16384;
1161 if (ter_state->mode == FE_TER_MODE_2K)
1162 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1163 else if (ter_state->mode == FE_TER_MODE_4K)
1164 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1165 else if (ter_state->mode == FE_TER_MODE_8K)
1166 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1168 if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1169 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1170 (stv0367_readbits(state,
1171 F367TER_STATUS_INV_SPECRUM) == 1)))
1172 offset = offset * -1;
1175 if (ter_state->bw == 6)
1176 offset = (offset * 6) / 8;
1177 else if (ter_state->bw == 7)
1178 offset = (offset * 7) / 8;
1180 ter_state->frequency += offset;
1182 tempo = 10; /* exit even if timing_offset stays null */
1183 while ((timing_offset == 0) && (tempo > 0)) {
1184 usleep_range(10000, 20000); /*was 20ms */
1185 /* fine tuning of timing offset if required */
1186 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1187 + 256 * stv0367_readbits(state,
1188 F367TER_TRL_TOFFSET_HI);
1189 if (timing_offset >= 32768)
1190 timing_offset -= 65536;
1191 trl_nomrate = (512 * stv0367_readbits(state,
1192 F367TER_TRL_NOMRATE_HI)
1193 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1194 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1196 timing_offset = ((signed)(1000000 / trl_nomrate) *
1197 timing_offset) / 2048;
1201 if (timing_offset <= 0) {
1202 timing_offset = (timing_offset - 11) / 22;
1205 timing_offset = (timing_offset + 11) / 22;
1209 for (counter = 0; counter < abs(timing_offset); counter++) {
1210 trl_nomrate += step;
1211 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1213 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1215 usleep_range(1000, 2000);
1218 usleep_range(5000, 6000);
1219 /* unlocks could happen in case of trl centring big step,
1220 then a core off/on restarts demod */
1221 u_var = stv0367_readbits(state, F367TER_LK);
1224 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1226 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1232 static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1234 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1235 struct stv0367_state *state = fe->demodulator_priv;
1236 struct stv0367ter_state *ter_state = state->ter_state;
1239 s8 num_trials, index;
1240 u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1242 if (state->reinit_on_setfrontend)
1243 stv0367ter_init(fe);
1245 if (fe->ops.tuner_ops.set_params) {
1246 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1247 fe->ops.i2c_gate_ctrl(fe, 1);
1248 fe->ops.tuner_ops.set_params(fe);
1249 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1250 fe->ops.i2c_gate_ctrl(fe, 0);
1253 switch (p->transmission_mode) {
1255 case TRANSMISSION_MODE_AUTO:
1256 case TRANSMISSION_MODE_2K:
1257 ter_state->mode = FE_TER_MODE_2K;
1259 /* case TRANSMISSION_MODE_4K:
1260 pLook.mode = FE_TER_MODE_4K;
1262 case TRANSMISSION_MODE_8K:
1263 ter_state->mode = FE_TER_MODE_8K;
1267 switch (p->guard_interval) {
1269 case GUARD_INTERVAL_1_32:
1270 case GUARD_INTERVAL_1_16:
1271 case GUARD_INTERVAL_1_8:
1272 case GUARD_INTERVAL_1_4:
1273 ter_state->guard = p->guard_interval;
1275 case GUARD_INTERVAL_AUTO:
1276 ter_state->guard = GUARD_INTERVAL_1_32;
1280 switch (p->bandwidth_hz) {
1282 ter_state->bw = FE_TER_CHAN_BW_6M;
1285 ter_state->bw = FE_TER_CHAN_BW_7M;
1289 ter_state->bw = FE_TER_CHAN_BW_8M;
1292 ter_state->hierarchy = FE_TER_HIER_NONE;
1294 switch (p->inversion) {
1301 if (ter_state->first_lock)
1306 ter_state->state = FE_TER_NOLOCK;
1309 while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1310 if (!ter_state->first_lock) {
1311 if (p->inversion == INVERSION_AUTO)
1312 ter_state->sense = SenseTrials[index];
1315 stv0367ter_algo(fe);
1317 if ((ter_state->state == FE_TER_LOCKOK) &&
1318 (p->inversion == INVERSION_AUTO) &&
1320 /* invert spectrum sense */
1321 SenseTrials[index] = SenseTrials[0];
1322 SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1331 static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1333 struct stv0367_state *state = fe->demodulator_priv;
1334 struct stv0367ter_state *ter_state = state->ter_state;
1337 /*wait for counting completion*/
1338 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1340 ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1342 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1344 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1345 ter_state->ucblocks = errs;
1348 (*ucblocks) = ter_state->ucblocks;
1353 static int stv0367ter_get_frontend(struct dvb_frontend *fe,
1354 struct dtv_frontend_properties *p)
1356 struct stv0367_state *state = fe->demodulator_priv;
1357 struct stv0367ter_state *ter_state = state->ter_state;
1358 enum stv0367_ter_mode mode;
1359 int constell = 0,/* snr = 0,*/ Data = 0;
1361 p->frequency = stv0367_get_tuner_freq(fe);
1362 if ((int)p->frequency < 0)
1363 p->frequency = -p->frequency;
1365 constell = stv0367_readbits(state, F367TER_TPS_CONST);
1367 p->modulation = QPSK;
1368 else if (constell == 1)
1369 p->modulation = QAM_16;
1371 p->modulation = QAM_64;
1373 p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1375 /* Get the Hierarchical mode */
1376 Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1380 p->hierarchy = HIERARCHY_NONE;
1383 p->hierarchy = HIERARCHY_1;
1386 p->hierarchy = HIERARCHY_2;
1389 p->hierarchy = HIERARCHY_4;
1392 p->hierarchy = HIERARCHY_AUTO;
1396 /* Get the FEC Rate */
1397 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1398 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1400 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1404 p->code_rate_HP = FEC_1_2;
1407 p->code_rate_HP = FEC_2_3;
1410 p->code_rate_HP = FEC_3_4;
1413 p->code_rate_HP = FEC_5_6;
1416 p->code_rate_HP = FEC_7_8;
1419 p->code_rate_HP = FEC_AUTO;
1423 mode = stv0367_readbits(state, F367TER_SYR_MODE);
1426 case FE_TER_MODE_2K:
1427 p->transmission_mode = TRANSMISSION_MODE_2K;
1429 /* case FE_TER_MODE_4K:
1430 p->transmission_mode = TRANSMISSION_MODE_4K;
1432 case FE_TER_MODE_8K:
1433 p->transmission_mode = TRANSMISSION_MODE_8K;
1436 p->transmission_mode = TRANSMISSION_MODE_AUTO;
1439 p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
1444 static u32 stv0367ter_snr_readreg(struct dvb_frontend *fe)
1446 struct stv0367_state *state = fe->demodulator_priv;
1449 u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
1452 usleep_range(2000, 3000);
1453 if (cut == 0x50) /*cut 1.0 cut 1.1*/
1454 snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
1456 snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
1460 snru32 /= 10;/*average on 10 values*/
1465 static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
1467 u32 snrval = stv0367ter_snr_readreg(fe);
1469 *snr = snrval / 1000;
1475 static int stv0367ter_status(struct dvb_frontend *fe)
1478 struct stv0367_state *state = fe->demodulator_priv;
1479 struct stv0367ter_state *ter_state = state->ter_state;
1482 locked = (stv0367_readbits(state, F367TER_LK));
1484 ter_state->unlock_counter += 1;
1486 ter_state->unlock_counter = 0;
1488 if (ter_state->unlock_counter > 2) {
1489 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
1490 (!stv0367_readbits(state, F367TER_LK))) {
1491 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1492 usleep_range(2000, 3000);
1493 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1495 locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
1496 (stv0367_readbits(state, F367TER_LK));
1504 static int stv0367ter_read_status(struct dvb_frontend *fe,
1505 enum fe_status *status)
1507 struct stv0367_state *state = fe->demodulator_priv;
1509 dprintk("%s:\n", __func__);
1513 if (stv0367_readbits(state, F367TER_LK)) {
1514 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
1515 | FE_HAS_SYNC | FE_HAS_LOCK;
1516 dprintk("%s: stv0367 has locked\n", __func__);
1522 static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
1524 struct stv0367_state *state = fe->demodulator_priv;
1525 struct stv0367ter_state *ter_state = state->ter_state;
1526 u32 Errors = 0, tber = 0, temporary = 0;
1527 int abc = 0, def = 0;
1530 /*wait for counting completion*/
1531 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
1532 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
1534 + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
1536 + ((u32)stv0367_readbits(state,
1537 F367TER_SFEC_ERR_CNT_LO));
1538 /*measurement not completed, load previous value*/
1540 tber = ter_state->pBER;
1544 abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
1545 def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
1549 } else if (abc == 0x7) {
1551 temporary = (Errors * 1000000000) / (8 * (1 << 14));
1552 temporary = temporary;
1553 } else if (Errors <= 42) {
1554 temporary = (Errors * 100000000) / (8 * (1 << 14));
1555 temporary = temporary * 10;
1556 } else if (Errors <= 429) {
1557 temporary = (Errors * 10000000) / (8 * (1 << 14));
1558 temporary = temporary * 100;
1559 } else if (Errors <= 4294) {
1560 temporary = (Errors * 1000000) / (8 * (1 << 14));
1561 temporary = temporary * 1000;
1562 } else if (Errors <= 42949) {
1563 temporary = (Errors * 100000) / (8 * (1 << 14));
1564 temporary = temporary * 10000;
1565 } else if (Errors <= 429496) {
1566 temporary = (Errors * 10000) / (8 * (1 << 14));
1567 temporary = temporary * 100000;
1568 } else { /*if (Errors<4294967) 2^22 max error*/
1569 temporary = (Errors * 1000) / (8 * (1 << 14));
1570 temporary = temporary * 100000; /* still to *10 */
1575 /*tber=Errors/(8*(1 <<14));*/
1578 /*tber=Errors/(8*(1 <<16));*/
1579 tber = temporary / 4;
1581 /*tber=Errors/(8*(1 <<18));*/
1582 tber = temporary / 16;
1584 /*tber=Errors/(8*(1 <<20));*/
1585 tber = temporary / 64;
1587 /*tber=Errors/(8*(1 <<22));*/
1588 tber = temporary / 256;
1590 /* should not pass here*/
1593 if ((Errors < 4294967) && (Errors > 429496))
1598 /* save actual value */
1599 ter_state->pBER = tber;
1606 static u32 stv0367ter_get_per(struct stv0367_state *state)
1608 struct stv0367ter_state *ter_state = state->ter_state;
1609 u32 Errors = 0, Per = 0, temporary = 0;
1610 int abc = 0, def = 0, cpt = 0;
1612 while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
1613 (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
1614 usleep_range(1000, 2000);
1615 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1617 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1619 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1622 abc = stv0367_readbits(state, F367TER_ERR_SRC1);
1623 def = stv0367_readbits(state, F367TER_NUM_EVT1);
1627 else if (abc == 0x9) {
1629 temporary = (Errors * 1000000000) / (8 * (1 << 8));
1630 temporary = temporary;
1631 } else if (Errors <= 42) {
1632 temporary = (Errors * 100000000) / (8 * (1 << 8));
1633 temporary = temporary * 10;
1634 } else if (Errors <= 429) {
1635 temporary = (Errors * 10000000) / (8 * (1 << 8));
1636 temporary = temporary * 100;
1637 } else if (Errors <= 4294) {
1638 temporary = (Errors * 1000000) / (8 * (1 << 8));
1639 temporary = temporary * 1000;
1640 } else if (Errors <= 42949) {
1641 temporary = (Errors * 100000) / (8 * (1 << 8));
1642 temporary = temporary * 10000;
1643 } else { /*if(Errors<=429496) 2^16 errors max*/
1644 temporary = (Errors * 10000) / (8 * (1 << 8));
1645 temporary = temporary * 100000;
1650 /*Per=Errors/(1 << 8);*/
1653 /*Per=Errors/(1 << 10);*/
1654 Per = temporary / 4;
1656 /*Per=Errors/(1 << 12);*/
1657 Per = temporary / 16;
1659 /*Per=Errors/(1 << 14);*/
1660 Per = temporary / 64;
1662 /*Per=Errors/(1 << 16);*/
1663 Per = temporary / 256;
1668 /* save actual value */
1669 ter_state->pPER = Per;
1674 static int stv0367_get_tune_settings(struct dvb_frontend *fe,
1675 struct dvb_frontend_tune_settings
1678 fe_tune_settings->min_delay_ms = 1000;
1679 fe_tune_settings->step_size = 0;
1680 fe_tune_settings->max_drift = 0;
1685 static void stv0367_release(struct dvb_frontend *fe)
1687 struct stv0367_state *state = fe->demodulator_priv;
1689 kfree(state->ter_state);
1690 kfree(state->cab_state);
1694 static const struct dvb_frontend_ops stv0367ter_ops = {
1695 .delsys = { SYS_DVBT },
1697 .name = "ST STV0367 DVB-T",
1698 .frequency_min = 47000000,
1699 .frequency_max = 862000000,
1700 .frequency_stepsize = 15625,
1701 .frequency_tolerance = 0,
1702 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1703 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
1705 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1706 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
1707 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
1708 FE_CAN_INVERSION_AUTO |
1711 .release = stv0367_release,
1712 .init = stv0367ter_init,
1713 .sleep = stv0367ter_sleep,
1714 .i2c_gate_ctrl = stv0367ter_gate_ctrl,
1715 .set_frontend = stv0367ter_set_frontend,
1716 .get_frontend = stv0367ter_get_frontend,
1717 .get_tune_settings = stv0367_get_tune_settings,
1718 .read_status = stv0367ter_read_status,
1719 .read_ber = stv0367ter_read_ber,/* too slow */
1720 /* .read_signal_strength = stv0367_read_signal_strength,*/
1721 .read_snr = stv0367ter_read_snr,
1722 .read_ucblocks = stv0367ter_read_ucblocks,
1725 struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
1726 struct i2c_adapter *i2c)
1728 struct stv0367_state *state = NULL;
1729 struct stv0367ter_state *ter_state = NULL;
1731 /* allocate memory for the internal state */
1732 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
1735 ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
1736 if (ter_state == NULL)
1739 /* setup the state */
1741 state->config = config;
1742 state->ter_state = ter_state;
1743 state->fe.ops = stv0367ter_ops;
1744 state->fe.demodulator_priv = state;
1745 state->chip_id = stv0367_readreg(state, 0xf000);
1747 /* demod operation options */
1748 state->use_i2c_gatectrl = 1;
1749 state->deftabs = STV0367_DEFTAB_GENERIC;
1750 state->reinit_on_setfrontend = 1;
1751 state->auto_if_khz = 0;
1753 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
1755 /* check if the demod is there */
1756 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
1766 EXPORT_SYMBOL_GPL(stv0367ter_attach);
1768 static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
1770 struct stv0367_state *state = fe->demodulator_priv;
1772 dprintk("%s:\n", __func__);
1774 stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
1779 static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
1781 struct stv0367_state *state = fe->demodulator_priv;
1782 u32 mclk_Hz = 0;/* master clock frequency (Hz) */
1786 if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
1787 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
1791 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
1795 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
1800 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
1801 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
1804 mclk_Hz = ExtClk_Hz;
1806 dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
1811 static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
1813 u32 ADCClk_Hz = ExtClk_Hz;
1815 ADCClk_Hz = stv0367cab_get_mclk(fe, ExtClk_Hz);
1820 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
1822 enum stv0367cab_mod QAMSize)
1825 stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
1827 /* Set Registers settings specific to the QAM size */
1829 case FE_CAB_MOD_QAM4:
1830 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1832 case FE_CAB_MOD_QAM16:
1833 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
1834 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1835 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1836 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1837 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1838 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1839 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1840 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
1842 case FE_CAB_MOD_QAM32:
1843 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1844 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
1845 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1846 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1847 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
1848 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
1849 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1850 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1852 case FE_CAB_MOD_QAM64:
1853 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
1854 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1855 if (SymbolRate > 4500000) {
1856 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1857 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1858 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
1859 } else if (SymbolRate > 2500000) {
1860 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1861 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1862 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1864 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1865 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1866 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1868 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1869 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1870 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
1872 case FE_CAB_MOD_QAM128:
1873 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1874 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
1875 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1876 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
1877 if (SymbolRate > 4500000)
1878 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1879 else if (SymbolRate > 2500000)
1880 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1882 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
1884 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
1885 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1886 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1888 case FE_CAB_MOD_QAM256:
1889 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
1890 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1891 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1892 if (SymbolRate > 4500000)
1893 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1894 else if (SymbolRate > 2500000)
1895 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1897 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1899 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1900 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
1901 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1902 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1904 case FE_CAB_MOD_QAM512:
1905 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1907 case FE_CAB_MOD_QAM1024:
1908 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1917 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
1918 u32 adc_hz, s32 derot_hz)
1923 adc_khz = adc_hz / 1000;
1925 dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
1928 if (derot_hz < 1000000)
1929 derot_hz = adc_hz / 4; /* ZIF operation */
1930 if (derot_hz > adc_hz)
1931 derot_hz = derot_hz - adc_hz;
1932 sampled_if = (u32)derot_hz / 1000;
1933 sampled_if *= 32768;
1934 sampled_if /= adc_khz;
1938 if (sampled_if > 8388607)
1939 sampled_if = 8388607;
1941 dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
1943 stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
1944 stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
1945 stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
1950 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
1954 sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
1955 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
1956 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
1959 sampled_if *= (adc_hz / 1000);
1961 sampled_if /= 32768;
1966 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
1967 u32 mclk_hz, u32 SymbolRate,
1968 enum stv0367cab_mod QAMSize)
1970 u32 QamSizeCorr = 0;
1971 u32 u32_tmp = 0, u32_tmp1 = 0;
1974 dprintk("%s:\n", __func__);
1976 /* Set Correction factor of SRC gain */
1978 case FE_CAB_MOD_QAM4:
1981 case FE_CAB_MOD_QAM16:
1984 case FE_CAB_MOD_QAM32:
1987 case FE_CAB_MOD_QAM64:
1990 case FE_CAB_MOD_QAM128:
1993 case FE_CAB_MOD_QAM256:
1996 case FE_CAB_MOD_QAM512:
1999 case FE_CAB_MOD_QAM1024:
2006 /* Transfer ratio calculation */
2008 u32_tmp = 256 * SymbolRate;
2009 u32_tmp = u32_tmp / adc_hz;
2011 stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2013 /* Symbol rate and SRC gain calculation */
2014 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2016 u32_tmp = SymbolRate;
2017 u32_tmp1 = SymbolRate;
2019 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2020 /* Symbol rate calculation */
2021 u32_tmp *= 2048; /* 2048 = 2^11 */
2022 u32_tmp = u32_tmp / adp_khz;
2023 u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2024 u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2025 u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2027 /* SRC Gain Calculation */
2028 u32_tmp1 *= 2048; /* *2*2^10 */
2029 u32_tmp1 /= 439; /* *2/878 */
2030 u32_tmp1 *= 256; /* *2^8 */
2031 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2032 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2033 u32_tmp1 = u32_tmp1 / 10000000;
2035 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2036 /* Symbol rate calculation */
2037 u32_tmp *= 1024 ; /* 1024 = 2**10 */
2038 u32_tmp = u32_tmp / adp_khz;
2039 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2040 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2041 u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2043 /* SRC Gain Calculation */
2044 u32_tmp1 *= 1024; /* *2*2^9 */
2045 u32_tmp1 /= 439; /* *2/878 */
2046 u32_tmp1 *= 256; /* *2^8 */
2047 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2048 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2049 u32_tmp1 = u32_tmp1 / 5000000;
2050 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2051 /* Symbol rate calculation */
2052 u32_tmp *= 512 ; /* 512 = 2**9 */
2053 u32_tmp = u32_tmp / adp_khz;
2054 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2055 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2056 u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2058 /* SRC Gain Calculation */
2059 u32_tmp1 *= 512; /* *2*2^8 */
2060 u32_tmp1 /= 439; /* *2/878 */
2061 u32_tmp1 *= 256; /* *2^8 */
2062 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2063 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2064 u32_tmp1 = u32_tmp1 / 2500000;
2066 /* Symbol rate calculation */
2067 u32_tmp *= 256 ; /* 256 = 2**8 */
2068 u32_tmp = u32_tmp / adp_khz;
2069 u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2070 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2071 u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2073 /* SRC Gain Calculation */
2074 u32_tmp1 *= 256; /* 2*2^7 */
2075 u32_tmp1 /= 439; /* *2/878 */
2076 u32_tmp1 *= 256; /* *2^8 */
2077 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2078 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2079 u32_tmp1 = u32_tmp1 / 1250000;
2083 /* Filters' coefficients are calculated and written
2084 into registers only if the filters are enabled */
2085 if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2086 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2088 /* AllPass filter must be enabled
2089 when the adjacents filter is used */
2090 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2091 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2093 /* AllPass filter must be disabled
2094 when the adjacents filter is not used */
2096 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2098 stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2099 stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2100 stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2101 stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2103 stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2104 stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2109 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2114 regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2115 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2116 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2117 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2119 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2121 if (regsym < 134217728) { /* 134217728L = 2**27*/
2122 regsym = regsym * 32; /* 32 = 2**5 */
2123 regsym = regsym / 32768; /* 32768L = 2**15 */
2124 regsym = adp_khz * regsym; /* AdpClk in kHz */
2125 regsym = regsym / 128; /* 128 = 2**7 */
2126 regsym *= 125 ; /* 125 = 1000/2**3 */
2127 regsym /= 2048 ; /* 2048 = 2**11 */
2128 } else if (regsym < 268435456) { /* 268435456L = 2**28 */
2129 regsym = regsym * 16; /* 16 = 2**4 */
2130 regsym = regsym / 32768; /* 32768L = 2**15 */
2131 regsym = adp_khz * regsym; /* AdpClk in kHz */
2132 regsym = regsym / 128; /* 128 = 2**7 */
2133 regsym *= 125 ; /* 125 = 1000/2**3*/
2134 regsym /= 1024 ; /* 256 = 2**10*/
2135 } else if (regsym < 536870912) { /* 536870912L = 2**29*/
2136 regsym = regsym * 8; /* 8 = 2**3 */
2137 regsym = regsym / 32768; /* 32768L = 2**15 */
2138 regsym = adp_khz * regsym; /* AdpClk in kHz */
2139 regsym = regsym / 128; /* 128 = 2**7 */
2140 regsym *= 125 ; /* 125 = 1000/2**3 */
2141 regsym /= 512 ; /* 128 = 2**9 */
2143 regsym = regsym * 4; /* 4 = 2**2 */
2144 regsym = regsym / 32768; /* 32768L = 2**15 */
2145 regsym = adp_khz * regsym; /* AdpClk in kHz */
2146 regsym = regsym / 128; /* 128 = 2**7 */
2147 regsym *= 125 ; /* 125 = 1000/2**3 */
2148 regsym /= 256 ; /* 64 = 2**8 */
2154 static u32 stv0367cab_fsm_status(struct stv0367_state *state)
2156 return stv0367_readbits(state, F367CAB_FSM_STATUS);
2159 static u32 stv0367cab_qamfec_lock(struct stv0367_state *state)
2161 return stv0367_readbits(state,
2162 (state->cab_state->qamfec_status_reg ?
2163 state->cab_state->qamfec_status_reg :
2164 F367CAB_QAMFEC_LOCK));
2168 enum stv0367_cab_signal_type stv0367cab_fsm_signaltype(u32 qam_fsm_status)
2170 enum stv0367_cab_signal_type signaltype = FE_CAB_NOAGC;
2172 switch (qam_fsm_status) {
2174 signaltype = FE_CAB_NOAGC;
2177 signaltype = FE_CAB_NOTIMING;
2180 signaltype = FE_CAB_TIMINGOK;
2183 signaltype = FE_CAB_NOCARRIER;
2186 signaltype = FE_CAB_CARRIEROK;
2189 signaltype = FE_CAB_NOBLIND;
2192 signaltype = FE_CAB_BLINDOK;
2195 signaltype = FE_CAB_NODEMOD;
2198 signaltype = FE_CAB_DEMODOK;
2201 signaltype = FE_CAB_DEMODOK;
2204 signaltype = FE_CAB_NODEMOD;
2207 signaltype = FE_CAB_NOBLIND;
2210 signaltype = FE_CAB_NOSIGNAL;
2219 static int stv0367cab_read_status(struct dvb_frontend *fe,
2220 enum fe_status *status)
2222 struct stv0367_state *state = fe->demodulator_priv;
2224 dprintk("%s:\n", __func__);
2228 /* update cab_state->state from QAM_FSM_STATUS */
2229 state->cab_state->state = stv0367cab_fsm_signaltype(
2230 stv0367cab_fsm_status(state));
2232 if (stv0367cab_qamfec_lock(state)) {
2233 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
2234 | FE_HAS_SYNC | FE_HAS_LOCK;
2235 dprintk("%s: stv0367 has locked\n", __func__);
2237 if (state->cab_state->state > FE_CAB_NOSIGNAL)
2238 *status |= FE_HAS_SIGNAL;
2240 if (state->cab_state->state > FE_CAB_NOCARRIER)
2241 *status |= FE_HAS_CARRIER;
2243 if (state->cab_state->state >= FE_CAB_DEMODOK)
2244 *status |= FE_HAS_VITERBI;
2246 if (state->cab_state->state >= FE_CAB_DATAOK)
2247 *status |= FE_HAS_SYNC;
2253 static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2255 struct stv0367_state *state = fe->demodulator_priv;
2257 dprintk("%s:\n", __func__);
2260 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2261 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2262 stv0367_writebits(state, F367CAB_STDBY, 1);
2263 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2264 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2265 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2266 stv0367_writebits(state, F367CAB_POFFQ, 1);
2267 stv0367_writebits(state, F367CAB_POFFI, 1);
2269 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2270 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2271 stv0367_writebits(state, F367CAB_STDBY, 0);
2272 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2273 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2274 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2275 stv0367_writebits(state, F367CAB_POFFQ, 0);
2276 stv0367_writebits(state, F367CAB_POFFI, 0);
2282 static int stv0367cab_sleep(struct dvb_frontend *fe)
2284 return stv0367cab_standby(fe, 1);
2287 static int stv0367cab_init(struct dvb_frontend *fe)
2289 struct stv0367_state *state = fe->demodulator_priv;
2290 struct stv0367cab_state *cab_state = state->cab_state;
2292 dprintk("%s:\n", __func__);
2294 stv0367_write_table(state,
2295 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
2297 switch (state->config->ts_mode) {
2298 case STV0367_DVBCI_CLOCK:
2299 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2300 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2302 case STV0367_SERIAL_PUNCT_CLOCK:
2303 case STV0367_SERIAL_CONT_CLOCK:
2304 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2306 case STV0367_PARALLEL_PUNCT_CLOCK:
2307 case STV0367_OUTPUTMODE_DEFAULT:
2308 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2312 switch (state->config->clk_pol) {
2313 case STV0367_RISINGEDGE_CLOCK:
2314 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2316 case STV0367_FALLINGEDGE_CLOCK:
2317 case STV0367_CLOCKPOLARITY_DEFAULT:
2318 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2322 stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2324 stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2326 stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2328 stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2330 stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2332 cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2333 cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2338 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2339 struct dtv_frontend_properties *p)
2341 struct stv0367cab_state *cab_state = state->cab_state;
2342 enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2343 u32 QAMFEC_Lock, QAM_Lock, u32_tmp, ifkhz,
2344 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2345 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2349 dprintk("%s:\n", __func__);
2351 stv0367_get_if_khz(state, &ifkhz);
2353 /* Timeouts calculation */
2354 /* A max lock time of 25 ms is allowed for delayed AGC */
2356 /* 100000 symbols needed by the TRL as a maximum value */
2357 TRLTimeOut = 100000000 / p->symbol_rate;
2358 /* CRLSymbols is the needed number of symbols to achieve a lock
2359 within [-4%, +4%] of the symbol rate.
2360 CRL timeout is calculated
2361 for a lock within [-search_range, +search_range].
2362 EQL timeout can be changed depending on
2363 the micro-reflections we want to handle.
2364 A characterization must be performed
2365 with these echoes to get new timeout values.
2367 switch (p->modulation) {
2369 CRLSymbols = 150000;
2373 CRLSymbols = 250000;
2377 CRLSymbols = 200000;
2381 CRLSymbols = 250000;
2385 CRLSymbols = 250000;
2389 CRLSymbols = 200000;
2394 if (pIntParams->search_range < 0) {
2395 CRLTimeOut = (25 * CRLSymbols *
2396 (-pIntParams->search_range / 1000)) /
2397 (pIntParams->symbol_rate / 1000);
2400 CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2401 (p->symbol_rate / 1000);
2403 CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2404 /* Timeouts below 50ms are coerced */
2405 if (CRLTimeOut < 50)
2407 /* A maximum of 100 TS packets is needed to get FEC lock even in case
2408 the spectrum inversion needs to be changed.
2409 This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2412 DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2414 dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2416 /* Reset the TRL to ensure nothing starts until the
2417 AGC is stable which ensures a better lock time
2419 stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2420 /* Set AGC accumulation time to minimum and lock threshold to maximum
2421 in order to speed up the AGC lock */
2422 TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2423 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2424 /* Modulus Mapper is disabled */
2425 stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2426 /* Disable the sweep function */
2427 stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2428 /* The sweep function is never used, Sweep rate must be set to 0 */
2429 /* Set the derotator frequency in Hz */
2430 stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2431 (1000 * (s32)ifkhz + cab_state->derot_offset));
2432 /* Disable the Allpass Filter when the symbol rate is out of range */
2433 if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2434 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2435 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2438 /* Check if the tuner is locked */
2439 tuner_lock = stv0367cab_tuner_get_status(fe);
2440 if (tuner_lock == 0)
2441 return FE_367CAB_NOTUNER;
2443 /* Release the TRL to start demodulator acquisition */
2444 /* Wait for QAM lock */
2446 stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2448 QAM_Lock = stv0367cab_fsm_status(state);
2449 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2452 * We don't wait longer, the frequency/phase offset
2455 LockTime = DemodTimeOut;
2456 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2459 * We don't wait longer, either there is no signal or
2460 * it is not the right symbol rate or it is an analog
2464 LockTime = DemodTimeOut;
2465 u32_tmp = stv0367_readbits(state,
2466 F367CAB_AGC_PWR_WORD_LO) +
2467 (stv0367_readbits(state,
2468 F367CAB_AGC_PWR_WORD_ME) << 8) +
2469 (stv0367_readbits(state,
2470 F367CAB_AGC_PWR_WORD_HI) << 16);
2471 if (u32_tmp >= 131072)
2472 u32_tmp = 262144 - u32_tmp;
2473 u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2474 F367CAB_AGC_IF_BWSEL)));
2476 if (u32_tmp < stv0367_readbits(state,
2477 F367CAB_AGC_PWRREF_LO) +
2478 256 * stv0367_readbits(state,
2479 F367CAB_AGC_PWRREF_HI) - 10)
2482 usleep_range(10000, 20000);
2485 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2486 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2488 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2490 } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2491 (LockTime < DemodTimeOut));
2493 dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2495 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2496 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2497 tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2498 dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2500 tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2501 dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2503 if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2504 /* Wait for FEC lock */
2507 usleep_range(5000, 7000);
2509 QAMFEC_Lock = stv0367cab_qamfec_lock(state);
2510 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
2515 signalType = FE_CAB_DATAOK;
2516 cab_state->spect_inv = stv0367_readbits(state,
2519 /* not clear for me */
2521 if (ifkhz > cab_state->adc_clk / 1000) {
2522 cab_state->freq_khz =
2523 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2524 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2525 - cab_state->adc_clk / 1000 + ifkhz;
2527 cab_state->freq_khz =
2528 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2529 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2533 cab_state->freq_khz =
2534 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
2535 stv0367cab_get_derot_freq(state,
2536 cab_state->adc_clk) -
2537 cab_state->adc_clk / 4000;
2540 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
2542 cab_state->locked = 1;
2544 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
2546 signalType = stv0367cab_fsm_signaltype(QAM_Lock);
2548 /* Set the AGC control values to tracking values */
2549 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
2553 static int stv0367cab_set_frontend(struct dvb_frontend *fe)
2555 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2556 struct stv0367_state *state = fe->demodulator_priv;
2557 struct stv0367cab_state *cab_state = state->cab_state;
2558 enum stv0367cab_mod QAMSize = 0;
2560 dprintk("%s: freq = %d, srate = %d\n", __func__,
2561 p->frequency, p->symbol_rate);
2563 cab_state->derot_offset = 0;
2565 switch (p->modulation) {
2567 QAMSize = FE_CAB_MOD_QAM16;
2570 QAMSize = FE_CAB_MOD_QAM32;
2573 QAMSize = FE_CAB_MOD_QAM64;
2576 QAMSize = FE_CAB_MOD_QAM128;
2579 QAMSize = FE_CAB_MOD_QAM256;
2585 if (state->reinit_on_setfrontend)
2586 stv0367cab_init(fe);
2588 /* Tuner Frequency Setting */
2589 if (fe->ops.tuner_ops.set_params) {
2590 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2591 fe->ops.i2c_gate_ctrl(fe, 1);
2592 fe->ops.tuner_ops.set_params(fe);
2593 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2594 fe->ops.i2c_gate_ctrl(fe, 0);
2597 stv0367cab_SetQamSize(
2602 stv0367cab_set_srate(state,
2607 /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
2608 cab_state->state = stv0367cab_algo(state, p);
2612 static int stv0367cab_get_frontend(struct dvb_frontend *fe,
2613 struct dtv_frontend_properties *p)
2615 struct stv0367_state *state = fe->demodulator_priv;
2616 struct stv0367cab_state *cab_state = state->cab_state;
2619 enum stv0367cab_mod QAMSize;
2621 dprintk("%s:\n", __func__);
2623 stv0367_get_if_khz(state, &ifkhz);
2624 p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
2626 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2628 case FE_CAB_MOD_QAM16:
2629 p->modulation = QAM_16;
2631 case FE_CAB_MOD_QAM32:
2632 p->modulation = QAM_32;
2634 case FE_CAB_MOD_QAM64:
2635 p->modulation = QAM_64;
2637 case FE_CAB_MOD_QAM128:
2638 p->modulation = QAM_128;
2640 case FE_CAB_MOD_QAM256:
2641 p->modulation = QAM_256;
2647 p->frequency = stv0367_get_tuner_freq(fe);
2649 dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
2653 (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
2654 cab_state->adc_clk / 4000);
2658 if (ifkhz > cab_state->adc_clk / 1000)
2659 p->frequency += (ifkhz
2660 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2661 - cab_state->adc_clk / 1000);
2663 p->frequency += (ifkhz
2664 - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
2670 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
2671 u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
2673 stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
2674 stv0367cab_GetPacketsCount(state, Monitor_results);
2679 static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
2681 struct stv0367_state *state = fe->demodulator_priv;
2686 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
2689 s32 RfAgcPwm = 0, IfAgcPwm = 0;
2692 stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
2695 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
2696 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
2697 RfAgcPwm = 100 * RfAgcPwm / 1023;
2700 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
2701 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
2702 if (IfAgcPwm >= 2048)
2707 IfAgcPwm = 100 * IfAgcPwm / 4095;
2709 /* For DTT75467 on NIM */
2710 if (RfAgcPwm < 90 && IfAgcPwm < 28) {
2711 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
2712 if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
2713 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
2717 if (i == RF_LOOKUP_TABLE_SIZE)
2719 } else { /*if IF AGC>10*/
2720 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
2721 if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
2722 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
2726 if (i == RF_LOOKUP_TABLE2_SIZE)
2732 static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
2734 struct stv0367_state *state = fe->demodulator_priv;
2736 s32 signal = stv0367cab_get_rf_lvl(state);
2738 dprintk("%s: signal=%d dBm\n", __func__, signal);
2743 *strength = (22 + signal) * (-1311);
2745 dprintk("%s: strength=%d\n", __func__, (*strength));
2750 static int stv0367cab_snr_power(struct dvb_frontend *fe)
2752 struct stv0367_state *state = fe->demodulator_priv;
2753 enum stv0367cab_mod QAMSize;
2755 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2757 case FE_CAB_MOD_QAM4:
2759 case FE_CAB_MOD_QAM16:
2761 case FE_CAB_MOD_QAM32:
2763 case FE_CAB_MOD_QAM64:
2765 case FE_CAB_MOD_QAM128:
2767 case FE_CAB_MOD_QAM256:
2769 case FE_CAB_MOD_QAM1024:
2778 static int stv0367cab_snr_readreg(struct dvb_frontend *fe, int avgdiv)
2780 struct stv0367_state *state = fe->demodulator_priv;
2784 for (i = 0; i < 10; i++) {
2785 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
2786 + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
2795 static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
2797 struct stv0367_state *state = fe->demodulator_priv;
2798 u32 noisepercentage;
2799 u32 regval = 0, temp = 0;
2802 power = stv0367cab_snr_power(fe);
2803 regval = stv0367cab_snr_readreg(fe, 1);
2807 * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
2811 /* table values, not needed to calculate logarithms */
2813 noisepercentage = 100;
2814 else if (temp >= 3981)
2815 noisepercentage = 93;
2816 else if (temp >= 3162)
2817 noisepercentage = 86;
2818 else if (temp >= 2512)
2819 noisepercentage = 79;
2820 else if (temp >= 1995)
2821 noisepercentage = 72;
2822 else if (temp >= 1585)
2823 noisepercentage = 65;
2824 else if (temp >= 1259)
2825 noisepercentage = 58;
2826 else if (temp >= 1000)
2827 noisepercentage = 50;
2828 else if (temp >= 794)
2829 noisepercentage = 43;
2830 else if (temp >= 501)
2831 noisepercentage = 36;
2832 else if (temp >= 316)
2833 noisepercentage = 29;
2834 else if (temp >= 200)
2835 noisepercentage = 22;
2836 else if (temp >= 158)
2837 noisepercentage = 14;
2838 else if (temp >= 126)
2839 noisepercentage = 7;
2841 noisepercentage = 0;
2843 dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
2845 *snr = (noisepercentage * 65535) / 100;
2850 static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
2852 struct stv0367_state *state = fe->demodulator_priv;
2853 int corrected, tscount;
2855 *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
2856 | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
2857 corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
2858 | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
2859 tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
2860 | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
2862 dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
2863 __func__, *ucblocks, corrected, tscount);
2868 static const struct dvb_frontend_ops stv0367cab_ops = {
2869 .delsys = { SYS_DVBC_ANNEX_A },
2871 .name = "ST STV0367 DVB-C",
2872 .frequency_min = 47000000,
2873 .frequency_max = 862000000,
2874 .frequency_stepsize = 62500,
2875 .symbol_rate_min = 870000,
2876 .symbol_rate_max = 11700000,
2877 .caps = 0x400 |/* FE_CAN_QAM_4 */
2878 FE_CAN_QAM_16 | FE_CAN_QAM_32 |
2879 FE_CAN_QAM_64 | FE_CAN_QAM_128 |
2880 FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
2882 .release = stv0367_release,
2883 .init = stv0367cab_init,
2884 .sleep = stv0367cab_sleep,
2885 .i2c_gate_ctrl = stv0367cab_gate_ctrl,
2886 .set_frontend = stv0367cab_set_frontend,
2887 .get_frontend = stv0367cab_get_frontend,
2888 .read_status = stv0367cab_read_status,
2889 /* .read_ber = stv0367cab_read_ber, */
2890 .read_signal_strength = stv0367cab_read_strength,
2891 .read_snr = stv0367cab_read_snr,
2892 .read_ucblocks = stv0367cab_read_ucblcks,
2893 .get_tune_settings = stv0367_get_tune_settings,
2896 struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
2897 struct i2c_adapter *i2c)
2899 struct stv0367_state *state = NULL;
2900 struct stv0367cab_state *cab_state = NULL;
2902 /* allocate memory for the internal state */
2903 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2906 cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
2907 if (cab_state == NULL)
2910 /* setup the state */
2912 state->config = config;
2913 cab_state->search_range = 280000;
2914 cab_state->qamfec_status_reg = F367CAB_QAMFEC_LOCK;
2915 state->cab_state = cab_state;
2916 state->fe.ops = stv0367cab_ops;
2917 state->fe.demodulator_priv = state;
2918 state->chip_id = stv0367_readreg(state, 0xf000);
2920 /* demod operation options */
2921 state->use_i2c_gatectrl = 1;
2922 state->deftabs = STV0367_DEFTAB_GENERIC;
2923 state->reinit_on_setfrontend = 1;
2924 state->auto_if_khz = 0;
2926 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2928 /* check if the demod is there */
2929 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2939 EXPORT_SYMBOL_GPL(stv0367cab_attach);
2942 * Functions for operation on Digital Devices hardware
2945 static void stv0367ddb_setup_ter(struct stv0367_state *state)
2947 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2948 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
2949 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
2950 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
2951 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2952 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2955 /* Buffer Q disabled, I Enabled, unsigned ADC */
2956 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
2957 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
2960 /* PLL bypassed and disabled */
2961 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2962 stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
2964 /* IC runs at 54 MHz with a 27 MHz crystal */
2965 stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
2968 /* PLL enabled and used */
2969 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2971 state->activedemod = demod_ter;
2974 static void stv0367ddb_setup_cab(struct stv0367_state *state)
2976 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2977 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
2978 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
2979 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
2980 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2981 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2984 /* Buffer Q disabled, I Enabled, signed ADC */
2985 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
2987 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
2990 /* PLL bypassed and disabled */
2991 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2993 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
2995 /* IC runs at 58 MHz with a 27 MHz crystal */
2996 stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
2999 /* PLL enabled and used */
3000 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
3002 state->cab_state->mclk = stv0367cab_get_mclk(&state->fe,
3003 state->config->xtal);
3004 state->cab_state->adc_clk = stv0367cab_get_adc_freq(&state->fe,
3005 state->config->xtal);
3007 state->activedemod = demod_cab;
3010 static int stv0367ddb_set_frontend(struct dvb_frontend *fe)
3012 struct stv0367_state *state = fe->demodulator_priv;
3014 switch (fe->dtv_property_cache.delivery_system) {
3016 if (state->activedemod != demod_ter)
3017 stv0367ddb_setup_ter(state);
3019 return stv0367ter_set_frontend(fe);
3020 case SYS_DVBC_ANNEX_A:
3021 if (state->activedemod != demod_cab)
3022 stv0367ddb_setup_cab(state);
3024 /* protect against division error oopses */
3025 if (fe->dtv_property_cache.symbol_rate == 0) {
3026 printk(KERN_ERR "Invalid symbol rate\n");
3030 return stv0367cab_set_frontend(fe);
3038 static void stv0367ddb_read_signal_strength(struct dvb_frontend *fe)
3040 struct stv0367_state *state = fe->demodulator_priv;
3041 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3044 switch (state->activedemod) {
3046 signalstrength = stv0367cab_get_rf_lvl(state) * 1000;
3049 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3053 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
3054 p->strength.stat[0].uvalue = signalstrength;
3057 static void stv0367ddb_read_snr(struct dvb_frontend *fe)
3059 struct stv0367_state *state = fe->demodulator_priv;
3060 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3062 u32 regval, tmpval, snrval = 0;
3064 switch (state->activedemod) {
3066 snrval = stv0367ter_snr_readreg(fe);
3069 cab_pwr = stv0367cab_snr_power(fe);
3070 regval = stv0367cab_snr_readreg(fe, 0);
3072 /* prevent division by zero */
3078 tmpval = (cab_pwr * 320) / regval;
3079 snrval = ((tmpval != 0) ? (intlog2(tmpval) / 5581) : 0);
3082 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3086 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
3087 p->cnr.stat[0].uvalue = snrval;
3090 static void stv0367ddb_read_ucblocks(struct dvb_frontend *fe)
3092 struct stv0367_state *state = fe->demodulator_priv;
3093 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3096 switch (state->activedemod) {
3098 stv0367ter_read_ucblocks(fe, &ucblocks);
3101 stv0367cab_read_ucblcks(fe, &ucblocks);
3104 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3108 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
3109 p->block_error.stat[0].uvalue = ucblocks;
3112 static int stv0367ddb_read_status(struct dvb_frontend *fe,
3113 enum fe_status *status)
3115 struct stv0367_state *state = fe->demodulator_priv;
3116 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3119 switch (state->activedemod) {
3121 ret = stv0367ter_read_status(fe, status);
3124 ret = stv0367cab_read_status(fe, status);
3130 /* stop and report on *_read_status failure */
3134 stv0367ddb_read_signal_strength(fe);
3136 /* read carrier/noise when a carrier is detected */
3137 if (*status & FE_HAS_CARRIER)
3138 stv0367ddb_read_snr(fe);
3140 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3142 /* read uncorrected blocks on FE_HAS_LOCK */
3143 if (*status & FE_HAS_LOCK)
3144 stv0367ddb_read_ucblocks(fe);
3146 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3151 static int stv0367ddb_get_frontend(struct dvb_frontend *fe,
3152 struct dtv_frontend_properties *p)
3154 struct stv0367_state *state = fe->demodulator_priv;
3156 switch (state->activedemod) {
3158 return stv0367ter_get_frontend(fe, p);
3160 return stv0367cab_get_frontend(fe, p);
3168 static int stv0367ddb_sleep(struct dvb_frontend *fe)
3170 struct stv0367_state *state = fe->demodulator_priv;
3172 switch (state->activedemod) {
3174 state->activedemod = demod_none;
3175 return stv0367ter_sleep(fe);
3177 state->activedemod = demod_none;
3178 return stv0367cab_sleep(fe);
3186 static int stv0367ddb_init(struct stv0367_state *state)
3188 struct stv0367ter_state *ter_state = state->ter_state;
3189 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
3191 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3193 if (stv0367_deftabs[state->deftabs][STV0367_TAB_BASE])
3194 stv0367_write_table(state,
3195 stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]);
3197 stv0367_write_table(state,
3198 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
3200 stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
3201 stv0367_write_table(state,
3202 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
3204 stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
3205 stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
3206 stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
3207 stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
3208 stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
3209 stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
3210 stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
3211 stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
3215 stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3216 stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
3217 stv0367_writereg(state, R367TER_TSCFGL, 0x20);
3218 stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
3220 stv0367_writereg(state, R367TER_TSCFGH, 0x71);
3221 stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3223 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3225 /* Also needed for QAM */
3226 stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
3228 stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
3230 /* QAM TS setup, note exact format also depends on descrambler */
3232 /* Inverted Clock, Swap, serial */
3233 stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
3235 /* Clock setup (PLL bypassed and disabled) */
3236 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
3238 /* IC runs at 58 MHz with a 27 MHz crystal */
3239 stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
3242 /* Buffer Q disabled, I Enabled, signed ADC */
3243 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
3244 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
3246 /* Improves the C/N lock limit */
3247 stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
3248 /* ZIF/IF Automatic mode */
3249 stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
3250 /* Improving burst noise performances */
3251 stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
3252 /* Improving ACI performances */
3253 stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
3255 /* PLL enabled and used */
3256 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
3258 stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));
3260 ter_state->pBER = 0;
3261 ter_state->first_lock = 0;
3262 ter_state->unlock_counter = 2;
3264 p->strength.len = 1;
3265 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3267 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3268 p->block_error.len = 1;
3269 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3274 static const struct dvb_frontend_ops stv0367ddb_ops = {
3275 .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT },
3277 .name = "ST STV0367 DDB DVB-C/T",
3278 .frequency_min = 47000000,
3279 .frequency_max = 865000000,
3280 .frequency_stepsize = 166667,
3281 .frequency_tolerance = 0,
3282 .symbol_rate_min = 870000,
3283 .symbol_rate_max = 11700000,
3285 0x400 |/* FE_CAN_QAM_4 */
3286 FE_CAN_QAM_16 | FE_CAN_QAM_32 |
3287 FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3290 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
3291 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
3292 FE_CAN_QPSK | FE_CAN_TRANSMISSION_MODE_AUTO |
3293 FE_CAN_RECOVER | FE_CAN_INVERSION_AUTO |
3296 .release = stv0367_release,
3297 .sleep = stv0367ddb_sleep,
3298 .i2c_gate_ctrl = stv0367cab_gate_ctrl, /* valid for TER and CAB */
3299 .set_frontend = stv0367ddb_set_frontend,
3300 .get_frontend = stv0367ddb_get_frontend,
3301 .get_tune_settings = stv0367_get_tune_settings,
3302 .read_status = stv0367ddb_read_status,
3305 struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config,
3306 struct i2c_adapter *i2c)
3308 struct stv0367_state *state = NULL;
3309 struct stv0367ter_state *ter_state = NULL;
3310 struct stv0367cab_state *cab_state = NULL;
3312 /* allocate memory for the internal state */
3313 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3316 ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
3317 if (ter_state == NULL)
3319 cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3320 if (cab_state == NULL)
3323 /* setup the state */
3325 state->config = config;
3326 state->ter_state = ter_state;
3327 cab_state->search_range = 280000;
3328 cab_state->qamfec_status_reg = F367CAB_DESCR_SYNCSTATE;
3329 state->cab_state = cab_state;
3330 state->fe.ops = stv0367ddb_ops;
3331 state->fe.demodulator_priv = state;
3332 state->chip_id = stv0367_readreg(state, R367TER_ID);
3334 /* demod operation options */
3335 state->use_i2c_gatectrl = 0;
3336 state->deftabs = STV0367_DEFTAB_DDB;
3337 state->reinit_on_setfrontend = 0;
3338 state->auto_if_khz = 1;
3339 state->activedemod = demod_none;
3341 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3343 /* check if the demod is there */
3344 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3347 dev_info(&i2c->dev, "Found %s with ChipID %02X at adr %02X\n",
3348 state->fe.ops.info.name, state->chip_id,
3349 config->demod_address);
3351 stv0367ddb_init(state);
3361 EXPORT_SYMBOL_GPL(stv0367ddb_attach);
3363 MODULE_PARM_DESC(debug, "Set debug");
3364 MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3366 MODULE_AUTHOR("Igor M. Liplianin");
3367 MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3368 MODULE_LICENSE("GPL");