drivers/media/dvb-frontends/mt352_priv.h

   1 /*
   2  *  Driver for Zarlink DVB-T MT352 demodulator
   3  *
   4  *  Written by Holger Waechtler <holger@qanu.de>
   5  *       and Daniel Mack <daniel@qanu.de>
   6  *
   7  *  AVerMedia AVerTV DVB-T 771 support by
   8  *       Wolfram Joost <dbox2@frokaschwei.de>
   9  *
  10  *  Support for Samsung TDTC9251DH01C(M) tuner
  11  *  Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
  12  *                     Amauri  Celani  <acelani@essegi.net>
  13  *
  14  *  DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
  15  *       Christopher Pascoe <c.pascoe@itee.uq.edu.au>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify
  18  *  it under the terms of the GNU General Public License as published by
  19  *  the Free Software Foundation; either version 2 of the License, or
  20  *  (at your option) any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful,
  23  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  *
  26  *  GNU General Public License for more details.
  27  */
  28
  29 #ifndef _MT352_PRIV_
  30 #define _MT352_PRIV_
  31
  32 #define ID_MT352        0x13
  33
  34 #define msb(x) (((x) >> 8) & 0xff)
  35 #define lsb(x) ((x) & 0xff)
  36
  37 enum mt352_reg_addr {
  38         STATUS_0           = 0x00,
  39         STATUS_1           = 0x01,
  40         STATUS_2           = 0x02,
  41         STATUS_3           = 0x03,
  42         STATUS_4           = 0x04,
  43         INTERRUPT_0        = 0x05,
  44         INTERRUPT_1        = 0x06,
  45         INTERRUPT_2        = 0x07,
  46         INTERRUPT_3        = 0x08,
  47         SNR                = 0x09,
  48         VIT_ERR_CNT_2      = 0x0A,
  49         VIT_ERR_CNT_1      = 0x0B,
  50         VIT_ERR_CNT_0      = 0x0C,
  51         RS_ERR_CNT_2       = 0x0D,
  52         RS_ERR_CNT_1       = 0x0E,
  53         RS_ERR_CNT_0       = 0x0F,
  54         RS_UBC_1           = 0x10,
  55         RS_UBC_0           = 0x11,
  56         AGC_GAIN_3         = 0x12,
  57         AGC_GAIN_2         = 0x13,
  58         AGC_GAIN_1         = 0x14,
  59         AGC_GAIN_0         = 0x15,
  60         FREQ_OFFSET_2      = 0x17,
  61         FREQ_OFFSET_1      = 0x18,
  62         FREQ_OFFSET_0      = 0x19,
  63         TIMING_OFFSET_1    = 0x1A,
  64         TIMING_OFFSET_0    = 0x1B,
  65         CHAN_FREQ_1        = 0x1C,
  66         CHAN_FREQ_0        = 0x1D,
  67         TPS_RECEIVED_1     = 0x1E,
  68         TPS_RECEIVED_0     = 0x1F,
  69         TPS_CURRENT_1      = 0x20,
  70         TPS_CURRENT_0      = 0x21,
  71         TPS_CELL_ID_1      = 0x22,
  72         TPS_CELL_ID_0      = 0x23,
  73         TPS_MISC_DATA_2    = 0x24,
  74         TPS_MISC_DATA_1    = 0x25,
  75         TPS_MISC_DATA_0    = 0x26,
  76         RESET              = 0x50,
  77         TPS_GIVEN_1        = 0x51,
  78         TPS_GIVEN_0        = 0x52,
  79         ACQ_CTL            = 0x53,
  80         TRL_NOMINAL_RATE_1 = 0x54,
  81         TRL_NOMINAL_RATE_0 = 0x55,
  82         INPUT_FREQ_1       = 0x56,
  83         INPUT_FREQ_0       = 0x57,
  84         TUNER_ADDR         = 0x58,
  85         CHAN_START_1       = 0x59,
  86         CHAN_START_0       = 0x5A,
  87         CONT_1             = 0x5B,
  88         CONT_0             = 0x5C,
  89         TUNER_GO           = 0x5D,
  90         STATUS_EN_0        = 0x5F,
  91         STATUS_EN_1        = 0x60,
  92         INTERRUPT_EN_0     = 0x61,
  93         INTERRUPT_EN_1     = 0x62,
  94         INTERRUPT_EN_2     = 0x63,
  95         INTERRUPT_EN_3     = 0x64,
  96         AGC_TARGET         = 0x67,
  97         AGC_CTL            = 0x68,
  98         CAPT_RANGE         = 0x75,
  99         SNR_SELECT_1       = 0x79,
 100         SNR_SELECT_0       = 0x7A,
 101         RS_ERR_PER_1       = 0x7C,
 102         RS_ERR_PER_0       = 0x7D,
 103         CHIP_ID            = 0x7F,
 104         CHAN_STOP_1        = 0x80,
 105         CHAN_STOP_0        = 0x81,
 106         CHAN_STEP_1        = 0x82,
 107         CHAN_STEP_0        = 0x83,
 108         FEC_LOCK_TIME      = 0x85,
 109         OFDM_LOCK_TIME     = 0x86,
 110         ACQ_DELAY          = 0x87,
 111         SCAN_CTL           = 0x88,
 112         CLOCK_CTL          = 0x89,
 113         CONFIG             = 0x8A,
 114         MCLK_RATIO         = 0x8B,
 115         GPP_CTL            = 0x8C,
 116         ADC_CTL_1          = 0x8E,
 117         ADC_CTL_0          = 0x8F
 118 };
 119
 120 /* here we assume 1/6MHz == 166.66kHz stepsize */
 121 #define IF_FREQUENCYx6 217    /* 6 * 36.16666666667MHz */
 122
 123 #endif                          /* _MT352_PRIV_ */