1 // SPDX-License-Identifier: GPL-2.0-only
3 * Fujitu mb86a20s ISDB-T/ISDB-Tsb Module driver
5 * Copyright (C) 2010-2013 Mauro Carvalho Chehab
6 * Copyright (C) 2009-2010 Douglas Landgraf <dougsland@redhat.com>
9 #include <linux/kernel.h>
10 #include <asm/div64.h>
12 #include <media/dvb_frontend.h>
17 enum mb86a20s_bandwidth {
19 MB86A20S_13SEG_PARTIAL = 1,
24 static u8 mb86a20s_subchannel[] = {
25 0xb0, 0xc0, 0xd0, 0xe0,
26 0xf0, 0x00, 0x10, 0x20,
29 struct mb86a20s_state {
30 struct i2c_adapter *i2c;
31 const struct mb86a20s_config *config;
34 struct dvb_frontend frontend;
37 enum mb86a20s_bandwidth bw;
41 u32 estimated_rate[NUM_LAYERS];
42 unsigned long get_strength_time;
52 #define BER_SAMPLING_RATE 1 /* Seconds */
55 * Initialization sequence: Use whatevere default values that PV SBTVD
56 * does on its initialisation, obtained via USB snoop
58 static struct regdata mb86a20s_init1[] = {
62 { 0x50, 0xd1 }, { 0x51, 0x20 },
65 static struct regdata mb86a20s_init2[] = {
66 { 0x50, 0xd1 }, { 0x51, 0x22 },
72 { 0x04, 0x08 }, { 0x05, 0x05 },
73 { 0x04, 0x0e }, { 0x05, 0x00 },
74 { 0x04, 0x0f }, { 0x05, 0x14 },
75 { 0x04, 0x0b }, { 0x05, 0x8c },
76 { 0x04, 0x00 }, { 0x05, 0x00 },
77 { 0x04, 0x01 }, { 0x05, 0x07 },
78 { 0x04, 0x02 }, { 0x05, 0x0f },
79 { 0x04, 0x03 }, { 0x05, 0xa0 },
80 { 0x04, 0x09 }, { 0x05, 0x00 },
81 { 0x04, 0x0a }, { 0x05, 0xff },
82 { 0x04, 0x27 }, { 0x05, 0x64 },
83 { 0x04, 0x28 }, { 0x05, 0x00 },
84 { 0x04, 0x1e }, { 0x05, 0xff },
85 { 0x04, 0x29 }, { 0x05, 0x0a },
86 { 0x04, 0x32 }, { 0x05, 0x0a },
87 { 0x04, 0x14 }, { 0x05, 0x02 },
88 { 0x04, 0x04 }, { 0x05, 0x00 },
89 { 0x04, 0x05 }, { 0x05, 0x22 },
90 { 0x04, 0x06 }, { 0x05, 0x0e },
91 { 0x04, 0x07 }, { 0x05, 0xd8 },
92 { 0x04, 0x12 }, { 0x05, 0x00 },
93 { 0x04, 0x13 }, { 0x05, 0xff },
96 * On this demod, when the bit count reaches the count below,
97 * it collects the bit error count. The bit counters are initialized
98 * to 65535 here. This warrants that all of them will be quickly
99 * calculated when device gets locked. As TMCC is parsed, the values
100 * will be adjusted later in the driver's code.
102 { 0x52, 0x01 }, /* Turn on BER before Viterbi */
103 { 0x50, 0xa7 }, { 0x51, 0x00 },
104 { 0x50, 0xa8 }, { 0x51, 0xff },
105 { 0x50, 0xa9 }, { 0x51, 0xff },
106 { 0x50, 0xaa }, { 0x51, 0x00 },
107 { 0x50, 0xab }, { 0x51, 0xff },
108 { 0x50, 0xac }, { 0x51, 0xff },
109 { 0x50, 0xad }, { 0x51, 0x00 },
110 { 0x50, 0xae }, { 0x51, 0xff },
111 { 0x50, 0xaf }, { 0x51, 0xff },
114 * On this demod, post BER counts blocks. When the count reaches the
115 * value below, it collects the block error count. The block counters
116 * are initialized to 127 here. This warrants that all of them will be
117 * quickly calculated when device gets locked. As TMCC is parsed, the
118 * values will be adjusted later in the driver's code.
120 { 0x5e, 0x07 }, /* Turn on BER after Viterbi */
121 { 0x50, 0xdc }, { 0x51, 0x00 },
122 { 0x50, 0xdd }, { 0x51, 0x7f },
123 { 0x50, 0xde }, { 0x51, 0x00 },
124 { 0x50, 0xdf }, { 0x51, 0x7f },
125 { 0x50, 0xe0 }, { 0x51, 0x00 },
126 { 0x50, 0xe1 }, { 0x51, 0x7f },
129 * On this demod, when the block count reaches the count below,
130 * it collects the block error count. The block counters are initialized
131 * to 127 here. This warrants that all of them will be quickly
132 * calculated when device gets locked. As TMCC is parsed, the values
133 * will be adjusted later in the driver's code.
135 { 0x50, 0xb0 }, { 0x51, 0x07 }, /* Enable PER */
136 { 0x50, 0xb2 }, { 0x51, 0x00 },
137 { 0x50, 0xb3 }, { 0x51, 0x7f },
138 { 0x50, 0xb4 }, { 0x51, 0x00 },
139 { 0x50, 0xb5 }, { 0x51, 0x7f },
140 { 0x50, 0xb6 }, { 0x51, 0x00 },
141 { 0x50, 0xb7 }, { 0x51, 0x7f },
143 { 0x50, 0x50 }, { 0x51, 0x02 }, /* MER manual mode */
144 { 0x50, 0x51 }, { 0x51, 0x04 }, /* MER symbol 4 */
145 { 0x45, 0x04 }, /* CN symbol 4 */
146 { 0x48, 0x04 }, /* CN manual mode */
147 { 0x50, 0xd5 }, { 0x51, 0x01 },
148 { 0x50, 0xd6 }, { 0x51, 0x1f },
149 { 0x50, 0xd2 }, { 0x51, 0x03 },
150 { 0x50, 0xd7 }, { 0x51, 0x3f },
152 { 0x28, 0x06 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x03 },
153 { 0x28, 0x07 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0d },
154 { 0x28, 0x08 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x02 },
155 { 0x28, 0x09 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x01 },
156 { 0x28, 0x0a }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x21 },
157 { 0x28, 0x0b }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x29 },
158 { 0x28, 0x0c }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x16 },
159 { 0x28, 0x0d }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x31 },
160 { 0x28, 0x0e }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0e },
161 { 0x28, 0x0f }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x4e },
162 { 0x28, 0x10 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x46 },
163 { 0x28, 0x11 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x0f },
164 { 0x28, 0x12 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x56 },
165 { 0x28, 0x13 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x35 },
166 { 0x28, 0x14 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbe },
167 { 0x28, 0x15 }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0x84 },
168 { 0x28, 0x16 }, { 0x29, 0x00 }, { 0x2a, 0x03 }, { 0x2b, 0xee },
169 { 0x28, 0x17 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x98 },
170 { 0x28, 0x18 }, { 0x29, 0x00 }, { 0x2a, 0x00 }, { 0x2b, 0x9f },
171 { 0x28, 0x19 }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0xb2 },
172 { 0x28, 0x1a }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0xc2 },
173 { 0x28, 0x1b }, { 0x29, 0x00 }, { 0x2a, 0x07 }, { 0x2b, 0x4a },
174 { 0x28, 0x1c }, { 0x29, 0x00 }, { 0x2a, 0x01 }, { 0x2b, 0xbc },
175 { 0x28, 0x1d }, { 0x29, 0x00 }, { 0x2a, 0x04 }, { 0x2b, 0xba },
176 { 0x28, 0x1e }, { 0x29, 0x00 }, { 0x2a, 0x06 }, { 0x2b, 0x14 },
177 { 0x50, 0x1e }, { 0x51, 0x5d },
178 { 0x50, 0x22 }, { 0x51, 0x00 },
179 { 0x50, 0x23 }, { 0x51, 0xc8 },
180 { 0x50, 0x24 }, { 0x51, 0x00 },
181 { 0x50, 0x25 }, { 0x51, 0xf0 },
182 { 0x50, 0x26 }, { 0x51, 0x00 },
183 { 0x50, 0x27 }, { 0x51, 0xc3 },
184 { 0x50, 0x39 }, { 0x51, 0x02 },
185 { 0x50, 0xd5 }, { 0x51, 0x01 },
189 static struct regdata mb86a20s_reset_reception[] = {
196 static struct regdata mb86a20s_per_ber_reset[] = {
197 { 0x53, 0x00 }, /* pre BER Counter reset */
200 { 0x5f, 0x00 }, /* post BER Counter reset */
203 { 0x50, 0xb1 }, /* PER Counter reset */
209 * I2C read/write functions and macros
212 static int mb86a20s_i2c_writereg(struct mb86a20s_state *state,
213 u8 i2c_addr, u8 reg, u8 data)
215 u8 buf[] = { reg, data };
216 struct i2c_msg msg = {
217 .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2
221 rc = i2c_transfer(state->i2c, &msg, 1);
223 dev_err(&state->i2c->dev,
224 "%s: writereg error (rc == %i, reg == 0x%02x, data == 0x%02x)\n",
225 __func__, rc, reg, data);
232 static int mb86a20s_i2c_writeregdata(struct mb86a20s_state *state,
233 u8 i2c_addr, struct regdata *rd, int size)
237 for (i = 0; i < size; i++) {
238 rc = mb86a20s_i2c_writereg(state, i2c_addr, rd[i].reg,
246 static int mb86a20s_i2c_readreg(struct mb86a20s_state *state,
251 struct i2c_msg msg[] = {
252 { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 },
253 { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &val, .len = 1 }
256 rc = i2c_transfer(state->i2c, msg, 2);
259 dev_err(&state->i2c->dev, "%s: reg=0x%x (error=%d)\n",
261 return (rc < 0) ? rc : -EIO;
267 #define mb86a20s_readreg(state, reg) \
268 mb86a20s_i2c_readreg(state, state->config->demod_address, reg)
269 #define mb86a20s_writereg(state, reg, val) \
270 mb86a20s_i2c_writereg(state, state->config->demod_address, reg, val)
271 #define mb86a20s_writeregdata(state, regdata) \
272 mb86a20s_i2c_writeregdata(state, state->config->demod_address, \
273 regdata, ARRAY_SIZE(regdata))
276 * Ancillary internal routines (likely compiled inlined)
278 * The functions below assume that gateway lock has already obtained
281 static int mb86a20s_read_status(struct dvb_frontend *fe, enum fe_status *status)
283 struct mb86a20s_state *state = fe->demodulator_priv;
288 val = mb86a20s_readreg(state, 0x0a);
294 *status |= FE_HAS_SIGNAL;
297 *status |= FE_HAS_CARRIER;
300 *status |= FE_HAS_VITERBI;
303 *status |= FE_HAS_SYNC;
306 * Actually, on state S8, it starts receiving TS, but the TS
307 * output is only on normal state after the transition to S9.
310 *status |= FE_HAS_LOCK;
312 dev_dbg(&state->i2c->dev, "%s: Status = 0x%02x (state = %d)\n",
313 __func__, *status, val);
318 static int mb86a20s_read_signal_strength(struct dvb_frontend *fe)
320 struct mb86a20s_state *state = fe->demodulator_priv;
321 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
323 unsigned rf_max, rf_min, rf;
325 if (state->get_strength_time &&
326 (!time_after(jiffies, state->get_strength_time)))
327 return c->strength.stat[0].uvalue;
329 /* Reset its value if an error happen */
330 c->strength.stat[0].uvalue = 0;
332 /* Does a binary search to get RF strength */
336 rf = (rf_max + rf_min) / 2;
337 rc = mb86a20s_writereg(state, 0x04, 0x1f);
340 rc = mb86a20s_writereg(state, 0x05, rf >> 8);
343 rc = mb86a20s_writereg(state, 0x04, 0x20);
346 rc = mb86a20s_writereg(state, 0x05, rf);
350 rc = mb86a20s_readreg(state, 0x02);
354 rf_min = (rf_max + rf_min) / 2;
356 rf_max = (rf_max + rf_min) / 2;
357 if (rf_max - rf_min < 4) {
358 rf = (rf_max + rf_min) / 2;
360 /* Rescale it from 2^12 (4096) to 2^16 */
361 rf = rf << (16 - 12);
365 dev_dbg(&state->i2c->dev,
366 "%s: signal strength = %d (%d < RF=%d < %d)\n",
367 __func__, rf, rf_min, rf >> 4, rf_max);
368 c->strength.stat[0].uvalue = rf;
369 state->get_strength_time = jiffies +
370 msecs_to_jiffies(1000);
376 static int mb86a20s_get_modulation(struct mb86a20s_state *state,
380 static unsigned char reg[] = {
381 [0] = 0x86, /* Layer A */
382 [1] = 0x8a, /* Layer B */
383 [2] = 0x8e, /* Layer C */
386 if (layer >= ARRAY_SIZE(reg))
388 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
391 rc = mb86a20s_readreg(state, 0x6e);
394 switch ((rc >> 4) & 0x07) {
408 static int mb86a20s_get_fec(struct mb86a20s_state *state,
413 static unsigned char reg[] = {
414 [0] = 0x87, /* Layer A */
415 [1] = 0x8b, /* Layer B */
416 [2] = 0x8f, /* Layer C */
419 if (layer >= ARRAY_SIZE(reg))
421 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
424 rc = mb86a20s_readreg(state, 0x6e);
427 switch ((rc >> 4) & 0x07) {
443 static int mb86a20s_get_interleaving(struct mb86a20s_state *state,
447 static const int interleaving[] = {
451 static const unsigned char reg[] = {
452 [0] = 0x88, /* Layer A */
453 [1] = 0x8c, /* Layer B */
454 [2] = 0x90, /* Layer C */
457 if (layer >= ARRAY_SIZE(reg))
459 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
462 rc = mb86a20s_readreg(state, 0x6e);
466 return interleaving[(rc >> 4) & 0x07];
469 static int mb86a20s_get_segment_count(struct mb86a20s_state *state,
473 static unsigned char reg[] = {
474 [0] = 0x89, /* Layer A */
475 [1] = 0x8d, /* Layer B */
476 [2] = 0x91, /* Layer C */
479 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
481 if (layer >= ARRAY_SIZE(reg))
484 rc = mb86a20s_writereg(state, 0x6d, reg[layer]);
487 rc = mb86a20s_readreg(state, 0x6e);
490 count = (rc >> 4) & 0x0f;
492 dev_dbg(&state->i2c->dev, "%s: segments: %d.\n", __func__, count);
497 static void mb86a20s_reset_frontend_cache(struct dvb_frontend *fe)
499 struct mb86a20s_state *state = fe->demodulator_priv;
500 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
502 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
504 /* Fixed parameters */
505 c->delivery_system = SYS_ISDBT;
506 c->bandwidth_hz = 6000000;
508 /* Initialize values that will be later autodetected */
509 c->isdbt_layer_enabled = 0;
510 c->transmission_mode = TRANSMISSION_MODE_AUTO;
511 c->guard_interval = GUARD_INTERVAL_AUTO;
512 c->isdbt_sb_mode = 0;
513 c->isdbt_sb_segment_count = 0;
517 * Estimates the bit rate using the per-segment bit rate given by
518 * ABNT/NBR 15601 spec (table 4).
520 static const u32 isdbt_rate[3][5][4] = {
522 { 280850, 312060, 330420, 340430 }, /* 1/2 */
523 { 374470, 416080, 440560, 453910 }, /* 2/3 */
524 { 421280, 468090, 495630, 510650 }, /* 3/4 */
525 { 468090, 520100, 550700, 567390 }, /* 5/6 */
526 { 491500, 546110, 578230, 595760 }, /* 7/8 */
528 { 561710, 624130, 660840, 680870 }, /* 1/2 */
529 { 748950, 832170, 881120, 907820 }, /* 2/3 */
530 { 842570, 936190, 991260, 1021300 }, /* 3/4 */
531 { 936190, 1040210, 1101400, 1134780 }, /* 5/6 */
532 { 983000, 1092220, 1156470, 1191520 }, /* 7/8 */
534 { 842570, 936190, 991260, 1021300 }, /* 1/2 */
535 { 1123430, 1248260, 1321680, 1361740 }, /* 2/3 */
536 { 1263860, 1404290, 1486900, 1531950 }, /* 3/4 */
537 { 1404290, 1560320, 1652110, 1702170 }, /* 5/6 */
538 { 1474500, 1638340, 1734710, 1787280 }, /* 7/8 */
542 static u32 isdbt_layer_min_bitrate(struct dtv_frontend_properties *c,
548 * If modulation/fec/guard is not detected, the default is
549 * to consider the lowest bit rate, to avoid taking too long time
552 switch (c->layer[layer].modulation) {
566 switch (c->layer[layer].fec) {
586 switch (c->guard_interval) {
588 case GUARD_INTERVAL_1_4:
591 case GUARD_INTERVAL_1_8:
594 case GUARD_INTERVAL_1_16:
597 case GUARD_INTERVAL_1_32:
602 return isdbt_rate[mod][fec][guard] * c->layer[layer].segment_count;
605 static int mb86a20s_get_frontend(struct dvb_frontend *fe)
607 struct mb86a20s_state *state = fe->demodulator_priv;
608 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
609 int layer, rc, rate, counter;
611 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
613 /* Reset frontend cache to default values */
614 mb86a20s_reset_frontend_cache(fe);
616 /* Check for partial reception */
617 rc = mb86a20s_writereg(state, 0x6d, 0x85);
620 rc = mb86a20s_readreg(state, 0x6e);
623 c->isdbt_partial_reception = (rc & 0x10) ? 1 : 0;
625 /* Get per-layer data */
627 for (layer = 0; layer < NUM_LAYERS; layer++) {
628 dev_dbg(&state->i2c->dev, "%s: getting data for layer %c.\n",
629 __func__, 'A' + layer);
631 rc = mb86a20s_get_segment_count(state, layer);
633 goto noperlayer_error;
634 if (rc >= 0 && rc < 14) {
635 c->layer[layer].segment_count = rc;
637 c->layer[layer].segment_count = 0;
638 state->estimated_rate[layer] = 0;
641 c->isdbt_layer_enabled |= 1 << layer;
642 rc = mb86a20s_get_modulation(state, layer);
644 goto noperlayer_error;
645 dev_dbg(&state->i2c->dev, "%s: modulation %d.\n",
647 c->layer[layer].modulation = rc;
648 rc = mb86a20s_get_fec(state, layer);
650 goto noperlayer_error;
651 dev_dbg(&state->i2c->dev, "%s: FEC %d.\n",
653 c->layer[layer].fec = rc;
654 rc = mb86a20s_get_interleaving(state, layer);
656 goto noperlayer_error;
657 dev_dbg(&state->i2c->dev, "%s: interleaving %d.\n",
659 c->layer[layer].interleaving = rc;
661 rate = isdbt_layer_min_bitrate(c, layer);
662 counter = rate * BER_SAMPLING_RATE;
664 /* Avoids sampling too quickly or to overflow the register */
667 else if (counter > (1 << 24) - 1)
668 counter = (1 << 24) - 1;
670 dev_dbg(&state->i2c->dev,
671 "%s: layer %c bitrate: %d kbps; counter = %d (0x%06x)\n",
672 __func__, 'A' + layer, rate / 1000, counter, counter);
674 state->estimated_rate[layer] = counter;
677 rc = mb86a20s_writereg(state, 0x6d, 0x84);
680 if ((rc & 0x60) == 0x20) {
681 c->isdbt_sb_mode = 1;
682 /* At least, one segment should exist */
683 if (!c->isdbt_sb_segment_count)
684 c->isdbt_sb_segment_count = 1;
687 /* Get transmission mode and guard interval */
688 rc = mb86a20s_readreg(state, 0x07);
691 c->transmission_mode = TRANSMISSION_MODE_AUTO;
692 if ((rc & 0x60) == 0x20) {
693 /* Only modes 2 and 3 are supported */
694 switch ((rc >> 2) & 0x03) {
696 c->transmission_mode = TRANSMISSION_MODE_4K;
699 c->transmission_mode = TRANSMISSION_MODE_8K;
703 c->guard_interval = GUARD_INTERVAL_AUTO;
705 /* Guard interval 1/32 is not supported */
708 c->guard_interval = GUARD_INTERVAL_1_4;
711 c->guard_interval = GUARD_INTERVAL_1_8;
714 c->guard_interval = GUARD_INTERVAL_1_16;
722 /* per-layer info is incomplete; discard all per-layer */
723 c->isdbt_layer_enabled = 0;
728 static int mb86a20s_reset_counters(struct dvb_frontend *fe)
730 struct mb86a20s_state *state = fe->demodulator_priv;
731 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
734 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
736 /* Reset the counters, if the channel changed */
737 if (state->last_frequency != c->frequency) {
738 memset(&c->cnr, 0, sizeof(c->cnr));
739 memset(&c->pre_bit_error, 0, sizeof(c->pre_bit_error));
740 memset(&c->pre_bit_count, 0, sizeof(c->pre_bit_count));
741 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
742 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
743 memset(&c->block_error, 0, sizeof(c->block_error));
744 memset(&c->block_count, 0, sizeof(c->block_count));
746 state->last_frequency = c->frequency;
749 /* Clear status for most stats */
751 /* BER/PER counter reset */
752 rc = mb86a20s_writeregdata(state, mb86a20s_per_ber_reset);
756 /* CNR counter reset */
757 rc = mb86a20s_readreg(state, 0x45);
761 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
764 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
768 /* MER counter reset */
769 rc = mb86a20s_writereg(state, 0x50, 0x50);
772 rc = mb86a20s_readreg(state, 0x51);
776 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
779 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
785 dev_err(&state->i2c->dev,
786 "%s: Can't reset FE statistics (error %d).\n",
792 static int mb86a20s_get_pre_ber(struct dvb_frontend *fe,
794 u32 *error, u32 *count)
796 struct mb86a20s_state *state = fe->demodulator_priv;
799 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
801 if (layer >= NUM_LAYERS)
804 /* Check if the BER measures are already available */
805 rc = mb86a20s_readreg(state, 0x54);
809 /* Check if data is available for that layer */
810 if (!(rc & (1 << layer))) {
811 dev_dbg(&state->i2c->dev,
812 "%s: preBER for layer %c is not available yet.\n",
813 __func__, 'A' + layer);
817 /* Read Bit Error Count */
818 rc = mb86a20s_readreg(state, 0x55 + layer * 3);
822 rc = mb86a20s_readreg(state, 0x56 + layer * 3);
826 rc = mb86a20s_readreg(state, 0x57 + layer * 3);
831 dev_dbg(&state->i2c->dev,
832 "%s: bit error before Viterbi for layer %c: %d.\n",
833 __func__, 'A' + layer, *error);
836 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
839 rc = mb86a20s_readreg(state, 0x51);
843 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
846 rc = mb86a20s_readreg(state, 0x51);
850 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
853 rc = mb86a20s_readreg(state, 0x51);
858 dev_dbg(&state->i2c->dev,
859 "%s: bit count before Viterbi for layer %c: %d.\n",
860 __func__, 'A' + layer, *count);
864 * As we get TMCC data from the frontend, we can better estimate the
865 * BER bit counters, in order to do the BER measure during a longer
866 * time. Use those data, if available, to update the bit count
870 if (state->estimated_rate[layer]
871 && state->estimated_rate[layer] != *count) {
872 dev_dbg(&state->i2c->dev,
873 "%s: updating layer %c preBER counter to %d.\n",
874 __func__, 'A' + layer, state->estimated_rate[layer]);
876 /* Turn off BER before Viterbi */
877 rc = mb86a20s_writereg(state, 0x52, 0x00);
879 /* Update counter for this layer */
880 rc = mb86a20s_writereg(state, 0x50, 0xa7 + layer * 3);
883 rc = mb86a20s_writereg(state, 0x51,
884 state->estimated_rate[layer] >> 16);
887 rc = mb86a20s_writereg(state, 0x50, 0xa8 + layer * 3);
890 rc = mb86a20s_writereg(state, 0x51,
891 state->estimated_rate[layer] >> 8);
894 rc = mb86a20s_writereg(state, 0x50, 0xa9 + layer * 3);
897 rc = mb86a20s_writereg(state, 0x51,
898 state->estimated_rate[layer]);
902 /* Turn on BER before Viterbi */
903 rc = mb86a20s_writereg(state, 0x52, 0x01);
905 /* Reset all preBER counters */
906 rc = mb86a20s_writereg(state, 0x53, 0x00);
909 rc = mb86a20s_writereg(state, 0x53, 0x07);
911 /* Reset counter to collect new data */
912 rc = mb86a20s_readreg(state, 0x53);
916 rc = mb86a20s_writereg(state, 0x53, val & ~(1 << layer));
919 rc = mb86a20s_writereg(state, 0x53, val | (1 << layer));
925 static int mb86a20s_get_post_ber(struct dvb_frontend *fe,
927 u32 *error, u32 *count)
929 struct mb86a20s_state *state = fe->demodulator_priv;
930 u32 counter, collect_rate;
933 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
935 if (layer >= NUM_LAYERS)
938 /* Check if the BER measures are already available */
939 rc = mb86a20s_readreg(state, 0x60);
943 /* Check if data is available for that layer */
944 if (!(rc & (1 << layer))) {
945 dev_dbg(&state->i2c->dev,
946 "%s: post BER for layer %c is not available yet.\n",
947 __func__, 'A' + layer);
951 /* Read Bit Error Count */
952 rc = mb86a20s_readreg(state, 0x64 + layer * 3);
956 rc = mb86a20s_readreg(state, 0x65 + layer * 3);
960 rc = mb86a20s_readreg(state, 0x66 + layer * 3);
965 dev_dbg(&state->i2c->dev,
966 "%s: post bit error for layer %c: %d.\n",
967 __func__, 'A' + layer, *error);
970 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
973 rc = mb86a20s_readreg(state, 0x51);
977 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
980 rc = mb86a20s_readreg(state, 0x51);
984 *count = counter * 204 * 8;
986 dev_dbg(&state->i2c->dev,
987 "%s: post bit count for layer %c: %d.\n",
988 __func__, 'A' + layer, *count);
991 * As we get TMCC data from the frontend, we can better estimate the
992 * BER bit counters, in order to do the BER measure during a longer
993 * time. Use those data, if available, to update the bit count
997 if (!state->estimated_rate[layer])
998 goto reset_measurement;
1000 collect_rate = state->estimated_rate[layer] / 204 / 8;
1001 if (collect_rate < 32)
1003 if (collect_rate > 65535)
1004 collect_rate = 65535;
1005 if (collect_rate != counter) {
1006 dev_dbg(&state->i2c->dev,
1007 "%s: updating postBER counter on layer %c to %d.\n",
1008 __func__, 'A' + layer, collect_rate);
1010 /* Turn off BER after Viterbi */
1011 rc = mb86a20s_writereg(state, 0x5e, 0x00);
1013 /* Update counter for this layer */
1014 rc = mb86a20s_writereg(state, 0x50, 0xdc + layer * 2);
1017 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1020 rc = mb86a20s_writereg(state, 0x50, 0xdd + layer * 2);
1023 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1027 /* Turn on BER after Viterbi */
1028 rc = mb86a20s_writereg(state, 0x5e, 0x07);
1030 /* Reset all preBER counters */
1031 rc = mb86a20s_writereg(state, 0x5f, 0x00);
1034 rc = mb86a20s_writereg(state, 0x5f, 0x07);
1040 /* Reset counter to collect new data */
1041 rc = mb86a20s_readreg(state, 0x5f);
1045 rc = mb86a20s_writereg(state, 0x5f, val & ~(1 << layer));
1048 rc = mb86a20s_writereg(state, 0x5f, val | (1 << layer));
1053 static int mb86a20s_get_blk_error(struct dvb_frontend *fe,
1055 u32 *error, u32 *count)
1057 struct mb86a20s_state *state = fe->demodulator_priv;
1060 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1062 if (layer >= NUM_LAYERS)
1065 /* Check if the PER measures are already available */
1066 rc = mb86a20s_writereg(state, 0x50, 0xb8);
1069 rc = mb86a20s_readreg(state, 0x51);
1073 /* Check if data is available for that layer */
1075 if (!(rc & (1 << layer))) {
1076 dev_dbg(&state->i2c->dev,
1077 "%s: block counts for layer %c aren't available yet.\n",
1078 __func__, 'A' + layer);
1082 /* Read Packet error Count */
1083 rc = mb86a20s_writereg(state, 0x50, 0xb9 + layer * 2);
1086 rc = mb86a20s_readreg(state, 0x51);
1090 rc = mb86a20s_writereg(state, 0x50, 0xba + layer * 2);
1093 rc = mb86a20s_readreg(state, 0x51);
1097 dev_dbg(&state->i2c->dev, "%s: block error for layer %c: %d.\n",
1098 __func__, 'A' + layer, *error);
1100 /* Read Bit Count */
1101 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1104 rc = mb86a20s_readreg(state, 0x51);
1108 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1111 rc = mb86a20s_readreg(state, 0x51);
1116 dev_dbg(&state->i2c->dev,
1117 "%s: block count for layer %c: %d.\n",
1118 __func__, 'A' + layer, *count);
1121 * As we get TMCC data from the frontend, we can better estimate the
1122 * BER bit counters, in order to do the BER measure during a longer
1123 * time. Use those data, if available, to update the bit count
1127 if (!state->estimated_rate[layer])
1128 goto reset_measurement;
1130 collect_rate = state->estimated_rate[layer] / 204 / 8;
1131 if (collect_rate < 32)
1133 if (collect_rate > 65535)
1134 collect_rate = 65535;
1136 if (collect_rate != *count) {
1137 dev_dbg(&state->i2c->dev,
1138 "%s: updating PER counter on layer %c to %d.\n",
1139 __func__, 'A' + layer, collect_rate);
1141 /* Stop PER measurement */
1142 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1145 rc = mb86a20s_writereg(state, 0x51, 0x00);
1149 /* Update this layer's counter */
1150 rc = mb86a20s_writereg(state, 0x50, 0xb2 + layer * 2);
1153 rc = mb86a20s_writereg(state, 0x51, collect_rate >> 8);
1156 rc = mb86a20s_writereg(state, 0x50, 0xb3 + layer * 2);
1159 rc = mb86a20s_writereg(state, 0x51, collect_rate & 0xff);
1163 /* start PER measurement */
1164 rc = mb86a20s_writereg(state, 0x50, 0xb0);
1167 rc = mb86a20s_writereg(state, 0x51, 0x07);
1171 /* Reset all counters to collect new data */
1172 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1175 rc = mb86a20s_writereg(state, 0x51, 0x07);
1178 rc = mb86a20s_writereg(state, 0x51, 0x00);
1184 /* Reset counter to collect new data */
1185 rc = mb86a20s_writereg(state, 0x50, 0xb1);
1188 rc = mb86a20s_readreg(state, 0x51);
1192 rc = mb86a20s_writereg(state, 0x51, val | (1 << layer));
1195 rc = mb86a20s_writereg(state, 0x51, val & ~(1 << layer));
1200 struct linear_segments {
1205 * All tables below return a dB/1000 measurement
1208 static const struct linear_segments cnr_to_db_table[] = {
1242 static const struct linear_segments cnr_64qam_table[] = {
1276 static const struct linear_segments cnr_16qam_table[] = {
1310 static const struct linear_segments cnr_qpsk_table[] = {
1344 static u32 interpolate_value(u32 value, const struct linear_segments *segments,
1351 if (value >= segments[0].x)
1352 return segments[0].y;
1353 if (value < segments[len-1].x)
1354 return segments[len-1].y;
1356 for (i = 1; i < len - 1; i++) {
1357 /* If value is identical, no need to interpolate */
1358 if (value == segments[i].x)
1359 return segments[i].y;
1360 if (value > segments[i].x)
1364 /* Linear interpolation between the two (x,y) points */
1365 dy = segments[i].y - segments[i - 1].y;
1366 dx = segments[i - 1].x - segments[i].x;
1367 tmp64 = value - segments[i].x;
1370 ret = segments[i].y - tmp64;
1375 static int mb86a20s_get_main_CNR(struct dvb_frontend *fe)
1377 struct mb86a20s_state *state = fe->demodulator_priv;
1378 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1379 u32 cnr_linear, cnr;
1382 /* Check if CNR is available */
1383 rc = mb86a20s_readreg(state, 0x45);
1388 dev_dbg(&state->i2c->dev, "%s: CNR is not available yet.\n",
1394 rc = mb86a20s_readreg(state, 0x46);
1397 cnr_linear = rc << 8;
1399 rc = mb86a20s_readreg(state, 0x46);
1404 cnr = interpolate_value(cnr_linear,
1405 cnr_to_db_table, ARRAY_SIZE(cnr_to_db_table));
1407 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1408 c->cnr.stat[0].svalue = cnr;
1410 dev_dbg(&state->i2c->dev, "%s: CNR is %d.%03d dB (%d)\n",
1411 __func__, cnr / 1000, cnr % 1000, cnr_linear);
1413 /* CNR counter reset */
1414 rc = mb86a20s_writereg(state, 0x45, val | 0x10);
1417 rc = mb86a20s_writereg(state, 0x45, val & 0x6f);
1422 static int mb86a20s_get_blk_error_layer_CNR(struct dvb_frontend *fe)
1424 struct mb86a20s_state *state = fe->demodulator_priv;
1425 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1428 const struct linear_segments *segs;
1431 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1433 /* Check if the measures are already available */
1434 rc = mb86a20s_writereg(state, 0x50, 0x5b);
1437 rc = mb86a20s_readreg(state, 0x51);
1441 /* Check if data is available */
1443 dev_dbg(&state->i2c->dev,
1444 "%s: MER measures aren't available yet.\n", __func__);
1448 /* Read all layers */
1449 for (layer = 0; layer < NUM_LAYERS; layer++) {
1450 if (!(c->isdbt_layer_enabled & (1 << layer))) {
1451 c->cnr.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1455 rc = mb86a20s_writereg(state, 0x50, 0x52 + layer * 3);
1458 rc = mb86a20s_readreg(state, 0x51);
1462 rc = mb86a20s_writereg(state, 0x50, 0x53 + layer * 3);
1465 rc = mb86a20s_readreg(state, 0x51);
1469 rc = mb86a20s_writereg(state, 0x50, 0x54 + layer * 3);
1472 rc = mb86a20s_readreg(state, 0x51);
1477 switch (c->layer[layer].modulation) {
1480 segs = cnr_qpsk_table;
1481 segs_len = ARRAY_SIZE(cnr_qpsk_table);
1484 segs = cnr_16qam_table;
1485 segs_len = ARRAY_SIZE(cnr_16qam_table);
1489 segs = cnr_64qam_table;
1490 segs_len = ARRAY_SIZE(cnr_64qam_table);
1493 cnr = interpolate_value(mer, segs, segs_len);
1495 c->cnr.stat[1 + layer].scale = FE_SCALE_DECIBEL;
1496 c->cnr.stat[1 + layer].svalue = cnr;
1498 dev_dbg(&state->i2c->dev,
1499 "%s: CNR for layer %c is %d.%03d dB (MER = %d).\n",
1500 __func__, 'A' + layer, cnr / 1000, cnr % 1000, mer);
1504 /* Start a new MER measurement */
1505 /* MER counter reset */
1506 rc = mb86a20s_writereg(state, 0x50, 0x50);
1509 rc = mb86a20s_readreg(state, 0x51);
1514 rc = mb86a20s_writereg(state, 0x51, val | 0x01);
1517 rc = mb86a20s_writereg(state, 0x51, val & 0x06);
1524 static void mb86a20s_stats_not_ready(struct dvb_frontend *fe)
1526 struct mb86a20s_state *state = fe->demodulator_priv;
1527 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1530 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1532 /* Fill the length of each status counter */
1534 /* Only global stats */
1535 c->strength.len = 1;
1537 /* Per-layer stats - 3 layers + global */
1538 c->cnr.len = NUM_LAYERS + 1;
1539 c->pre_bit_error.len = NUM_LAYERS + 1;
1540 c->pre_bit_count.len = NUM_LAYERS + 1;
1541 c->post_bit_error.len = NUM_LAYERS + 1;
1542 c->post_bit_count.len = NUM_LAYERS + 1;
1543 c->block_error.len = NUM_LAYERS + 1;
1544 c->block_count.len = NUM_LAYERS + 1;
1546 /* Signal is always available */
1547 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
1548 c->strength.stat[0].uvalue = 0;
1550 /* Put all of them at FE_SCALE_NOT_AVAILABLE */
1551 for (layer = 0; layer < NUM_LAYERS + 1; layer++) {
1552 c->cnr.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1553 c->pre_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1554 c->pre_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1555 c->post_bit_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1556 c->post_bit_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1557 c->block_error.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1558 c->block_count.stat[layer].scale = FE_SCALE_NOT_AVAILABLE;
1562 static int mb86a20s_get_stats(struct dvb_frontend *fe, int status_nr)
1564 struct mb86a20s_state *state = fe->demodulator_priv;
1565 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1567 u32 bit_error = 0, bit_count = 0;
1568 u32 t_pre_bit_error = 0, t_pre_bit_count = 0;
1569 u32 t_post_bit_error = 0, t_post_bit_count = 0;
1570 u32 block_error = 0, block_count = 0;
1571 u32 t_block_error = 0, t_block_count = 0;
1572 int active_layers = 0, pre_ber_layers = 0, post_ber_layers = 0;
1575 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1577 mb86a20s_get_main_CNR(fe);
1579 /* Get per-layer stats */
1580 mb86a20s_get_blk_error_layer_CNR(fe);
1583 * At state 7, only CNR is available
1584 * For BER measures, state=9 is required
1585 * FIXME: we may get MER measures with state=8
1590 for (layer = 0; layer < NUM_LAYERS; layer++) {
1591 if (c->isdbt_layer_enabled & (1 << layer)) {
1592 /* Layer is active and has rc segments */
1595 /* Handle BER before vterbi */
1596 rc = mb86a20s_get_pre_ber(fe, layer,
1597 &bit_error, &bit_count);
1599 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1600 c->pre_bit_error.stat[1 + layer].uvalue += bit_error;
1601 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1602 c->pre_bit_count.stat[1 + layer].uvalue += bit_count;
1603 } else if (rc != -EBUSY) {
1605 * If an I/O error happened,
1606 * measures are now unavailable
1608 c->pre_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1609 c->pre_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1610 dev_err(&state->i2c->dev,
1611 "%s: Can't get BER for layer %c (error %d).\n",
1612 __func__, 'A' + layer, rc);
1614 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1617 /* Handle BER post vterbi */
1618 rc = mb86a20s_get_post_ber(fe, layer,
1619 &bit_error, &bit_count);
1621 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1622 c->post_bit_error.stat[1 + layer].uvalue += bit_error;
1623 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1624 c->post_bit_count.stat[1 + layer].uvalue += bit_count;
1625 } else if (rc != -EBUSY) {
1627 * If an I/O error happened,
1628 * measures are now unavailable
1630 c->post_bit_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1631 c->post_bit_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1632 dev_err(&state->i2c->dev,
1633 "%s: Can't get BER for layer %c (error %d).\n",
1634 __func__, 'A' + layer, rc);
1636 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1639 /* Handle Block errors for PER/UCB reports */
1640 rc = mb86a20s_get_blk_error(fe, layer,
1644 c->block_error.stat[1 + layer].scale = FE_SCALE_COUNTER;
1645 c->block_error.stat[1 + layer].uvalue += block_error;
1646 c->block_count.stat[1 + layer].scale = FE_SCALE_COUNTER;
1647 c->block_count.stat[1 + layer].uvalue += block_count;
1648 } else if (rc != -EBUSY) {
1650 * If an I/O error happened,
1651 * measures are now unavailable
1653 c->block_error.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1654 c->block_count.stat[1 + layer].scale = FE_SCALE_NOT_AVAILABLE;
1655 dev_err(&state->i2c->dev,
1656 "%s: Can't get PER for layer %c (error %d).\n",
1657 __func__, 'A' + layer, rc);
1660 if (c->block_error.stat[1 + layer].scale != FE_SCALE_NOT_AVAILABLE)
1663 /* Update total preBER */
1664 t_pre_bit_error += c->pre_bit_error.stat[1 + layer].uvalue;
1665 t_pre_bit_count += c->pre_bit_count.stat[1 + layer].uvalue;
1667 /* Update total postBER */
1668 t_post_bit_error += c->post_bit_error.stat[1 + layer].uvalue;
1669 t_post_bit_count += c->post_bit_count.stat[1 + layer].uvalue;
1671 /* Update total PER */
1672 t_block_error += c->block_error.stat[1 + layer].uvalue;
1673 t_block_count += c->block_count.stat[1 + layer].uvalue;
1678 * Start showing global count if at least one error count is
1681 if (pre_ber_layers) {
1683 * At least one per-layer BER measure was read. We can now
1684 * calculate the total BER
1686 * Total Bit Error/Count is calculated as the sum of the
1687 * bit errors on all active layers.
1689 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1690 c->pre_bit_error.stat[0].uvalue = t_pre_bit_error;
1691 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1692 c->pre_bit_count.stat[0].uvalue = t_pre_bit_count;
1694 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1695 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1699 * Start showing global count if at least one error count is
1702 if (post_ber_layers) {
1704 * At least one per-layer BER measure was read. We can now
1705 * calculate the total BER
1707 * Total Bit Error/Count is calculated as the sum of the
1708 * bit errors on all active layers.
1710 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1711 c->post_bit_error.stat[0].uvalue = t_post_bit_error;
1712 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1713 c->post_bit_count.stat[0].uvalue = t_post_bit_count;
1715 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1716 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1721 * At least one per-layer UCB measure was read. We can now
1722 * calculate the total UCB
1724 * Total block Error/Count is calculated as the sum of the
1725 * block errors on all active layers.
1727 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1728 c->block_error.stat[0].uvalue = t_block_error;
1729 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1730 c->block_count.stat[0].uvalue = t_block_count;
1732 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1733 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1740 * The functions below are called via DVB callbacks, so they need to
1741 * properly use the I2C gate control
1744 static int mb86a20s_initfe(struct dvb_frontend *fe)
1746 struct mb86a20s_state *state = fe->demodulator_priv;
1750 u8 regD5 = 1, reg71, reg09 = 0x3a;
1752 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1754 if (fe->ops.i2c_gate_ctrl)
1755 fe->ops.i2c_gate_ctrl(fe, 0);
1757 /* Initialize the frontend */
1758 rc = mb86a20s_writeregdata(state, mb86a20s_init1);
1762 if (!state->inversion)
1764 rc = mb86a20s_writereg(state, 0x09, reg09);
1771 rc = mb86a20s_writereg(state, 0x39, reg71);
1774 rc = mb86a20s_writereg(state, 0x71, state->bw);
1777 if (state->subchannel) {
1778 rc = mb86a20s_writereg(state, 0x44, state->subchannel);
1783 fclk = state->config->fclk;
1787 /* Adjust IF frequency to match tuner */
1788 if (fe->ops.tuner_ops.get_if_frequency)
1789 fe->ops.tuner_ops.get_if_frequency(fe, &state->if_freq);
1791 if (!state->if_freq)
1792 state->if_freq = 3300000;
1794 pll = (((u64)1) << 34) * state->if_freq;
1795 do_div(pll, 63 * fclk);
1796 pll = (1 << 25) - pll;
1797 rc = mb86a20s_writereg(state, 0x28, 0x2a);
1800 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1803 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1806 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1809 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n",
1810 __func__, fclk, state->if_freq, (long long)pll);
1812 /* pll = freq[Hz] * 2^24/10^6 / 16.285714286 */
1813 pll = state->if_freq * 1677721600L;
1814 do_div(pll, 1628571429L);
1815 rc = mb86a20s_writereg(state, 0x28, 0x20);
1818 rc = mb86a20s_writereg(state, 0x29, (pll >> 16) & 0xff);
1821 rc = mb86a20s_writereg(state, 0x2a, (pll >> 8) & 0xff);
1824 rc = mb86a20s_writereg(state, 0x2b, pll & 0xff);
1827 dev_dbg(&state->i2c->dev, "%s: IF=%d, IF reg=0x%06llx\n",
1828 __func__, state->if_freq, (long long)pll);
1830 if (!state->config->is_serial)
1833 rc = mb86a20s_writereg(state, 0x50, 0xd5);
1836 rc = mb86a20s_writereg(state, 0x51, regD5);
1840 rc = mb86a20s_writeregdata(state, mb86a20s_init2);
1846 if (fe->ops.i2c_gate_ctrl)
1847 fe->ops.i2c_gate_ctrl(fe, 1);
1850 state->need_init = true;
1851 dev_info(&state->i2c->dev,
1852 "mb86a20s: Init failed. Will try again later\n");
1854 state->need_init = false;
1855 dev_dbg(&state->i2c->dev, "Initialization succeeded.\n");
1860 static int mb86a20s_set_frontend(struct dvb_frontend *fe)
1862 struct mb86a20s_state *state = fe->demodulator_priv;
1863 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1865 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1867 if (!c->isdbt_layer_enabled)
1868 c->isdbt_layer_enabled = 7;
1870 if (c->isdbt_layer_enabled == 1)
1871 state->bw = MB86A20S_1SEG;
1872 else if (c->isdbt_partial_reception)
1873 state->bw = MB86A20S_13SEG_PARTIAL;
1875 state->bw = MB86A20S_13SEG;
1877 if (c->inversion == INVERSION_ON)
1878 state->inversion = true;
1880 state->inversion = false;
1882 if (!c->isdbt_sb_mode) {
1883 state->subchannel = 0;
1885 if (c->isdbt_sb_subchannel >= ARRAY_SIZE(mb86a20s_subchannel))
1886 c->isdbt_sb_subchannel = 0;
1888 state->subchannel = mb86a20s_subchannel[c->isdbt_sb_subchannel];
1892 * Gate should already be opened, but it doesn't hurt to
1895 if (fe->ops.i2c_gate_ctrl)
1896 fe->ops.i2c_gate_ctrl(fe, 1);
1897 fe->ops.tuner_ops.set_params(fe);
1899 if (fe->ops.tuner_ops.get_if_frequency)
1900 fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
1903 * Make it more reliable: if, for some reason, the initial
1904 * device initialization doesn't happen, initialize it when
1905 * a SBTVD parameters are adjusted.
1907 * Unfortunately, due to a hard to track bug at tda829x/tda18271,
1908 * the agc callback logic is not called during DVB attach time,
1909 * causing mb86a20s to not be initialized with Kworld SBTVD.
1910 * So, this hack is needed, in order to make Kworld SBTVD to work.
1912 * It is also needed to change the IF after the initial init.
1914 * HACK: Always init the frontend when set_frontend is called:
1915 * it was noticed that, on some devices, it fails to lock on a
1916 * different channel. So, it is better to reset everything, even
1917 * wasting some time, than to loose channel lock.
1919 mb86a20s_initfe(fe);
1921 if (fe->ops.i2c_gate_ctrl)
1922 fe->ops.i2c_gate_ctrl(fe, 0);
1924 rc = mb86a20s_writeregdata(state, mb86a20s_reset_reception);
1925 mb86a20s_reset_counters(fe);
1926 mb86a20s_stats_not_ready(fe);
1928 if (fe->ops.i2c_gate_ctrl)
1929 fe->ops.i2c_gate_ctrl(fe, 1);
1934 static int mb86a20s_read_status_and_stats(struct dvb_frontend *fe,
1935 enum fe_status *status)
1937 struct mb86a20s_state *state = fe->demodulator_priv;
1940 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
1942 if (fe->ops.i2c_gate_ctrl)
1943 fe->ops.i2c_gate_ctrl(fe, 0);
1946 status_nr = mb86a20s_read_status(fe, status);
1947 if (status_nr < 7) {
1948 mb86a20s_stats_not_ready(fe);
1949 mb86a20s_reset_frontend_cache(fe);
1951 if (status_nr < 0) {
1952 dev_err(&state->i2c->dev,
1953 "%s: Can't read frontend lock status\n", __func__);
1958 /* Get signal strength */
1959 rc = mb86a20s_read_signal_strength(fe);
1961 dev_err(&state->i2c->dev,
1962 "%s: Can't reset VBER registers.\n", __func__);
1963 mb86a20s_stats_not_ready(fe);
1964 mb86a20s_reset_frontend_cache(fe);
1966 rc = 0; /* Status is OK */
1970 if (status_nr >= 7) {
1972 rc = mb86a20s_get_frontend(fe);
1974 dev_err(&state->i2c->dev,
1975 "%s: Can't get FE TMCC data.\n", __func__);
1976 rc = 0; /* Status is OK */
1980 /* Get statistics */
1981 rc = mb86a20s_get_stats(fe, status_nr);
1982 if (rc < 0 && rc != -EBUSY) {
1983 dev_err(&state->i2c->dev,
1984 "%s: Can't get FE statistics.\n", __func__);
1988 rc = 0; /* Don't return EBUSY to userspace */
1993 mb86a20s_stats_not_ready(fe);
1996 if (fe->ops.i2c_gate_ctrl)
1997 fe->ops.i2c_gate_ctrl(fe, 1);
2002 static int mb86a20s_read_signal_strength_from_cache(struct dvb_frontend *fe,
2005 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2008 *strength = c->strength.stat[0].uvalue;
2013 static int mb86a20s_tune(struct dvb_frontend *fe,
2015 unsigned int mode_flags,
2016 unsigned int *delay,
2017 enum fe_status *status)
2019 struct mb86a20s_state *state = fe->demodulator_priv;
2022 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2025 rc = mb86a20s_set_frontend(fe);
2027 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
2028 mb86a20s_read_status_and_stats(fe, status);
2033 static void mb86a20s_release(struct dvb_frontend *fe)
2035 struct mb86a20s_state *state = fe->demodulator_priv;
2037 dev_dbg(&state->i2c->dev, "%s called.\n", __func__);
2042 static enum dvbfe_algo mb86a20s_get_frontend_algo(struct dvb_frontend *fe)
2044 return DVBFE_ALGO_HW;
2047 static const struct dvb_frontend_ops mb86a20s_ops;
2049 struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config,
2050 struct i2c_adapter *i2c)
2052 struct mb86a20s_state *state;
2055 dev_dbg(&i2c->dev, "%s called.\n", __func__);
2057 /* allocate memory for the internal state */
2058 state = kzalloc(sizeof(*state), GFP_KERNEL);
2062 /* setup the state */
2063 state->config = config;
2066 /* create dvb_frontend */
2067 memcpy(&state->frontend.ops, &mb86a20s_ops,
2068 sizeof(struct dvb_frontend_ops));
2069 state->frontend.demodulator_priv = state;
2071 /* Check if it is a mb86a20s frontend */
2072 rev = mb86a20s_readreg(state, 0);
2076 "Frontend revision %d is unknown - aborting.\n",
2081 dev_info(&i2c->dev, "Detected a Fujitsu mb86a20s frontend\n");
2082 return &state->frontend;
2084 EXPORT_SYMBOL(mb86a20s_attach);
2086 static const struct dvb_frontend_ops mb86a20s_ops = {
2087 .delsys = { SYS_ISDBT },
2088 /* Use dib8000 values per default */
2090 .name = "Fujitsu mb86A20s",
2091 .caps = FE_CAN_RECOVER |
2092 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2093 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2094 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2095 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_QAM_AUTO |
2096 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
2097 /* Actually, those values depend on the used tuner */
2098 .frequency_min_hz = 45 * MHz,
2099 .frequency_max_hz = 864 * MHz,
2100 .frequency_stepsize_hz = 62500,
2103 .release = mb86a20s_release,
2105 .init = mb86a20s_initfe,
2106 .set_frontend = mb86a20s_set_frontend,
2107 .read_status = mb86a20s_read_status_and_stats,
2108 .read_signal_strength = mb86a20s_read_signal_strength_from_cache,
2109 .tune = mb86a20s_tune,
2110 .get_frontend_algo = mb86a20s_get_frontend_algo,
2113 MODULE_DESCRIPTION("DVB Frontend module for Fujitsu mb86A20s hardware");
2114 MODULE_AUTHOR("Mauro Carvalho Chehab");
2115 MODULE_LICENSE("GPL");