1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Montage Technology M88DS3103/M88RS6000 demodulator driver
5 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
8 #include "m88ds3103_priv.h"
10 static const struct dvb_frontend_ops m88ds3103_ops;
12 /* write single register with mask */
13 static int m88ds3103_update_bits(struct m88ds3103_dev *dev,
14 u8 reg, u8 mask, u8 val)
19 /* no need for read if whole reg is written */
21 ret = regmap_bulk_read(dev->regmap, reg, &tmp, 1);
30 return regmap_bulk_write(dev->regmap, reg, &val, 1);
33 /* write reg val table using reg addr auto increment */
34 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_dev *dev,
35 const struct m88ds3103_reg_val *tab, int tab_len)
37 struct i2c_client *client = dev->client;
41 dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
48 for (i = 0, j = 0; i < tab_len; i++, j++) {
51 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
52 !((j + 1) % (dev->cfg->i2c_wr_max - 1))) {
53 ret = regmap_bulk_write(dev->regmap, tab[i].reg - j, buf, j + 1);
63 dev_dbg(&client->dev, "failed=%d\n", ret);
68 * m88ds3103b demod has an internal device related to clocking. First the i2c
69 * gate must be opened, for one transaction, then writes will be allowed.
71 static int m88ds3103b_dt_write(struct m88ds3103_dev *dev, int reg, int data)
73 struct i2c_client *client = dev->client;
74 u8 buf[] = {reg, data};
77 struct i2c_msg msg = {
78 .addr = dev->dt_addr, .flags = 0, .buf = buf, .len = 2
81 m88ds3103_update_bits(dev, 0x11, 0x01, 0x00);
84 ret = regmap_write(dev->regmap, 0x03, val);
86 dev_dbg(&client->dev, "fail=%d\n", ret);
88 ret = i2c_transfer(dev->dt_client->adapter, &msg, 1);
90 dev_err(&client->dev, "0x%02x (ret=%i, reg=0x%02x, value=0x%02x)\n",
91 dev->dt_addr, ret, reg, data);
93 m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
96 m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
98 dev_dbg(&client->dev, "0x%02x reg 0x%02x, value 0x%02x\n",
99 dev->dt_addr, reg, data);
105 * m88ds3103b demod has an internal device related to clocking. First the i2c
106 * gate must be opened, for two transactions, then reads will be allowed.
108 static int m88ds3103b_dt_read(struct m88ds3103_dev *dev, u8 reg)
110 struct i2c_client *client = dev->client;
115 struct i2c_msg msg[] = {
117 .addr = dev->dt_addr,
123 .addr = dev->dt_addr,
130 m88ds3103_update_bits(dev, 0x11, 0x01, 0x00);
133 ret = regmap_write(dev->regmap, 0x03, val);
135 dev_dbg(&client->dev, "fail=%d\n", ret);
137 ret = i2c_transfer(dev->dt_client->adapter, msg, 2);
139 dev_err(&client->dev, "0x%02x (ret=%d, reg=0x%02x)\n",
140 dev->dt_addr, ret, reg);
142 m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
145 m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
147 dev_dbg(&client->dev, "0x%02x reg 0x%02x, value 0x%02x\n",
148 dev->dt_addr, reg, b1[0]);
154 * Get the demodulator AGC PWM voltage setting supplied to the tuner.
156 int m88ds3103_get_agc_pwm(struct dvb_frontend *fe, u8 *_agc_pwm)
158 struct m88ds3103_dev *dev = fe->demodulator_priv;
162 ret = regmap_read(dev->regmap, 0x3f, &tmp);
167 EXPORT_SYMBOL(m88ds3103_get_agc_pwm);
169 static int m88ds3103_read_status(struct dvb_frontend *fe,
170 enum fe_status *status)
172 struct m88ds3103_dev *dev = fe->demodulator_priv;
173 struct i2c_client *client = dev->client;
174 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
186 switch (c->delivery_system) {
188 ret = regmap_read(dev->regmap, 0xd1, &utmp);
192 if ((utmp & 0x07) == 0x07)
193 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
194 FE_HAS_VITERBI | FE_HAS_SYNC |
198 ret = regmap_read(dev->regmap, 0x0d, &utmp);
202 if ((utmp & 0x8f) == 0x8f)
203 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
204 FE_HAS_VITERBI | FE_HAS_SYNC |
208 dev_dbg(&client->dev, "invalid delivery_system\n");
213 dev->fe_status = *status;
214 dev_dbg(&client->dev, "lock=%02x status=%02x\n", utmp, *status);
217 if (dev->fe_status & FE_HAS_VITERBI) {
218 unsigned int cnr, noise, signal, noise_tot, signal_tot;
221 /* more iterations for more accurate estimation */
222 #define M88DS3103_SNR_ITERATIONS 3
224 switch (c->delivery_system) {
228 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
229 ret = regmap_read(dev->regmap, 0xff, &utmp);
236 /* use of single register limits max value to 15 dB */
237 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
238 itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS);
240 cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10));
246 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
247 ret = regmap_bulk_read(dev->regmap, 0x8c, buf, 3);
251 noise = buf[1] << 6; /* [13:6] */
252 noise |= buf[0] & 0x3f; /* [5:0] */
254 signal = buf[2] * buf[2];
258 signal_tot += signal;
261 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
262 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
264 /* SNR(X) dB = 10 * log10(X) dB */
265 if (signal > noise) {
266 itmp = signal / noise;
267 cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24));
271 dev_dbg(&client->dev, "invalid delivery_system\n");
277 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
278 c->cnr.stat[0].svalue = cnr;
280 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
283 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
287 if (dev->fe_status & FE_HAS_LOCK) {
288 unsigned int utmp, post_bit_error, post_bit_count;
290 switch (c->delivery_system) {
292 ret = regmap_write(dev->regmap, 0xf9, 0x04);
296 ret = regmap_read(dev->regmap, 0xf8, &utmp);
300 /* measurement ready? */
301 if (!(utmp & 0x10)) {
302 ret = regmap_bulk_read(dev->regmap, 0xf6, buf, 2);
306 post_bit_error = buf[1] << 8 | buf[0] << 0;
307 post_bit_count = 0x800000;
308 dev->post_bit_error += post_bit_error;
309 dev->post_bit_count += post_bit_count;
310 dev->dvbv3_ber = post_bit_error;
312 /* restart measurement */
314 ret = regmap_write(dev->regmap, 0xf8, utmp);
320 ret = regmap_bulk_read(dev->regmap, 0xd5, buf, 3);
324 utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
328 ret = regmap_bulk_read(dev->regmap, 0xf7, buf, 2);
332 post_bit_error = buf[1] << 8 | buf[0] << 0;
333 post_bit_count = 32 * utmp; /* TODO: FEC */
334 dev->post_bit_error += post_bit_error;
335 dev->post_bit_count += post_bit_count;
336 dev->dvbv3_ber = post_bit_error;
338 /* restart measurement */
339 ret = regmap_write(dev->regmap, 0xd1, 0x01);
343 ret = regmap_write(dev->regmap, 0xf9, 0x01);
347 ret = regmap_write(dev->regmap, 0xf9, 0x00);
351 ret = regmap_write(dev->regmap, 0xd1, 0x00);
357 dev_dbg(&client->dev, "invalid delivery_system\n");
362 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
363 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
364 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
365 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
367 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
368 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
373 dev_dbg(&client->dev, "failed=%d\n", ret);
377 static int m88ds3103b_select_mclk(struct m88ds3103_dev *dev)
379 struct i2c_client *client = dev->client;
380 struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
381 u32 adc_Freq_MHz[3] = {96, 93, 99};
382 u8 reg16_list[3] = {96, 92, 100}, reg16, reg15;
385 u32 old_setting = dev->mclk;
386 u32 tuner_freq_MHz = c->frequency / 1000;
390 big_symbol = (c->symbol_rate > 45010000) ? 1 : 0;
397 /* TODO: IS THIS NECESSARY ? */
398 for (i = 0; i < 3; i++) {
399 offset_MHz[i] = tuner_freq_MHz % adc_Freq_MHz[i];
401 if (offset_MHz[i] > (adc_Freq_MHz[i] / 2))
402 offset_MHz[i] = adc_Freq_MHz[i] - offset_MHz[i];
404 if (offset_MHz[i] > max_offset) {
405 max_offset = offset_MHz[i];
406 reg16 = reg16_list[i];
407 dev->mclk = adc_Freq_MHz[i] * 1000 * 1000;
412 dev_dbg(&client->dev, "modifying mclk %u -> %u\n",
413 old_setting, dev->mclk);
418 if (dev->mclk == 93000000)
419 regmap_write(dev->regmap, 0xA0, 0x42);
420 else if (dev->mclk == 96000000)
421 regmap_write(dev->regmap, 0xA0, 0x44);
422 else if (dev->mclk == 99000000)
423 regmap_write(dev->regmap, 0xA0, 0x46);
424 else if (dev->mclk == 110250000)
425 regmap_write(dev->regmap, 0xA0, 0x4E);
427 regmap_write(dev->regmap, 0xA0, 0x44);
429 reg15 = m88ds3103b_dt_read(dev, 0x15);
431 m88ds3103b_dt_write(dev, 0x05, 0x40);
432 m88ds3103b_dt_write(dev, 0x11, 0x08);
439 m88ds3103b_dt_write(dev, 0x15, reg15);
440 m88ds3103b_dt_write(dev, 0x16, reg16);
442 usleep_range(5000, 5500);
444 m88ds3103b_dt_write(dev, 0x05, 0x00);
445 m88ds3103b_dt_write(dev, 0x11, (u8)(big_symbol ? 0x0E : 0x0A));
447 usleep_range(5000, 5500);
452 static int m88ds3103b_set_mclk(struct m88ds3103_dev *dev, u32 mclk_khz)
454 u8 reg15, reg16, reg1D, reg1E, reg1F, tmp;
455 u8 sm, f0 = 0, f1 = 0, f2 = 0, f3 = 0;
459 reg15 = m88ds3103b_dt_read(dev, 0x15);
460 reg16 = m88ds3103b_dt_read(dev, 0x16);
461 reg1D = m88ds3103b_dt_read(dev, 0x1D);
463 if (dev->cfg->ts_mode != M88DS3103_TS_SERIAL) {
466 else if (reg16 == 100)
475 pll_div_fb = (reg15 & 0x01) << 8;
479 div = 9000 * pll_div_fb * 4;
482 if (dev->cfg->ts_mode == M88DS3103_TS_SERIAL) {
490 } else if (div <= 34) {
494 f1 = (div - f0) / (N - 1);
497 } else if (div <= 64) {
501 f1 = (div - f0) / (N - 1);
502 f2 = (div - f0 - f1) / (N - 2);
503 f3 = div - f0 - f1 - f2;
515 else if ((f0 < 8) && (f0 != 0))
520 else if ((f1 < 8) && (f1 != 0))
525 else if ((f2 < 8) && (f2 != 0))
530 else if ((f3 < 8) && (f3 != 0))
540 } else if (div <= 48) {
544 f1 = (div - f0) / (N - 1);
547 } else if (div <= 64) {
551 f1 = (div - f0) / (N - 1);
552 f2 = (div - f0 - f1) / (N - 2);
553 f3 = div - f0 - f1 - f2;
565 else if ((f0 < 9) && (f0 != 0))
570 else if ((f1 < 9) && (f1 != 0))
575 else if ((f2 < 9) && (f2 != 0))
580 else if ((f3 < 9) && (f3 != 0))
586 /* Write to registers */
588 //reg15 |= (pll_div_fb >> 8) & 0x01;
590 //reg16 = pll_div_fb & 0xFF;
596 reg1E = ((f3 << 4) + f2) & 0xFF;
597 reg1F = ((f1 << 4) + f0) & 0xFF;
599 m88ds3103b_dt_write(dev, 0x05, 0x40);
600 m88ds3103b_dt_write(dev, 0x11, 0x08);
601 m88ds3103b_dt_write(dev, 0x1D, reg1D);
602 m88ds3103b_dt_write(dev, 0x1E, reg1E);
603 m88ds3103b_dt_write(dev, 0x1F, reg1F);
605 m88ds3103b_dt_write(dev, 0x17, 0xc1);
606 m88ds3103b_dt_write(dev, 0x17, 0x81);
608 usleep_range(5000, 5500);
610 m88ds3103b_dt_write(dev, 0x05, 0x00);
611 m88ds3103b_dt_write(dev, 0x11, 0x0A);
613 usleep_range(5000, 5500);
618 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
620 struct m88ds3103_dev *dev = fe->demodulator_priv;
621 struct i2c_client *client = dev->client;
622 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
624 const struct m88ds3103_reg_val *init;
625 u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
628 u32 tuner_frequency_khz, target_mclk, u32tmp;
630 static const struct reg_sequence reset_buf[] = {
631 {0x07, 0x80}, {0x07, 0x00}
634 dev_dbg(&client->dev,
635 "delivery_system=%d modulation=%d frequency=%u symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
636 c->delivery_system, c->modulation, c->frequency, c->symbol_rate,
637 c->inversion, c->pilot, c->rolloff);
645 ret = regmap_multi_reg_write(dev->regmap, reset_buf, 2);
649 /* Disable demod clock path */
650 if (dev->chip_id == M88RS6000_CHIP_ID) {
651 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
652 ret = regmap_read(dev->regmap, 0xb2, &u32tmp);
655 if (u32tmp == 0x01) {
656 ret = regmap_write(dev->regmap, 0x00, 0x00);
659 ret = regmap_write(dev->regmap, 0xb2, 0x00);
665 ret = regmap_write(dev->regmap, 0x06, 0xe0);
671 if (fe->ops.tuner_ops.set_params) {
672 ret = fe->ops.tuner_ops.set_params(fe);
677 if (fe->ops.tuner_ops.get_frequency) {
678 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency_khz);
683 * Use nominal target frequency as tuner driver does not provide
684 * actual frequency used. Carrier offset calculation is not
687 tuner_frequency_khz = c->frequency;
690 /* set M88RS6000/DS3103B demod main mclk and ts mclk from tuner die */
691 if (dev->chip_id == M88RS6000_CHIP_ID) {
692 if (c->symbol_rate > 45010000)
693 dev->mclk = 110250000;
695 dev->mclk = 96000000;
697 if (c->delivery_system == SYS_DVBS)
698 target_mclk = 96000000;
700 target_mclk = 144000000;
702 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
703 m88ds3103b_select_mclk(dev);
704 m88ds3103b_set_mclk(dev, target_mclk / 1000);
707 /* Enable demod clock path */
708 ret = regmap_write(dev->regmap, 0x06, 0x00);
711 usleep_range(10000, 20000);
713 /* set M88DS3103 mclk and ts mclk. */
714 dev->mclk = 96000000;
716 switch (dev->cfg->ts_mode) {
717 case M88DS3103_TS_SERIAL:
718 case M88DS3103_TS_SERIAL_D7:
719 target_mclk = dev->cfg->ts_clk;
721 case M88DS3103_TS_PARALLEL:
722 case M88DS3103_TS_CI:
723 if (c->delivery_system == SYS_DVBS)
724 target_mclk = 96000000;
726 if (c->symbol_rate < 18000000)
727 target_mclk = 96000000;
728 else if (c->symbol_rate < 28000000)
729 target_mclk = 144000000;
731 target_mclk = 192000000;
735 dev_dbg(&client->dev, "invalid ts_mode\n");
740 switch (target_mclk) {
742 u8tmp1 = 0x02; /* 0b10 */
743 u8tmp2 = 0x01; /* 0b01 */
746 u8tmp1 = 0x00; /* 0b00 */
747 u8tmp2 = 0x01; /* 0b01 */
750 u8tmp1 = 0x03; /* 0b11 */
751 u8tmp2 = 0x00; /* 0b00 */
754 ret = m88ds3103_update_bits(dev, 0x22, 0xc0, u8tmp1 << 6);
757 ret = m88ds3103_update_bits(dev, 0x24, 0xc0, u8tmp2 << 6);
762 ret = regmap_write(dev->regmap, 0xb2, 0x01);
766 ret = regmap_write(dev->regmap, 0x00, 0x01);
770 switch (c->delivery_system) {
772 if (dev->chip_id == M88RS6000_CHIP_ID) {
773 len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
774 init = m88rs6000_dvbs_init_reg_vals;
776 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
777 init = m88ds3103_dvbs_init_reg_vals;
781 if (dev->chip_id == M88RS6000_CHIP_ID) {
782 len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
783 init = m88rs6000_dvbs2_init_reg_vals;
785 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
786 init = m88ds3103_dvbs2_init_reg_vals;
790 dev_dbg(&client->dev, "invalid delivery_system\n");
795 /* program init table */
796 if (c->delivery_system != dev->delivery_system) {
797 ret = m88ds3103_wr_reg_val_tab(dev, init, len);
802 if (dev->chip_id == M88RS6000_CHIP_ID) {
803 if (c->delivery_system == SYS_DVBS2 &&
804 c->symbol_rate <= 5000000) {
805 ret = regmap_write(dev->regmap, 0xc0, 0x04);
811 ret = regmap_bulk_write(dev->regmap, 0x8a, buf, 3);
815 ret = m88ds3103_update_bits(dev, 0x9d, 0x08, 0x08);
819 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
820 buf[0] = m88ds3103b_dt_read(dev, 0x15);
821 buf[1] = m88ds3103b_dt_read(dev, 0x16);
823 if (c->symbol_rate > 45010000) {
826 buf[0] |= ((147 - 32) >> 8) & 0x01;
827 buf[1] = (147 - 32) & 0xFF;
829 dev->mclk = 110250 * 1000;
832 buf[0] |= ((128 - 32) >> 8) & 0x01;
833 buf[1] = (128 - 32) & 0xFF;
835 dev->mclk = 96000 * 1000;
837 m88ds3103b_dt_write(dev, 0x15, buf[0]);
838 m88ds3103b_dt_write(dev, 0x16, buf[1]);
840 regmap_read(dev->regmap, 0x30, &u32tmp);
842 regmap_write(dev->regmap, 0x30, u32tmp & 0xff);
845 ret = regmap_write(dev->regmap, 0xf1, 0x01);
849 if (dev->chiptype != M88DS3103_CHIPTYPE_3103B) {
850 ret = m88ds3103_update_bits(dev, 0x30, 0x80, 0x80);
856 switch (dev->cfg->ts_mode) {
857 case M88DS3103_TS_SERIAL:
861 case M88DS3103_TS_SERIAL_D7:
865 case M88DS3103_TS_PARALLEL:
867 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
872 case M88DS3103_TS_CI:
876 dev_dbg(&client->dev, "invalid ts_mode\n");
881 if (dev->cfg->ts_clk_pol)
885 ret = regmap_write(dev->regmap, 0xfd, u8tmp);
889 switch (dev->cfg->ts_mode) {
890 case M88DS3103_TS_SERIAL:
891 case M88DS3103_TS_SERIAL_D7:
892 ret = m88ds3103_update_bits(dev, 0x29, 0x20, u8tmp1);
899 case M88DS3103_TS_PARALLEL:
900 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
901 ret = m88ds3103_update_bits(dev, 0x29, 0x01, u8tmp1);
907 u16tmp = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk);
908 u8tmp1 = u16tmp / 2 - 1;
909 u8tmp2 = DIV_ROUND_UP(u16tmp, 2) - 1;
912 dev_dbg(&client->dev, "target_mclk=%u ts_clk=%u ts_clk_divide_ratio=%u\n",
913 target_mclk, dev->cfg->ts_clk, u16tmp);
915 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
916 /* u8tmp2[5:0] => ea[5:0] */
917 u8tmp = (u8tmp1 >> 2) & 0x0f;
918 ret = regmap_update_bits(dev->regmap, 0xfe, 0x0f, u8tmp);
921 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
922 ret = regmap_write(dev->regmap, 0xea, u8tmp);
926 if (c->symbol_rate <= 3000000)
928 else if (c->symbol_rate <= 10000000)
933 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B)
934 m88ds3103b_set_mclk(dev, target_mclk / 1000);
936 ret = regmap_write(dev->regmap, 0xc3, 0x08);
940 ret = regmap_write(dev->regmap, 0xc8, u8tmp);
944 ret = regmap_write(dev->regmap, 0xc4, 0x08);
948 ret = regmap_write(dev->regmap, 0xc7, 0x00);
952 u16tmp = DIV_ROUND_CLOSEST_ULL((u64)c->symbol_rate * 0x10000, dev->mclk);
953 buf[0] = (u16tmp >> 0) & 0xff;
954 buf[1] = (u16tmp >> 8) & 0xff;
955 ret = regmap_bulk_write(dev->regmap, 0x61, buf, 2);
959 ret = m88ds3103_update_bits(dev, 0x4d, 0x02, dev->cfg->spec_inv << 1);
963 ret = m88ds3103_update_bits(dev, 0x30, 0x10, dev->cfg->agc_inv << 4);
967 ret = regmap_write(dev->regmap, 0x33, dev->cfg->agc);
971 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
972 /* enable/disable 192M LDPC clock */
973 ret = m88ds3103_update_bits(dev, 0x29, 0x10,
974 (c->delivery_system == SYS_DVBS) ? 0x10 : 0x0);
978 ret = m88ds3103_update_bits(dev, 0xc9, 0x08, 0x08);
983 dev_dbg(&client->dev, "carrier offset=%d\n",
984 (tuner_frequency_khz - c->frequency));
986 /* Use 32-bit calc as there is no s64 version of DIV_ROUND_CLOSEST() */
987 s32tmp = 0x10000 * (tuner_frequency_khz - c->frequency);
988 s32tmp = DIV_ROUND_CLOSEST(s32tmp, dev->mclk / 1000);
989 buf[0] = (s32tmp >> 0) & 0xff;
990 buf[1] = (s32tmp >> 8) & 0xff;
991 ret = regmap_bulk_write(dev->regmap, 0x5e, buf, 2);
995 ret = regmap_write(dev->regmap, 0x00, 0x00);
999 ret = regmap_write(dev->regmap, 0xb2, 0x00);
1003 dev->delivery_system = c->delivery_system;
1007 dev_dbg(&client->dev, "failed=%d\n", ret);
1011 static int m88ds3103_init(struct dvb_frontend *fe)
1013 struct m88ds3103_dev *dev = fe->demodulator_priv;
1014 struct i2c_client *client = dev->client;
1015 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1018 const struct firmware *firmware;
1021 dev_dbg(&client->dev, "\n");
1023 /* set cold state by default */
1026 /* wake up device from sleep */
1027 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x01);
1030 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x00);
1033 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x00);
1037 /* firmware status */
1038 ret = regmap_read(dev->regmap, 0xb9, &utmp);
1042 dev_dbg(&client->dev, "firmware=%02x\n", utmp);
1047 /* global reset, global diseqc reset, global fec reset */
1048 ret = regmap_write(dev->regmap, 0x07, 0xe0);
1051 ret = regmap_write(dev->regmap, 0x07, 0x00);
1055 /* cold state - try to download firmware */
1056 dev_info(&client->dev, "found a '%s' in cold state\n",
1057 dev->fe.ops.info.name);
1059 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B)
1060 name = M88DS3103B_FIRMWARE;
1061 else if (dev->chip_id == M88RS6000_CHIP_ID)
1062 name = M88RS6000_FIRMWARE;
1064 name = M88DS3103_FIRMWARE;
1066 /* request the firmware, this will block and timeout */
1067 ret = reject_firmware(&firmware, name, &client->dev);
1069 dev_err(&client->dev, "firmware file '%s' not found\n", name);
1073 dev_info(&client->dev, "downloading firmware from file '%s'\n", name);
1075 ret = regmap_write(dev->regmap, 0xb2, 0x01);
1077 goto err_release_firmware;
1079 for (rem = firmware->size; rem > 0; rem -= (dev->cfg->i2c_wr_max - 1)) {
1080 len = min(dev->cfg->i2c_wr_max - 1, rem);
1081 ret = regmap_bulk_write(dev->regmap, 0xb0,
1082 &firmware->data[firmware->size - rem],
1085 dev_err(&client->dev, "firmware download failed %d\n",
1087 goto err_release_firmware;
1091 ret = regmap_write(dev->regmap, 0xb2, 0x00);
1093 goto err_release_firmware;
1095 release_firmware(firmware);
1097 ret = regmap_read(dev->regmap, 0xb9, &utmp);
1103 dev_info(&client->dev, "firmware did not run\n");
1107 dev_info(&client->dev, "found a '%s' in warm state\n",
1108 dev->fe.ops.info.name);
1109 dev_info(&client->dev, "firmware version: %X.%X\n",
1110 (utmp >> 4) & 0xf, (utmp >> 0 & 0xf));
1112 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
1113 m88ds3103b_dt_write(dev, 0x21, 0x92);
1114 m88ds3103b_dt_write(dev, 0x15, 0x6C);
1115 m88ds3103b_dt_write(dev, 0x17, 0xC1);
1116 m88ds3103b_dt_write(dev, 0x17, 0x81);
1122 /* init stats here in order signal app which stats are supported */
1124 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1125 c->post_bit_error.len = 1;
1126 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1127 c->post_bit_count.len = 1;
1128 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1131 err_release_firmware:
1132 release_firmware(firmware);
1134 dev_dbg(&client->dev, "failed=%d\n", ret);
1138 static int m88ds3103_sleep(struct dvb_frontend *fe)
1140 struct m88ds3103_dev *dev = fe->demodulator_priv;
1141 struct i2c_client *client = dev->client;
1145 dev_dbg(&client->dev, "\n");
1148 dev->delivery_system = SYS_UNDEFINED;
1151 if (dev->chip_id == M88RS6000_CHIP_ID)
1155 ret = m88ds3103_update_bits(dev, utmp, 0x01, 0x00);
1160 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
1163 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
1166 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
1172 dev_dbg(&client->dev, "failed=%d\n", ret);
1176 static int m88ds3103_get_frontend(struct dvb_frontend *fe,
1177 struct dtv_frontend_properties *c)
1179 struct m88ds3103_dev *dev = fe->demodulator_priv;
1180 struct i2c_client *client = dev->client;
1184 dev_dbg(&client->dev, "\n");
1186 if (!dev->warm || !(dev->fe_status & FE_HAS_LOCK)) {
1191 switch (c->delivery_system) {
1193 ret = regmap_bulk_read(dev->regmap, 0xe0, &buf[0], 1);
1197 ret = regmap_bulk_read(dev->regmap, 0xe6, &buf[1], 1);
1201 switch ((buf[0] >> 2) & 0x01) {
1203 c->inversion = INVERSION_OFF;
1206 c->inversion = INVERSION_ON;
1210 switch ((buf[1] >> 5) & 0x07) {
1212 c->fec_inner = FEC_7_8;
1215 c->fec_inner = FEC_5_6;
1218 c->fec_inner = FEC_3_4;
1221 c->fec_inner = FEC_2_3;
1224 c->fec_inner = FEC_1_2;
1227 dev_dbg(&client->dev, "invalid fec_inner\n");
1230 c->modulation = QPSK;
1234 ret = regmap_bulk_read(dev->regmap, 0x7e, &buf[0], 1);
1238 ret = regmap_bulk_read(dev->regmap, 0x89, &buf[1], 1);
1242 ret = regmap_bulk_read(dev->regmap, 0xf2, &buf[2], 1);
1246 switch ((buf[0] >> 0) & 0x0f) {
1248 c->fec_inner = FEC_2_5;
1251 c->fec_inner = FEC_1_2;
1254 c->fec_inner = FEC_3_5;
1257 c->fec_inner = FEC_2_3;
1260 c->fec_inner = FEC_3_4;
1263 c->fec_inner = FEC_4_5;
1266 c->fec_inner = FEC_5_6;
1269 c->fec_inner = FEC_8_9;
1272 c->fec_inner = FEC_9_10;
1275 dev_dbg(&client->dev, "invalid fec_inner\n");
1278 switch ((buf[0] >> 5) & 0x01) {
1280 c->pilot = PILOT_OFF;
1283 c->pilot = PILOT_ON;
1287 switch ((buf[0] >> 6) & 0x07) {
1289 c->modulation = QPSK;
1292 c->modulation = PSK_8;
1295 c->modulation = APSK_16;
1298 c->modulation = APSK_32;
1301 dev_dbg(&client->dev, "invalid modulation\n");
1304 switch ((buf[1] >> 7) & 0x01) {
1306 c->inversion = INVERSION_OFF;
1309 c->inversion = INVERSION_ON;
1313 switch ((buf[2] >> 0) & 0x03) {
1315 c->rolloff = ROLLOFF_35;
1318 c->rolloff = ROLLOFF_25;
1321 c->rolloff = ROLLOFF_20;
1324 dev_dbg(&client->dev, "invalid rolloff\n");
1328 dev_dbg(&client->dev, "invalid delivery_system\n");
1333 ret = regmap_bulk_read(dev->regmap, 0x6d, buf, 2);
1337 c->symbol_rate = DIV_ROUND_CLOSEST_ULL((u64)(buf[1] << 8 | buf[0] << 0) * dev->mclk, 0x10000);
1341 dev_dbg(&client->dev, "failed=%d\n", ret);
1345 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
1347 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1349 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
1350 *snr = div_s64(c->cnr.stat[0].svalue, 100);
1357 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
1359 struct m88ds3103_dev *dev = fe->demodulator_priv;
1361 *ber = dev->dvbv3_ber;
1366 static int m88ds3103_set_tone(struct dvb_frontend *fe,
1367 enum fe_sec_tone_mode fe_sec_tone_mode)
1369 struct m88ds3103_dev *dev = fe->demodulator_priv;
1370 struct i2c_client *client = dev->client;
1372 unsigned int utmp, tone, reg_a1_mask;
1374 dev_dbg(&client->dev, "fe_sec_tone_mode=%d\n", fe_sec_tone_mode);
1381 switch (fe_sec_tone_mode) {
1391 dev_dbg(&client->dev, "invalid fe_sec_tone_mode\n");
1396 utmp = tone << 7 | dev->cfg->envelope_mode << 5;
1397 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1402 ret = m88ds3103_update_bits(dev, 0xa1, reg_a1_mask, utmp);
1408 dev_dbg(&client->dev, "failed=%d\n", ret);
1412 static int m88ds3103_set_voltage(struct dvb_frontend *fe,
1413 enum fe_sec_voltage fe_sec_voltage)
1415 struct m88ds3103_dev *dev = fe->demodulator_priv;
1416 struct i2c_client *client = dev->client;
1419 bool voltage_sel, voltage_dis;
1421 dev_dbg(&client->dev, "fe_sec_voltage=%d\n", fe_sec_voltage);
1428 switch (fe_sec_voltage) {
1429 case SEC_VOLTAGE_18:
1431 voltage_dis = false;
1433 case SEC_VOLTAGE_13:
1434 voltage_sel = false;
1435 voltage_dis = false;
1437 case SEC_VOLTAGE_OFF:
1438 voltage_sel = false;
1442 dev_dbg(&client->dev, "invalid fe_sec_voltage\n");
1447 /* output pin polarity */
1448 voltage_sel ^= dev->cfg->lnb_hv_pol;
1449 voltage_dis ^= dev->cfg->lnb_en_pol;
1451 utmp = voltage_dis << 1 | voltage_sel << 0;
1452 ret = m88ds3103_update_bits(dev, 0xa2, 0x03, utmp);
1458 dev_dbg(&client->dev, "failed=%d\n", ret);
1462 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1463 struct dvb_diseqc_master_cmd *diseqc_cmd)
1465 struct m88ds3103_dev *dev = fe->demodulator_priv;
1466 struct i2c_client *client = dev->client;
1469 unsigned long timeout;
1471 dev_dbg(&client->dev, "msg=%*ph\n",
1472 diseqc_cmd->msg_len, diseqc_cmd->msg);
1479 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1484 utmp = dev->cfg->envelope_mode << 5;
1485 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1489 ret = regmap_bulk_write(dev->regmap, 0xa3, diseqc_cmd->msg,
1490 diseqc_cmd->msg_len);
1494 ret = regmap_write(dev->regmap, 0xa1,
1495 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1499 /* wait DiSEqC TX ready */
1500 #define SEND_MASTER_CMD_TIMEOUT 120
1501 timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT);
1503 /* DiSEqC message period is 13.5 ms per byte */
1504 utmp = diseqc_cmd->msg_len * 13500;
1505 usleep_range(utmp - 4000, utmp);
1507 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1508 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1511 utmp = (utmp >> 6) & 0x1;
1515 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1516 jiffies_to_msecs(jiffies) -
1517 (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT));
1519 dev_dbg(&client->dev, "diseqc tx timeout\n");
1521 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1526 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1537 dev_dbg(&client->dev, "failed=%d\n", ret);
1541 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1542 enum fe_sec_mini_cmd fe_sec_mini_cmd)
1544 struct m88ds3103_dev *dev = fe->demodulator_priv;
1545 struct i2c_client *client = dev->client;
1547 unsigned int utmp, burst;
1548 unsigned long timeout;
1550 dev_dbg(&client->dev, "fe_sec_mini_cmd=%d\n", fe_sec_mini_cmd);
1557 utmp = dev->cfg->envelope_mode << 5;
1558 ret = m88ds3103_update_bits(dev, 0xa2, 0xe0, utmp);
1562 switch (fe_sec_mini_cmd) {
1570 dev_dbg(&client->dev, "invalid fe_sec_mini_cmd\n");
1575 ret = regmap_write(dev->regmap, 0xa1, burst);
1579 /* wait DiSEqC TX ready */
1580 #define SEND_BURST_TIMEOUT 40
1581 timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT);
1583 /* DiSEqC ToneBurst period is 12.5 ms */
1584 usleep_range(8500, 12500);
1586 for (utmp = 1; !time_after(jiffies, timeout) && utmp;) {
1587 ret = regmap_read(dev->regmap, 0xa1, &utmp);
1590 utmp = (utmp >> 6) & 0x1;
1594 dev_dbg(&client->dev, "diseqc tx took %u ms\n",
1595 jiffies_to_msecs(jiffies) -
1596 (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT));
1598 dev_dbg(&client->dev, "diseqc tx timeout\n");
1600 ret = m88ds3103_update_bits(dev, 0xa1, 0xc0, 0x40);
1605 ret = m88ds3103_update_bits(dev, 0xa2, 0xc0, 0x80);
1616 dev_dbg(&client->dev, "failed=%d\n", ret);
1620 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1621 struct dvb_frontend_tune_settings *s)
1623 s->min_delay_ms = 3000;
1628 static void m88ds3103_release(struct dvb_frontend *fe)
1630 struct m88ds3103_dev *dev = fe->demodulator_priv;
1631 struct i2c_client *client = dev->client;
1633 i2c_unregister_device(client);
1636 static int m88ds3103_select(struct i2c_mux_core *muxc, u32 chan)
1638 struct m88ds3103_dev *dev = i2c_mux_priv(muxc);
1639 struct i2c_client *client = dev->client;
1641 struct i2c_msg msg = {
1642 .addr = client->addr,
1648 /* Open tuner I2C repeater for 1 xfer, closes automatically */
1649 ret = __i2c_transfer(client->adapter, &msg, 1);
1651 dev_warn(&client->dev, "i2c wr failed=%d\n", ret);
1661 * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide
1662 * proper I2C client for legacy media attach binding.
1663 * New users must use I2C client binding directly!
1665 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1666 struct i2c_adapter *i2c,
1667 struct i2c_adapter **tuner_i2c_adapter)
1669 struct i2c_client *client;
1670 struct i2c_board_info board_info;
1671 struct m88ds3103_platform_data pdata = {};
1673 pdata.clk = cfg->clock;
1674 pdata.i2c_wr_max = cfg->i2c_wr_max;
1675 pdata.ts_mode = cfg->ts_mode;
1676 pdata.ts_clk = cfg->ts_clk;
1677 pdata.ts_clk_pol = cfg->ts_clk_pol;
1678 pdata.spec_inv = cfg->spec_inv;
1679 pdata.agc = cfg->agc;
1680 pdata.agc_inv = cfg->agc_inv;
1681 pdata.clk_out = cfg->clock_out;
1682 pdata.envelope_mode = cfg->envelope_mode;
1683 pdata.lnb_hv_pol = cfg->lnb_hv_pol;
1684 pdata.lnb_en_pol = cfg->lnb_en_pol;
1685 pdata.attach_in_use = true;
1687 memset(&board_info, 0, sizeof(board_info));
1688 strscpy(board_info.type, "m88ds3103", I2C_NAME_SIZE);
1689 board_info.addr = cfg->i2c_addr;
1690 board_info.platform_data = &pdata;
1691 client = i2c_new_client_device(i2c, &board_info);
1692 if (!i2c_client_has_driver(client))
1695 *tuner_i2c_adapter = pdata.get_i2c_adapter(client);
1696 return pdata.get_dvb_frontend(client);
1698 EXPORT_SYMBOL(m88ds3103_attach);
1700 static const struct dvb_frontend_ops m88ds3103_ops = {
1701 .delsys = {SYS_DVBS, SYS_DVBS2},
1703 .name = "Montage Technology M88DS3103",
1704 .frequency_min_hz = 950 * MHz,
1705 .frequency_max_hz = 2150 * MHz,
1706 .frequency_tolerance_hz = 5 * MHz,
1707 .symbol_rate_min = 1000000,
1708 .symbol_rate_max = 45000000,
1709 .caps = FE_CAN_INVERSION_AUTO |
1721 FE_CAN_2G_MODULATION
1724 .release = m88ds3103_release,
1726 .get_tune_settings = m88ds3103_get_tune_settings,
1728 .init = m88ds3103_init,
1729 .sleep = m88ds3103_sleep,
1731 .set_frontend = m88ds3103_set_frontend,
1732 .get_frontend = m88ds3103_get_frontend,
1734 .read_status = m88ds3103_read_status,
1735 .read_snr = m88ds3103_read_snr,
1736 .read_ber = m88ds3103_read_ber,
1738 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1739 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1741 .set_tone = m88ds3103_set_tone,
1742 .set_voltage = m88ds3103_set_voltage,
1745 static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client)
1747 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1749 dev_dbg(&client->dev, "\n");
1754 static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client)
1756 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1758 dev_dbg(&client->dev, "\n");
1760 return dev->muxc->adapter[0];
1763 static int m88ds3103_probe(struct i2c_client *client,
1764 const struct i2c_device_id *id)
1766 struct m88ds3103_dev *dev;
1767 struct m88ds3103_platform_data *pdata = client->dev.platform_data;
1771 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1777 dev->client = client;
1778 dev->config.clock = pdata->clk;
1779 dev->config.i2c_wr_max = pdata->i2c_wr_max;
1780 dev->config.ts_mode = pdata->ts_mode;
1781 dev->config.ts_clk = pdata->ts_clk * 1000;
1782 dev->config.ts_clk_pol = pdata->ts_clk_pol;
1783 dev->config.spec_inv = pdata->spec_inv;
1784 dev->config.agc_inv = pdata->agc_inv;
1785 dev->config.clock_out = pdata->clk_out;
1786 dev->config.envelope_mode = pdata->envelope_mode;
1787 dev->config.agc = pdata->agc;
1788 dev->config.lnb_hv_pol = pdata->lnb_hv_pol;
1789 dev->config.lnb_en_pol = pdata->lnb_en_pol;
1790 dev->cfg = &dev->config;
1792 dev->regmap_config.reg_bits = 8;
1793 dev->regmap_config.val_bits = 8;
1794 dev->regmap_config.lock_arg = dev;
1795 dev->regmap = devm_regmap_init_i2c(client, &dev->regmap_config);
1796 if (IS_ERR(dev->regmap)) {
1797 ret = PTR_ERR(dev->regmap);
1801 /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
1802 ret = regmap_read(dev->regmap, 0x00, &utmp);
1806 dev->chip_id = utmp >> 1;
1807 dev->chiptype = (u8)id->driver_data;
1809 dev_dbg(&client->dev, "chip_id=%02x\n", dev->chip_id);
1811 switch (dev->chip_id) {
1812 case M88RS6000_CHIP_ID:
1813 case M88DS3103_CHIP_ID:
1817 dev_err(&client->dev, "Unknown device. Chip_id=%02x\n", dev->chip_id);
1821 switch (dev->cfg->clock_out) {
1822 case M88DS3103_CLOCK_OUT_DISABLED:
1825 case M88DS3103_CLOCK_OUT_ENABLED:
1828 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1836 if (!pdata->ts_clk) {
1841 /* 0x29 register is defined differently for m88rs6000. */
1842 /* set internal tuner address to 0x21 */
1843 if (dev->chip_id == M88RS6000_CHIP_ID)
1846 ret = regmap_write(dev->regmap, 0x29, utmp);
1851 ret = m88ds3103_update_bits(dev, 0x08, 0x01, 0x00);
1854 ret = m88ds3103_update_bits(dev, 0x04, 0x01, 0x01);
1857 ret = m88ds3103_update_bits(dev, 0x23, 0x10, 0x10);
1861 /* create mux i2c adapter for tuner */
1862 dev->muxc = i2c_mux_alloc(client->adapter, &client->dev, 1, 0, 0,
1863 m88ds3103_select, NULL);
1868 dev->muxc->priv = dev;
1869 ret = i2c_mux_add_adapter(dev->muxc, 0, 0, 0);
1873 /* create dvb_frontend */
1874 memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1875 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B)
1876 strscpy(dev->fe.ops.info.name, "Montage Technology M88DS3103B",
1877 sizeof(dev->fe.ops.info.name));
1878 else if (dev->chip_id == M88RS6000_CHIP_ID)
1879 strscpy(dev->fe.ops.info.name, "Montage Technology M88RS6000",
1880 sizeof(dev->fe.ops.info.name));
1881 if (!pdata->attach_in_use)
1882 dev->fe.ops.release = NULL;
1883 dev->fe.demodulator_priv = dev;
1884 i2c_set_clientdata(client, dev);
1886 /* setup callbacks */
1887 pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend;
1888 pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter;
1890 if (dev->chiptype == M88DS3103_CHIPTYPE_3103B) {
1891 /* enable i2c repeater for tuner */
1892 m88ds3103_update_bits(dev, 0x11, 0x01, 0x01);
1894 /* get frontend address */
1895 ret = regmap_read(dev->regmap, 0x29, &utmp);
1898 dev->dt_addr = ((utmp & 0x80) == 0) ? 0x42 >> 1 : 0x40 >> 1;
1899 dev_dbg(&client->dev, "dt addr is 0x%02x\n", dev->dt_addr);
1901 dev->dt_client = i2c_new_dummy_device(client->adapter,
1903 if (IS_ERR(dev->dt_client)) {
1904 ret = PTR_ERR(dev->dt_client);
1913 dev_dbg(&client->dev, "failed=%d\n", ret);
1917 static int m88ds3103_remove(struct i2c_client *client)
1919 struct m88ds3103_dev *dev = i2c_get_clientdata(client);
1921 dev_dbg(&client->dev, "\n");
1924 i2c_unregister_device(dev->dt_client);
1926 i2c_mux_del_adapters(dev->muxc);
1932 static const struct i2c_device_id m88ds3103_id_table[] = {
1933 {"m88ds3103", M88DS3103_CHIPTYPE_3103},
1934 {"m88rs6000", M88DS3103_CHIPTYPE_RS6000},
1935 {"m88ds3103b", M88DS3103_CHIPTYPE_3103B},
1938 MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table);
1940 static struct i2c_driver m88ds3103_driver = {
1942 .name = "m88ds3103",
1943 .suppress_bind_attrs = true,
1945 .probe = m88ds3103_probe,
1946 .remove = m88ds3103_remove,
1947 .id_table = m88ds3103_id_table,
1950 module_i2c_driver(m88ds3103_driver);
1952 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1953 MODULE_DESCRIPTION("Montage Technology M88DS3103 DVB-S/S2 demodulator driver");
1954 MODULE_LICENSE("GPL");