1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for LG Electronics LGDT3304 and LGDT3305 - VSB/QAM
5 * Copyright (C) 2008, 2009, 2010 Michael Krufky <mkrufky@linuxtv.org>
7 * LGDT3304 support by Jarod Wilson <jarod@redhat.com>
10 #include <asm/div64.h>
11 #include <linux/dvb/frontend.h>
12 #include <linux/slab.h>
13 #include <media/dvb_math.h>
17 module_param(debug, int, 0644);
18 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
23 #define lg_printk(kern, fmt, arg...) \
24 printk(kern "%s: " fmt, __func__, ##arg)
26 #define lg_info(fmt, arg...) printk(KERN_INFO "lgdt3305: " fmt, ##arg)
27 #define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg)
28 #define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg)
29 #define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \
30 lg_printk(KERN_DEBUG, fmt, ##arg)
31 #define lg_reg(fmt, arg...) if (debug & DBG_REG) \
32 lg_printk(KERN_DEBUG, fmt, ##arg)
34 #define lg_fail(ret) \
39 lg_err("error %d on line %d\n", ret, __LINE__); \
43 struct lgdt3305_state {
44 struct i2c_adapter *i2c_adap;
45 const struct lgdt3305_config *cfg;
47 struct dvb_frontend frontend;
49 enum fe_modulation current_modulation;
50 u32 current_frequency;
54 /* ------------------------------------------------------------------------ */
56 /* FIXME: verify & document the LGDT3304 registers */
58 #define LGDT3305_GEN_CTRL_1 0x0000
59 #define LGDT3305_GEN_CTRL_2 0x0001
60 #define LGDT3305_GEN_CTRL_3 0x0002
61 #define LGDT3305_GEN_STATUS 0x0003
62 #define LGDT3305_GEN_CONTROL 0x0007
63 #define LGDT3305_GEN_CTRL_4 0x000a
64 #define LGDT3305_DGTL_AGC_REF_1 0x0012
65 #define LGDT3305_DGTL_AGC_REF_2 0x0013
66 #define LGDT3305_CR_CTR_FREQ_1 0x0106
67 #define LGDT3305_CR_CTR_FREQ_2 0x0107
68 #define LGDT3305_CR_CTR_FREQ_3 0x0108
69 #define LGDT3305_CR_CTR_FREQ_4 0x0109
70 #define LGDT3305_CR_MSE_1 0x011b
71 #define LGDT3305_CR_MSE_2 0x011c
72 #define LGDT3305_CR_LOCK_STATUS 0x011d
73 #define LGDT3305_CR_CTRL_7 0x0126
74 #define LGDT3305_AGC_POWER_REF_1 0x0300
75 #define LGDT3305_AGC_POWER_REF_2 0x0301
76 #define LGDT3305_AGC_DELAY_PT_1 0x0302
77 #define LGDT3305_AGC_DELAY_PT_2 0x0303
78 #define LGDT3305_RFAGC_LOOP_FLTR_BW_1 0x0306
79 #define LGDT3305_RFAGC_LOOP_FLTR_BW_2 0x0307
80 #define LGDT3305_IFBW_1 0x0308
81 #define LGDT3305_IFBW_2 0x0309
82 #define LGDT3305_AGC_CTRL_1 0x030c
83 #define LGDT3305_AGC_CTRL_4 0x0314
84 #define LGDT3305_EQ_MSE_1 0x0413
85 #define LGDT3305_EQ_MSE_2 0x0414
86 #define LGDT3305_EQ_MSE_3 0x0415
87 #define LGDT3305_PT_MSE_1 0x0417
88 #define LGDT3305_PT_MSE_2 0x0418
89 #define LGDT3305_PT_MSE_3 0x0419
90 #define LGDT3305_FEC_BLOCK_CTRL 0x0504
91 #define LGDT3305_FEC_LOCK_STATUS 0x050a
92 #define LGDT3305_FEC_PKT_ERR_1 0x050c
93 #define LGDT3305_FEC_PKT_ERR_2 0x050d
94 #define LGDT3305_TP_CTRL_1 0x050e
95 #define LGDT3305_BERT_PERIOD 0x0801
96 #define LGDT3305_BERT_ERROR_COUNT_1 0x080a
97 #define LGDT3305_BERT_ERROR_COUNT_2 0x080b
98 #define LGDT3305_BERT_ERROR_COUNT_3 0x080c
99 #define LGDT3305_BERT_ERROR_COUNT_4 0x080d
101 static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val)
104 u8 buf[] = { reg >> 8, reg & 0xff, val };
105 struct i2c_msg msg = {
106 .addr = state->cfg->i2c_addr, .flags = 0,
107 .buf = buf, .len = 3,
110 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
112 ret = i2c_transfer(state->i2c_adap, &msg, 1);
115 lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
116 msg.buf[0], msg.buf[1], msg.buf[2], ret);
125 static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val)
128 u8 reg_buf[] = { reg >> 8, reg & 0xff };
129 struct i2c_msg msg[] = {
130 { .addr = state->cfg->i2c_addr,
131 .flags = 0, .buf = reg_buf, .len = 2 },
132 { .addr = state->cfg->i2c_addr,
133 .flags = I2C_M_RD, .buf = val, .len = 1 },
136 lg_reg("reg: 0x%04x\n", reg);
138 ret = i2c_transfer(state->i2c_adap, msg, 2);
141 lg_err("error (addr %02x reg %04x error (ret == %i)\n",
142 state->cfg->i2c_addr, reg, ret);
151 #define read_reg(state, reg) \
154 int ret = lgdt3305_read_reg(state, reg, &__val); \
160 static int lgdt3305_set_reg_bit(struct lgdt3305_state *state,
161 u16 reg, int bit, int onoff)
166 lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
168 ret = lgdt3305_read_reg(state, reg, &val);
173 val |= (onoff & 1) << bit;
175 ret = lgdt3305_write_reg(state, reg, val);
180 struct lgdt3305_reg {
185 static int lgdt3305_write_regs(struct lgdt3305_state *state,
186 struct lgdt3305_reg *regs, int len)
190 lg_reg("writing %d registers...\n", len);
192 for (i = 0; i < len - 1; i++) {
193 ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val);
200 /* ------------------------------------------------------------------------ */
202 static int lgdt3305_soft_reset(struct lgdt3305_state *state)
208 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0);
213 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1);
218 static inline int lgdt3305_mpeg_mode(struct lgdt3305_state *state,
219 enum lgdt3305_mpeg_mode mode)
221 lg_dbg("(%d)\n", mode);
222 return lgdt3305_set_reg_bit(state, LGDT3305_TP_CTRL_1, 5, mode);
225 static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state)
229 enum lgdt3305_tp_clock_edge edge = state->cfg->tpclk_edge;
230 enum lgdt3305_tp_clock_mode mode = state->cfg->tpclk_mode;
231 enum lgdt3305_tp_valid_polarity valid = state->cfg->tpvalid_polarity;
233 lg_dbg("edge = %d, valid = %d\n", edge, valid);
235 ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val);
248 ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val);
252 ret = lgdt3305_soft_reset(state);
257 static int lgdt3305_set_modulation(struct lgdt3305_state *state,
258 struct dtv_frontend_properties *p)
265 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_1, &opermode);
271 switch (p->modulation) {
284 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode);
289 static int lgdt3305_set_filter_extension(struct lgdt3305_state *state,
290 struct dtv_frontend_properties *p)
294 switch (p->modulation) {
305 lg_dbg("val = %d\n", val);
307 return lgdt3305_set_reg_bit(state, 0x043f, 2, val);
310 /* ------------------------------------------------------------------------ */
312 static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state,
313 struct dtv_frontend_properties *p)
317 switch (p->modulation) {
331 lg_dbg("agc ref: 0x%04x\n", agc_ref);
333 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8);
334 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff);
339 static int lgdt3305_rfagc_loop(struct lgdt3305_state *state,
340 struct dtv_frontend_properties *p)
342 u16 ifbw, rfbw, agcdelay;
344 switch (p->modulation) {
354 /* FIXME: investigate optimal ifbw & rfbw values for the
355 * DT3304 and re-write this switch..case block */
356 if (state->cfg->demod_chip == LGDT3304)
358 else /* (state->cfg->demod_chip == LGDT3305) */
365 if (state->cfg->rf_agc_loop) {
366 lg_dbg("agcdelay: 0x%04x, rfbw: 0x%04x\n", agcdelay, rfbw);
368 /* rf agc loop filter bandwidth */
369 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1,
371 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2,
374 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1,
376 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2,
379 lg_dbg("ifbw: 0x%04x\n", ifbw);
381 /* if agc loop filter bandwidth */
382 lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8);
383 lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff);
389 static int lgdt3305_agc_setup(struct lgdt3305_state *state,
390 struct dtv_frontend_properties *p)
394 switch (p->modulation) {
408 lg_dbg("lockdten = %d, acqen = %d\n", lockdten, acqen);
410 /* control agc function */
411 switch (state->cfg->demod_chip) {
413 lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1);
414 lgdt3305_set_reg_bit(state, 0x030e, 2, acqen);
417 lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1);
418 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 2, acqen);
424 return lgdt3305_rfagc_loop(state, p);
427 static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state,
428 struct dtv_frontend_properties *p)
432 switch (p->modulation) {
434 if (state->cfg->usref_8vsb)
435 usref = state->cfg->usref_8vsb;
438 if (state->cfg->usref_qam64)
439 usref = state->cfg->usref_qam64;
442 if (state->cfg->usref_qam256)
443 usref = state->cfg->usref_qam256;
450 lg_dbg("set manual mode: 0x%04x\n", usref);
452 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 3, 1);
454 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1,
455 0xff & (usref >> 8));
456 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2,
457 0xff & (usref >> 0));
462 /* ------------------------------------------------------------------------ */
464 static int lgdt3305_spectral_inversion(struct lgdt3305_state *state,
465 struct dtv_frontend_properties *p,
470 lg_dbg("(%d)\n", inversion);
472 switch (p->modulation) {
474 ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7,
475 inversion ? 0xf9 : 0x79);
479 ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL,
480 inversion ? 0xfd : 0xff);
488 static int lgdt3305_set_if(struct lgdt3305_state *state,
489 struct dtv_frontend_properties *p)
492 u8 nco1, nco2, nco3, nco4;
495 switch (p->modulation) {
497 if_freq_khz = state->cfg->vsb_if_khz;
501 if_freq_khz = state->cfg->qam_if_khz;
507 nco = if_freq_khz / 10;
509 switch (p->modulation) {
523 nco1 = (nco >> 24) & 0x3f;
525 nco2 = (nco >> 16) & 0xff;
526 nco3 = (nco >> 8) & 0xff;
529 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1);
530 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2);
531 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3);
532 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4);
534 lg_dbg("%d KHz -> [%02x%02x%02x%02x]\n",
535 if_freq_khz, nco1, nco2, nco3, nco4);
540 /* ------------------------------------------------------------------------ */
542 static int lgdt3305_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
544 struct lgdt3305_state *state = fe->demodulator_priv;
546 if (state->cfg->deny_i2c_rptr)
549 lg_dbg("(%d)\n", enable);
551 return lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_2, 5,
555 static int lgdt3305_sleep(struct dvb_frontend *fe)
557 struct lgdt3305_state *state = fe->demodulator_priv;
558 u8 gen_ctrl_3, gen_ctrl_4;
562 gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3);
563 gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4);
565 /* hold in software reset while sleeping */
567 /* tristate the IF-AGC pin */
569 /* tristate the RF-AGC pin */
572 /* disable vsb/qam module */
574 /* disable adc module */
577 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3);
578 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4);
583 static int lgdt3305_init(struct dvb_frontend *fe)
585 struct lgdt3305_state *state = fe->demodulator_priv;
588 static struct lgdt3305_reg lgdt3304_init_data[] = {
589 { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, },
590 { .reg = 0x000d, .val = 0x02, },
591 { .reg = 0x000e, .val = 0x02, },
592 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, },
593 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, },
594 { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, },
595 { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, },
596 { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, },
597 { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, },
598 { .reg = LGDT3305_CR_CTRL_7, .val = 0xf9, },
599 { .reg = 0x0112, .val = 0x17, },
600 { .reg = 0x0113, .val = 0x15, },
601 { .reg = 0x0114, .val = 0x18, },
602 { .reg = 0x0115, .val = 0xff, },
603 { .reg = 0x0116, .val = 0x3c, },
604 { .reg = 0x0214, .val = 0x67, },
605 { .reg = 0x0424, .val = 0x8d, },
606 { .reg = 0x0427, .val = 0x12, },
607 { .reg = 0x0428, .val = 0x4f, },
608 { .reg = LGDT3305_IFBW_1, .val = 0x80, },
609 { .reg = LGDT3305_IFBW_2, .val = 0x00, },
610 { .reg = 0x030a, .val = 0x08, },
611 { .reg = 0x030b, .val = 0x9b, },
612 { .reg = 0x030d, .val = 0x00, },
613 { .reg = 0x030e, .val = 0x1c, },
614 { .reg = 0x0314, .val = 0xe1, },
615 { .reg = 0x000d, .val = 0x82, },
616 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, },
617 { .reg = LGDT3305_TP_CTRL_1, .val = 0x5b, },
620 static struct lgdt3305_reg lgdt3305_init_data[] = {
621 { .reg = LGDT3305_GEN_CTRL_1, .val = 0x03, },
622 { .reg = LGDT3305_GEN_CTRL_2, .val = 0xb0, },
623 { .reg = LGDT3305_GEN_CTRL_3, .val = 0x01, },
624 { .reg = LGDT3305_GEN_CONTROL, .val = 0x6f, },
625 { .reg = LGDT3305_GEN_CTRL_4, .val = 0x03, },
626 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, },
627 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, },
628 { .reg = LGDT3305_CR_CTR_FREQ_1, .val = 0x00, },
629 { .reg = LGDT3305_CR_CTR_FREQ_2, .val = 0x00, },
630 { .reg = LGDT3305_CR_CTR_FREQ_3, .val = 0x00, },
631 { .reg = LGDT3305_CR_CTR_FREQ_4, .val = 0x00, },
632 { .reg = LGDT3305_CR_CTRL_7, .val = 0x79, },
633 { .reg = LGDT3305_AGC_POWER_REF_1, .val = 0x32, },
634 { .reg = LGDT3305_AGC_POWER_REF_2, .val = 0xc4, },
635 { .reg = LGDT3305_AGC_DELAY_PT_1, .val = 0x0d, },
636 { .reg = LGDT3305_AGC_DELAY_PT_2, .val = 0x30, },
637 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1, .val = 0x80, },
638 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2, .val = 0x00, },
639 { .reg = LGDT3305_IFBW_1, .val = 0x80, },
640 { .reg = LGDT3305_IFBW_2, .val = 0x00, },
641 { .reg = LGDT3305_AGC_CTRL_1, .val = 0x30, },
642 { .reg = LGDT3305_AGC_CTRL_4, .val = 0x61, },
643 { .reg = LGDT3305_FEC_BLOCK_CTRL, .val = 0xff, },
644 { .reg = LGDT3305_TP_CTRL_1, .val = 0x1b, },
649 switch (state->cfg->demod_chip) {
651 ret = lgdt3305_write_regs(state, lgdt3304_init_data,
652 ARRAY_SIZE(lgdt3304_init_data));
655 ret = lgdt3305_write_regs(state, lgdt3305_init_data,
656 ARRAY_SIZE(lgdt3305_init_data));
664 ret = lgdt3305_soft_reset(state);
669 static int lgdt3304_set_parameters(struct dvb_frontend *fe)
671 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
672 struct lgdt3305_state *state = fe->demodulator_priv;
675 lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
677 if (fe->ops.tuner_ops.set_params) {
678 ret = fe->ops.tuner_ops.set_params(fe);
679 if (fe->ops.i2c_gate_ctrl)
680 fe->ops.i2c_gate_ctrl(fe, 0);
683 state->current_frequency = p->frequency;
686 ret = lgdt3305_set_modulation(state, p);
690 ret = lgdt3305_passband_digital_agc(state, p);
694 ret = lgdt3305_agc_setup(state, p);
698 /* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */
699 switch (p->modulation) {
701 lgdt3305_write_reg(state, 0x030d, 0x00);
702 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f);
703 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c);
704 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac);
705 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba);
709 lgdt3305_write_reg(state, 0x030d, 0x14);
710 ret = lgdt3305_set_if(state, p);
719 ret = lgdt3305_spectral_inversion(state, p,
720 state->cfg->spectral_inversion
725 state->current_modulation = p->modulation;
727 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
731 /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
732 ret = lgdt3305_mpeg_mode_polarity(state);
737 static int lgdt3305_set_parameters(struct dvb_frontend *fe)
739 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
740 struct lgdt3305_state *state = fe->demodulator_priv;
743 lg_dbg("(%d, %d)\n", p->frequency, p->modulation);
745 if (fe->ops.tuner_ops.set_params) {
746 ret = fe->ops.tuner_ops.set_params(fe);
747 if (fe->ops.i2c_gate_ctrl)
748 fe->ops.i2c_gate_ctrl(fe, 0);
751 state->current_frequency = p->frequency;
754 ret = lgdt3305_set_modulation(state, p);
758 ret = lgdt3305_passband_digital_agc(state, p);
761 ret = lgdt3305_set_agc_power_ref(state, p);
764 ret = lgdt3305_agc_setup(state, p);
769 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f);
772 ret = lgdt3305_set_reg_bit(state, LGDT3305_CR_CTR_FREQ_1, 6, 1);
776 ret = lgdt3305_set_if(state, p);
779 ret = lgdt3305_spectral_inversion(state, p,
780 state->cfg->spectral_inversion
785 ret = lgdt3305_set_filter_extension(state, p);
789 state->current_modulation = p->modulation;
791 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
795 /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
796 ret = lgdt3305_mpeg_mode_polarity(state);
801 static int lgdt3305_get_frontend(struct dvb_frontend *fe,
802 struct dtv_frontend_properties *p)
804 struct lgdt3305_state *state = fe->demodulator_priv;
808 p->modulation = state->current_modulation;
809 p->frequency = state->current_frequency;
813 /* ------------------------------------------------------------------------ */
815 static int lgdt3305_read_cr_lock_status(struct lgdt3305_state *state,
820 char *cr_lock_state = "";
824 ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val);
828 switch (state->current_modulation) {
834 switch (val & 0x07) {
836 cr_lock_state = "QAM UNLOCK";
839 cr_lock_state = "QAM 1stLock";
842 cr_lock_state = "QAM 2ndLock";
845 cr_lock_state = "QAM FinalLock";
848 cr_lock_state = "CLOCKQAM-INVALID!";
853 if (val & (1 << 7)) {
855 cr_lock_state = "CLOCKVSB";
861 lg_dbg("(%d) %s\n", *locked, cr_lock_state);
866 static int lgdt3305_read_fec_lock_status(struct lgdt3305_state *state,
870 int ret, mpeg_lock, fec_lock, viterbi_lock;
874 switch (state->current_modulation) {
877 ret = lgdt3305_read_reg(state,
878 LGDT3305_FEC_LOCK_STATUS, &val);
882 mpeg_lock = (val & (1 << 0)) ? 1 : 0;
883 fec_lock = (val & (1 << 2)) ? 1 : 0;
884 viterbi_lock = (val & (1 << 3)) ? 1 : 0;
886 *locked = mpeg_lock && fec_lock && viterbi_lock;
888 lg_dbg("(%d) %s%s%s\n", *locked,
889 mpeg_lock ? "mpeg lock " : "",
890 fec_lock ? "fec lock " : "",
891 viterbi_lock ? "viterbi lock" : "");
901 static int lgdt3305_read_status(struct dvb_frontend *fe, enum fe_status *status)
903 struct lgdt3305_state *state = fe->demodulator_priv;
905 int ret, signal, inlock, nofecerr, snrgood,
906 cr_lock, fec_lock, sync_lock;
910 ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val);
914 signal = (val & (1 << 4)) ? 1 : 0;
915 inlock = (val & (1 << 3)) ? 0 : 1;
916 sync_lock = (val & (1 << 2)) ? 1 : 0;
917 nofecerr = (val & (1 << 1)) ? 1 : 0;
918 snrgood = (val & (1 << 0)) ? 1 : 0;
920 lg_dbg("%s%s%s%s%s\n",
921 signal ? "SIGNALEXIST " : "",
922 inlock ? "INLOCK " : "",
923 sync_lock ? "SYNCLOCK " : "",
924 nofecerr ? "NOFECERR " : "",
925 snrgood ? "SNRGOOD " : "");
927 ret = lgdt3305_read_cr_lock_status(state, &cr_lock);
932 *status |= FE_HAS_SIGNAL;
934 *status |= FE_HAS_CARRIER;
936 *status |= FE_HAS_VITERBI;
938 *status |= FE_HAS_SYNC;
940 switch (state->current_modulation) {
943 /* signal bit is unreliable on the DT3304 in QAM mode */
944 if (((LGDT3304 == state->cfg->demod_chip)) && (cr_lock))
945 *status |= FE_HAS_SIGNAL;
947 ret = lgdt3305_read_fec_lock_status(state, &fec_lock);
952 *status |= FE_HAS_LOCK;
956 *status |= FE_HAS_LOCK;
965 /* ------------------------------------------------------------------------ */
967 /* borrowed from lgdt330x.c */
968 static u32 calculate_snr(u32 mse, u32 c)
970 if (mse == 0) /* no signal */
975 /* Negative SNR, which is possible, but realisticly the
976 demod will lose lock before the signal gets this bad. The
977 API only allows for unsigned values, so just return 0 */
983 static int lgdt3305_read_snr(struct dvb_frontend *fe, u16 *snr)
985 struct lgdt3305_state *state = fe->demodulator_priv;
986 u32 noise; /* noise value */
987 u32 c; /* per-modulation SNR calculation constant */
989 switch (state->current_modulation) {
992 /* Use Phase Tracker Mean-Square Error Register */
993 /* SNR for ranges from -13.11 to +44.08 */
994 noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) |
995 (read_reg(state, LGDT3305_PT_MSE_2) << 8) |
996 (read_reg(state, LGDT3305_PT_MSE_3) & 0xff);
997 c = 73957994; /* log10(25*32^2)*2^24 */
999 /* Use Equalizer Mean-Square Error Register */
1000 /* SNR for ranges from -16.12 to +44.08 */
1001 noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) |
1002 (read_reg(state, LGDT3305_EQ_MSE_2) << 8) |
1003 (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff);
1004 c = 73957994; /* log10(25*32^2)*2^24 */
1009 noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) |
1010 (read_reg(state, LGDT3305_CR_MSE_2) & 0xff);
1012 c = (state->current_modulation == QAM_64) ?
1013 97939837 : 98026066;
1014 /* log10(688128)*2^24 and log10(696320)*2^24 */
1019 state->snr = calculate_snr(noise, c);
1020 /* report SNR in dB * 10 */
1021 *snr = (state->snr / ((1 << 24) / 10));
1022 lg_dbg("noise = 0x%08x, snr = %d.%02d dB\n", noise,
1023 state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
1028 static int lgdt3305_read_signal_strength(struct dvb_frontend *fe,
1031 /* borrowed from lgdt330x.c
1033 * Calculate strength from SNR up to 35dB
1034 * Even though the SNR can go higher than 35dB,
1035 * there is some comfort factor in having a range of
1036 * strong signals that can show at 100%
1038 struct lgdt3305_state *state = fe->demodulator_priv;
1044 ret = fe->ops.read_snr(fe, &snr);
1047 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
1048 /* scale the range 0 - 35*2^24 into 0 - 65535 */
1049 if (state->snr >= 8960 * 0x10000)
1052 *strength = state->snr / 8960;
1057 /* ------------------------------------------------------------------------ */
1059 static int lgdt3305_read_ber(struct dvb_frontend *fe, u32 *ber)
1065 static int lgdt3305_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1067 struct lgdt3305_state *state = fe->demodulator_priv;
1070 (read_reg(state, LGDT3305_FEC_PKT_ERR_1) << 8) |
1071 (read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff);
1076 static int lgdt3305_get_tune_settings(struct dvb_frontend *fe,
1077 struct dvb_frontend_tune_settings
1080 fe_tune_settings->min_delay_ms = 500;
1085 static void lgdt3305_release(struct dvb_frontend *fe)
1087 struct lgdt3305_state *state = fe->demodulator_priv;
1092 static const struct dvb_frontend_ops lgdt3304_ops;
1093 static const struct dvb_frontend_ops lgdt3305_ops;
1095 struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config,
1096 struct i2c_adapter *i2c_adap)
1098 struct lgdt3305_state *state = NULL;
1102 lg_dbg("(%d-%04x)\n",
1103 i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1104 config ? config->i2c_addr : 0);
1106 state = kzalloc(sizeof(struct lgdt3305_state), GFP_KERNEL);
1110 state->cfg = config;
1111 state->i2c_adap = i2c_adap;
1113 switch (config->demod_chip) {
1115 memcpy(&state->frontend.ops, &lgdt3304_ops,
1116 sizeof(struct dvb_frontend_ops));
1119 memcpy(&state->frontend.ops, &lgdt3305_ops,
1120 sizeof(struct dvb_frontend_ops));
1125 state->frontend.demodulator_priv = state;
1127 /* verify that we're talking to a lg dt3304/5 */
1128 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val);
1129 if ((lg_fail(ret)) | (val == 0))
1131 ret = lgdt3305_write_reg(state, 0x0808, 0x80);
1134 ret = lgdt3305_read_reg(state, 0x0808, &val);
1135 if ((lg_fail(ret)) | (val != 0x80))
1137 ret = lgdt3305_write_reg(state, 0x0808, 0x00);
1141 state->current_frequency = -1;
1142 state->current_modulation = -1;
1144 return &state->frontend;
1146 lg_warn("unable to detect %s hardware\n",
1147 config->demod_chip ? "LGDT3304" : "LGDT3305");
1151 EXPORT_SYMBOL_GPL(lgdt3305_attach);
1153 static const struct dvb_frontend_ops lgdt3304_ops = {
1154 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1156 .name = "LG Electronics LGDT3304 VSB/QAM Frontend",
1157 .frequency_min_hz = 54 * MHz,
1158 .frequency_max_hz = 858 * MHz,
1159 .frequency_stepsize_hz = 62500,
1160 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1162 .i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl,
1163 .init = lgdt3305_init,
1164 .sleep = lgdt3305_sleep,
1165 .set_frontend = lgdt3304_set_parameters,
1166 .get_frontend = lgdt3305_get_frontend,
1167 .get_tune_settings = lgdt3305_get_tune_settings,
1168 .read_status = lgdt3305_read_status,
1169 .read_ber = lgdt3305_read_ber,
1170 .read_signal_strength = lgdt3305_read_signal_strength,
1171 .read_snr = lgdt3305_read_snr,
1172 .read_ucblocks = lgdt3305_read_ucblocks,
1173 .release = lgdt3305_release,
1176 static const struct dvb_frontend_ops lgdt3305_ops = {
1177 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
1179 .name = "LG Electronics LGDT3305 VSB/QAM Frontend",
1180 .frequency_min_hz = 54 * MHz,
1181 .frequency_max_hz = 858 * MHz,
1182 .frequency_stepsize_hz = 62500,
1183 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1185 .i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl,
1186 .init = lgdt3305_init,
1187 .sleep = lgdt3305_sleep,
1188 .set_frontend = lgdt3305_set_parameters,
1189 .get_frontend = lgdt3305_get_frontend,
1190 .get_tune_settings = lgdt3305_get_tune_settings,
1191 .read_status = lgdt3305_read_status,
1192 .read_ber = lgdt3305_read_ber,
1193 .read_signal_strength = lgdt3305_read_signal_strength,
1194 .read_snr = lgdt3305_read_snr,
1195 .read_ucblocks = lgdt3305_read_ucblocks,
1196 .release = lgdt3305_release,
1199 MODULE_DESCRIPTION("LG Electronics LGDT3304/5 ATSC/QAM-B Demodulator Driver");
1200 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
1201 MODULE_LICENSE("GPL");
1202 MODULE_VERSION("0.2");