2 Montage Technology DS3000 - DVBS/S2 Demodulator driver
3 Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
5 Copyright (C) 2009-2012 TurboSight.com
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/slab.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/firmware.h>
29 #include <media/dvb_frontend.h>
35 #define dprintk(args...) \
43 #define DS3000_SAMPLE_RATE 96000 /* in kHz */
45 /* Register values to initialise the demod in DVB-S mode */
46 static u8 ds3000_dvbs_init_tab[] = {
130 /* Register values to initialise the demod in DVB-S2 mode */
131 static u8 ds3000_dvbs2_init_tab[] = {
230 struct ds3000_state {
231 struct i2c_adapter *i2c;
232 const struct ds3000_config *config;
233 struct dvb_frontend frontend;
234 /* previous uncorrected block counter for DVB-S2 */
238 static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
240 u8 buf[] = { reg, data };
241 struct i2c_msg msg = { .addr = state->config->demod_address,
242 .flags = 0, .buf = buf, .len = 2 };
245 dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
247 err = i2c_transfer(state->i2c, &msg, 1);
249 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
250 __func__, err, reg, data);
257 static int ds3000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
259 struct ds3000_state *state = fe->demodulator_priv;
262 ds3000_writereg(state, 0x03, 0x12);
264 ds3000_writereg(state, 0x03, 0x02);
269 /* I2C write for 8k firmware load */
270 static int ds3000_writeFW(struct ds3000_state *state, int reg,
271 const u8 *data, u16 len)
277 buf = kmalloc(33, GFP_KERNEL);
283 msg.addr = state->config->demod_address;
288 for (i = 0; i < len; i += 32) {
289 memcpy(buf + 1, data + i, 32);
291 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
293 ret = i2c_transfer(state->i2c, &msg, 1);
295 printk(KERN_ERR "%s: write error(err == %i, reg == 0x%02x\n",
309 static int ds3000_readreg(struct ds3000_state *state, u8 reg)
314 struct i2c_msg msg[] = {
316 .addr = state->config->demod_address,
321 .addr = state->config->demod_address,
328 ret = i2c_transfer(state->i2c, msg, 2);
331 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
335 dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
340 static int ds3000_load_firmware(struct dvb_frontend *fe,
341 const struct firmware *fw);
343 static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
345 struct ds3000_state *state = fe->demodulator_priv;
346 const struct firmware *fw;
349 dprintk("%s()\n", __func__);
351 ret = ds3000_readreg(state, 0xb2);
356 /* request the firmware, this will block until someone uploads it */
357 printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
359 ret = reject_firmware(&fw, "/*(DEBLOBBED)*/",
360 state->i2c->dev.parent);
361 printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
363 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not found?)\n",
368 ret = ds3000_load_firmware(fe, fw);
370 printk("%s: Writing firmware to device failed\n", __func__);
372 release_firmware(fw);
374 dprintk("%s: Firmware upload %s\n", __func__,
375 ret == 0 ? "complete" : "failed");
380 static int ds3000_load_firmware(struct dvb_frontend *fe,
381 const struct firmware *fw)
383 struct ds3000_state *state = fe->demodulator_priv;
386 dprintk("%s\n", __func__);
387 dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
391 fw->data[fw->size - 2],
392 fw->data[fw->size - 1]);
394 /* Begin the firmware load process */
395 ds3000_writereg(state, 0xb2, 0x01);
396 /* write the entire firmware */
397 ret = ds3000_writeFW(state, 0xb0, fw->data, fw->size);
398 ds3000_writereg(state, 0xb2, 0x00);
403 static int ds3000_set_voltage(struct dvb_frontend *fe,
404 enum fe_sec_voltage voltage)
406 struct ds3000_state *state = fe->demodulator_priv;
409 dprintk("%s(%d)\n", __func__, voltage);
411 data = ds3000_readreg(state, 0xa2);
412 data |= 0x03; /* bit0 V/H, bit1 off/on */
422 case SEC_VOLTAGE_OFF:
426 ds3000_writereg(state, 0xa2, data);
431 static int ds3000_read_status(struct dvb_frontend *fe, enum fe_status *status)
433 struct ds3000_state *state = fe->demodulator_priv;
434 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
439 switch (c->delivery_system) {
441 lock = ds3000_readreg(state, 0xd1);
442 if ((lock & 0x07) == 0x07)
443 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
444 FE_HAS_VITERBI | FE_HAS_SYNC |
449 lock = ds3000_readreg(state, 0x0d);
450 if ((lock & 0x8f) == 0x8f)
451 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
452 FE_HAS_VITERBI | FE_HAS_SYNC |
460 if (state->config->set_lock_led)
461 state->config->set_lock_led(fe, *status == 0 ? 0 : 1);
463 dprintk("%s: status = 0x%02x\n", __func__, lock);
468 /* read DS3000 BER value */
469 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
471 struct ds3000_state *state = fe->demodulator_priv;
472 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
474 u32 ber_reading, lpdc_frames;
476 dprintk("%s()\n", __func__);
478 switch (c->delivery_system) {
480 /* set the number of bytes checked during
482 ds3000_writereg(state, 0xf9, 0x04);
483 /* read BER estimation status */
484 data = ds3000_readreg(state, 0xf8);
485 /* check if BER estimation is ready */
486 if ((data & 0x10) == 0) {
487 /* this is the number of error bits,
488 to calculate the bit error rate
490 *ber = (ds3000_readreg(state, 0xf7) << 8) |
491 ds3000_readreg(state, 0xf6);
492 /* start counting error bits */
493 /* need to be set twice
494 otherwise it fails sometimes */
496 ds3000_writereg(state, 0xf8, data);
497 ds3000_writereg(state, 0xf8, data);
499 /* used to indicate that BER estimation
500 is not ready, i.e. BER is unknown */
504 /* read the number of LPDC decoded frames */
505 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
506 (ds3000_readreg(state, 0xd6) << 8) |
507 ds3000_readreg(state, 0xd5);
508 /* read the number of packets with bad CRC */
509 ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
510 ds3000_readreg(state, 0xf7);
511 if (lpdc_frames > 750) {
512 /* clear LPDC frame counters */
513 ds3000_writereg(state, 0xd1, 0x01);
514 /* clear bad packets counter */
515 ds3000_writereg(state, 0xf9, 0x01);
516 /* enable bad packets counter */
517 ds3000_writereg(state, 0xf9, 0x00);
518 /* enable LPDC frame counters */
519 ds3000_writereg(state, 0xd1, 0x00);
522 /* used to indicate that BER estimation is not ready,
523 i.e. BER is unknown */
533 static int ds3000_read_signal_strength(struct dvb_frontend *fe,
534 u16 *signal_strength)
536 if (fe->ops.tuner_ops.get_rf_strength)
537 fe->ops.tuner_ops.get_rf_strength(fe, signal_strength);
542 /* calculate DS3000 snr value in dB */
543 static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
545 struct ds3000_state *state = fe->demodulator_priv;
546 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
547 u8 snr_reading, snr_value;
548 u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
549 static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
550 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
551 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
552 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
554 static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
555 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
556 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
557 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
558 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
559 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
560 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
561 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
562 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
563 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
564 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
565 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
566 0x49e9, 0x4a20, 0x4a57
569 dprintk("%s()\n", __func__);
571 switch (c->delivery_system) {
573 snr_reading = ds3000_readreg(state, 0xff);
575 if (snr_reading == 0)
578 if (snr_reading > 20)
580 snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
581 /* cook the value to be suitable for szap-s2
582 human readable output */
583 *snr = snr_value * 8 * 655;
585 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
589 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
590 (ds3000_readreg(state, 0x8d) << 4);
591 dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
592 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
597 if (dvbs2_noise_reading == 0) {
599 /* cook the value to be suitable for szap-s2
600 human readable output */
604 if (tmp > dvbs2_noise_reading) {
605 snr_reading = tmp / dvbs2_noise_reading;
606 if (snr_reading > 80)
608 snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
609 /* cook the value to be suitable for szap-s2
610 human readable output */
611 *snr = snr_value * 5 * 655;
613 snr_reading = dvbs2_noise_reading / tmp;
614 if (snr_reading > 80)
616 *snr = -(dvbs2_snr_tab[snr_reading - 1] / 1000);
618 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
628 /* read DS3000 uncorrected blocks */
629 static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
631 struct ds3000_state *state = fe->demodulator_priv;
632 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
636 dprintk("%s()\n", __func__);
638 switch (c->delivery_system) {
640 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
641 ds3000_readreg(state, 0xf4);
642 data = ds3000_readreg(state, 0xf8);
643 /* clear packet counters */
645 ds3000_writereg(state, 0xf8, data);
646 /* enable packet counters */
648 ds3000_writereg(state, 0xf8, data);
651 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
652 ds3000_readreg(state, 0xe1);
653 if (_ucblocks > state->prevUCBS2)
654 *ucblocks = _ucblocks - state->prevUCBS2;
656 *ucblocks = state->prevUCBS2 - _ucblocks;
657 state->prevUCBS2 = _ucblocks;
666 static int ds3000_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
668 struct ds3000_state *state = fe->demodulator_priv;
671 dprintk("%s(%d)\n", __func__, tone);
672 if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
673 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
677 data = ds3000_readreg(state, 0xa2);
679 ds3000_writereg(state, 0xa2, data);
683 dprintk("%s: setting tone on\n", __func__);
684 data = ds3000_readreg(state, 0xa1);
687 ds3000_writereg(state, 0xa1, data);
690 dprintk("%s: setting tone off\n", __func__);
691 data = ds3000_readreg(state, 0xa2);
693 ds3000_writereg(state, 0xa2, data);
700 static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
701 struct dvb_diseqc_master_cmd *d)
703 struct ds3000_state *state = fe->demodulator_priv;
707 /* Dump DiSEqC message */
708 dprintk("%s(", __func__);
709 for (i = 0 ; i < d->msg_len;) {
710 dprintk("0x%02x", d->msg[i]);
711 if (++i < d->msg_len)
715 /* enable DiSEqC message send pin */
716 data = ds3000_readreg(state, 0xa2);
718 ds3000_writereg(state, 0xa2, data);
721 for (i = 0; i < d->msg_len; i++)
722 ds3000_writereg(state, 0xa3 + i, d->msg[i]);
724 data = ds3000_readreg(state, 0xa1);
725 /* clear DiSEqC message length and status,
726 enable DiSEqC message send */
728 /* set DiSEqC mode, modulation active during 33 pulses,
729 set DiSEqC message length */
730 data |= ((d->msg_len - 1) << 3) | 0x07;
731 ds3000_writereg(state, 0xa1, data);
733 /* wait up to 150ms for DiSEqC transmission to complete */
734 for (i = 0; i < 15; i++) {
735 data = ds3000_readreg(state, 0xa1);
736 if ((data & 0x40) == 0)
741 /* DiSEqC timeout after 150ms */
743 data = ds3000_readreg(state, 0xa1);
746 ds3000_writereg(state, 0xa1, data);
748 data = ds3000_readreg(state, 0xa2);
751 ds3000_writereg(state, 0xa2, data);
756 data = ds3000_readreg(state, 0xa2);
759 ds3000_writereg(state, 0xa2, data);
764 /* Send DiSEqC burst */
765 static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
766 enum fe_sec_mini_cmd burst)
768 struct ds3000_state *state = fe->demodulator_priv;
772 dprintk("%s()\n", __func__);
774 data = ds3000_readreg(state, 0xa2);
776 ds3000_writereg(state, 0xa2, data);
779 if (burst == SEC_MINI_A)
780 /* Unmodulated tone burst */
781 ds3000_writereg(state, 0xa1, 0x02);
782 else if (burst == SEC_MINI_B)
783 /* Modulated tone burst */
784 ds3000_writereg(state, 0xa1, 0x01);
789 for (i = 0; i < 5; i++) {
790 data = ds3000_readreg(state, 0xa1);
791 if ((data & 0x40) == 0)
797 data = ds3000_readreg(state, 0xa1);
800 ds3000_writereg(state, 0xa1, data);
802 data = ds3000_readreg(state, 0xa2);
805 ds3000_writereg(state, 0xa2, data);
810 data = ds3000_readreg(state, 0xa2);
813 ds3000_writereg(state, 0xa2, data);
818 static void ds3000_release(struct dvb_frontend *fe)
820 struct ds3000_state *state = fe->demodulator_priv;
822 if (state->config->set_lock_led)
823 state->config->set_lock_led(fe, 0);
825 dprintk("%s\n", __func__);
829 static const struct dvb_frontend_ops ds3000_ops;
831 struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
832 struct i2c_adapter *i2c)
834 struct ds3000_state *state;
837 dprintk("%s\n", __func__);
839 /* allocate memory for the internal state */
840 state = kzalloc(sizeof(*state), GFP_KERNEL);
844 state->config = config;
846 state->prevUCBS2 = 0;
848 /* check if the demod is present */
849 ret = ds3000_readreg(state, 0x00) & 0xfe;
852 printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
856 printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
857 ds3000_readreg(state, 0x02),
858 ds3000_readreg(state, 0x01));
860 memcpy(&state->frontend.ops, &ds3000_ops,
861 sizeof(struct dvb_frontend_ops));
862 state->frontend.demodulator_priv = state;
865 * Some devices like T480 starts with voltage on. Be sure
866 * to turn voltage off during init, as this can otherwise
867 * interfere with Unicable SCR systems.
869 ds3000_set_voltage(&state->frontend, SEC_VOLTAGE_OFF);
870 return &state->frontend;
872 EXPORT_SYMBOL(ds3000_attach);
874 static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
875 s32 carrier_offset_khz)
877 struct ds3000_state *state = fe->demodulator_priv;
880 tmp = carrier_offset_khz;
882 tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
887 ds3000_writereg(state, 0x5f, tmp >> 8);
888 ds3000_writereg(state, 0x5e, tmp & 0xff);
893 static int ds3000_set_frontend(struct dvb_frontend *fe)
895 struct ds3000_state *state = fe->demodulator_priv;
896 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
899 enum fe_status status;
904 dprintk("%s() ", __func__);
906 if (state->config->set_ts_params)
907 state->config->set_ts_params(fe, 0);
909 if (fe->ops.tuner_ops.set_params)
910 fe->ops.tuner_ops.set_params(fe);
912 /* ds3000 global reset */
913 ds3000_writereg(state, 0x07, 0x80);
914 ds3000_writereg(state, 0x07, 0x00);
915 /* ds3000 build-in uC reset */
916 ds3000_writereg(state, 0xb2, 0x01);
917 /* ds3000 software reset */
918 ds3000_writereg(state, 0x00, 0x01);
920 switch (c->delivery_system) {
922 /* initialise the demod in DVB-S mode */
923 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
924 ds3000_writereg(state,
925 ds3000_dvbs_init_tab[i],
926 ds3000_dvbs_init_tab[i + 1]);
927 value = ds3000_readreg(state, 0xfe);
930 ds3000_writereg(state, 0xfe, value);
933 /* initialise the demod in DVB-S2 mode */
934 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
935 ds3000_writereg(state,
936 ds3000_dvbs2_init_tab[i],
937 ds3000_dvbs2_init_tab[i + 1]);
938 if (c->symbol_rate >= 30000000)
939 ds3000_writereg(state, 0xfe, 0x54);
941 ds3000_writereg(state, 0xfe, 0x98);
947 /* enable 27MHz clock output */
948 ds3000_writereg(state, 0x29, 0x80);
949 /* enable ac coupling */
950 ds3000_writereg(state, 0x25, 0x8a);
952 if ((c->symbol_rate < ds3000_ops.info.symbol_rate_min) ||
953 (c->symbol_rate > ds3000_ops.info.symbol_rate_max)) {
954 dprintk("%s() symbol_rate %u out of range (%u ... %u)\n",
955 __func__, c->symbol_rate,
956 ds3000_ops.info.symbol_rate_min,
957 ds3000_ops.info.symbol_rate_max);
961 /* enhance symbol rate performance */
962 if ((c->symbol_rate / 1000) <= 5000) {
963 value = 29777 / (c->symbol_rate / 1000) + 1;
966 ds3000_writereg(state, 0xc3, 0x0d);
967 ds3000_writereg(state, 0xc8, value);
968 ds3000_writereg(state, 0xc4, 0x10);
969 ds3000_writereg(state, 0xc7, 0x0e);
970 } else if ((c->symbol_rate / 1000) <= 10000) {
971 value = 92166 / (c->symbol_rate / 1000) + 1;
974 ds3000_writereg(state, 0xc3, 0x07);
975 ds3000_writereg(state, 0xc8, value);
976 ds3000_writereg(state, 0xc4, 0x09);
977 ds3000_writereg(state, 0xc7, 0x12);
978 } else if ((c->symbol_rate / 1000) <= 20000) {
979 value = 64516 / (c->symbol_rate / 1000) + 1;
980 ds3000_writereg(state, 0xc3, value);
981 ds3000_writereg(state, 0xc8, 0x0e);
982 ds3000_writereg(state, 0xc4, 0x07);
983 ds3000_writereg(state, 0xc7, 0x18);
985 value = 129032 / (c->symbol_rate / 1000) + 1;
986 ds3000_writereg(state, 0xc3, value);
987 ds3000_writereg(state, 0xc8, 0x0a);
988 ds3000_writereg(state, 0xc4, 0x05);
989 ds3000_writereg(state, 0xc7, 0x24);
992 /* normalized symbol rate rounded to the closest integer */
993 value = (((c->symbol_rate / 1000) << 16) +
994 (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
995 ds3000_writereg(state, 0x61, value & 0x00ff);
996 ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
998 /* co-channel interference cancellation disabled */
999 ds3000_writereg(state, 0x56, 0x00);
1001 /* equalizer disabled */
1002 ds3000_writereg(state, 0x76, 0x00);
1004 /*ds3000_writereg(state, 0x08, 0x03);
1005 ds3000_writereg(state, 0xfd, 0x22);
1006 ds3000_writereg(state, 0x08, 0x07);
1007 ds3000_writereg(state, 0xfd, 0x42);
1008 ds3000_writereg(state, 0x08, 0x07);*/
1010 if (state->config->ci_mode) {
1011 switch (c->delivery_system) {
1014 ds3000_writereg(state, 0xfd, 0x80);
1017 ds3000_writereg(state, 0xfd, 0x01);
1022 /* ds3000 out of software reset */
1023 ds3000_writereg(state, 0x00, 0x00);
1024 /* start ds3000 build-in uC */
1025 ds3000_writereg(state, 0xb2, 0x00);
1027 if (fe->ops.tuner_ops.get_frequency) {
1028 fe->ops.tuner_ops.get_frequency(fe, &frequency);
1029 offset_khz = frequency - c->frequency;
1030 ds3000_set_carrier_offset(fe, offset_khz);
1033 for (i = 0; i < 30 ; i++) {
1034 ds3000_read_status(fe, &status);
1035 if (status & FE_HAS_LOCK)
1044 static int ds3000_tune(struct dvb_frontend *fe,
1046 unsigned int mode_flags,
1047 unsigned int *delay,
1048 enum fe_status *status)
1051 int ret = ds3000_set_frontend(fe);
1058 return ds3000_read_status(fe, status);
1061 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1063 struct ds3000_state *state = fe->demodulator_priv;
1065 if (state->config->set_lock_led)
1066 state->config->set_lock_led(fe, 0);
1068 dprintk("%s()\n", __func__);
1069 return DVBFE_ALGO_HW;
1073 * Initialise or wake up device
1075 * Power config will reset and load initial firmware if required
1077 static int ds3000_initfe(struct dvb_frontend *fe)
1079 struct ds3000_state *state = fe->demodulator_priv;
1082 dprintk("%s()\n", __func__);
1084 ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
1087 /* Load the firmware if required */
1088 ret = ds3000_firmware_ondemand(fe);
1090 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
1097 static const struct dvb_frontend_ops ds3000_ops = {
1098 .delsys = { SYS_DVBS, SYS_DVBS2 },
1100 .name = "Montage Technology DS3000",
1101 .frequency_min_hz = 950 * MHz,
1102 .frequency_max_hz = 2150 * MHz,
1103 .frequency_stepsize_hz = 1011 * kHz,
1104 .frequency_tolerance_hz = 5 * MHz,
1105 .symbol_rate_min = 1000000,
1106 .symbol_rate_max = 45000000,
1107 .caps = FE_CAN_INVERSION_AUTO |
1108 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1109 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1110 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1111 FE_CAN_2G_MODULATION |
1112 FE_CAN_QPSK | FE_CAN_RECOVER
1115 .release = ds3000_release,
1117 .init = ds3000_initfe,
1118 .i2c_gate_ctrl = ds3000_i2c_gate_ctrl,
1119 .read_status = ds3000_read_status,
1120 .read_ber = ds3000_read_ber,
1121 .read_signal_strength = ds3000_read_signal_strength,
1122 .read_snr = ds3000_read_snr,
1123 .read_ucblocks = ds3000_read_ucblocks,
1124 .set_voltage = ds3000_set_voltage,
1125 .set_tone = ds3000_set_tone,
1126 .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
1127 .diseqc_send_burst = ds3000_diseqc_send_burst,
1128 .get_frontend_algo = ds3000_get_algo,
1130 .set_frontend = ds3000_set_frontend,
1131 .tune = ds3000_tune,
1134 module_param(debug, int, 0644);
1135 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1137 MODULE_DESCRIPTION("DVB Frontend module for Montage Technology DS3000 hardware");
1138 MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
1139 MODULE_LICENSE("GPL");