drivers/media/dvb-frontends/ds3000.c

   1 /*
   2     Montage Technology DS3000 - DVBS/S2 Demodulator driver
   3     Copyright (C) 2009-2012 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
   4
   5     Copyright (C) 2009-2012 TurboSight.com
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11
  12     This program is distributed in the hope that it will be useful,
  13     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/slab.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/firmware.h>
  28
  29 #include "dvb_frontend.h"
  30 #include "ts2020.h"
  31 #include "ds3000.h"
  32
  33 static int debug;
  34
  35 #define dprintk(args...) \
  36         do { \
  37                 if (debug) \
  38                         printk(args); \
  39         } while (0)
  40
  41 /*(DEBLOBBED)*/
  42
  43 #define DS3000_SAMPLE_RATE 96000 /* in kHz */
  44
  45 /* Register values to initialise the demod in DVB-S mode */
  46 static u8 ds3000_dvbs_init_tab[] = {
  47         0x23, 0x05,
  48         0x08, 0x03,
  49         0x0c, 0x00,
  50         0x21, 0x54,
  51         0x25, 0x82,
  52         0x27, 0x31,
  53         0x30, 0x08,
  54         0x31, 0x40,
  55         0x32, 0x32,
  56         0x33, 0x35,
  57         0x35, 0xff,
  58         0x3a, 0x00,
  59         0x37, 0x10,
  60         0x38, 0x10,
  61         0x39, 0x02,
  62         0x42, 0x60,
  63         0x4a, 0x40,
  64         0x4b, 0x04,
  65         0x4d, 0x91,
  66         0x5d, 0xc8,
  67         0x50, 0x77,
  68         0x51, 0x77,
  69         0x52, 0x36,
  70         0x53, 0x36,
  71         0x56, 0x01,
  72         0x63, 0x43,
  73         0x64, 0x30,
  74         0x65, 0x40,
  75         0x68, 0x26,
  76         0x69, 0x4c,
  77         0x70, 0x20,
  78         0x71, 0x70,
  79         0x72, 0x04,
  80         0x73, 0x00,
  81         0x70, 0x40,
  82         0x71, 0x70,
  83         0x72, 0x04,
  84         0x73, 0x00,
  85         0x70, 0x60,
  86         0x71, 0x70,
  87         0x72, 0x04,
  88         0x73, 0x00,
  89         0x70, 0x80,
  90         0x71, 0x70,
  91         0x72, 0x04,
  92         0x73, 0x00,
  93         0x70, 0xa0,
  94         0x71, 0x70,
  95         0x72, 0x04,
  96         0x73, 0x00,
  97         0x70, 0x1f,
  98         0x76, 0x00,
  99         0x77, 0xd1,
 100         0x78, 0x0c,
 101         0x79, 0x80,
 102         0x7f, 0x04,
 103         0x7c, 0x00,
 104         0x80, 0x86,
 105         0x81, 0xa6,
 106         0x85, 0x04,
 107         0xcd, 0xf4,
 108         0x90, 0x33,
 109         0xa0, 0x44,
 110         0xc0, 0x18,
 111         0xc3, 0x10,
 112         0xc4, 0x08,
 113         0xc5, 0x80,
 114         0xc6, 0x80,
 115         0xc7, 0x0a,
 116         0xc8, 0x1a,
 117         0xc9, 0x80,
 118         0xfe, 0x92,
 119         0xe0, 0xf8,
 120         0xe6, 0x8b,
 121         0xd0, 0x40,
 122         0xf8, 0x20,
 123         0xfa, 0x0f,
 124         0xfd, 0x20,
 125         0xad, 0x20,
 126         0xae, 0x07,
 127         0xb8, 0x00,
 128 };
 129
 130 /* Register values to initialise the demod in DVB-S2 mode */
 131 static u8 ds3000_dvbs2_init_tab[] = {
 132         0x23, 0x0f,
 133         0x08, 0x07,
 134         0x0c, 0x00,
 135         0x21, 0x54,
 136         0x25, 0x82,
 137         0x27, 0x31,
 138         0x30, 0x08,
 139         0x31, 0x32,
 140         0x32, 0x32,
 141         0x33, 0x35,
 142         0x35, 0xff,
 143         0x3a, 0x00,
 144         0x37, 0x10,
 145         0x38, 0x10,
 146         0x39, 0x02,
 147         0x42, 0x60,
 148         0x4a, 0x80,
 149         0x4b, 0x04,
 150         0x4d, 0x81,
 151         0x5d, 0x88,
 152         0x50, 0x36,
 153         0x51, 0x36,
 154         0x52, 0x36,
 155         0x53, 0x36,
 156         0x63, 0x60,
 157         0x64, 0x10,
 158         0x65, 0x10,
 159         0x68, 0x04,
 160         0x69, 0x29,
 161         0x70, 0x20,
 162         0x71, 0x70,
 163         0x72, 0x04,
 164         0x73, 0x00,
 165         0x70, 0x40,
 166         0x71, 0x70,
 167         0x72, 0x04,
 168         0x73, 0x00,
 169         0x70, 0x60,
 170         0x71, 0x70,
 171         0x72, 0x04,
 172         0x73, 0x00,
 173         0x70, 0x80,
 174         0x71, 0x70,
 175         0x72, 0x04,
 176         0x73, 0x00,
 177         0x70, 0xa0,
 178         0x71, 0x70,
 179         0x72, 0x04,
 180         0x73, 0x00,
 181         0x70, 0x1f,
 182         0xa0, 0x44,
 183         0xc0, 0x08,
 184         0xc1, 0x10,
 185         0xc2, 0x08,
 186         0xc3, 0x10,
 187         0xc4, 0x08,
 188         0xc5, 0xf0,
 189         0xc6, 0xf0,
 190         0xc7, 0x0a,
 191         0xc8, 0x1a,
 192         0xc9, 0x80,
 193         0xca, 0x23,
 194         0xcb, 0x24,
 195         0xce, 0x74,
 196         0x90, 0x03,
 197         0x76, 0x80,
 198         0x77, 0x42,
 199         0x78, 0x0a,
 200         0x79, 0x80,
 201         0xad, 0x40,
 202         0xae, 0x07,
 203         0x7f, 0xd4,
 204         0x7c, 0x00,
 205         0x80, 0xa8,
 206         0x81, 0xda,
 207         0x7c, 0x01,
 208         0x80, 0xda,
 209         0x81, 0xec,
 210         0x7c, 0x02,
 211         0x80, 0xca,
 212         0x81, 0xeb,
 213         0x7c, 0x03,
 214         0x80, 0xba,
 215         0x81, 0xdb,
 216         0x85, 0x08,
 217         0x86, 0x00,
 218         0x87, 0x02,
 219         0x89, 0x80,
 220         0x8b, 0x44,
 221         0x8c, 0xaa,
 222         0x8a, 0x10,
 223         0xba, 0x00,
 224         0xf5, 0x04,
 225         0xfe, 0x44,
 226         0xd2, 0x32,
 227         0xb8, 0x00,
 228 };
 229
 230 struct ds3000_state {
 231         struct i2c_adapter *i2c;
 232         const struct ds3000_config *config;
 233         struct dvb_frontend frontend;
 234         /* previous uncorrected block counter for DVB-S2 */
 235         u16 prevUCBS2;
 236 };
 237
 238 static int ds3000_writereg(struct ds3000_state *state, int reg, int data)
 239 {
 240         u8 buf[] = { reg, data };
 241         struct i2c_msg msg = { .addr = state->config->demod_address,
 242                 .flags = 0, .buf = buf, .len = 2 };
 243         int err;
 244
 245         dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data);
 246
 247         err = i2c_transfer(state->i2c, &msg, 1);
 248         if (err != 1) {
 249                 printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x, value == 0x%02x)\n",
 250                        __func__, err, reg, data);
 251                 return -EREMOTEIO;
 252         }
 253
 254         return 0;
 255 }
 256
 257 static int ds3000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 258 {
 259         struct ds3000_state *state = fe->demodulator_priv;
 260
 261         if (enable)
 262                 ds3000_writereg(state, 0x03, 0x12);
 263         else
 264                 ds3000_writereg(state, 0x03, 0x02);
 265
 266         return 0;
 267 }
 268
 269 /* I2C write for 8k firmware load */
 270 static int ds3000_writeFW(struct ds3000_state *state, int reg,
 271                                 const u8 *data, u16 len)
 272 {
 273         int i, ret = 0;
 274         struct i2c_msg msg;
 275         u8 *buf;
 276
 277         buf = kmalloc(33, GFP_KERNEL);
 278         if (buf == NULL) {
 279                 printk(KERN_ERR "Unable to kmalloc\n");
 280                 return -ENOMEM;
 281         }
 282
 283         *(buf) = reg;
 284
 285         msg.addr = state->config->demod_address;
 286         msg.flags = 0;
 287         msg.buf = buf;
 288         msg.len = 33;
 289
 290         for (i = 0; i < len; i += 32) {
 291                 memcpy(buf + 1, data + i, 32);
 292
 293                 dprintk("%s: write reg 0x%02x, len = %d\n", __func__, reg, len);
 294
 295                 ret = i2c_transfer(state->i2c, &msg, 1);
 296                 if (ret != 1) {
 297                         printk(KERN_ERR "%s: write error(err == %i, reg == 0x%02x\n",
 298                                __func__, ret, reg);
 299                         ret = -EREMOTEIO;
 300                         goto error;
 301                 }
 302         }
 303         ret = 0;
 304
 305 error:
 306         kfree(buf);
 307
 308         return ret;
 309 }
 310
 311 static int ds3000_readreg(struct ds3000_state *state, u8 reg)
 312 {
 313         int ret;
 314         u8 b0[] = { reg };
 315         u8 b1[] = { 0 };
 316         struct i2c_msg msg[] = {
 317                 {
 318                         .addr = state->config->demod_address,
 319                         .flags = 0,
 320                         .buf = b0,
 321                         .len = 1
 322                 }, {
 323                         .addr = state->config->demod_address,
 324                         .flags = I2C_M_RD,
 325                         .buf = b1,
 326                         .len = 1
 327                 }
 328         };
 329
 330         ret = i2c_transfer(state->i2c, msg, 2);
 331
 332         if (ret != 2) {
 333                 printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret);
 334                 return ret;
 335         }
 336
 337         dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]);
 338
 339         return b1[0];
 340 }
 341
 342 static int ds3000_load_firmware(struct dvb_frontend *fe,
 343                                         const struct firmware *fw);
 344
 345 static int ds3000_firmware_ondemand(struct dvb_frontend *fe)
 346 {
 347         struct ds3000_state *state = fe->demodulator_priv;
 348         const struct firmware *fw;
 349         int ret = 0;
 350
 351         dprintk("%s()\n", __func__);
 352
 353         ret = ds3000_readreg(state, 0xb2);
 354         if (ret < 0)
 355                 return ret;
 356
 357         /* Load firmware */
 358         /* request the firmware, this will block until someone uploads it */
 359         printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__,
 360                                 "/*(DEBLOBBED)*/");
 361         ret = reject_firmware(&fw, "/*(DEBLOBBED)*/",
 362                                 state->i2c->dev.parent);
 363         printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__);
 364         if (ret) {
 365                 printk(KERN_ERR "%s: No firmware uploaded (timeout or file not found?)\n",
 366                        __func__);
 367                 return ret;
 368         }
 369
 370         ret = ds3000_load_firmware(fe, fw);
 371         if (ret)
 372                 printk("%s: Writing firmware to device failed\n", __func__);
 373
 374         release_firmware(fw);
 375
 376         dprintk("%s: Firmware upload %s\n", __func__,
 377                         ret == 0 ? "complete" : "failed");
 378
 379         return ret;
 380 }
 381
 382 static int ds3000_load_firmware(struct dvb_frontend *fe,
 383                                         const struct firmware *fw)
 384 {
 385         struct ds3000_state *state = fe->demodulator_priv;
 386         int ret = 0;
 387
 388         dprintk("%s\n", __func__);
 389         dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n",
 390                         fw->size,
 391                         fw->data[0],
 392                         fw->data[1],
 393                         fw->data[fw->size - 2],
 394                         fw->data[fw->size - 1]);
 395
 396         /* Begin the firmware load process */
 397         ds3000_writereg(state, 0xb2, 0x01);
 398         /* write the entire firmware */
 399         ret = ds3000_writeFW(state, 0xb0, fw->data, fw->size);
 400         ds3000_writereg(state, 0xb2, 0x00);
 401
 402         return ret;
 403 }
 404
 405 static int ds3000_set_voltage(struct dvb_frontend *fe,
 406                               enum fe_sec_voltage voltage)
 407 {
 408         struct ds3000_state *state = fe->demodulator_priv;
 409         u8 data;
 410
 411         dprintk("%s(%d)\n", __func__, voltage);
 412
 413         data = ds3000_readreg(state, 0xa2);
 414         data |= 0x03; /* bit0 V/H, bit1 off/on */
 415
 416         switch (voltage) {
 417         case SEC_VOLTAGE_18:
 418                 data &= ~0x03;
 419                 break;
 420         case SEC_VOLTAGE_13:
 421                 data &= ~0x03;
 422                 data |= 0x01;
 423                 break;
 424         case SEC_VOLTAGE_OFF:
 425                 break;
 426         }
 427
 428         ds3000_writereg(state, 0xa2, data);
 429
 430         return 0;
 431 }
 432
 433 static int ds3000_read_status(struct dvb_frontend *fe, enum fe_status *status)
 434 {
 435         struct ds3000_state *state = fe->demodulator_priv;
 436         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 437         int lock;
 438
 439         *status = 0;
 440
 441         switch (c->delivery_system) {
 442         case SYS_DVBS:
 443                 lock = ds3000_readreg(state, 0xd1);
 444                 if ((lock & 0x07) == 0x07)
 445                         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 446                                 FE_HAS_VITERBI | FE_HAS_SYNC |
 447                                 FE_HAS_LOCK;
 448
 449                 break;
 450         case SYS_DVBS2:
 451                 lock = ds3000_readreg(state, 0x0d);
 452                 if ((lock & 0x8f) == 0x8f)
 453                         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 454                                 FE_HAS_VITERBI | FE_HAS_SYNC |
 455                                 FE_HAS_LOCK;
 456
 457                 break;
 458         default:
 459                 return -EINVAL;
 460         }
 461
 462         if (state->config->set_lock_led)
 463                 state->config->set_lock_led(fe, *status == 0 ? 0 : 1);
 464
 465         dprintk("%s: status = 0x%02x\n", __func__, lock);
 466
 467         return 0;
 468 }
 469
 470 /* read DS3000 BER value */
 471 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
 472 {
 473         struct ds3000_state *state = fe->demodulator_priv;
 474         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 475         u8 data;
 476         u32 ber_reading, lpdc_frames;
 477
 478         dprintk("%s()\n", __func__);
 479
 480         switch (c->delivery_system) {
 481         case SYS_DVBS:
 482                 /* set the number of bytes checked during
 483                 BER estimation */
 484                 ds3000_writereg(state, 0xf9, 0x04);
 485                 /* read BER estimation status */
 486                 data = ds3000_readreg(state, 0xf8);
 487                 /* check if BER estimation is ready */
 488                 if ((data & 0x10) == 0) {
 489                         /* this is the number of error bits,
 490                         to calculate the bit error rate
 491                         divide to 8388608 */
 492                         *ber = (ds3000_readreg(state, 0xf7) << 8) |
 493                                 ds3000_readreg(state, 0xf6);
 494                         /* start counting error bits */
 495                         /* need to be set twice
 496                         otherwise it fails sometimes */
 497                         data |= 0x10;
 498                         ds3000_writereg(state, 0xf8, data);
 499                         ds3000_writereg(state, 0xf8, data);
 500                 } else
 501                         /* used to indicate that BER estimation
 502                         is not ready, i.e. BER is unknown */
 503                         *ber = 0xffffffff;
 504                 break;
 505         case SYS_DVBS2:
 506                 /* read the number of LPDC decoded frames */
 507                 lpdc_frames = (ds3000_readreg(state, 0xd7) << 16) |
 508                                 (ds3000_readreg(state, 0xd6) << 8) |
 509                                 ds3000_readreg(state, 0xd5);
 510                 /* read the number of packets with bad CRC */
 511                 ber_reading = (ds3000_readreg(state, 0xf8) << 8) |
 512                                 ds3000_readreg(state, 0xf7);
 513                 if (lpdc_frames > 750) {
 514                         /* clear LPDC frame counters */
 515                         ds3000_writereg(state, 0xd1, 0x01);
 516                         /* clear bad packets counter */
 517                         ds3000_writereg(state, 0xf9, 0x01);
 518                         /* enable bad packets counter */
 519                         ds3000_writereg(state, 0xf9, 0x00);
 520                         /* enable LPDC frame counters */
 521                         ds3000_writereg(state, 0xd1, 0x00);
 522                         *ber = ber_reading;
 523                 } else
 524                         /* used to indicate that BER estimation is not ready,
 525                         i.e. BER is unknown */
 526                         *ber = 0xffffffff;
 527                 break;
 528         default:
 529                 return -EINVAL;
 530         }
 531
 532         return 0;
 533 }
 534
 535 static int ds3000_read_signal_strength(struct dvb_frontend *fe,
 536                                                 u16 *signal_strength)
 537 {
 538         if (fe->ops.tuner_ops.get_rf_strength)
 539                 fe->ops.tuner_ops.get_rf_strength(fe, signal_strength);
 540
 541         return 0;
 542 }
 543
 544 /* calculate DS3000 snr value in dB */
 545 static int ds3000_read_snr(struct dvb_frontend *fe, u16 *snr)
 546 {
 547         struct ds3000_state *state = fe->demodulator_priv;
 548         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 549         u8 snr_reading, snr_value;
 550         u32 dvbs2_signal_reading, dvbs2_noise_reading, tmp;
 551         static const u16 dvbs_snr_tab[] = { /* 20 x Table (rounded up) */
 552                 0x0000, 0x1b13, 0x2aea, 0x3627, 0x3ede, 0x45fe, 0x4c03,
 553                 0x513a, 0x55d4, 0x59f2, 0x5dab, 0x6111, 0x6431, 0x6717,
 554                 0x69c9, 0x6c4e, 0x6eac, 0x70e8, 0x7304, 0x7505
 555         };
 556         static const u16 dvbs2_snr_tab[] = { /* 80 x Table (rounded up) */
 557                 0x0000, 0x0bc2, 0x12a3, 0x1785, 0x1b4e, 0x1e65, 0x2103,
 558                 0x2347, 0x2546, 0x2710, 0x28ae, 0x2a28, 0x2b83, 0x2cc5,
 559                 0x2df1, 0x2f09, 0x3010, 0x3109, 0x31f4, 0x32d2, 0x33a6,
 560                 0x3470, 0x3531, 0x35ea, 0x369b, 0x3746, 0x37ea, 0x3888,
 561                 0x3920, 0x39b3, 0x3a42, 0x3acc, 0x3b51, 0x3bd3, 0x3c51,
 562                 0x3ccb, 0x3d42, 0x3db6, 0x3e27, 0x3e95, 0x3f00, 0x3f68,
 563                 0x3fcf, 0x4033, 0x4094, 0x40f4, 0x4151, 0x41ac, 0x4206,
 564                 0x425e, 0x42b4, 0x4308, 0x435b, 0x43ac, 0x43fc, 0x444a,
 565                 0x4497, 0x44e2, 0x452d, 0x4576, 0x45bd, 0x4604, 0x4649,
 566                 0x468e, 0x46d1, 0x4713, 0x4755, 0x4795, 0x47d4, 0x4813,
 567                 0x4851, 0x488d, 0x48c9, 0x4904, 0x493f, 0x4978, 0x49b1,
 568                 0x49e9, 0x4a20, 0x4a57
 569         };
 570
 571         dprintk("%s()\n", __func__);
 572
 573         switch (c->delivery_system) {
 574         case SYS_DVBS:
 575                 snr_reading = ds3000_readreg(state, 0xff);
 576                 snr_reading /= 8;
 577                 if (snr_reading == 0)
 578                         *snr = 0x0000;
 579                 else {
 580                         if (snr_reading > 20)
 581                                 snr_reading = 20;
 582                         snr_value = dvbs_snr_tab[snr_reading - 1] * 10 / 23026;
 583                         /* cook the value to be suitable for szap-s2
 584                         human readable output */
 585                         *snr = snr_value * 8 * 655;
 586                 }
 587                 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
 588                                 snr_reading, *snr);
 589                 break;
 590         case SYS_DVBS2:
 591                 dvbs2_noise_reading = (ds3000_readreg(state, 0x8c) & 0x3f) +
 592                                 (ds3000_readreg(state, 0x8d) << 4);
 593                 dvbs2_signal_reading = ds3000_readreg(state, 0x8e);
 594                 tmp = dvbs2_signal_reading * dvbs2_signal_reading >> 1;
 595                 if (tmp == 0) {
 596                         *snr = 0x0000;
 597                         return 0;
 598                 }
 599                 if (dvbs2_noise_reading == 0) {
 600                         snr_value = 0x0013;
 601                         /* cook the value to be suitable for szap-s2
 602                         human readable output */
 603                         *snr = 0xffff;
 604                         return 0;
 605                 }
 606                 if (tmp > dvbs2_noise_reading) {
 607                         snr_reading = tmp / dvbs2_noise_reading;
 608                         if (snr_reading > 80)
 609                                 snr_reading = 80;
 610                         snr_value = dvbs2_snr_tab[snr_reading - 1] / 1000;
 611                         /* cook the value to be suitable for szap-s2
 612                         human readable output */
 613                         *snr = snr_value * 5 * 655;
 614                 } else {
 615                         snr_reading = dvbs2_noise_reading / tmp;
 616                         if (snr_reading > 80)
 617                                 snr_reading = 80;
 618                         *snr = -(dvbs2_snr_tab[snr_reading - 1] / 1000);
 619                 }
 620                 dprintk("%s: raw / cooked = 0x%02x / 0x%04x\n", __func__,
 621                                 snr_reading, *snr);
 622                 break;
 623         default:
 624                 return -EINVAL;
 625         }
 626
 627         return 0;
 628 }
 629
 630 /* read DS3000 uncorrected blocks */
 631 static int ds3000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
 632 {
 633         struct ds3000_state *state = fe->demodulator_priv;
 634         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 635         u8 data;
 636         u16 _ucblocks;
 637
 638         dprintk("%s()\n", __func__);
 639
 640         switch (c->delivery_system) {
 641         case SYS_DVBS:
 642                 *ucblocks = (ds3000_readreg(state, 0xf5) << 8) |
 643                                 ds3000_readreg(state, 0xf4);
 644                 data = ds3000_readreg(state, 0xf8);
 645                 /* clear packet counters */
 646                 data &= ~0x20;
 647                 ds3000_writereg(state, 0xf8, data);
 648                 /* enable packet counters */
 649                 data |= 0x20;
 650                 ds3000_writereg(state, 0xf8, data);
 651                 break;
 652         case SYS_DVBS2:
 653                 _ucblocks = (ds3000_readreg(state, 0xe2) << 8) |
 654                                 ds3000_readreg(state, 0xe1);
 655                 if (_ucblocks > state->prevUCBS2)
 656                         *ucblocks = _ucblocks - state->prevUCBS2;
 657                 else
 658                         *ucblocks = state->prevUCBS2 - _ucblocks;
 659                 state->prevUCBS2 = _ucblocks;
 660                 break;
 661         default:
 662                 return -EINVAL;
 663         }
 664
 665         return 0;
 666 }
 667
 668 static int ds3000_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
 669 {
 670         struct ds3000_state *state = fe->demodulator_priv;
 671         u8 data;
 672
 673         dprintk("%s(%d)\n", __func__, tone);
 674         if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
 675                 printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone);
 676                 return -EINVAL;
 677         }
 678
 679         data = ds3000_readreg(state, 0xa2);
 680         data &= ~0xc0;
 681         ds3000_writereg(state, 0xa2, data);
 682
 683         switch (tone) {
 684         case SEC_TONE_ON:
 685                 dprintk("%s: setting tone on\n", __func__);
 686                 data = ds3000_readreg(state, 0xa1);
 687                 data &= ~0x43;
 688                 data |= 0x04;
 689                 ds3000_writereg(state, 0xa1, data);
 690                 break;
 691         case SEC_TONE_OFF:
 692                 dprintk("%s: setting tone off\n", __func__);
 693                 data = ds3000_readreg(state, 0xa2);
 694                 data |= 0x80;
 695                 ds3000_writereg(state, 0xa2, data);
 696                 break;
 697         }
 698
 699         return 0;
 700 }
 701
 702 static int ds3000_send_diseqc_msg(struct dvb_frontend *fe,
 703                                 struct dvb_diseqc_master_cmd *d)
 704 {
 705         struct ds3000_state *state = fe->demodulator_priv;
 706         int i;
 707         u8 data;
 708
 709         /* Dump DiSEqC message */
 710         dprintk("%s(", __func__);
 711         for (i = 0 ; i < d->msg_len;) {
 712                 dprintk("0x%02x", d->msg[i]);
 713                 if (++i < d->msg_len)
 714                         dprintk(", ");
 715         }
 716
 717         /* enable DiSEqC message send pin */
 718         data = ds3000_readreg(state, 0xa2);
 719         data &= ~0xc0;
 720         ds3000_writereg(state, 0xa2, data);
 721
 722         /* DiSEqC message */
 723         for (i = 0; i < d->msg_len; i++)
 724                 ds3000_writereg(state, 0xa3 + i, d->msg[i]);
 725
 726         data = ds3000_readreg(state, 0xa1);
 727         /* clear DiSEqC message length and status,
 728         enable DiSEqC message send */
 729         data &= ~0xf8;
 730         /* set DiSEqC mode, modulation active during 33 pulses,
 731         set DiSEqC message length */
 732         data |= ((d->msg_len - 1) << 3) | 0x07;
 733         ds3000_writereg(state, 0xa1, data);
 734
 735         /* wait up to 150ms for DiSEqC transmission to complete */
 736         for (i = 0; i < 15; i++) {
 737                 data = ds3000_readreg(state, 0xa1);
 738                 if ((data & 0x40) == 0)
 739                         break;
 740                 msleep(10);
 741         }
 742
 743         /* DiSEqC timeout after 150ms */
 744         if (i == 15) {
 745                 data = ds3000_readreg(state, 0xa1);
 746                 data &= ~0x80;
 747                 data |= 0x40;
 748                 ds3000_writereg(state, 0xa1, data);
 749
 750                 data = ds3000_readreg(state, 0xa2);
 751                 data &= ~0xc0;
 752                 data |= 0x80;
 753                 ds3000_writereg(state, 0xa2, data);
 754
 755                 return -ETIMEDOUT;
 756         }
 757
 758         data = ds3000_readreg(state, 0xa2);
 759         data &= ~0xc0;
 760         data |= 0x80;
 761         ds3000_writereg(state, 0xa2, data);
 762
 763         return 0;
 764 }
 765
 766 /* Send DiSEqC burst */
 767 static int ds3000_diseqc_send_burst(struct dvb_frontend *fe,
 768                                     enum fe_sec_mini_cmd burst)
 769 {
 770         struct ds3000_state *state = fe->demodulator_priv;
 771         int i;
 772         u8 data;
 773
 774         dprintk("%s()\n", __func__);
 775
 776         data = ds3000_readreg(state, 0xa2);
 777         data &= ~0xc0;
 778         ds3000_writereg(state, 0xa2, data);
 779
 780         /* DiSEqC burst */
 781         if (burst == SEC_MINI_A)
 782                 /* Unmodulated tone burst */
 783                 ds3000_writereg(state, 0xa1, 0x02);
 784         else if (burst == SEC_MINI_B)
 785                 /* Modulated tone burst */
 786                 ds3000_writereg(state, 0xa1, 0x01);
 787         else
 788                 return -EINVAL;
 789
 790         msleep(13);
 791         for (i = 0; i < 5; i++) {
 792                 data = ds3000_readreg(state, 0xa1);
 793                 if ((data & 0x40) == 0)
 794                         break;
 795                 msleep(1);
 796         }
 797
 798         if (i == 5) {
 799                 data = ds3000_readreg(state, 0xa1);
 800                 data &= ~0x80;
 801                 data |= 0x40;
 802                 ds3000_writereg(state, 0xa1, data);
 803
 804                 data = ds3000_readreg(state, 0xa2);
 805                 data &= ~0xc0;
 806                 data |= 0x80;
 807                 ds3000_writereg(state, 0xa2, data);
 808
 809                 return -ETIMEDOUT;
 810         }
 811
 812         data = ds3000_readreg(state, 0xa2);
 813         data &= ~0xc0;
 814         data |= 0x80;
 815         ds3000_writereg(state, 0xa2, data);
 816
 817         return 0;
 818 }
 819
 820 static void ds3000_release(struct dvb_frontend *fe)
 821 {
 822         struct ds3000_state *state = fe->demodulator_priv;
 823
 824         if (state->config->set_lock_led)
 825                 state->config->set_lock_led(fe, 0);
 826
 827         dprintk("%s\n", __func__);
 828         kfree(state);
 829 }
 830
 831 static const struct dvb_frontend_ops ds3000_ops;
 832
 833 struct dvb_frontend *ds3000_attach(const struct ds3000_config *config,
 834                                     struct i2c_adapter *i2c)
 835 {
 836         struct ds3000_state *state = NULL;
 837         int ret;
 838
 839         dprintk("%s\n", __func__);
 840
 841         /* allocate memory for the internal state */
 842         state = kzalloc(sizeof(struct ds3000_state), GFP_KERNEL);
 843         if (state == NULL) {
 844                 printk(KERN_ERR "Unable to kmalloc\n");
 845                 goto error2;
 846         }
 847
 848         state->config = config;
 849         state->i2c = i2c;
 850         state->prevUCBS2 = 0;
 851
 852         /* check if the demod is present */
 853         ret = ds3000_readreg(state, 0x00) & 0xfe;
 854         if (ret != 0xe0) {
 855                 printk(KERN_ERR "Invalid probe, probably not a DS3000\n");
 856                 goto error3;
 857         }
 858
 859         printk(KERN_INFO "DS3000 chip version: %d.%d attached.\n",
 860                         ds3000_readreg(state, 0x02),
 861                         ds3000_readreg(state, 0x01));
 862
 863         memcpy(&state->frontend.ops, &ds3000_ops,
 864                         sizeof(struct dvb_frontend_ops));
 865         state->frontend.demodulator_priv = state;
 866
 867         /*
 868          * Some devices like T480 starts with voltage on. Be sure
 869          * to turn voltage off during init, as this can otherwise
 870          * interfere with Unicable SCR systems.
 871          */
 872         ds3000_set_voltage(&state->frontend, SEC_VOLTAGE_OFF);
 873         return &state->frontend;
 874
 875 error3:
 876         kfree(state);
 877 error2:
 878         return NULL;
 879 }
 880 EXPORT_SYMBOL(ds3000_attach);
 881
 882 static int ds3000_set_carrier_offset(struct dvb_frontend *fe,
 883                                         s32 carrier_offset_khz)
 884 {
 885         struct ds3000_state *state = fe->demodulator_priv;
 886         s32 tmp;
 887
 888         tmp = carrier_offset_khz;
 889         tmp *= 65536;
 890         tmp = (2 * tmp + DS3000_SAMPLE_RATE) / (2 * DS3000_SAMPLE_RATE);
 891
 892         if (tmp < 0)
 893                 tmp += 65536;
 894
 895         ds3000_writereg(state, 0x5f, tmp >> 8);
 896         ds3000_writereg(state, 0x5e, tmp & 0xff);
 897
 898         return 0;
 899 }
 900
 901 static int ds3000_set_frontend(struct dvb_frontend *fe)
 902 {
 903         struct ds3000_state *state = fe->demodulator_priv;
 904         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 905
 906         int i;
 907         enum fe_status status;
 908         s32 offset_khz;
 909         u32 frequency;
 910         u16 value;
 911
 912         dprintk("%s() ", __func__);
 913
 914         if (state->config->set_ts_params)
 915                 state->config->set_ts_params(fe, 0);
 916         /* Tune */
 917         if (fe->ops.tuner_ops.set_params)
 918                 fe->ops.tuner_ops.set_params(fe);
 919
 920         /* ds3000 global reset */
 921         ds3000_writereg(state, 0x07, 0x80);
 922         ds3000_writereg(state, 0x07, 0x00);
 923         /* ds3000 build-in uC reset */
 924         ds3000_writereg(state, 0xb2, 0x01);
 925         /* ds3000 software reset */
 926         ds3000_writereg(state, 0x00, 0x01);
 927
 928         switch (c->delivery_system) {
 929         case SYS_DVBS:
 930                 /* initialise the demod in DVB-S mode */
 931                 for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
 932                         ds3000_writereg(state,
 933                                 ds3000_dvbs_init_tab[i],
 934                                 ds3000_dvbs_init_tab[i + 1]);
 935                 value = ds3000_readreg(state, 0xfe);
 936                 value &= 0xc0;
 937                 value |= 0x1b;
 938                 ds3000_writereg(state, 0xfe, value);
 939                 break;
 940         case SYS_DVBS2:
 941                 /* initialise the demod in DVB-S2 mode */
 942                 for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
 943                         ds3000_writereg(state,
 944                                 ds3000_dvbs2_init_tab[i],
 945                                 ds3000_dvbs2_init_tab[i + 1]);
 946                 if (c->symbol_rate >= 30000000)
 947                         ds3000_writereg(state, 0xfe, 0x54);
 948                 else
 949                         ds3000_writereg(state, 0xfe, 0x98);
 950                 break;
 951         default:
 952                 return -EINVAL;
 953         }
 954
 955         /* enable 27MHz clock output */
 956         ds3000_writereg(state, 0x29, 0x80);
 957         /* enable ac coupling */
 958         ds3000_writereg(state, 0x25, 0x8a);
 959
 960         if ((c->symbol_rate < ds3000_ops.info.symbol_rate_min) ||
 961                         (c->symbol_rate > ds3000_ops.info.symbol_rate_max)) {
 962                 dprintk("%s() symbol_rate %u out of range (%u ... %u)\n",
 963                                 __func__, c->symbol_rate,
 964                                 ds3000_ops.info.symbol_rate_min,
 965                                 ds3000_ops.info.symbol_rate_max);
 966                 return -EINVAL;
 967         }
 968
 969         /* enhance symbol rate performance */
 970         if ((c->symbol_rate / 1000) <= 5000) {
 971                 value = 29777 / (c->symbol_rate / 1000) + 1;
 972                 if (value % 2 != 0)
 973                         value++;
 974                 ds3000_writereg(state, 0xc3, 0x0d);
 975                 ds3000_writereg(state, 0xc8, value);
 976                 ds3000_writereg(state, 0xc4, 0x10);
 977                 ds3000_writereg(state, 0xc7, 0x0e);
 978         } else if ((c->symbol_rate / 1000) <= 10000) {
 979                 value = 92166 / (c->symbol_rate / 1000) + 1;
 980                 if (value % 2 != 0)
 981                         value++;
 982                 ds3000_writereg(state, 0xc3, 0x07);
 983                 ds3000_writereg(state, 0xc8, value);
 984                 ds3000_writereg(state, 0xc4, 0x09);
 985                 ds3000_writereg(state, 0xc7, 0x12);
 986         } else if ((c->symbol_rate / 1000) <= 20000) {
 987                 value = 64516 / (c->symbol_rate / 1000) + 1;
 988                 ds3000_writereg(state, 0xc3, value);
 989                 ds3000_writereg(state, 0xc8, 0x0e);
 990                 ds3000_writereg(state, 0xc4, 0x07);
 991                 ds3000_writereg(state, 0xc7, 0x18);
 992         } else {
 993                 value = 129032 / (c->symbol_rate / 1000) + 1;
 994                 ds3000_writereg(state, 0xc3, value);
 995                 ds3000_writereg(state, 0xc8, 0x0a);
 996                 ds3000_writereg(state, 0xc4, 0x05);
 997                 ds3000_writereg(state, 0xc7, 0x24);
 998         }
 999
1000         /* normalized symbol rate rounded to the closest integer */
1001         value = (((c->symbol_rate / 1000) << 16) +
1002                         (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
1003         ds3000_writereg(state, 0x61, value & 0x00ff);
1004         ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
1005
1006         /* co-channel interference cancellation disabled */
1007         ds3000_writereg(state, 0x56, 0x00);
1008
1009         /* equalizer disabled */
1010         ds3000_writereg(state, 0x76, 0x00);
1011
1012         /*ds3000_writereg(state, 0x08, 0x03);
1013         ds3000_writereg(state, 0xfd, 0x22);
1014         ds3000_writereg(state, 0x08, 0x07);
1015         ds3000_writereg(state, 0xfd, 0x42);
1016         ds3000_writereg(state, 0x08, 0x07);*/
1017
1018         if (state->config->ci_mode) {
1019                 switch (c->delivery_system) {
1020                 case SYS_DVBS:
1021                 default:
1022                         ds3000_writereg(state, 0xfd, 0x80);
1023                 break;
1024                 case SYS_DVBS2:
1025                         ds3000_writereg(state, 0xfd, 0x01);
1026                         break;
1027                 }
1028         }
1029
1030         /* ds3000 out of software reset */
1031         ds3000_writereg(state, 0x00, 0x00);
1032         /* start ds3000 build-in uC */
1033         ds3000_writereg(state, 0xb2, 0x00);
1034
1035         if (fe->ops.tuner_ops.get_frequency) {
1036                 fe->ops.tuner_ops.get_frequency(fe, &frequency);
1037                 offset_khz = frequency - c->frequency;
1038                 ds3000_set_carrier_offset(fe, offset_khz);
1039         }
1040
1041         for (i = 0; i < 30 ; i++) {
1042                 ds3000_read_status(fe, &status);
1043                 if (status & FE_HAS_LOCK)
1044                         break;
1045
1046                 msleep(10);
1047         }
1048
1049         return 0;
1050 }
1051
1052 static int ds3000_tune(struct dvb_frontend *fe,
1053                         bool re_tune,
1054                         unsigned int mode_flags,
1055                         unsigned int *delay,
1056                         enum fe_status *status)
1057 {
1058         if (re_tune) {
1059                 int ret = ds3000_set_frontend(fe);
1060                 if (ret)
1061                         return ret;
1062         }
1063
1064         *delay = HZ / 5;
1065
1066         return ds3000_read_status(fe, status);
1067 }
1068
1069 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
1070 {
1071         struct ds3000_state *state = fe->demodulator_priv;
1072
1073         if (state->config->set_lock_led)
1074                 state->config->set_lock_led(fe, 0);
1075
1076         dprintk("%s()\n", __func__);
1077         return DVBFE_ALGO_HW;
1078 }
1079
1080 /*
1081  * Initialise or wake up device
1082  *
1083  * Power config will reset and load initial firmware if required
1084  */
1085 static int ds3000_initfe(struct dvb_frontend *fe)
1086 {
1087         struct ds3000_state *state = fe->demodulator_priv;
1088         int ret;
1089
1090         dprintk("%s()\n", __func__);
1091         /* hard reset */
1092         ds3000_writereg(state, 0x08, 0x01 | ds3000_readreg(state, 0x08));
1093         msleep(1);
1094
1095         /* Load the firmware if required */
1096         ret = ds3000_firmware_ondemand(fe);
1097         if (ret != 0) {
1098                 printk(KERN_ERR "%s: Unable initialize firmware\n", __func__);
1099                 return ret;
1100         }
1101
1102         return 0;
1103 }
1104
1105 static const struct dvb_frontend_ops ds3000_ops = {
1106         .delsys = { SYS_DVBS, SYS_DVBS2 },
1107         .info = {
1108                 .name = "Montage Technology DS3000",
1109                 .frequency_min = 950000,
1110                 .frequency_max = 2150000,
1111                 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
1112                 .frequency_tolerance = 5000,
1113                 .symbol_rate_min = 1000000,
1114                 .symbol_rate_max = 45000000,
1115                 .caps = FE_CAN_INVERSION_AUTO |
1116                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1117                         FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1118                         FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1119                         FE_CAN_2G_MODULATION |
1120                         FE_CAN_QPSK | FE_CAN_RECOVER
1121         },
1122
1123         .release = ds3000_release,
1124
1125         .init = ds3000_initfe,
1126         .i2c_gate_ctrl = ds3000_i2c_gate_ctrl,
1127         .read_status = ds3000_read_status,
1128         .read_ber = ds3000_read_ber,
1129         .read_signal_strength = ds3000_read_signal_strength,
1130         .read_snr = ds3000_read_snr,
1131         .read_ucblocks = ds3000_read_ucblocks,
1132         .set_voltage = ds3000_set_voltage,
1133         .set_tone = ds3000_set_tone,
1134         .diseqc_send_master_cmd = ds3000_send_diseqc_msg,
1135         .diseqc_send_burst = ds3000_diseqc_send_burst,
1136         .get_frontend_algo = ds3000_get_algo,
1137
1138         .set_frontend = ds3000_set_frontend,
1139         .tune = ds3000_tune,
1140 };
1141
1142 module_param(debug, int, 0644);
1143 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1144
1145 MODULE_DESCRIPTION("DVB Frontend module for Montage Technology DS3000 hardware");
1146 MODULE_AUTHOR("Konstantin Dimitrov <kosio.dimitrov@gmail.com>");
1147 MODULE_LICENSE("GPL");
1148 /*(DEBLOBBED)*/