1 // SPDX-License-Identifier: GPL-2.0-only
3 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
5 * Copyright (C) 2003-2007 Micronas
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
14 #include <linux/i2c.h>
15 #include <asm/div64.h>
17 #include <media/dvb_frontend.h>
19 #include "drxd_firm.h"
21 #define DRX_FW_FILENAME_A2 "/*(DEBLOBBED)*/"
22 #define DRX_FW_FILENAME_B1 "/*(DEBLOBBED)*/"
26 #define DRX_I2C_RMW 0x10
27 #define DRX_I2C_BROADCAST 0x20
28 #define DRX_I2C_CLEARCRC 0x80
29 #define DRX_I2C_SINGLE_MASTER 0xC0
30 #define DRX_I2C_MODEFLAGS 0xC0
31 #define DRX_I2C_FLAGS 0xF0
33 #define DEFAULT_LOCK_TIMEOUT 1100
35 #define DRX_CHANNEL_AUTO 0
36 #define DRX_CHANNEL_HIGH 1
37 #define DRX_CHANNEL_LOW 2
39 #define DRX_LOCK_MPEG 1
40 #define DRX_LOCK_FEC 2
41 #define DRX_LOCK_DEMOD 4
43 /****************************************************************************/
52 DRXD_UNINITIALIZED = 0,
65 OM_DVBT_Diversity_Front,
70 enum AGC_CTRL_MODE ctrlMode;
71 u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
72 u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
73 u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
74 u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
75 u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
101 struct dvb_frontend frontend;
102 struct dvb_frontend_ops ops;
103 struct dtv_frontend_properties props;
105 const struct firmware *fw;
108 struct i2c_adapter *i2c;
110 struct drxd_config config;
117 u16 hi_cfg_timing_div;
118 u16 hi_cfg_bridge_delay;
119 u16 hi_cfg_wakeup_key;
122 u16 intermediate_freq;
125 enum CSCDState cscd_state;
126 enum CDrxdState drxd_state;
129 s16 osc_clock_deviation;
130 u16 expected_sys_clock_freq;
137 struct SCfgAgc if_agc_cfg;
138 struct SCfgAgc rf_agc_cfg;
140 struct SNoiseCal noise_cal;
143 u32 org_fe_fs_add_incr;
144 u16 current_fe_if_incr;
147 u16 m_FeAgRegAgAgcSio;
149 u16 m_EcOcRegOcModeLop;
150 u16 m_EcOcRegSncSncLvl;
151 u8 *m_InitAtomicRead;
163 u8 *m_InitDiversityFront;
164 u8 *m_InitDiversityEnd;
165 u8 *m_DisableDiversity;
166 u8 *m_StartDiversityFront;
167 u8 *m_StartDiversityEnd;
169 u8 *m_DiversityDelay8MHZ;
170 u8 *m_DiversityDelay6MHZ;
173 u32 microcode_length;
180 enum app_env app_env_default;
181 enum app_env app_env_diversity;
185 /****************************************************************************/
186 /* I2C **********************************************************************/
187 /****************************************************************************/
189 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
191 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
193 if (i2c_transfer(adap, &msg, 1) != 1)
198 static int i2c_read(struct i2c_adapter *adap,
199 u8 adr, u8 *msg, int len, u8 *answ, int alen)
201 struct i2c_msg msgs[2] = {
203 .addr = adr, .flags = 0,
204 .buf = msg, .len = len
206 .addr = adr, .flags = I2C_M_RD,
207 .buf = answ, .len = alen
210 if (i2c_transfer(adap, msgs, 2) != 2)
215 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
219 tmp64 = (u64)a * (u64)b;
225 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
227 u8 adr = state->config.demod_address;
228 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
229 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
232 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
235 *data = mm2[0] | (mm2[1] << 8);
236 return mm2[0] | (mm2[1] << 8);
239 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
241 u8 adr = state->config.demod_address;
242 u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
243 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
247 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
251 mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
255 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
257 u8 adr = state->config.demod_address;
258 u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
259 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
260 data & 0xff, (data >> 8) & 0xff
263 if (i2c_write(state->i2c, adr, mm, 6) < 0)
268 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
270 u8 adr = state->config.demod_address;
271 u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
272 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
273 data & 0xff, (data >> 8) & 0xff,
274 (data >> 16) & 0xff, (data >> 24) & 0xff
277 if (i2c_write(state->i2c, adr, mm, 8) < 0)
282 static int write_chunk(struct drxd_state *state,
283 u32 reg, u8 *data, u32 len, u8 flags)
285 u8 adr = state->config.demod_address;
286 u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
287 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
291 for (i = 0; i < len; i++)
293 if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
294 printk(KERN_ERR "error in write_chunk\n");
300 static int WriteBlock(struct drxd_state *state,
301 u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
303 while (BlockSize > 0) {
304 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
306 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
309 Address += (Chunk >> 1);
315 static int WriteTable(struct drxd_state *state, u8 * pTable)
324 u32 Address = pTable[0] | (pTable[1] << 8) |
325 (pTable[2] << 16) | (pTable[3] << 24);
327 if (Address == 0xFFFFFFFF)
329 pTable += sizeof(u32);
331 Length = pTable[0] | (pTable[1] << 8);
332 pTable += sizeof(u16);
335 status = WriteBlock(state, Address, Length * 2, pTable, 0);
336 pTable += (Length * 2);
341 /****************************************************************************/
342 /****************************************************************************/
343 /****************************************************************************/
345 static int ResetCEFR(struct drxd_state *state)
347 return WriteTable(state, state->m_ResetCEFR);
350 static int InitCP(struct drxd_state *state)
352 return WriteTable(state, state->m_InitCP);
355 static int InitCE(struct drxd_state *state)
358 enum app_env AppEnv = state->app_env_default;
361 status = WriteTable(state, state->m_InitCE);
365 if (state->operation_mode == OM_DVBT_Diversity_Front ||
366 state->operation_mode == OM_DVBT_Diversity_End) {
367 AppEnv = state->app_env_diversity;
369 if (AppEnv == APPENV_STATIC) {
370 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
373 } else if (AppEnv == APPENV_PORTABLE) {
374 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
377 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
378 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
381 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
382 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
388 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
395 static int StopOC(struct drxd_state *state)
399 u16 ocModeLop = state->m_EcOcRegOcModeLop;
404 /* Store output configuration */
405 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
408 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
409 state->m_EcOcRegSncSncLvl = ocSyncLvl;
410 /* m_EcOcRegOcModeLop = ocModeLop; */
412 /* Flush FIFO (byte-boundary) at fixed rate */
413 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
416 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
419 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
422 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
425 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
426 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
427 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
430 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
435 /* Output pins to '0' */
436 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
440 /* Force the OC out of sync */
441 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
442 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
445 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
446 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
447 ocModeLop |= 0x2; /* Magically-out-of-sync */
448 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
451 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
454 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
462 static int StartOC(struct drxd_state *state)
468 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
472 /* Restore output configuration */
473 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
476 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
480 /* Output pins active again */
481 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
486 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
493 static int InitEQ(struct drxd_state *state)
495 return WriteTable(state, state->m_InitEQ);
498 static int InitEC(struct drxd_state *state)
500 return WriteTable(state, state->m_InitEC);
503 static int InitSC(struct drxd_state *state)
505 return WriteTable(state, state->m_InitSC);
508 static int InitAtomicRead(struct drxd_state *state)
510 return WriteTable(state, state->m_InitAtomicRead);
513 static int CorrectSysClockDeviation(struct drxd_state *state);
515 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
518 const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
519 SC_RA_RAM_LOCK_FEC__M |
520 SC_RA_RAM_LOCK_DEMOD__M);
521 const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
522 SC_RA_RAM_LOCK_DEMOD__M);
523 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
529 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
531 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
535 if (state->drxd_state != DRXD_STARTED)
538 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
539 *pLockStatus |= DRX_LOCK_MPEG;
540 CorrectSysClockDeviation(state);
543 if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
544 *pLockStatus |= DRX_LOCK_FEC;
546 if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
547 *pLockStatus |= DRX_LOCK_DEMOD;
551 /****************************************************************************/
553 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
557 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
560 if (cfg->ctrlMode == AGC_CTRL_USER) {
562 u16 FeAgRegPm1AgcWri;
563 u16 FeAgRegAgModeLop;
565 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
568 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
569 FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
570 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
574 FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
575 FE_AG_REG_PM1_AGC_WRI__M);
576 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
580 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
581 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
582 ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
583 ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
584 ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
588 u16 FeAgRegAgModeLop;
589 u16 FeAgRegEgcSetLvl;
594 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
597 FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
599 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
600 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
604 /* == Settle level == */
606 FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
607 FE_AG_REG_EGC_SET_LVL__M);
608 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
614 slope = (u16) ((cfg->maxOutputLevel -
615 cfg->minOutputLevel) / 2);
616 offset = (u16) ((cfg->maxOutputLevel +
617 cfg->minOutputLevel) / 2 - 511);
619 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
622 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
628 const u16 maxRur = 8;
629 static const u16 slowIncrDecLUT[] = {
631 static const u16 fastIncrDecLUT[] = {
639 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
641 u16 fineSpeed = (u16) (cfg->speed -
645 u16 invRurCount = (u16) (cfg->speed /
648 if (invRurCount > maxRur) {
650 fineSpeed += fineSteps;
652 rurCount = maxRur - invRurCount;
657 (2^(fineSpeed/fineSteps))
658 => range[default...2*default>
660 (2^(fineSpeed/fineSteps))
664 fastIncrDecLUT[fineSpeed /
668 slowIncrDecLUT[fineSpeed /
672 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
675 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
678 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
681 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
684 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
692 /* No OFF mode for IF control */
698 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
702 if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
705 if (cfg->ctrlMode == AGC_CTRL_USER) {
708 u16 level = (cfg->outputLevel);
710 if (level == DRXD_FE_CTRL_MAX)
713 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
719 /* Powerdown PD2, WRI source */
720 state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
721 state->m_FeAgRegAgPwd |=
722 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
723 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
727 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
730 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
731 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
732 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
733 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
734 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
738 /* enable AGC2 pin */
740 u16 FeAgRegAgAgcSio = 0;
741 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
745 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
747 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
748 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
754 } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
759 /* Automatic control */
760 /* Powerup PD2, AGC2 as output, TGC source */
761 (state->m_FeAgRegAgPwd) &=
762 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
763 (state->m_FeAgRegAgPwd) |=
764 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
765 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
769 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
772 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
773 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
774 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
775 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
776 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
780 level = (((cfg->settleLevel) >> 4) &
781 FE_AG_REG_TGC_SET_LVL__M);
782 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
786 /* Min/max: don't care */
790 /* enable AGC2 pin */
792 u16 FeAgRegAgAgcSio = 0;
793 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
797 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
799 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
800 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
810 /* No RF AGC control */
811 /* Powerdown PD2, AGC2 as output, WRI source */
812 (state->m_FeAgRegAgPwd) &=
813 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
814 (state->m_FeAgRegAgPwd) |=
815 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
816 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
820 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
823 AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
824 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
825 AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
826 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
827 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
831 /* set FeAgRegAgAgcSio AGC2 (RF) as input */
833 u16 FeAgRegAgAgcSio = 0;
834 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
838 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
840 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
841 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
850 static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
855 if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
857 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
858 Value &= FE_AG_REG_GC1_AGC_DAT__M;
870 u32 R1 = state->if_agc_cfg.R1;
871 u32 R2 = state->if_agc_cfg.R2;
872 u32 R3 = state->if_agc_cfg.R3;
874 u32 Vmax, Rpar, Vmin, Vout;
876 if (R2 == 0 && (R1 == 0 || R3 == 0))
879 Vmax = (3300 * R2) / (R1 + R2);
880 Rpar = (R2 * R3) / (R3 + R2);
881 Vmin = (3300 * Rpar) / (R1 + Rpar);
882 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
890 static int load_firmware(struct drxd_state *state, const char *fw_name)
892 const struct firmware *fw;
894 if (reject_firmware(&fw, fw_name, state->dev) < 0) {
895 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
899 state->microcode = kmemdup(fw->data, fw->size, GFP_KERNEL);
900 if (!state->microcode) {
901 release_firmware(fw);
905 state->microcode_length = fw->size;
906 release_firmware(fw);
910 static int DownloadMicrocode(struct drxd_state *state,
911 const u8 *pMCImage, u32 Length)
919 pSrc = (u8 *) pMCImage;
920 /* We're not using Flags */
921 /* Flags = (pSrc[0] << 8) | pSrc[1]; */
923 nBlocks = (pSrc[0] << 8) | pSrc[1];
926 for (i = 0; i < nBlocks; i++) {
927 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
928 (pSrc[2] << 8) | pSrc[3];
931 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
934 /* We're not using Flags */
935 /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
938 /* We're not using BlockCRC */
939 /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
942 status = WriteBlock(state, Address, BlockSize,
943 pSrc, DRX_I2C_CLEARCRC);
952 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
957 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
963 if (nrRetries > DRXD_MAX_RETRIES) {
967 status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0);
968 } while (status != 0);
971 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
975 static int HI_CfgCommand(struct drxd_state *state)
979 mutex_lock(&state->mutex);
980 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
981 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
982 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
983 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
984 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
986 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
988 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
989 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
990 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
991 HI_RA_RAM_SRV_CMD_CONFIG, 0);
993 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL);
994 mutex_unlock(&state->mutex);
998 static int InitHI(struct drxd_state *state)
1000 state->hi_cfg_wakeup_key = (state->chip_adr);
1001 /* port/bridge/power down ctrl */
1002 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
1003 return HI_CfgCommand(state);
1006 static int HI_ResetCommand(struct drxd_state *state)
1010 mutex_lock(&state->mutex);
1011 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1012 HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1014 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL);
1015 mutex_unlock(&state->mutex);
1020 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
1022 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
1024 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1026 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
1028 return HI_CfgCommand(state);
1031 #define HI_TR_WRITE 0x9
1032 #define HI_TR_READ 0xA
1033 #define HI_TR_READ_WRITE 0xB
1034 #define HI_TR_BROADCAST 0x4
1037 static int AtomicReadBlock(struct drxd_state *state,
1038 u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
1043 /* Parameter check */
1044 if ((!pData) || ((DataSize & 1) != 0))
1047 mutex_lock(&state->mutex);
1050 /* Instruct HI to read n bytes */
1051 /* TODO use proper names forthese egisters */
1052 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1055 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1058 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1061 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1064 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1068 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1075 for (i = 0; i < (DataSize / 2); i += 1) {
1078 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1082 pData[2 * i] = (u8) (word & 0xFF);
1083 pData[(2 * i) + 1] = (u8) (word >> 8);
1086 mutex_unlock(&state->mutex);
1090 static int AtomicReadReg32(struct drxd_state *state,
1091 u32 Addr, u32 *pData, u8 Flags)
1093 u8 buf[sizeof(u32)];
1098 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1099 *pData = (((u32) buf[0]) << 0) +
1100 (((u32) buf[1]) << 8) +
1101 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1106 static int StopAllProcessors(struct drxd_state *state)
1108 return Write16(state, HI_COMM_EXEC__A,
1109 SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1112 static int EnableAndResetMB(struct drxd_state *state)
1114 if (state->type_A) {
1115 /* disable? monitor bus observe @ EC_OC */
1116 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1119 /* do inverse broadcast, followed by explicit write to HI */
1120 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1121 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1125 static int InitCC(struct drxd_state *state)
1129 if (state->osc_clock_freq == 0 ||
1130 state->osc_clock_freq > 20000 ||
1131 (state->osc_clock_freq % 4000) != 0) {
1132 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
1136 status |= Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1137 status |= Write16(state, CC_REG_PLL_MODE__A,
1138 CC_REG_PLL_MODE_BYPASS_PLL |
1139 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1140 status |= Write16(state, CC_REG_REF_DIVIDE__A,
1141 state->osc_clock_freq / 4000, 0);
1142 status |= Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL,
1144 status |= Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1149 static int ResetECOD(struct drxd_state *state)
1154 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1156 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1159 status = WriteTable(state, state->m_ResetECRAM);
1161 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1165 /* Configure PGA switch */
1167 static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1176 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1179 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1180 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1181 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1186 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1189 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1190 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
1191 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1195 /* enable fine and coarse gain, enable AAF,
1197 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1201 /* PGA off, bypass */
1204 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1207 AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1208 AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
1209 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1214 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1217 AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1218 AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
1219 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1223 /* disable fine and coarse gain, enable AAF,
1225 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1233 static int InitFE(struct drxd_state *state)
1238 status = WriteTable(state, state->m_InitFE_1);
1242 if (state->type_A) {
1243 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1244 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1248 status = SetCfgPga(state, 0);
1251 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1252 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1258 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1261 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1265 status = WriteTable(state, state->m_InitFE_2);
1274 static int InitFT(struct drxd_state *state)
1277 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1280 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
1283 static int SC_WaitForReady(struct drxd_state *state)
1287 for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
1288 int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0);
1295 static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1297 int status = 0, ret;
1300 status = Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1304 SC_WaitForReady(state);
1306 ret = Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
1308 if (ret < 0 || errCode == 0xFFFF) {
1309 printk(KERN_ERR "Command Error\n");
1316 static int SC_ProcStartCommand(struct drxd_state *state,
1317 u16 subCmd, u16 param0, u16 param1)
1319 int ret, status = 0;
1322 mutex_lock(&state->mutex);
1324 ret = Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1325 if (ret < 0 || scExec != 1) {
1329 SC_WaitForReady(state);
1330 status |= Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1331 status |= Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1332 status |= Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1334 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
1336 mutex_unlock(&state->mutex);
1340 static int SC_SetPrefParamCommand(struct drxd_state *state,
1341 u16 subCmd, u16 param0, u16 param1)
1345 mutex_lock(&state->mutex);
1347 status = SC_WaitForReady(state);
1350 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1353 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1356 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1360 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1364 mutex_unlock(&state->mutex);
1369 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1373 mutex_lock(&state->mutex);
1375 status = SC_WaitForReady(state);
1378 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1381 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1385 mutex_unlock(&state->mutex);
1390 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1395 u16 EcOcRegIprInvMpg = 0;
1396 u16 EcOcRegOcModeLop = 0;
1397 u16 EcOcRegOcModeHip = 0;
1398 u16 EcOcRegOcMpgSio = 0;
1400 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
1402 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1403 if (bEnableOutput) {
1405 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1407 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1409 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1411 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1414 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
1416 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1418 /* Don't Insert RS Byte */
1419 if (state->insert_rs_byte) {
1421 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
1423 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1425 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1428 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1430 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1432 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1435 /* Mode = Parallel */
1436 if (state->enable_parallel)
1438 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1441 EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1444 /* EcOcRegIprInvMpg |= 0x00FF; */
1445 EcOcRegIprInvMpg &= (~(0x00FF));
1447 /* Invert Error ( we don't use the pin ) */
1448 /* EcOcRegIprInvMpg |= 0x0100; */
1449 EcOcRegIprInvMpg &= (~(0x0100));
1451 /* Invert Start ( we don't use the pin ) */
1452 /* EcOcRegIprInvMpg |= 0x0200; */
1453 EcOcRegIprInvMpg &= (~(0x0200));
1455 /* Invert Valid ( we don't use the pin ) */
1456 /* EcOcRegIprInvMpg |= 0x0400; */
1457 EcOcRegIprInvMpg &= (~(0x0400));
1460 /* EcOcRegIprInvMpg |= 0x0800; */
1461 EcOcRegIprInvMpg &= (~(0x0800));
1463 /* EcOcRegOcModeLop =0x05; */
1464 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1467 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1470 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1473 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1480 static int SetDeviceTypeId(struct drxd_state *state)
1486 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1489 /* TODO: why twice? */
1490 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1493 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
1497 state->diversity = 0;
1498 if (deviceId == 0) { /* on A2 only 3975 available */
1500 printk(KERN_INFO "DRX3975D-A2\n");
1503 printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
1506 state->diversity = 1;
1513 state->diversity = 1;
1528 /* Init Table selection */
1529 state->m_InitAtomicRead = DRXD_InitAtomicRead;
1530 state->m_InitSC = DRXD_InitSC;
1531 state->m_ResetECRAM = DRXD_ResetECRAM;
1532 if (state->type_A) {
1533 state->m_ResetCEFR = DRXD_ResetCEFR;
1534 state->m_InitFE_1 = DRXD_InitFEA2_1;
1535 state->m_InitFE_2 = DRXD_InitFEA2_2;
1536 state->m_InitCP = DRXD_InitCPA2;
1537 state->m_InitCE = DRXD_InitCEA2;
1538 state->m_InitEQ = DRXD_InitEQA2;
1539 state->m_InitEC = DRXD_InitECA2;
1540 if (load_firmware(state, DRX_FW_FILENAME_A2))
1543 state->m_ResetCEFR = NULL;
1544 state->m_InitFE_1 = DRXD_InitFEB1_1;
1545 state->m_InitFE_2 = DRXD_InitFEB1_2;
1546 state->m_InitCP = DRXD_InitCPB1;
1547 state->m_InitCE = DRXD_InitCEB1;
1548 state->m_InitEQ = DRXD_InitEQB1;
1549 state->m_InitEC = DRXD_InitECB1;
1550 if (load_firmware(state, DRX_FW_FILENAME_B1))
1553 if (state->diversity) {
1554 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1555 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1556 state->m_DisableDiversity = DRXD_DisableDiversity;
1557 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1558 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1559 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1560 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1562 state->m_InitDiversityFront = NULL;
1563 state->m_InitDiversityEnd = NULL;
1564 state->m_DisableDiversity = NULL;
1565 state->m_StartDiversityFront = NULL;
1566 state->m_StartDiversityEnd = NULL;
1567 state->m_DiversityDelay8MHZ = NULL;
1568 state->m_DiversityDelay6MHZ = NULL;
1574 static int CorrectSysClockDeviation(struct drxd_state *state)
1580 u32 sysClockInHz = 0;
1581 u32 sysClockFreq = 0; /* in kHz */
1582 s16 oscClockDeviation;
1586 /* Retrieve bandwidth and incr, sanity check */
1588 /* These accesses should be AtomicReadReg32, but that
1589 causes trouble (at least for diversity */
1590 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1593 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1597 if (state->type_A) {
1598 if ((nomincr - incr < -500) || (nomincr - incr > 500))
1601 if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
1605 switch (state->props.bandwidth_hz) {
1607 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1610 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1613 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1619 /* Compute new sysclock value
1620 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1622 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1623 sysClockFreq = (u32) (sysClockInHz / 1000);
1625 if ((sysClockInHz % 1000) > 500)
1628 /* Compute clock deviation in ppm */
1629 oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1631 (state->expected_sys_clock_freq)) *
1634 (state->expected_sys_clock_freq));
1636 Diff = oscClockDeviation - state->osc_clock_deviation;
1637 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
1638 if (Diff >= -200 && Diff <= 200) {
1639 state->sys_clock_freq = (u16) sysClockFreq;
1640 if (oscClockDeviation != state->osc_clock_deviation) {
1641 if (state->config.osc_deviation) {
1642 state->config.osc_deviation(state->priv,
1645 state->osc_clock_deviation =
1649 /* switch OFF SRMM scan in SC */
1650 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1653 /* overrule FE_IF internal value for
1654 proper re-locking */
1655 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1658 state->cscd_state = CSCD_SAVED;
1665 static int DRX_Stop(struct drxd_state *state)
1669 if (state->drxd_state != DRXD_STARTED)
1673 if (state->cscd_state != CSCD_SAVED) {
1675 status = DRX_GetLockStatus(state, &lock);
1680 status = StopOC(state);
1684 state->drxd_state = DRXD_STOPPED;
1686 status = ConfigureMPEGOutput(state, 0);
1690 if (state->type_A) {
1691 /* Stop relevant processors off the device */
1692 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1696 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1699 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1703 /* Stop all processors except HI & CC & FE */
1704 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1707 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1710 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1713 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1716 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1719 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1722 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1731 #if 0 /* Currently unused */
1732 static int SetOperationMode(struct drxd_state *state, int oMode)
1737 if (state->drxd_state != DRXD_STOPPED) {
1742 if (oMode == state->operation_mode) {
1747 if (oMode != OM_Default && !state->diversity) {
1753 case OM_DVBT_Diversity_Front:
1754 status = WriteTable(state, state->m_InitDiversityFront);
1756 case OM_DVBT_Diversity_End:
1757 status = WriteTable(state, state->m_InitDiversityEnd);
1760 /* We need to check how to
1761 get DRXD out of diversity */
1763 status = WriteTable(state, state->m_DisableDiversity);
1769 state->operation_mode = oMode;
1774 static int StartDiversity(struct drxd_state *state)
1780 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1781 status = WriteTable(state, state->m_StartDiversityFront);
1784 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
1785 status = WriteTable(state, state->m_StartDiversityEnd);
1788 if (state->props.bandwidth_hz == 8000000) {
1789 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1793 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1798 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1801 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1802 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1803 /* combining enabled */
1804 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1805 B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1806 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1807 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1815 static int SetFrequencyShift(struct drxd_state *state,
1816 u32 offsetFreq, int channelMirrored)
1818 int negativeShift = (state->tuner_mirrors == channelMirrored);
1820 /* Handle all mirroring
1822 * Note: ADC mirroring (aliasing) is implictly handled by limiting
1823 * feFsRegAddInc to 28 bits below
1824 * (if the result before masking is more than 28 bits, this means
1825 * that the ADC is mirroring.
1826 * The masking is in fact the aliasing of the ADC)
1830 /* Compute register value, unsigned computation */
1831 state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
1833 1 << 28, state->sys_clock_freq);
1834 /* Remove integer part */
1835 state->fe_fs_add_incr &= 0x0FFFFFFFL;
1837 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
1839 /* Save the frequency shift without tunerOffset compensation
1840 for CtrlGetChannel. */
1841 state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1842 1 << 28, state->sys_clock_freq);
1843 /* Remove integer part */
1844 state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1846 state->org_fe_fs_add_incr = ((1L << 28) -
1847 state->org_fe_fs_add_incr);
1849 return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1850 state->fe_fs_add_incr, 0);
1853 static int SetCfgNoiseCalibration(struct drxd_state *state,
1854 struct SNoiseCal *noiseCal)
1860 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1863 if (noiseCal->cpOpt) {
1864 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1866 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1867 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1871 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1875 if (!state->type_A) {
1876 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1879 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1888 static int DRX_Start(struct drxd_state *state, s32 off)
1890 struct dtv_frontend_properties *p = &state->props;
1893 u16 transmissionParams = 0;
1894 u16 operationMode = 0;
1895 u16 qpskTdTpsPwr = 0;
1896 u16 qam16TdTpsPwr = 0;
1897 u16 qam64TdTpsPwr = 0;
1900 int mirrorFreqSpect;
1902 u16 qpskSnCeGain = 0;
1903 u16 qam16SnCeGain = 0;
1904 u16 qam64SnCeGain = 0;
1905 u16 qpskIsGainMan = 0;
1906 u16 qam16IsGainMan = 0;
1907 u16 qam64IsGainMan = 0;
1908 u16 qpskIsGainExp = 0;
1909 u16 qam16IsGainExp = 0;
1910 u16 qam64IsGainExp = 0;
1911 u16 bandwidthParam = 0;
1914 off = (off - 500) / 1000;
1916 off = (off + 500) / 1000;
1919 if (state->drxd_state != DRXD_STOPPED)
1921 status = ResetECOD(state);
1924 if (state->type_A) {
1925 status = InitSC(state);
1929 status = InitFT(state);
1932 status = InitCP(state);
1935 status = InitCE(state);
1938 status = InitEQ(state);
1941 status = InitSC(state);
1946 /* Restore current IF & RF AGC settings */
1948 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1951 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1955 mirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1957 switch (p->transmission_mode) {
1958 default: /* Not set, detect it automatically */
1959 operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1960 fallthrough; /* try first guess DRX_FFTMODE_8K */
1961 case TRANSMISSION_MODE_8K:
1962 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1963 if (state->type_A) {
1964 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1972 case TRANSMISSION_MODE_2K:
1973 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1974 if (state->type_A) {
1975 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1985 switch (p->guard_interval) {
1986 case GUARD_INTERVAL_1_4:
1987 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
1989 case GUARD_INTERVAL_1_8:
1990 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
1992 case GUARD_INTERVAL_1_16:
1993 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
1995 case GUARD_INTERVAL_1_32:
1996 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
1998 default: /* Not set, detect it automatically */
1999 operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
2000 /* try first guess 1/4 */
2001 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2005 switch (p->hierarchy) {
2007 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2008 if (state->type_A) {
2009 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2012 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2016 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2017 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
2018 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
2021 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2023 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2025 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2028 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2030 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2032 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2037 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
2038 if (state->type_A) {
2039 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2042 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2046 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2047 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
2048 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
2051 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2053 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
2055 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
2058 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2060 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
2062 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
2066 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
2067 if (state->type_A) {
2068 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2071 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2075 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2076 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
2077 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
2080 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2082 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
2084 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
2087 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2089 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
2091 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
2094 case HIERARCHY_AUTO:
2096 /* Not set, detect it automatically, start with none */
2097 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2098 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2099 if (state->type_A) {
2100 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2103 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2107 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
2108 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2109 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2112 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
2114 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2116 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2119 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
2121 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2123 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2130 switch (p->modulation) {
2132 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2133 fallthrough; /* try first guess DRX_CONSTELLATION_QAM64 */
2135 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2136 if (state->type_A) {
2137 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2140 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2143 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2146 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2149 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2153 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2156 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2159 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2162 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2168 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2169 if (state->type_A) {
2170 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2173 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2176 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2179 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2182 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2186 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2189 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2192 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2195 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2202 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2203 if (state->type_A) {
2204 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2207 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2210 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2213 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2216 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2220 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2223 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2226 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2229 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2239 switch (DRX_CHANNEL_HIGH) {
2241 case DRX_CHANNEL_AUTO:
2242 case DRX_CHANNEL_LOW:
2243 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2244 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2246 case DRX_CHANNEL_HIGH:
2247 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2248 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2252 switch (p->code_rate_HP) {
2254 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2256 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2259 operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2262 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2264 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2267 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2269 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2272 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2274 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2277 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2279 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2285 /* First determine real bandwidth (Hz) */
2286 /* Also set delay for impulse noise cruncher (only A2) */
2287 /* Also set parameters for EC_OC fix, note
2288 EC_OC_REG_TMD_HIL_MAR is changed
2289 by SC for fix for some 8K,1/8 guard but is restored by
2292 switch (p->bandwidth_hz) {
2294 p->bandwidth_hz = 8000000;
2297 /* (64/7)*(8/8)*1000000 */
2298 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2301 status = Write16(state,
2302 FE_AG_REG_IND_DEL__A, 50, 0x0000);
2305 /* (64/7)*(7/8)*1000000 */
2306 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2307 bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
2308 status = Write16(state,
2309 FE_AG_REG_IND_DEL__A, 59, 0x0000);
2312 /* (64/7)*(6/8)*1000000 */
2313 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2314 bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
2315 status = Write16(state,
2316 FE_AG_REG_IND_DEL__A, 71, 0x0000);
2324 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2330 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2334 /* enable SLAVE mode in 2k 1/32 to
2335 prevent timing change glitches */
2336 if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2337 (p->guard_interval == GUARD_INTERVAL_1_32)) {
2339 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2342 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2344 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2349 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2353 if (state->cscd_state == CSCD_INIT) {
2354 /* switch on SRMM scan in SC */
2355 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2358 /* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
2359 state->cscd_state = CSCD_SET;
2362 /* Now compute FE_IF_REG_INCR */
2363 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2364 ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2365 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2366 (1ULL << 21), bandwidth) - (1 << 23);
2367 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2370 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2373 /* Bandwidth setting done */
2375 /* Mirror & frequency offset */
2376 SetFrequencyShift(state, off, mirrorFreqSpect);
2378 /* Start SC, write channel settings to SC */
2380 /* Enable SC after setting all other parameters */
2381 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2384 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2388 /* Write SC parameter registers, operation mode */
2390 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2391 SC_RA_RAM_OP_AUTO_GUARD__M |
2392 SC_RA_RAM_OP_AUTO_CONST__M |
2393 SC_RA_RAM_OP_AUTO_HIER__M |
2394 SC_RA_RAM_OP_AUTO_RATE__M);
2396 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2400 /* Start correct processes to get in lock */
2401 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2405 status = StartOC(state);
2409 if (state->operation_mode != OM_Default) {
2410 status = StartDiversity(state);
2415 state->drxd_state = DRXD_STARTED;
2421 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2423 u32 ulRfAgcOutputLevel = 0xffffffff;
2424 u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
2425 u32 ulRfAgcMinLevel = 0; /* Currently unused */
2426 u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2427 u32 ulRfAgcSpeed = 0; /* Currently unused */
2428 u32 ulRfAgcMode = 0; /*2; Off */
2429 u32 ulRfAgcR1 = 820;
2430 u32 ulRfAgcR2 = 2200;
2431 u32 ulRfAgcR3 = 150;
2432 u32 ulIfAgcMode = 0; /* Auto */
2433 u32 ulIfAgcOutputLevel = 0xffffffff;
2434 u32 ulIfAgcSettleLevel = 0xffffffff;
2435 u32 ulIfAgcMinLevel = 0xffffffff;
2436 u32 ulIfAgcMaxLevel = 0xffffffff;
2437 u32 ulIfAgcSpeed = 0xffffffff;
2438 u32 ulIfAgcR1 = 820;
2439 u32 ulIfAgcR2 = 2200;
2440 u32 ulIfAgcR3 = 150;
2441 u32 ulClock = state->config.clock;
2442 u32 ulSerialMode = 0;
2443 u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
2444 u32 ulHiI2cDelay = HI_I2C_DELAY;
2445 u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2446 u32 ulHiI2cPatch = 0;
2447 u32 ulEnvironment = APPENV_PORTABLE;
2448 u32 ulEnvironmentDiversity = APPENV_MOBILE;
2449 u32 ulIFFilter = IFFILTER_SAW;
2451 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2452 state->if_agc_cfg.outputLevel = 0;
2453 state->if_agc_cfg.settleLevel = 140;
2454 state->if_agc_cfg.minOutputLevel = 0;
2455 state->if_agc_cfg.maxOutputLevel = 1023;
2456 state->if_agc_cfg.speed = 904;
2458 if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2459 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2460 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
2463 if (ulIfAgcMode == 0 &&
2464 ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2465 ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2466 ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2467 ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2468 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2469 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2470 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2471 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2472 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
2475 state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2476 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2477 state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
2479 state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2480 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2481 state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
2483 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2484 /* rest of the RFAgcCfg structure currently unused */
2485 if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2486 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2487 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
2490 if (ulRfAgcMode == 0 &&
2491 ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2492 ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2493 ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2494 ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2495 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2496 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2497 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2498 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2499 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
2502 if (ulRfAgcMode == 2)
2503 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2505 if (ulEnvironment <= 2)
2506 state->app_env_default = (enum app_env)
2508 if (ulEnvironmentDiversity <= 2)
2509 state->app_env_diversity = (enum app_env)
2510 (ulEnvironmentDiversity);
2512 if (ulIFFilter == IFFILTER_DISCRETE) {
2513 /* discrete filter */
2514 state->noise_cal.cpOpt = 0;
2515 state->noise_cal.cpNexpOfs = 40;
2516 state->noise_cal.tdCal2k = -40;
2517 state->noise_cal.tdCal8k = -24;
2520 state->noise_cal.cpOpt = 1;
2521 state->noise_cal.cpNexpOfs = 0;
2522 state->noise_cal.tdCal2k = -21;
2523 state->noise_cal.tdCal8k = -24;
2525 state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2527 state->chip_adr = (state->config.demod_address << 1) | 1;
2528 switch (ulHiI2cPatch) {
2530 state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2533 state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2536 state->m_HiI2cPatch = NULL;
2539 /* modify tuner and clock attributes */
2540 state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
2541 /* expected system clock frequency in kHz */
2542 state->expected_sys_clock_freq = 48000;
2543 /* real system clock frequency in kHz */
2544 state->sys_clock_freq = 48000;
2545 state->osc_clock_freq = (u16) ulClock;
2546 state->osc_clock_deviation = 0;
2547 state->cscd_state = CSCD_INIT;
2548 state->drxd_state = DRXD_UNINITIALIZED;
2552 state->tuner_mirrors = 0;
2554 /* modify MPEG output attributes */
2555 state->insert_rs_byte = state->config.insert_rs_byte;
2556 state->enable_parallel = (ulSerialMode != 1);
2558 /* Timing div, 250ns/Psys */
2559 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2561 state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2562 ulHiI2cDelay) / 1000;
2563 /* Bridge delay, uses oscilator clock */
2564 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2565 state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2566 ulHiI2cBridgeDelay) / 1000;
2568 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2569 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2570 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2574 static int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
2579 if (state->init_done)
2582 CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2585 state->operation_mode = OM_Default;
2587 status = SetDeviceTypeId(state);
2591 /* Apply I2c address patch to B1 */
2592 if (!state->type_A && state->m_HiI2cPatch) {
2593 status = WriteTable(state, state->m_HiI2cPatch);
2598 if (state->type_A) {
2599 /* HI firmware patch for UIO readout,
2600 avoid clearing of result register */
2601 status = Write16(state, 0x43012D, 0x047f, 0);
2606 status = HI_ResetCommand(state);
2610 status = StopAllProcessors(state);
2613 status = InitCC(state);
2617 state->osc_clock_deviation = 0;
2619 if (state->config.osc_deviation)
2620 state->osc_clock_deviation =
2621 state->config.osc_deviation(state->priv, 0, 0);
2623 /* Handle clock deviation */
2625 s32 devA = (s32) (state->osc_clock_deviation) *
2626 (s32) (state->expected_sys_clock_freq);
2627 /* deviation in kHz */
2628 s32 deviation = (devA / (1000000L));
2629 /* rounding, signed */
2634 if ((devB * (devA % 1000000L) > 1000000L)) {
2636 deviation += (devB / 2);
2639 state->sys_clock_freq =
2640 (u16) ((state->expected_sys_clock_freq) +
2643 status = InitHI(state);
2646 status = InitAtomicRead(state);
2650 status = EnableAndResetMB(state);
2653 if (state->type_A) {
2654 status = ResetCEFR(state);
2659 status = DownloadMicrocode(state, fw, fw_size);
2663 status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2669 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
2670 SetCfgPga(state, 0); /* PGA = 0 dB */
2672 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2675 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2677 status = InitFE(state);
2680 status = InitFT(state);
2683 status = InitCP(state);
2686 status = InitCE(state);
2689 status = InitEQ(state);
2692 status = InitEC(state);
2695 status = InitSC(state);
2699 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2702 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2706 state->cscd_state = CSCD_INIT;
2707 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2710 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2714 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2715 (VERSION_MAJOR % 10)) << 24;
2716 driverVersion += (((VERSION_MINOR / 10) << 4) +
2717 (VERSION_MINOR % 10)) << 16;
2718 driverVersion += ((VERSION_PATCH / 1000) << 12) +
2719 ((VERSION_PATCH / 100) << 8) +
2720 ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
2722 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2726 status = StopOC(state);
2730 state->drxd_state = DRXD_STOPPED;
2731 state->init_done = 1;
2737 static int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
2739 DRX_GetLockStatus(state, pLockStatus);
2741 /*if (*pLockStatus&DRX_LOCK_MPEG) */
2742 if (*pLockStatus & DRX_LOCK_FEC) {
2743 ConfigureMPEGOutput(state, 1);
2744 /* Get status again, in case we have MPEG lock now */
2745 /*DRX_GetLockStatus(state, pLockStatus); */
2751 /****************************************************************************/
2752 /****************************************************************************/
2753 /****************************************************************************/
2755 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2757 struct drxd_state *state = fe->demodulator_priv;
2761 res = ReadIFAgc(state, &value);
2765 *strength = 0xffff - (value << 4);
2769 static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status)
2771 struct drxd_state *state = fe->demodulator_priv;
2774 DRXD_status(state, &lock);
2776 /* No MPEG lock in V255 firmware, bug ? */
2778 if (lock & DRX_LOCK_MPEG)
2779 *status |= FE_HAS_LOCK;
2781 if (lock & DRX_LOCK_FEC)
2782 *status |= FE_HAS_LOCK;
2784 if (lock & DRX_LOCK_FEC)
2785 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2786 if (lock & DRX_LOCK_DEMOD)
2787 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
2792 static int drxd_init(struct dvb_frontend *fe)
2794 struct drxd_state *state = fe->demodulator_priv;
2796 return DRXD_init(state, NULL, 0);
2799 static int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2801 struct drxd_state *state = fe->demodulator_priv;
2803 if (state->config.disable_i2c_gate_ctrl == 1)
2806 return DRX_ConfigureI2CBridge(state, onoff);
2809 static int drxd_get_tune_settings(struct dvb_frontend *fe,
2810 struct dvb_frontend_tune_settings *sets)
2812 sets->min_delay_ms = 10000;
2813 sets->max_drift = 0;
2814 sets->step_size = 0;
2818 static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
2824 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
2830 static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
2836 static int drxd_sleep(struct dvb_frontend *fe)
2838 struct drxd_state *state = fe->demodulator_priv;
2840 ConfigureMPEGOutput(state, 0);
2844 static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2846 return drxd_config_i2c(fe, enable);
2849 static int drxd_set_frontend(struct dvb_frontend *fe)
2851 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2852 struct drxd_state *state = fe->demodulator_priv;
2858 if (fe->ops.tuner_ops.set_params) {
2859 fe->ops.tuner_ops.set_params(fe);
2860 if (fe->ops.i2c_gate_ctrl)
2861 fe->ops.i2c_gate_ctrl(fe, 0);
2866 return DRX_Start(state, off);
2869 static void drxd_release(struct dvb_frontend *fe)
2871 struct drxd_state *state = fe->demodulator_priv;
2876 static const struct dvb_frontend_ops drxd_ops = {
2877 .delsys = { SYS_DVBT},
2879 .name = "Micronas DRXD DVB-T",
2880 .frequency_min_hz = 47125 * kHz,
2881 .frequency_max_hz = 855250 * kHz,
2882 .frequency_stepsize_hz = 166667,
2883 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2884 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2886 FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2888 FE_CAN_TRANSMISSION_MODE_AUTO |
2889 FE_CAN_GUARD_INTERVAL_AUTO |
2890 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
2892 .release = drxd_release,
2894 .sleep = drxd_sleep,
2895 .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2897 .set_frontend = drxd_set_frontend,
2898 .get_tune_settings = drxd_get_tune_settings,
2900 .read_status = drxd_read_status,
2901 .read_ber = drxd_read_ber,
2902 .read_signal_strength = drxd_read_signal_strength,
2903 .read_snr = drxd_read_snr,
2904 .read_ucblocks = drxd_read_ucblocks,
2907 struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2908 void *priv, struct i2c_adapter *i2c,
2911 struct drxd_state *state = NULL;
2913 state = kzalloc(sizeof(*state), GFP_KERNEL);
2917 state->ops = drxd_ops;
2919 state->config = *config;
2923 mutex_init(&state->mutex);
2925 if (Read16(state, 0, NULL, 0) < 0)
2928 state->frontend.ops = drxd_ops;
2929 state->frontend.demodulator_priv = state;
2930 ConfigureMPEGOutput(state, 0);
2931 /* add few initialization to allow gate control */
2932 CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2935 return &state->frontend;
2938 printk(KERN_ERR "drxd: not found\n");
2942 EXPORT_SYMBOL(drxd_attach);
2944 MODULE_DESCRIPTION("DRXD driver");
2945 MODULE_AUTHOR("Micronas");
2946 MODULE_LICENSE("GPL");