2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions are met:
8 * Redistributions of source code must retain the above copyright notice,
9 this list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice,
11 this list of conditions and the following disclaimer in the documentation
12 and/or other materials provided with the distribution.
13 * Neither the name of Trident Microsystems nor Hauppauge Computer Works
14 nor the names of its contributors may be used to endorse or promote
15 products derived from this software without specific prior written
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 POSSIBILITY OF SUCH DAMAGE.
30 DRXJ specific implementation of DRX driver
31 authors: Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen
33 The Linux DVB Driver for Micronas DRX39xx family (drx3933j) was
34 written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
36 This program is free software; you can redistribute it and/or modify
37 it under the terms of the GNU General Public License as published by
38 the Free Software Foundation; either version 2 of the License, or
39 (at your option) any later version.
41 This program is distributed in the hope that it will be useful,
42 but WITHOUT ANY WARRANTY; without even the implied warranty of
43 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
45 GNU General Public License for more details.
47 You should have received a copy of the GNU General Public License
48 along with this program; if not, write to the Free Software
49 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
52 /*-----------------------------------------------------------------------------
54 ----------------------------------------------------------------------------*/
56 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
58 #include <linux/module.h>
59 #include <linux/init.h>
60 #include <linux/string.h>
61 #include <linux/slab.h>
62 #include <asm/div64.h>
64 #include <media/dvb_frontend.h>
70 /*============================================================================*/
71 /*=== DEFINES ================================================================*/
72 /*============================================================================*/
74 #define DRX39XX_MAIN_FIRMWARE "/*(DEBLOBBED)*/"
77 * \brief Maximum u32 value.
80 #define MAX_U32 ((u32) (0xFFFFFFFFL))
83 /* Customer configurable hardware settings, etc */
84 #ifndef MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
85 #define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
88 #ifndef MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
89 #define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x02
92 #ifndef MPEG_OUTPUT_CLK_DRIVE_STRENGTH
93 #define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x06
96 #ifndef OOB_CRX_DRIVE_STRENGTH
97 #define OOB_CRX_DRIVE_STRENGTH 0x02
100 #ifndef OOB_DRX_DRIVE_STRENGTH
101 #define OOB_DRX_DRIVE_STRENGTH 0x02
103 /*** START DJCOMBO patches to DRXJ registermap constants *********************/
104 /*** registermap 200706071303 from drxj **************************************/
105 #define ATV_TOP_CR_AMP_TH_FM 0x0
106 #define ATV_TOP_CR_AMP_TH_L 0xA
107 #define ATV_TOP_CR_AMP_TH_LP 0xA
108 #define ATV_TOP_CR_AMP_TH_BG 0x8
109 #define ATV_TOP_CR_AMP_TH_DK 0x8
110 #define ATV_TOP_CR_AMP_TH_I 0x8
111 #define ATV_TOP_CR_CONT_CR_D_MN 0x18
112 #define ATV_TOP_CR_CONT_CR_D_FM 0x0
113 #define ATV_TOP_CR_CONT_CR_D_L 0x20
114 #define ATV_TOP_CR_CONT_CR_D_LP 0x20
115 #define ATV_TOP_CR_CONT_CR_D_BG 0x18
116 #define ATV_TOP_CR_CONT_CR_D_DK 0x18
117 #define ATV_TOP_CR_CONT_CR_D_I 0x18
118 #define ATV_TOP_CR_CONT_CR_I_MN 0x80
119 #define ATV_TOP_CR_CONT_CR_I_FM 0x0
120 #define ATV_TOP_CR_CONT_CR_I_L 0x80
121 #define ATV_TOP_CR_CONT_CR_I_LP 0x80
122 #define ATV_TOP_CR_CONT_CR_I_BG 0x80
123 #define ATV_TOP_CR_CONT_CR_I_DK 0x80
124 #define ATV_TOP_CR_CONT_CR_I_I 0x80
125 #define ATV_TOP_CR_CONT_CR_P_MN 0x4
126 #define ATV_TOP_CR_CONT_CR_P_FM 0x0
127 #define ATV_TOP_CR_CONT_CR_P_L 0x4
128 #define ATV_TOP_CR_CONT_CR_P_LP 0x4
129 #define ATV_TOP_CR_CONT_CR_P_BG 0x4
130 #define ATV_TOP_CR_CONT_CR_P_DK 0x4
131 #define ATV_TOP_CR_CONT_CR_P_I 0x4
132 #define ATV_TOP_CR_OVM_TH_MN 0xA0
133 #define ATV_TOP_CR_OVM_TH_FM 0x0
134 #define ATV_TOP_CR_OVM_TH_L 0xA0
135 #define ATV_TOP_CR_OVM_TH_LP 0xA0
136 #define ATV_TOP_CR_OVM_TH_BG 0xA0
137 #define ATV_TOP_CR_OVM_TH_DK 0xA0
138 #define ATV_TOP_CR_OVM_TH_I 0xA0
139 #define ATV_TOP_EQU0_EQU_C0_FM 0x0
140 #define ATV_TOP_EQU0_EQU_C0_L 0x3
141 #define ATV_TOP_EQU0_EQU_C0_LP 0x3
142 #define ATV_TOP_EQU0_EQU_C0_BG 0x7
143 #define ATV_TOP_EQU0_EQU_C0_DK 0x0
144 #define ATV_TOP_EQU0_EQU_C0_I 0x3
145 #define ATV_TOP_EQU1_EQU_C1_FM 0x0
146 #define ATV_TOP_EQU1_EQU_C1_L 0x1F6
147 #define ATV_TOP_EQU1_EQU_C1_LP 0x1F6
148 #define ATV_TOP_EQU1_EQU_C1_BG 0x197
149 #define ATV_TOP_EQU1_EQU_C1_DK 0x198
150 #define ATV_TOP_EQU1_EQU_C1_I 0x1F6
151 #define ATV_TOP_EQU2_EQU_C2_FM 0x0
152 #define ATV_TOP_EQU2_EQU_C2_L 0x28
153 #define ATV_TOP_EQU2_EQU_C2_LP 0x28
154 #define ATV_TOP_EQU2_EQU_C2_BG 0xC5
155 #define ATV_TOP_EQU2_EQU_C2_DK 0xB0
156 #define ATV_TOP_EQU2_EQU_C2_I 0x28
157 #define ATV_TOP_EQU3_EQU_C3_FM 0x0
158 #define ATV_TOP_EQU3_EQU_C3_L 0x192
159 #define ATV_TOP_EQU3_EQU_C3_LP 0x192
160 #define ATV_TOP_EQU3_EQU_C3_BG 0x12E
161 #define ATV_TOP_EQU3_EQU_C3_DK 0x18E
162 #define ATV_TOP_EQU3_EQU_C3_I 0x192
163 #define ATV_TOP_STD_MODE_MN 0x0
164 #define ATV_TOP_STD_MODE_FM 0x1
165 #define ATV_TOP_STD_MODE_L 0x0
166 #define ATV_TOP_STD_MODE_LP 0x0
167 #define ATV_TOP_STD_MODE_BG 0x0
168 #define ATV_TOP_STD_MODE_DK 0x0
169 #define ATV_TOP_STD_MODE_I 0x0
170 #define ATV_TOP_STD_VID_POL_MN 0x0
171 #define ATV_TOP_STD_VID_POL_FM 0x0
172 #define ATV_TOP_STD_VID_POL_L 0x2
173 #define ATV_TOP_STD_VID_POL_LP 0x2
174 #define ATV_TOP_STD_VID_POL_BG 0x0
175 #define ATV_TOP_STD_VID_POL_DK 0x0
176 #define ATV_TOP_STD_VID_POL_I 0x0
177 #define ATV_TOP_VID_AMP_MN 0x380
178 #define ATV_TOP_VID_AMP_FM 0x0
179 #define ATV_TOP_VID_AMP_L 0xF50
180 #define ATV_TOP_VID_AMP_LP 0xF50
181 #define ATV_TOP_VID_AMP_BG 0x380
182 #define ATV_TOP_VID_AMP_DK 0x394
183 #define ATV_TOP_VID_AMP_I 0x3D8
184 #define IQM_CF_OUT_ENA_OFDM__M 0x4
185 #define IQM_FS_ADJ_SEL_B_QAM 0x1
186 #define IQM_FS_ADJ_SEL_B_OFF 0x0
187 #define IQM_FS_ADJ_SEL_B_VSB 0x2
188 #define IQM_RC_ADJ_SEL_B_OFF 0x0
189 #define IQM_RC_ADJ_SEL_B_QAM 0x1
190 #define IQM_RC_ADJ_SEL_B_VSB 0x2
191 /*** END DJCOMBO patches to DRXJ registermap *********************************/
193 #include "drx_driver_version.h"
195 /* #define DRX_DEBUG */
200 /*-----------------------------------------------------------------------------
202 ----------------------------------------------------------------------------*/
204 /*-----------------------------------------------------------------------------
206 ----------------------------------------------------------------------------*/
207 #ifndef DRXJ_WAKE_UP_KEY
208 #define DRXJ_WAKE_UP_KEY (demod->my_i2c_dev_addr->i2c_addr)
212 * \def DRXJ_DEF_I2C_ADDR
213 * \brief Default I2C address of a demodulator instance.
215 #define DRXJ_DEF_I2C_ADDR (0x52)
218 * \def DRXJ_DEF_DEMOD_DEV_ID
219 * \brief Default device identifier of a demodultor instance.
221 #define DRXJ_DEF_DEMOD_DEV_ID (1)
224 * \def DRXJ_SCAN_TIMEOUT
225 * \brief Timeout value for waiting on demod lock during channel scan (millisec).
227 #define DRXJ_SCAN_TIMEOUT 1000
231 * \brief HI timing delay for I2C timing (in nano seconds)
233 * Used to compute HI_CFG_DIV
235 #define HI_I2C_DELAY 42
238 * \def HI_I2C_BRIDGE_DELAY
239 * \brief HI timing delay for I2C timing (in nano seconds)
241 * Used to compute HI_CFG_BDL
243 #define HI_I2C_BRIDGE_DELAY 750
246 * \brief Time Window for MER and SER Measurement in Units of Segment duration.
248 #define VSB_TOP_MEASUREMENT_PERIOD 64
249 #define SYMBOLS_PER_SEGMENT 832
252 * \brief bit rate and segment rate constants used for SER and BER.
254 /* values taken from the QAM microcode */
255 #define DRXJ_QAM_SL_SIG_POWER_QAM_UNKNOWN 0
256 #define DRXJ_QAM_SL_SIG_POWER_QPSK 32768
257 #define DRXJ_QAM_SL_SIG_POWER_QAM8 24576
258 #define DRXJ_QAM_SL_SIG_POWER_QAM16 40960
259 #define DRXJ_QAM_SL_SIG_POWER_QAM32 20480
260 #define DRXJ_QAM_SL_SIG_POWER_QAM64 43008
261 #define DRXJ_QAM_SL_SIG_POWER_QAM128 20992
262 #define DRXJ_QAM_SL_SIG_POWER_QAM256 43520
264 * \brief Min supported symbolrates.
266 #ifndef DRXJ_QAM_SYMBOLRATE_MIN
267 #define DRXJ_QAM_SYMBOLRATE_MIN (520000)
271 * \brief Max supported symbolrates.
273 #ifndef DRXJ_QAM_SYMBOLRATE_MAX
274 #define DRXJ_QAM_SYMBOLRATE_MAX (7233000)
278 * \def DRXJ_QAM_MAX_WAITTIME
279 * \brief Maximal wait time for QAM auto constellation in ms
281 #ifndef DRXJ_QAM_MAX_WAITTIME
282 #define DRXJ_QAM_MAX_WAITTIME 900
285 #ifndef DRXJ_QAM_FEC_LOCK_WAITTIME
286 #define DRXJ_QAM_FEC_LOCK_WAITTIME 150
289 #ifndef DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME
290 #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 200
294 * \def SCU status and results
297 #define DRX_SCU_READY 0
298 #define DRXJ_MAX_WAITTIME 100 /* ms */
299 #define FEC_RS_MEASUREMENT_PERIOD 12894 /* 1 sec */
300 #define FEC_RS_MEASUREMENT_PRESCALE 1 /* n sec */
303 * \def DRX_AUD_MAX_DEVIATION
304 * \brief Needed for calculation of prescale feature in AUD
306 #ifndef DRXJ_AUD_MAX_FM_DEVIATION
307 #define DRXJ_AUD_MAX_FM_DEVIATION 100 /* kHz */
311 * \brief Needed for calculation of NICAM prescale feature in AUD
313 #ifndef DRXJ_AUD_MAX_NICAM_PRESCALE
314 #define DRXJ_AUD_MAX_NICAM_PRESCALE (9) /* dB */
318 * \brief Needed for calculation of NICAM prescale feature in AUD
320 #ifndef DRXJ_AUD_MAX_WAITTIME
321 #define DRXJ_AUD_MAX_WAITTIME 250 /* ms */
324 /* ATV config changed flags */
325 #define DRXJ_ATV_CHANGED_COEF (0x00000001UL)
326 #define DRXJ_ATV_CHANGED_PEAK_FLT (0x00000008UL)
327 #define DRXJ_ATV_CHANGED_NOISE_FLT (0x00000010UL)
328 #define DRXJ_ATV_CHANGED_OUTPUT (0x00000020UL)
329 #define DRXJ_ATV_CHANGED_SIF_ATT (0x00000040UL)
332 #define DRX_UIO_MODE_FIRMWARE_SMA DRX_UIO_MODE_FIRMWARE0
333 #define DRX_UIO_MODE_FIRMWARE_SAW DRX_UIO_MODE_FIRMWARE1
336 * MICROCODE RELATED DEFINES
339 /* Magic word for checking correct Endianness of microcode data */
340 #define DRX_UCODE_MAGIC_WORD ((((u16)'H')<<8)+((u16)'L'))
342 /* CRC flag in ucode header, flags field. */
343 #define DRX_UCODE_CRC_FLAG (0x0001)
346 * Maximum size of buffer used to verify the microcode.
347 * Must be an even number
349 #define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE)
351 #if DRX_UCODE_MAX_BUF_SIZE & 1
352 #error DRX_UCODE_MAX_BUF_SIZE must be an even number
359 #define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \
360 (mode == DRX_POWER_MODE_10) || \
361 (mode == DRX_POWER_MODE_11) || \
362 (mode == DRX_POWER_MODE_12) || \
363 (mode == DRX_POWER_MODE_13) || \
364 (mode == DRX_POWER_MODE_14) || \
365 (mode == DRX_POWER_MODE_15) || \
366 (mode == DRX_POWER_MODE_16) || \
367 (mode == DRX_POWER_DOWN))
369 /* Pin safe mode macro */
370 #define DRXJ_PIN_SAFE_MODE 0x0000
371 /*============================================================================*/
372 /*=== GLOBAL VARIABLEs =======================================================*/
373 /*============================================================================*/
378 * \brief Temporary register definitions.
379 * (register definitions that are not yet available in register master)
382 /*****************************************************************************/
383 /* Audio block 0x103 is write only. To avoid shadowing in driver accessing */
384 /* RAM addresses directly. This must be READ ONLY to avoid problems. */
385 /* Writing to the interface addresses are more than only writing the RAM */
387 /*****************************************************************************/
389 * \brief RAM location of MODUS registers
391 #define AUD_DEM_RAM_MODUS_HI__A 0x10204A3
392 #define AUD_DEM_RAM_MODUS_HI__M 0xF000
394 #define AUD_DEM_RAM_MODUS_LO__A 0x10204A4
395 #define AUD_DEM_RAM_MODUS_LO__M 0x0FFF
398 * \brief RAM location of I2S config registers
400 #define AUD_DEM_RAM_I2S_CONFIG1__A 0x10204B1
401 #define AUD_DEM_RAM_I2S_CONFIG2__A 0x10204B2
404 * \brief RAM location of DCO config registers
406 #define AUD_DEM_RAM_DCO_B_HI__A 0x1020461
407 #define AUD_DEM_RAM_DCO_B_LO__A 0x1020462
408 #define AUD_DEM_RAM_DCO_A_HI__A 0x1020463
409 #define AUD_DEM_RAM_DCO_A_LO__A 0x1020464
412 * \brief RAM location of Threshold registers
414 #define AUD_DEM_RAM_NICAM_THRSHLD__A 0x102045A
415 #define AUD_DEM_RAM_A2_THRSHLD__A 0x10204BB
416 #define AUD_DEM_RAM_BTSC_THRSHLD__A 0x10204A6
419 * \brief RAM location of Carrier Threshold registers
421 #define AUD_DEM_RAM_CM_A_THRSHLD__A 0x10204AF
422 #define AUD_DEM_RAM_CM_B_THRSHLD__A 0x10204B0
425 * \brief FM Matrix register fix
427 #ifdef AUD_DEM_WR_FM_MATRIX__A
428 #undef AUD_DEM_WR_FM_MATRIX__A
430 #define AUD_DEM_WR_FM_MATRIX__A 0x105006F
432 /*============================================================================*/
434 * \brief Defines required for audio
436 #define AUD_VOLUME_ZERO_DB 115
437 #define AUD_VOLUME_DB_MIN -60
438 #define AUD_VOLUME_DB_MAX 12
439 #define AUD_CARRIER_STRENGTH_QP_0DB 0x4000
440 #define AUD_CARRIER_STRENGTH_QP_0DB_LOG10T100 421
441 #define AUD_MAX_AVC_REF_LEVEL 15
442 #define AUD_I2S_FREQUENCY_MAX 48000UL
443 #define AUD_I2S_FREQUENCY_MIN 12000UL
444 #define AUD_RDS_ARRAY_SIZE 18
447 * \brief Needed for calculation of prescale feature in AUD
449 #ifndef DRX_AUD_MAX_FM_DEVIATION
450 #define DRX_AUD_MAX_FM_DEVIATION (100) /* kHz */
454 * \brief Needed for calculation of NICAM prescale feature in AUD
456 #ifndef DRX_AUD_MAX_NICAM_PRESCALE
457 #define DRX_AUD_MAX_NICAM_PRESCALE (9) /* dB */
460 /*============================================================================*/
461 /* Values for I2S Master/Slave pin configurations */
462 #define SIO_PDR_I2S_CL_CFG_MODE__MASTER 0x0004
463 #define SIO_PDR_I2S_CL_CFG_DRIVE__MASTER 0x0008
464 #define SIO_PDR_I2S_CL_CFG_MODE__SLAVE 0x0004
465 #define SIO_PDR_I2S_CL_CFG_DRIVE__SLAVE 0x0000
467 #define SIO_PDR_I2S_DA_CFG_MODE__MASTER 0x0003
468 #define SIO_PDR_I2S_DA_CFG_DRIVE__MASTER 0x0008
469 #define SIO_PDR_I2S_DA_CFG_MODE__SLAVE 0x0003
470 #define SIO_PDR_I2S_DA_CFG_DRIVE__SLAVE 0x0008
472 #define SIO_PDR_I2S_WS_CFG_MODE__MASTER 0x0004
473 #define SIO_PDR_I2S_WS_CFG_DRIVE__MASTER 0x0008
474 #define SIO_PDR_I2S_WS_CFG_MODE__SLAVE 0x0004
475 #define SIO_PDR_I2S_WS_CFG_DRIVE__SLAVE 0x0000
477 /*============================================================================*/
478 /*=== REGISTER ACCESS MACROS =================================================*/
479 /*============================================================================*/
482 * This macro is used to create byte arrays for block writes.
483 * Block writes speed up I2C traffic between host and demod.
484 * The macro takes care of the required byte order in a 16 bits word.
485 * x -> lowbyte(x), highbyte(x)
487 #define DRXJ_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
488 ((u8)((((u16)x)>>8)&0xFF))
490 * This macro is used to convert byte array to 16 bit register value for block read.
491 * Block read speed up I2C traffic between host and demod.
492 * The macro takes care of the required byte order in a 16 bits word.
494 #define DRXJ_8TO16(x) ((u16) (x[0] | (x[1] << 8)))
496 /*============================================================================*/
497 /*=== MISC DEFINES ===========================================================*/
498 /*============================================================================*/
500 /*============================================================================*/
501 /*=== HI COMMAND RELATED DEFINES =============================================*/
502 /*============================================================================*/
505 * \brief General maximum number of retries for ucode command interfaces
507 #define DRXJ_MAX_RETRIES (100)
509 /*============================================================================*/
510 /*=== STANDARD RELATED MACROS ================================================*/
511 /*============================================================================*/
513 #define DRXJ_ISATVSTD(std) ((std == DRX_STANDARD_PAL_SECAM_BG) || \
514 (std == DRX_STANDARD_PAL_SECAM_DK) || \
515 (std == DRX_STANDARD_PAL_SECAM_I) || \
516 (std == DRX_STANDARD_PAL_SECAM_L) || \
517 (std == DRX_STANDARD_PAL_SECAM_LP) || \
518 (std == DRX_STANDARD_NTSC) || \
519 (std == DRX_STANDARD_FM))
521 #define DRXJ_ISQAMSTD(std) ((std == DRX_STANDARD_ITU_A) || \
522 (std == DRX_STANDARD_ITU_B) || \
523 (std == DRX_STANDARD_ITU_C) || \
524 (std == DRX_STANDARD_ITU_D))
526 /*-----------------------------------------------------------------------------
528 ----------------------------------------------------------------------------*/
530 * DRXJ DAP structures
533 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
536 u8 *data, u32 flags);
539 static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
542 u16 wdata, u16 *rdata);
544 static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
546 u16 *data, u32 flags);
548 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
550 u32 *data, u32 flags);
552 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
555 u8 *data, u32 flags);
557 static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
559 u16 data, u32 flags);
561 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
563 u32 data, u32 flags);
565 static struct drxj_data drxj_data_g = {
566 false, /* has_lna : true if LNA (aka PGA) present */
567 false, /* has_oob : true if OOB supported */
568 false, /* has_ntsc: true if NTSC supported */
569 false, /* has_btsc: true if BTSC supported */
570 false, /* has_smatx: true if SMA_TX pin is available */
571 false, /* has_smarx: true if SMA_RX pin is available */
572 false, /* has_gpio : true if GPIO pin is available */
573 false, /* has_irqn : true if IRQN pin is available */
574 0, /* mfx A1/A2/A... */
577 false, /* tuner mirrors RF signal */
578 /* standard/channel settings */
579 DRX_STANDARD_UNKNOWN, /* current standard */
580 DRX_CONSTELLATION_AUTO, /* constellation */
581 0, /* frequency in KHz */
582 DRX_BANDWIDTH_UNKNOWN, /* curr_bandwidth */
583 DRX_MIRROR_NO, /* mirror */
585 /* signal quality information: */
586 /* default values taken from the QAM Programming guide */
587 /* fec_bits_desired should not be less than 4000000 */
588 4000000, /* fec_bits_desired */
590 4, /* qam_vd_prescale */
591 0xFFFF, /* qamVDPeriod */
592 204 * 8, /* fec_rs_plen annex A */
593 1, /* fec_rs_prescale */
594 FEC_RS_MEASUREMENT_PERIOD, /* fec_rs_period */
595 true, /* reset_pkt_err_acc */
596 0, /* pkt_err_acc_start */
598 /* HI configuration */
599 0, /* hi_cfg_timing_div */
600 0, /* hi_cfg_bridge_delay */
601 0, /* hi_cfg_wake_up_key */
603 0, /* HICfgTimeout */
604 /* UIO configuration */
605 DRX_UIO_MODE_DISABLE, /* uio_sma_rx_mode */
606 DRX_UIO_MODE_DISABLE, /* uio_sma_tx_mode */
607 DRX_UIO_MODE_DISABLE, /* uioASELMode */
608 DRX_UIO_MODE_DISABLE, /* uio_irqn_mode */
610 0UL, /* iqm_fs_rate_ofs */
611 false, /* pos_image */
613 0UL, /* iqm_rc_rate_ofs */
614 /* AUD information */
615 /* false, * flagSetAUDdone */
616 /* false, * detectedRDS */
617 /* true, * flagASDRequest */
618 /* false, * flagHDevClear */
619 /* false, * flagHDevSet */
620 /* (u16) 0xFFF, * rdsLastCount */
622 /* ATV configuration */
623 0UL, /* flags cfg changes */
624 /* shadow of ATV_TOP_EQU0__A */
626 ATV_TOP_EQU0_EQU_C0_FM,
627 ATV_TOP_EQU0_EQU_C0_L,
628 ATV_TOP_EQU0_EQU_C0_LP,
629 ATV_TOP_EQU0_EQU_C0_BG,
630 ATV_TOP_EQU0_EQU_C0_DK,
631 ATV_TOP_EQU0_EQU_C0_I},
632 /* shadow of ATV_TOP_EQU1__A */
634 ATV_TOP_EQU1_EQU_C1_FM,
635 ATV_TOP_EQU1_EQU_C1_L,
636 ATV_TOP_EQU1_EQU_C1_LP,
637 ATV_TOP_EQU1_EQU_C1_BG,
638 ATV_TOP_EQU1_EQU_C1_DK,
639 ATV_TOP_EQU1_EQU_C1_I},
640 /* shadow of ATV_TOP_EQU2__A */
642 ATV_TOP_EQU2_EQU_C2_FM,
643 ATV_TOP_EQU2_EQU_C2_L,
644 ATV_TOP_EQU2_EQU_C2_LP,
645 ATV_TOP_EQU2_EQU_C2_BG,
646 ATV_TOP_EQU2_EQU_C2_DK,
647 ATV_TOP_EQU2_EQU_C2_I},
648 /* shadow of ATV_TOP_EQU3__A */
650 ATV_TOP_EQU3_EQU_C3_FM,
651 ATV_TOP_EQU3_EQU_C3_L,
652 ATV_TOP_EQU3_EQU_C3_LP,
653 ATV_TOP_EQU3_EQU_C3_BG,
654 ATV_TOP_EQU3_EQU_C3_DK,
655 ATV_TOP_EQU3_EQU_C3_I},
656 false, /* flag: true=bypass */
657 ATV_TOP_VID_PEAK__PRE, /* shadow of ATV_TOP_VID_PEAK__A */
658 ATV_TOP_NOISE_TH__PRE, /* shadow of ATV_TOP_NOISE_TH__A */
659 true, /* flag CVBS output enable */
660 false, /* flag SIF output enable */
661 DRXJ_SIF_ATTENUATION_0DB, /* current SIF att setting */
662 { /* qam_rf_agc_cfg */
663 DRX_STANDARD_ITU_B, /* standard */
664 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
665 0, /* output_level */
666 0, /* min_output_level */
667 0xFFFF, /* max_output_level */
672 { /* qam_if_agc_cfg */
673 DRX_STANDARD_ITU_B, /* standard */
674 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
675 0, /* output_level */
676 0, /* min_output_level */
677 0xFFFF, /* max_output_level */
679 0x0000, /* top (don't care) */
680 0x0000 /* c.o.c. (don't care) */
682 { /* vsb_rf_agc_cfg */
683 DRX_STANDARD_8VSB, /* standard */
684 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
685 0, /* output_level */
686 0, /* min_output_level */
687 0xFFFF, /* max_output_level */
689 0x0000, /* top (don't care) */
690 0x0000 /* c.o.c. (don't care) */
692 { /* vsb_if_agc_cfg */
693 DRX_STANDARD_8VSB, /* standard */
694 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
695 0, /* output_level */
696 0, /* min_output_level */
697 0xFFFF, /* max_output_level */
699 0x0000, /* top (don't care) */
700 0x0000 /* c.o.c. (don't care) */
704 { /* qam_pre_saw_cfg */
705 DRX_STANDARD_ITU_B, /* standard */
707 false /* use_pre_saw */
709 { /* vsb_pre_saw_cfg */
710 DRX_STANDARD_8VSB, /* standard */
712 false /* use_pre_saw */
715 /* Version information */
718 "01234567890", /* human readable version microcode */
719 "01234567890" /* human readable version device specific code */
722 { /* struct drx_version for microcode */
730 { /* struct drx_version for device specific code */
740 { /* struct drx_version_list for microcode */
741 (struct drx_version *) (NULL),
742 (struct drx_version_list *) (NULL)
744 { /* struct drx_version_list for device specific code */
745 (struct drx_version *) (NULL),
746 (struct drx_version_list *) (NULL)
750 false, /* smart_ant_inverted */
751 /* Tracking filter setting for OOB */
761 false, /* oob_power_on */
762 0, /* mpeg_ts_static_bitrate */
763 false, /* disable_te_ihandling */
764 false, /* bit_reverse_mpeg_outout */
765 DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO, /* mpeg_output_clock_rate */
766 DRXJ_MPEG_START_WIDTH_1CLKCYC, /* mpeg_start_width */
768 /* Pre SAW & Agc configuration for ATV */
770 DRX_STANDARD_NTSC, /* standard */
772 true /* use_pre_saw */
775 DRX_STANDARD_NTSC, /* standard */
776 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
777 0, /* output_level */
778 0, /* min_output_level (d.c.) */
779 0, /* max_output_level (d.c.) */
782 4000 /* cut-off current */
785 DRX_STANDARD_NTSC, /* standard */
786 DRX_AGC_CTRL_AUTO, /* ctrl_mode */
787 0, /* output_level */
788 0, /* min_output_level (d.c.) */
789 0, /* max_output_level (d.c.) */
792 0 /* c.o.c. (d.c.) */
794 140, /* ATV PGA config */
795 0, /* curr_symbol_rate */
797 false, /* pdr_safe_mode */
798 SIO_PDR_GPIO_CFG__PRE, /* pdr_safe_restore_val_gpio */
799 SIO_PDR_VSYNC_CFG__PRE, /* pdr_safe_restore_val_v_sync */
800 SIO_PDR_SMA_RX_CFG__PRE, /* pdr_safe_restore_val_sma_rx */
801 SIO_PDR_SMA_TX_CFG__PRE, /* pdr_safe_restore_val_sma_tx */
804 DRXJ_OOB_LO_POW_MINUS10DB, /* oob_lo_pow */
806 false /* aud_data, only first member */
811 * \var drxj_default_addr_g
812 * \brief Default I2C address and device identifier.
814 static struct i2c_device_addr drxj_default_addr_g = {
815 DRXJ_DEF_I2C_ADDR, /* i2c address */
816 DRXJ_DEF_DEMOD_DEV_ID /* device id */
820 * \var drxj_default_comm_attr_g
821 * \brief Default common attributes of a drxj demodulator instance.
823 static struct drx_common_attr drxj_default_comm_attr_g = {
824 NULL, /* ucode file */
825 true, /* ucode verify switch */
826 {0}, /* version record */
828 44000, /* IF in kHz in case no tuner instance is used */
829 (151875 - 0), /* system clock frequency in kHz */
830 0, /* oscillator frequency kHz */
831 0, /* oscillator deviation in ppm, signed */
832 false, /* If true mirror frequency spectrum */
834 /* MPEG output configuration */
835 true, /* If true, enable MPEG output */
836 false, /* If true, insert RS byte */
837 false, /* If true, parallel out otherwise serial */
838 false, /* If true, invert DATA signals */
839 false, /* If true, invert ERR signal */
840 false, /* If true, invert STR signals */
841 false, /* If true, invert VAL signals */
842 false, /* If true, invert CLK signals */
843 true, /* If true, static MPEG clockrate will
844 be used, otherwise clockrate will
845 adapt to the bitrate of the TS */
846 19392658UL, /* Maximum bitrate in b/s in case
847 static clockrate is selected */
848 DRX_MPEG_STR_WIDTH_1 /* MPEG Start width in clock cycles */
850 /* Initilisations below can be omitted, they require no user input and
851 are initially 0, NULL or false. The compiler will initialize them to these
852 values when omitted. */
853 false, /* is_opened */
856 NULL, /* no scan params yet */
857 0, /* current scan index */
858 0, /* next scan frequency */
859 false, /* scan ready flag */
860 0, /* max channels to scan */
861 0, /* nr of channels scanned */
862 NULL, /* default scan function */
863 NULL, /* default context pointer */
864 0, /* millisec to wait for demod lock */
865 DRXJ_DEMOD_LOCK, /* desired lock */
868 /* Power management */
872 1, /* nr of I2C port to which tuner is */
873 0L, /* minimum RF input frequency, in kHz */
874 0L, /* maximum RF input frequency, in kHz */
875 false, /* Rf Agc Polarity */
876 false, /* If Agc Polarity */
877 false, /* tuner slow mode */
879 { /* current channel (all 0) */
880 0UL /* channel.frequency */
882 DRX_STANDARD_UNKNOWN, /* current standard */
883 DRX_STANDARD_UNKNOWN, /* previous standard */
884 DRX_STANDARD_UNKNOWN, /* di_cache_standard */
885 false, /* use_bootloader */
886 0UL, /* capabilities */
891 * \var drxj_default_demod_g
892 * \brief Default drxj demodulator instance.
894 static struct drx_demod_instance drxj_default_demod_g = {
895 &drxj_default_addr_g, /* i2c address & device id */
896 &drxj_default_comm_attr_g, /* demod common attributes */
897 &drxj_data_g /* demod device specific attributes */
901 * \brief Default audio data structure for DRK demodulator instance.
903 * This structure is DRXK specific.
906 static struct drx_aud_data drxj_default_aud_data_g = {
907 false, /* audio_is_active */
908 DRX_AUD_STANDARD_AUTO, /* audio_standard */
912 false, /* output_enable */
913 48000, /* frequency */
914 DRX_I2S_MODE_MASTER, /* mode */
915 DRX_I2S_WORDLENGTH_32, /* word_length */
916 DRX_I2S_POLARITY_RIGHT, /* polarity */
917 DRX_I2S_FORMAT_WS_WITH_DATA /* format */
923 DRX_AUD_AVC_OFF, /* avc_mode */
924 0, /* avc_ref_level */
925 DRX_AUD_AVC_MAX_GAIN_12DB, /* avc_max_gain */
926 DRX_AUD_AVC_MAX_ATTEN_24DB, /* avc_max_atten */
927 0, /* strength_left */
928 0 /* strength_right */
930 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON, /* auto_sound */
942 DRX_NO_CARRIER_NOISE, /* opt */
949 DRX_NO_CARRIER_MUTE, /* opt */
957 DRX_AUD_SRC_STEREO_OR_A, /* source_i2s */
958 DRX_AUD_I2S_MATRIX_STEREO, /* matrix_i2s */
959 DRX_AUD_FM_MATRIX_SOUND_A /* matrix_fm */
961 DRX_AUD_DEVIATION_NORMAL, /* deviation */
962 DRX_AUD_AVSYNC_OFF, /* av_sync */
966 DRX_AUD_MAX_FM_DEVIATION, /* fm_deviation */
967 DRX_AUD_MAX_NICAM_PRESCALE /* nicam_gain */
969 DRX_AUD_FM_DEEMPH_75US, /* deemph */
970 DRX_BTSC_STEREO, /* btsc_detect */
971 0, /* rds_data_counter */
972 false /* rds_data_present */
975 /*-----------------------------------------------------------------------------
977 ----------------------------------------------------------------------------*/
996 /*============================================================================*/
997 /*=== MICROCODE RELATED STRUCTURES ===========================================*/
998 /*============================================================================*/
1001 * struct drxu_code_block_hdr - Structure of the microcode block headers
1003 * @addr: Destination address of the data in this block
1004 * @size: Size of the block data following this header counted in
1006 * @CRC: CRC value of the data block, only valid if CRC flag is
1009 struct drxu_code_block_hdr {
1016 /*-----------------------------------------------------------------------------
1018 ----------------------------------------------------------------------------*/
1019 /* Some prototypes */
1021 hi_command(struct i2c_device_addr *dev_addr,
1022 const struct drxj_hi_cmd *cmd, u16 *result);
1025 ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat);
1028 ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode);
1030 static int power_down_aud(struct drx_demod_instance *demod);
1033 ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw);
1036 ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain);
1038 /*============================================================================*/
1039 /*============================================================================*/
1040 /*== HELPER FUNCTIONS ==*/
1041 /*============================================================================*/
1042 /*============================================================================*/
1045 /*============================================================================*/
1048 * \fn u32 frac28(u32 N, u32 D)
1049 * \brief Compute: (1<<28)*N/D
1052 * \return (1<<28)*N/D
1053 * This function is used to avoid floating-point calculations as they may
1054 * not be present on the target platform.
1056 * frac28 performs an unsigned 28/28 bits division to 32-bit fixed point
1057 * fraction used for setting the Frequency Shifter registers.
1058 * N and D can hold numbers up to width: 28-bits.
1059 * The 4 bits integer part and the 28 bits fractional part are calculated.
1061 * Usage condition: ((1<<28)*n)/d < ((1<<32)-1) => (n/d) < 15.999
1063 * N: 0...(1<<28)-1 = 268435454
1067 static u32 frac28(u32 N, u32 D)
1073 R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */
1074 Q1 = N / D; /* integer part, only the 4 least significant bits
1075 will be visible in the result */
1077 /* division using radix 16, 7 nibbles in the result */
1078 for (i = 0; i < 7; i++) {
1079 Q1 = (Q1 << 4) | R0 / D;
1090 * \fn u32 log1_times100( u32 x)
1091 * \brief Compute: 100*log10(x)
1093 * \return 100*log10(x)
1096 * = 100*(log2(x)/log2(10)))
1097 * = (100*(2^15)*log2(x))/((2^15)*log2(10))
1098 * = ((200*(2^15)*log2(x))/((2^15)*log2(10)))/2
1099 * = ((200*(2^15)*(log2(x/y)+log2(y)))/((2^15)*log2(10)))/2
1100 * = ((200*(2^15)*log2(x/y))+(200*(2^15)*log2(y)))/((2^15)*log2(10)))/2
1102 * where y = 2^k and 1<= (x/y) < 2
1105 static u32 log1_times100(u32 x)
1107 static const u8 scale = 15;
1108 static const u8 index_width = 5;
1110 log2lut[n] = (1<<scale) * 200 * log2( 1.0 + ( (1.0/(1<<INDEXWIDTH)) * n ))
1111 0 <= n < ((1<<INDEXWIDTH)+1)
1114 static const u32 log2lut[] = {
1116 290941, /* 290941.300628 */
1117 573196, /* 573196.476418 */
1118 847269, /* 847269.179851 */
1119 1113620, /* 1113620.489452 */
1120 1372674, /* 1372673.576986 */
1121 1624818, /* 1624817.752104 */
1122 1870412, /* 1870411.981536 */
1123 2109788, /* 2109787.962654 */
1124 2343253, /* 2343252.817465 */
1125 2571091, /* 2571091.461923 */
1126 2793569, /* 2793568.696416 */
1127 3010931, /* 3010931.055901 */
1128 3223408, /* 3223408.452106 */
1129 3431216, /* 3431215.635215 */
1130 3634553, /* 3634553.498355 */
1131 3833610, /* 3833610.244726 */
1132 4028562, /* 4028562.434393 */
1133 4219576, /* 4219575.925308 */
1134 4406807, /* 4406806.721144 */
1135 4590402, /* 4590401.736809 */
1136 4770499, /* 4770499.491025 */
1137 4947231, /* 4947230.734179 */
1138 5120719, /* 5120719.018555 */
1139 5291081, /* 5291081.217197 */
1140 5458428, /* 5458427.996830 */
1141 5622864, /* 5622864.249668 */
1142 5784489, /* 5784489.488298 */
1143 5943398, /* 5943398.207380 */
1144 6099680, /* 6099680.215452 */
1145 6253421, /* 6253420.939751 */
1146 6404702, /* 6404701.706649 */
1147 6553600, /* 6553600.000000 */
1159 /* Scale x (normalize) */
1160 /* computing y in log(x/y) = log(x) - log(y) */
1161 if ((x & (((u32) (-1)) << (scale + 1))) == 0) {
1162 for (k = scale; k > 0; k--) {
1163 if (x & (((u32) 1) << scale))
1168 for (k = scale; k < 31; k++) {
1169 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
1175 Now x has binary point between bit[scale] and bit[scale-1]
1176 and 1.0 <= x < 2.0 */
1178 /* correction for division: log(x) = log(x/y)+log(y) */
1179 y = k * ((((u32) 1) << scale) * 200);
1181 /* remove integer part */
1182 x &= ((((u32) 1) << scale) - 1);
1184 i = (u8) (x >> (scale - index_width));
1185 /* compute delta (x-a) */
1186 d = x & ((((u32) 1) << (scale - index_width)) - 1);
1187 /* compute log, multiplication ( d* (.. )) must be within range ! */
1189 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - index_width));
1190 /* Conver to log10() */
1191 y /= 108853; /* (log2(10) << scale) */
1202 * \fn u32 frac_times1e6( u16 N, u32 D)
1203 * \brief Compute: (N/D) * 1000000.
1204 * \param N nominator 16-bits.
1205 * \param D denominator 32-bits.
1207 * \retval ((N/D) * 1000000), 32 bits
1211 static u32 frac_times1e6(u32 N, u32 D)
1217 frac = (N * 1000000) / D
1218 To let it fit in a 32 bits computation:
1219 frac = (N * (1000000 >> 4)) / (D >> 4)
1220 This would result in a problem in case D < 16 (div by 0).
1221 So we do it more elaborate as shown below.
1223 frac = (((u32) N) * (1000000 >> 4)) / D;
1225 remainder = (((u32) N) * (1000000 >> 4)) % D;
1227 frac += remainder / D;
1228 remainder = remainder % D;
1229 if ((remainder * 2) > D)
1235 /*============================================================================*/
1239 * \brief Values for NICAM prescaler gain. Computed from dB to integer
1240 * and rounded. For calc used formula: 16*10^(prescaleGain[dB]/20).
1244 /* Currently, unused as we lack support for analog TV */
1245 static const u16 nicam_presc_table_val[43] = {
1246 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4,
1247 5, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16,
1248 18, 20, 23, 25, 28, 32, 36, 40, 45,
1249 51, 57, 64, 71, 80, 90, 101, 113, 127
1253 /*============================================================================*/
1254 /*== END HELPER FUNCTIONS ==*/
1255 /*============================================================================*/
1257 /*============================================================================*/
1258 /*============================================================================*/
1259 /*== DRXJ DAP FUNCTIONS ==*/
1260 /*============================================================================*/
1261 /*============================================================================*/
1264 This layer takes care of some device specific register access protocols:
1265 -conversion to short address format
1266 -access to audio block
1267 This layer is placed between the drx_dap_fasi and the rest of the drxj
1268 specific implementation. This layer can use address map knowledge whereas
1269 dap_fasi may not use memory map knowledge.
1271 * For audio currently only 16 bits read and write register access is
1272 supported. More is not needed. RMW and 32 or 8 bit access on audio
1273 registers will have undefined behaviour. Flags (RMW, CRC reset, broadcast
1274 single/multi master) will be ignored.
1276 TODO: check ignoring single/multimaster is ok for AUD access ?
1279 #define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false)
1280 #define DRXJ_DAP_AUDTRIF_TIMEOUT 80 /* millisec */
1281 /*============================================================================*/
1284 * \fn bool is_handled_by_aud_tr_if( u32 addr )
1285 * \brief Check if this address is handled by the audio token ring interface.
1288 * \retval true Yes, handled by audio token ring interface
1289 * \retval false No, not handled by audio token ring interface
1293 bool is_handled_by_aud_tr_if(u32 addr)
1295 bool retval = false;
1297 if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) &&
1298 (DRXDAP_FASI_ADDR2BANK(addr) > 1) &&
1299 (DRXDAP_FASI_ADDR2BANK(addr) < 6)) {
1306 /*============================================================================*/
1308 int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
1311 struct i2c_device_addr *r_dev_addr,
1312 u16 r_count, u8 *r_data)
1314 struct drx39xxj_state *state;
1315 struct i2c_msg msg[2];
1316 unsigned int num_msgs;
1318 if (w_dev_addr == NULL) {
1320 state = r_dev_addr->user_data;
1321 msg[0].addr = r_dev_addr->i2c_addr >> 1;
1322 msg[0].flags = I2C_M_RD;
1323 msg[0].buf = r_data;
1324 msg[0].len = r_count;
1326 } else if (r_dev_addr == NULL) {
1328 state = w_dev_addr->user_data;
1329 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1332 msg[0].len = w_count;
1335 /* Both write and read */
1336 state = w_dev_addr->user_data;
1337 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1340 msg[0].len = w_count;
1341 msg[1].addr = r_dev_addr->i2c_addr >> 1;
1342 msg[1].flags = I2C_M_RD;
1343 msg[1].buf = r_data;
1344 msg[1].len = r_count;
1348 if (state->i2c == NULL) {
1349 pr_err("i2c was zero, aborting\n");
1352 if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
1353 pr_warn("drx3933: I2C write/read failed\n");
1358 if (w_dev_addr == NULL || r_dev_addr == NULL)
1361 state = w_dev_addr->user_data;
1363 if (state->i2c == NULL)
1366 msg[0].addr = w_dev_addr->i2c_addr;
1369 msg[0].len = w_count;
1370 msg[1].addr = r_dev_addr->i2c_addr;
1371 msg[1].flags = I2C_M_RD;
1372 msg[1].buf = r_data;
1373 msg[1].len = r_count;
1376 pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
1377 w_dev_addr->i2c_addr, state->i2c, w_count, r_count);
1379 if (i2c_transfer(state->i2c, msg, 2) != 2) {
1380 pr_warn("drx3933: I2C write/read failed\n");
1387 /*============================================================================*/
1389 /*****************************
1391 * int drxdap_fasi_read_block (
1392 * struct i2c_device_addr *dev_addr, -- address of I2C device
1393 * u32 addr, -- address of chip register/memory
1394 * u16 datasize, -- number of bytes to read
1395 * u8 *data, -- data to receive
1396 * u32 flags) -- special device flags
1398 * Read block data from chip address. Because the chip is word oriented,
1399 * the number of bytes to read must be even.
1401 * Make sure that the buffer to receive the data is large enough.
1403 * Although this function expects an even number of bytes, it is still byte
1404 * oriented, and the data read back is NOT translated to the endianness of
1405 * the target platform.
1408 * - 0 if reading was successful
1409 * in that case: data read is in *data.
1410 * - -EIO if anything went wrong
1412 ******************************/
1414 static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
1417 u8 *data, u32 flags)
1422 u16 overhead_size = 0;
1424 /* Check parameters ******************************************************* */
1425 if (dev_addr == NULL)
1428 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1429 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1431 if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1432 ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
1433 DRXDAP_FASI_LONG_FORMAT(addr)) ||
1434 (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
1435 ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
1439 /* ReadModifyWrite & mode flag bits are not allowed */
1440 flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
1441 #if DRXDAP_SINGLE_MASTER
1442 flags |= DRXDAP_FASI_SINGLE_MASTER;
1445 /* Read block from I2C **************************************************** */
1447 u16 todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ?
1448 datasize : DRXDAP_MAX_RCHUNKSIZE);
1452 addr &= ~DRXDAP_FASI_FLAGS;
1455 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1456 /* short format address preferred but long format otherwise */
1457 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1459 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1460 buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1461 buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1462 buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1463 buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1465 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1468 #if (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1)
1469 buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1471 (u8) (((addr >> 16) & 0x0F) |
1472 ((addr >> 18) & 0xF0));
1474 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED == 1) && (DRXDAPFASI_SHORT_ADDR_ALLOWED == 1))
1478 #if DRXDAP_SINGLE_MASTER
1480 * In single master mode, split the read and write actions.
1481 * No special action is needed for write chunks here.
1483 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf,
1486 rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data);
1488 /* In multi master mode, do everything in one RW action */
1489 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,
1493 addr += (todo >> 1);
1495 } while (datasize && rc == 0);
1501 /*****************************
1503 * int drxdap_fasi_read_reg16 (
1504 * struct i2c_device_addr *dev_addr, -- address of I2C device
1505 * u32 addr, -- address of chip register/memory
1506 * u16 *data, -- data to receive
1507 * u32 flags) -- special device flags
1509 * Read one 16-bit register or memory location. The data received back is
1510 * converted back to the target platform's endianness.
1513 * - 0 if reading was successful
1514 * in that case: read data is at *data
1515 * - -EIO if anything went wrong
1517 ******************************/
1519 static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr,
1521 u16 *data, u32 flags)
1523 u8 buf[sizeof(*data)];
1529 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1530 *data = buf[0] + (((u16) buf[1]) << 8);
1534 /*****************************
1536 * int drxdap_fasi_read_reg32 (
1537 * struct i2c_device_addr *dev_addr, -- address of I2C device
1538 * u32 addr, -- address of chip register/memory
1539 * u32 *data, -- data to receive
1540 * u32 flags) -- special device flags
1542 * Read one 32-bit register or memory location. The data received back is
1543 * converted back to the target platform's endianness.
1546 * - 0 if reading was successful
1547 * in that case: read data is at *data
1548 * - -EIO if anything went wrong
1550 ******************************/
1552 static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
1554 u32 *data, u32 flags)
1556 u8 buf[sizeof(*data)];
1562 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1563 *data = (((u32) buf[0]) << 0) +
1564 (((u32) buf[1]) << 8) +
1565 (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1569 /*****************************
1571 * int drxdap_fasi_write_block (
1572 * struct i2c_device_addr *dev_addr, -- address of I2C device
1573 * u32 addr, -- address of chip register/memory
1574 * u16 datasize, -- number of bytes to read
1575 * u8 *data, -- data to receive
1576 * u32 flags) -- special device flags
1578 * Write block data to chip address. Because the chip is word oriented,
1579 * the number of bytes to write must be even.
1581 * Although this function expects an even number of bytes, it is still byte
1582 * oriented, and the data being written is NOT translated from the endianness of
1583 * the target platform.
1586 * - 0 if writing was successful
1587 * - -EIO if anything went wrong
1589 ******************************/
1591 static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
1594 u8 *data, u32 flags)
1596 u8 buf[DRXDAP_MAX_WCHUNKSIZE];
1599 u16 overhead_size = 0;
1602 /* Check parameters ******************************************************* */
1603 if (dev_addr == NULL)
1606 overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
1607 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1609 if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1610 ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
1611 DRXDAP_FASI_LONG_FORMAT(addr)) ||
1612 (overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
1613 ((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1))
1616 flags &= DRXDAP_FASI_FLAGS;
1617 flags &= ~DRXDAP_FASI_MODEFLAGS;
1618 #if DRXDAP_SINGLE_MASTER
1619 flags |= DRXDAP_FASI_SINGLE_MASTER;
1622 /* Write block to I2C ***************************************************** */
1623 block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1;
1628 /* Buffer device address */
1629 addr &= ~DRXDAP_FASI_FLAGS;
1631 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1632 /* short format address preferred but long format otherwise */
1633 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1635 #if ((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1)
1636 buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1637 buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1638 buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1639 buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1641 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1644 #if ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1)
1645 buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1647 (u8) (((addr >> 16) & 0x0F) |
1648 ((addr >> 18) & 0xF0));
1650 #if (((DRXDAPFASI_LONG_ADDR_ALLOWED) == 1) && ((DRXDAPFASI_SHORT_ADDR_ALLOWED) == 1))
1655 In single master mode block_size can be 0. In such a case this I2C
1656 sequense will be visible: (1) write address {i2c addr,
1657 4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
1658 (3) write address (4) write data etc...
1659 Address must be rewritten because HI is reset after data transport and
1662 todo = (block_size < datasize ? block_size : datasize);
1664 u16 overhead_size_i2c_addr = 0;
1665 u16 data_block_size = 0;
1667 overhead_size_i2c_addr =
1668 (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1);
1670 (DRXDAP_MAX_WCHUNKSIZE - overhead_size_i2c_addr) & ~1;
1672 /* write device address */
1673 st = drxbsp_i2c_write_read(dev_addr,
1676 (struct i2c_device_addr *)(NULL),
1679 if ((st != 0) && (first_err == 0)) {
1680 /* at the end, return the first error encountered */
1686 datasize ? data_block_size : datasize);
1688 memcpy(&buf[bufx], data, todo);
1689 /* write (address if can do and) data */
1690 st = drxbsp_i2c_write_read(dev_addr,
1691 (u16) (bufx + todo),
1693 (struct i2c_device_addr *)(NULL),
1696 if ((st != 0) && (first_err == 0)) {
1697 /* at the end, return the first error encountered */
1702 addr += (todo >> 1);
1708 /*****************************
1710 * int drxdap_fasi_write_reg16 (
1711 * struct i2c_device_addr *dev_addr, -- address of I2C device
1712 * u32 addr, -- address of chip register/memory
1713 * u16 data, -- data to send
1714 * u32 flags) -- special device flags
1716 * Write one 16-bit register or memory location. The data being written is
1717 * converted from the target platform's endianness to little endian.
1720 * - 0 if writing was successful
1721 * - -EIO if anything went wrong
1723 ******************************/
1725 static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr,
1727 u16 data, u32 flags)
1729 u8 buf[sizeof(data)];
1731 buf[0] = (u8) ((data >> 0) & 0xFF);
1732 buf[1] = (u8) ((data >> 8) & 0xFF);
1734 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1737 /*****************************
1739 * int drxdap_fasi_read_modify_write_reg16 (
1740 * struct i2c_device_addr *dev_addr, -- address of I2C device
1741 * u32 waddr, -- address of chip register/memory
1742 * u32 raddr, -- chip address to read back from
1743 * u16 wdata, -- data to send
1744 * u16 *rdata) -- data to receive back
1746 * Write 16-bit data, then read back the original contents of that location.
1747 * Requires long addressing format to be allowed.
1749 * Before sending data, the data is converted to little endian. The
1750 * data received back is converted back to the target platform's endianness.
1752 * WARNING: This function is only guaranteed to work if there is one
1753 * master on the I2C bus.
1756 * - 0 if reading was successful
1757 * in that case: read back data is at *rdata
1758 * - -EIO if anything went wrong
1760 ******************************/
1762 static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
1765 u16 wdata, u16 *rdata)
1769 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1773 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);
1775 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);
1781 /*****************************
1783 * int drxdap_fasi_write_reg32 (
1784 * struct i2c_device_addr *dev_addr, -- address of I2C device
1785 * u32 addr, -- address of chip register/memory
1786 * u32 data, -- data to send
1787 * u32 flags) -- special device flags
1789 * Write one 32-bit register or memory location. The data being written is
1790 * converted from the target platform's endianness to little endian.
1793 * - 0 if writing was successful
1794 * - -EIO if anything went wrong
1796 ******************************/
1798 static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
1800 u32 data, u32 flags)
1802 u8 buf[sizeof(data)];
1804 buf[0] = (u8) ((data >> 0) & 0xFF);
1805 buf[1] = (u8) ((data >> 8) & 0xFF);
1806 buf[2] = (u8) ((data >> 16) & 0xFF);
1807 buf[3] = (u8) ((data >> 24) & 0xFF);
1809 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1812 /*============================================================================*/
1815 * \fn int drxj_dap_rm_write_reg16short
1816 * \brief Read modify write 16 bits audio register using short format only.
1818 * \param waddr Address to write to
1819 * \param raddr Address to read from (usually SIO_HI_RA_RAM_S0_RMWBUF__A)
1820 * \param wdata Data to write
1821 * \param rdata Buffer for data to read
1824 * \retval -EIO Timeout, I2C error, illegal bank
1826 * 16 bits register read modify write access using short addressing format only.
1827 * Requires knowledge of the registermap, thus device dependent.
1828 * Using DAP FASI directly to avoid endless recursion of RMWs to audio registers.
1832 /* TODO correct define should be #if ( DRXDAPFASI_SHORT_ADDR_ALLOWED==1 )
1833 See comments drxj_dap_read_modify_write_reg16 */
1834 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 0)
1835 static int drxj_dap_rm_write_reg16short(struct i2c_device_addr *dev_addr,
1838 u16 wdata, u16 *rdata)
1846 rc = drxdap_fasi_write_reg16(dev_addr,
1847 SIO_HI_RA_RAM_S0_FLG_ACC__A,
1848 SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M,
1851 /* Write new data: triggers RMW */
1852 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata,
1857 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata,
1861 /* Reset RMW flag */
1862 rc = drxdap_fasi_write_reg16(dev_addr,
1863 SIO_HI_RA_RAM_S0_FLG_ACC__A,
1871 /*============================================================================*/
1873 static int drxj_dap_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
1876 u16 wdata, u16 *rdata)
1878 /* TODO: correct short/long addressing format decision,
1879 now long format has higher prio then short because short also
1880 needs virt bnks (not impl yet) for certain audio registers */
1881 #if (DRXDAPFASI_LONG_ADDR_ALLOWED == 1)
1882 return drxdap_fasi_read_modify_write_reg16(dev_addr,
1884 raddr, wdata, rdata);
1886 return drxj_dap_rm_write_reg16short(dev_addr, waddr, raddr, wdata, rdata);
1891 /*============================================================================*/
1894 * \fn int drxj_dap_read_aud_reg16
1895 * \brief Read 16 bits audio register
1901 * \retval -EIO Timeout, I2C error, illegal bank
1903 * 16 bits register read access via audio token ring interface.
1906 static int drxj_dap_read_aud_reg16(struct i2c_device_addr *dev_addr,
1907 u32 addr, u16 *data)
1909 u32 start_timer = 0;
1910 u32 current_timer = 0;
1911 u32 delta_timer = 0;
1915 /* No read possible for bank 3, return with error */
1916 if (DRXDAP_FASI_ADDR2BANK(addr) == 3) {
1919 const u32 write_bit = ((dr_xaddr_t) 1) << 16;
1921 /* Force reset write bit */
1922 addr &= (~write_bit);
1925 start_timer = jiffies_to_msecs(jiffies);
1927 /* RMW to aud TR IF until request is granted or timeout */
1928 stat = drxj_dap_read_modify_write_reg16(dev_addr,
1930 SIO_HI_RA_RAM_S0_RMWBUF__A,
1931 0x0000, &tr_status);
1936 current_timer = jiffies_to_msecs(jiffies);
1937 delta_timer = current_timer - start_timer;
1938 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
1943 } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
1944 AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
1945 ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
1946 AUD_TOP_TR_CTR_FIFO_FULL_FULL));
1947 } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */
1949 /* Wait for read ready status or timeout */
1951 start_timer = jiffies_to_msecs(jiffies);
1953 while ((tr_status & AUD_TOP_TR_CTR_FIFO_RD_RDY__M) !=
1954 AUD_TOP_TR_CTR_FIFO_RD_RDY_READY) {
1955 stat = drxj_dap_read_reg16(dev_addr,
1957 &tr_status, 0x0000);
1961 current_timer = jiffies_to_msecs(jiffies);
1962 delta_timer = current_timer - start_timer;
1963 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
1967 } /* while ( ... ) */
1972 stat = drxj_dap_read_modify_write_reg16(dev_addr,
1973 AUD_TOP_TR_RD_REG__A,
1974 SIO_HI_RA_RAM_S0_RMWBUF__A,
1979 /*============================================================================*/
1981 static int drxj_dap_read_reg16(struct i2c_device_addr *dev_addr,
1983 u16 *data, u32 flags)
1988 if ((dev_addr == NULL) || (data == NULL))
1991 if (is_handled_by_aud_tr_if(addr))
1992 stat = drxj_dap_read_aud_reg16(dev_addr, addr, data);
1994 stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags);
1998 /*============================================================================*/
2001 * \fn int drxj_dap_write_aud_reg16
2002 * \brief Write 16 bits audio register
2008 * \retval -EIO Timeout, I2C error, illegal bank
2010 * 16 bits register write access via audio token ring interface.
2013 static int drxj_dap_write_aud_reg16(struct i2c_device_addr *dev_addr,
2018 /* No write possible for bank 2, return with error */
2019 if (DRXDAP_FASI_ADDR2BANK(addr) == 2) {
2022 u32 start_timer = 0;
2023 u32 current_timer = 0;
2024 u32 delta_timer = 0;
2026 const u32 write_bit = ((dr_xaddr_t) 1) << 16;
2028 /* Force write bit */
2030 start_timer = jiffies_to_msecs(jiffies);
2032 /* RMW to aud TR IF until request is granted or timeout */
2033 stat = drxj_dap_read_modify_write_reg16(dev_addr,
2035 SIO_HI_RA_RAM_S0_RMWBUF__A,
2040 current_timer = jiffies_to_msecs(jiffies);
2041 delta_timer = current_timer - start_timer;
2042 if (delta_timer > DRXJ_DAP_AUDTRIF_TIMEOUT) {
2047 } while (((tr_status & AUD_TOP_TR_CTR_FIFO_LOCK__M) ==
2048 AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED) ||
2049 ((tr_status & AUD_TOP_TR_CTR_FIFO_FULL__M) ==
2050 AUD_TOP_TR_CTR_FIFO_FULL_FULL));
2052 } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */
2057 /*============================================================================*/
2059 static int drxj_dap_write_reg16(struct i2c_device_addr *dev_addr,
2061 u16 data, u32 flags)
2066 if (dev_addr == NULL)
2069 if (is_handled_by_aud_tr_if(addr))
2070 stat = drxj_dap_write_aud_reg16(dev_addr, addr, data);
2072 stat = drxdap_fasi_write_reg16(dev_addr,
2078 /*============================================================================*/
2080 /* Free data ram in SIO HI */
2081 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2082 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2084 #define DRXJ_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2085 #define DRXJ_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2086 #define DRXJ_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2087 #define DRXJ_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2090 * \fn int drxj_dap_atomic_read_write_block()
2091 * \brief Basic access routine for atomic read or write access
2092 * \param dev_addr pointer to i2c dev address
2093 * \param addr destination/source address
2094 * \param datasize size of data buffer in bytes
2095 * \param data pointer to data buffer
2098 * \retval -EIO Timeout, I2C error, illegal bank
2102 int drxj_dap_atomic_read_write_block(struct i2c_device_addr *dev_addr,
2105 u8 *data, bool read_flag)
2107 struct drxj_hi_cmd hi_cmd;
2113 /* Parameter check */
2114 if (!data || !dev_addr || ((datasize % 2)) || ((datasize / 2) > 8))
2117 /* Set up HI parameters to read or write n bytes */
2118 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_ATOMIC_COPY;
2120 (u16) ((DRXDAP_FASI_ADDR2BLOCK(DRXJ_HI_ATOMIC_BUF_START) << 6) +
2121 DRXDAP_FASI_ADDR2BANK(DRXJ_HI_ATOMIC_BUF_START));
2123 (u16) DRXDAP_FASI_ADDR2OFFSET(DRXJ_HI_ATOMIC_BUF_START);
2124 hi_cmd.param3 = (u16) ((datasize / 2) - 1);
2126 hi_cmd.param3 |= DRXJ_HI_ATOMIC_WRITE;
2128 hi_cmd.param3 |= DRXJ_HI_ATOMIC_READ;
2129 hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) +
2130 DRXDAP_FASI_ADDR2BANK(addr));
2131 hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr);
2134 /* write data to buffer */
2135 for (i = 0; i < (datasize / 2); i++) {
2137 word = ((u16) data[2 * i]);
2138 word += (((u16) data[(2 * i) + 1]) << 8);
2139 drxj_dap_write_reg16(dev_addr,
2140 (DRXJ_HI_ATOMIC_BUF_START + i),
2145 rc = hi_command(dev_addr, &hi_cmd, &dummy);
2147 pr_err("error %d\n", rc);
2152 /* read data from buffer */
2153 for (i = 0; i < (datasize / 2); i++) {
2154 rc = drxj_dap_read_reg16(dev_addr,
2155 (DRXJ_HI_ATOMIC_BUF_START + i),
2158 pr_err("error %d\n", rc);
2161 data[2 * i] = (u8) (word & 0xFF);
2162 data[(2 * i) + 1] = (u8) (word >> 8);
2173 /*============================================================================*/
2176 * \fn int drxj_dap_atomic_read_reg32()
2177 * \brief Atomic read of 32 bits words
2180 int drxj_dap_atomic_read_reg32(struct i2c_device_addr *dev_addr,
2182 u32 *data, u32 flags)
2184 u8 buf[sizeof(*data)] = { 0 };
2191 rc = drxj_dap_atomic_read_write_block(dev_addr, addr,
2192 sizeof(*data), buf, true);
2197 word = (u32) buf[3];
2199 word |= (u32) buf[2];
2201 word |= (u32) buf[1];
2203 word |= (u32) buf[0];
2210 /*============================================================================*/
2212 /*============================================================================*/
2213 /*== END DRXJ DAP FUNCTIONS ==*/
2214 /*============================================================================*/
2216 /*============================================================================*/
2217 /*============================================================================*/
2218 /*== HOST INTERFACE FUNCTIONS ==*/
2219 /*============================================================================*/
2220 /*============================================================================*/
2223 * \fn int hi_cfg_command()
2224 * \brief Configure HI with settings stored in the demod structure.
2225 * \param demod Demodulator.
2228 * This routine was created because to much orthogonal settings have
2229 * been put into one HI API function (configure). Especially the I2C bridge
2230 * enable/disable should not need re-configuration of the HI.
2233 static int hi_cfg_command(const struct drx_demod_instance *demod)
2235 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2236 struct drxj_hi_cmd hi_cmd;
2240 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2242 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_CONFIG;
2243 hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
2244 hi_cmd.param2 = ext_attr->hi_cfg_timing_div;
2245 hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay;
2246 hi_cmd.param4 = ext_attr->hi_cfg_wake_up_key;
2247 hi_cmd.param5 = ext_attr->hi_cfg_ctrl;
2248 hi_cmd.param6 = ext_attr->hi_cfg_transmit;
2250 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
2252 pr_err("error %d\n", rc);
2256 /* Reset power down flag (set one call only) */
2257 ext_attr->hi_cfg_ctrl &= (~(SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2266 * \fn int hi_command()
2267 * \brief Configure HI with settings stored in the demod structure.
2268 * \param dev_addr I2C address.
2269 * \param cmd HI command.
2270 * \param result HI command result.
2273 * Sends command to HI
2277 hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 *result)
2281 bool powerdown_cmd = false;
2284 /* Write parameters */
2287 case SIO_HI_RA_RAM_CMD_CONFIG:
2288 case SIO_HI_RA_RAM_CMD_ATOMIC_COPY:
2289 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0);
2291 pr_err("error %d\n", rc);
2294 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0);
2296 pr_err("error %d\n", rc);
2299 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0);
2301 pr_err("error %d\n", rc);
2304 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0);
2306 pr_err("error %d\n", rc);
2310 case SIO_HI_RA_RAM_CMD_BRDCTRL:
2311 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
2313 pr_err("error %d\n", rc);
2316 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0);
2318 pr_err("error %d\n", rc);
2322 case SIO_HI_RA_RAM_CMD_NULL:
2331 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0);
2333 pr_err("error %d\n", rc);
2337 if ((cmd->cmd) == SIO_HI_RA_RAM_CMD_RESET)
2340 /* Detect power down to omit reading result */
2341 powerdown_cmd = (bool) ((cmd->cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
2343 param5) & SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M)
2344 == SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ));
2345 if (!powerdown_cmd) {
2346 /* Wait until command rdy */
2349 if (nr_retries > DRXJ_MAX_RETRIES) {
2350 pr_err("timeout\n");
2354 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0);
2356 pr_err("error %d\n", rc);
2359 } while (wait_cmd != 0);
2362 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0);
2364 pr_err("error %d\n", rc);
2369 /* if ( powerdown_cmd == true ) */
2376 * \fn int init_hi( const struct drx_demod_instance *demod )
2377 * \brief Initialise and configurate HI.
2378 * \param demod pointer to demod data.
2379 * \return int Return status.
2380 * \retval 0 Success.
2381 * \retval -EIO Failure.
2383 * Needs to know Psys (System Clock period) and Posc (Osc Clock period)
2384 * Need to store configuration in driver because of the way I2C
2385 * bridging is controlled.
2388 static int init_hi(const struct drx_demod_instance *demod)
2390 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2391 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2392 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2395 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2396 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2397 dev_addr = demod->my_i2c_dev_addr;
2399 /* PATCH for bug 5003, HI ucode v3.1.0 */
2400 rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0);
2402 pr_err("error %d\n", rc);
2406 /* Timing div, 250ns/Psys */
2407 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2408 ext_attr->hi_cfg_timing_div =
2409 (u16) ((common_attr->sys_clock_freq / 1000) * HI_I2C_DELAY) / 1000;
2411 if ((ext_attr->hi_cfg_timing_div) > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
2412 ext_attr->hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
2413 /* Bridge delay, uses oscilator clock */
2414 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2415 /* SDA brdige delay */
2416 ext_attr->hi_cfg_bridge_delay =
2417 (u16) ((common_attr->osc_clock_freq / 1000) * HI_I2C_BRIDGE_DELAY) /
2420 if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M)
2421 ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
2422 /* SCL bridge delay, same as SDA for now */
2423 ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) <<
2424 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B);
2425 /* Wakeup key, setting the read flag (as suggest in the documentation) does
2426 not always result into a working solution (barebones worked VI2C failed).
2427 Not setting the bit works in all cases . */
2428 ext_attr->hi_cfg_wake_up_key = DRXJ_WAKE_UP_KEY;
2429 /* port/bridge/power down ctrl */
2430 ext_attr->hi_cfg_ctrl = (SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE);
2431 /* transit mode time out delay and watch dog divider */
2432 ext_attr->hi_cfg_transmit = SIO_HI_RA_RAM_PAR_6__PRE;
2434 rc = hi_cfg_command(demod);
2436 pr_err("error %d\n", rc);
2446 /*============================================================================*/
2447 /*== END HOST INTERFACE FUNCTIONS ==*/
2448 /*============================================================================*/
2450 /*============================================================================*/
2451 /*============================================================================*/
2452 /*== AUXILIARY FUNCTIONS ==*/
2453 /*============================================================================*/
2454 /*============================================================================*/
2457 * \fn int get_device_capabilities()
2458 * \brief Get and store device capabilities.
2459 * \param demod Pointer to demodulator instance.
2462 * \retval -EIO Failure
2464 * Depending on pulldowns on MDx pins the following internals are set:
2465 * * common_attr->osc_clock_freq
2466 * * ext_attr->has_lna
2467 * * ext_attr->has_ntsc
2468 * * ext_attr->has_btsc
2469 * * ext_attr->has_oob
2472 static int get_device_capabilities(struct drx_demod_instance *demod)
2474 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2475 struct drxj_data *ext_attr = (struct drxj_data *) NULL;
2476 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2477 u16 sio_pdr_ohw_cfg = 0;
2478 u32 sio_top_jtagid_lo = 0;
2482 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2483 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2484 dev_addr = demod->my_i2c_dev_addr;
2486 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2488 pr_err("error %d\n", rc);
2491 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0);
2493 pr_err("error %d\n", rc);
2496 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2498 pr_err("error %d\n", rc);
2502 switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
2504 /* ignore (bypass ?) */
2508 common_attr->osc_clock_freq = 27000;
2512 common_attr->osc_clock_freq = 20250;
2516 common_attr->osc_clock_freq = 4000;
2523 Determine device capabilities
2524 Based on pinning v47
2526 rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0);
2528 pr_err("error %d\n", rc);
2531 ext_attr->mfx = (u8) ((sio_top_jtagid_lo >> 29) & 0xF);
2533 switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
2535 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
2537 pr_err("error %d\n", rc);
2540 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0);
2542 pr_err("error %d\n", rc);
2545 bid = (bid >> 10) & 0xf;
2546 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0);
2548 pr_err("error %d\n", rc);
2552 ext_attr->has_lna = true;
2553 ext_attr->has_ntsc = false;
2554 ext_attr->has_btsc = false;
2555 ext_attr->has_oob = false;
2556 ext_attr->has_smatx = true;
2557 ext_attr->has_smarx = false;
2558 ext_attr->has_gpio = false;
2559 ext_attr->has_irqn = false;
2562 ext_attr->has_lna = false;
2563 ext_attr->has_ntsc = false;
2564 ext_attr->has_btsc = false;
2565 ext_attr->has_oob = false;
2566 ext_attr->has_smatx = true;
2567 ext_attr->has_smarx = false;
2568 ext_attr->has_gpio = false;
2569 ext_attr->has_irqn = false;
2572 ext_attr->has_lna = true;
2573 ext_attr->has_ntsc = true;
2574 ext_attr->has_btsc = false;
2575 ext_attr->has_oob = false;
2576 ext_attr->has_smatx = true;
2577 ext_attr->has_smarx = true;
2578 ext_attr->has_gpio = true;
2579 ext_attr->has_irqn = false;
2582 ext_attr->has_lna = false;
2583 ext_attr->has_ntsc = true;
2584 ext_attr->has_btsc = false;
2585 ext_attr->has_oob = false;
2586 ext_attr->has_smatx = true;
2587 ext_attr->has_smarx = true;
2588 ext_attr->has_gpio = true;
2589 ext_attr->has_irqn = false;
2592 ext_attr->has_lna = true;
2593 ext_attr->has_ntsc = true;
2594 ext_attr->has_btsc = true;
2595 ext_attr->has_oob = false;
2596 ext_attr->has_smatx = true;
2597 ext_attr->has_smarx = true;
2598 ext_attr->has_gpio = true;
2599 ext_attr->has_irqn = false;
2602 ext_attr->has_lna = false;
2603 ext_attr->has_ntsc = true;
2604 ext_attr->has_btsc = true;
2605 ext_attr->has_oob = false;
2606 ext_attr->has_smatx = true;
2607 ext_attr->has_smarx = true;
2608 ext_attr->has_gpio = true;
2609 ext_attr->has_irqn = false;
2612 ext_attr->has_lna = true;
2613 ext_attr->has_ntsc = false;
2614 ext_attr->has_btsc = false;
2615 ext_attr->has_oob = true;
2616 ext_attr->has_smatx = true;
2617 ext_attr->has_smarx = true;
2618 ext_attr->has_gpio = true;
2619 ext_attr->has_irqn = true;
2622 ext_attr->has_lna = false;
2623 ext_attr->has_ntsc = true;
2624 ext_attr->has_btsc = true;
2625 ext_attr->has_oob = true;
2626 ext_attr->has_smatx = true;
2627 ext_attr->has_smarx = true;
2628 ext_attr->has_gpio = true;
2629 ext_attr->has_irqn = true;
2632 ext_attr->has_lna = true;
2633 ext_attr->has_ntsc = true;
2634 ext_attr->has_btsc = true;
2635 ext_attr->has_oob = true;
2636 ext_attr->has_smatx = true;
2637 ext_attr->has_smarx = true;
2638 ext_attr->has_gpio = true;
2639 ext_attr->has_irqn = true;
2642 ext_attr->has_lna = false;
2643 ext_attr->has_ntsc = true;
2644 ext_attr->has_btsc = true;
2645 ext_attr->has_oob = true;
2646 ext_attr->has_smatx = true;
2647 ext_attr->has_smarx = true;
2648 ext_attr->has_gpio = true;
2649 ext_attr->has_irqn = true;
2652 /* Unknown device variant */
2663 * \fn int power_up_device()
2664 * \brief Power up device.
2665 * \param demod Pointer to demodulator instance.
2668 * \retval -EIO Failure, I2C or max retries reached
2672 #ifndef DRXJ_MAX_RETRIES_POWERUP
2673 #define DRXJ_MAX_RETRIES_POWERUP 10
2676 static int power_up_device(struct drx_demod_instance *demod)
2678 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2680 u16 retry_count = 0;
2681 struct i2c_device_addr wake_up_addr;
2683 dev_addr = demod->my_i2c_dev_addr;
2684 wake_up_addr.i2c_addr = DRXJ_WAKE_UP_KEY;
2685 wake_up_addr.i2c_dev_id = dev_addr->i2c_dev_id;
2686 wake_up_addr.user_data = dev_addr->user_data;
2688 * I2C access may fail in this case: no ack
2689 * dummy write must be used to wake uop device, dummy read must be used to
2690 * reset HI state machine (avoiding actual writes)
2694 drxbsp_i2c_write_read(&wake_up_addr, 1, &data,
2695 (struct i2c_device_addr *)(NULL), 0,
2699 } while ((drxbsp_i2c_write_read
2700 ((struct i2c_device_addr *) (NULL), 0, (u8 *)(NULL), dev_addr, 1,
2702 != 0) && (retry_count < DRXJ_MAX_RETRIES_POWERUP));
2704 /* Need some recovery time .... */
2707 if (retry_count == DRXJ_MAX_RETRIES_POWERUP)
2713 /*----------------------------------------------------------------------------*/
2714 /* MPEG Output Configuration Functions - begin */
2715 /*----------------------------------------------------------------------------*/
2717 * \fn int ctrl_set_cfg_mpeg_output()
2718 * \brief Set MPEG output configuration of the device.
2719 * \param devmod Pointer to demodulator instance.
2720 * \param cfg_data Pointer to mpeg output configuaration.
2723 * Configure MPEG output parameters.
2727 ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data)
2729 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
2730 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
2731 struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
2733 u16 fec_oc_reg_mode = 0;
2734 u16 fec_oc_reg_ipr_mode = 0;
2735 u16 fec_oc_reg_ipr_invert = 0;
2736 u32 max_bit_rate = 0;
2739 u16 sio_pdr_md_cfg = 0;
2740 /* data mask for the output data byte */
2741 u16 invert_data_mask =
2742 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2743 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2744 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2745 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2747 /* check arguments */
2748 if ((demod == NULL) || (cfg_data == NULL))
2751 dev_addr = demod->my_i2c_dev_addr;
2752 ext_attr = (struct drxj_data *) demod->my_ext_attr;
2753 common_attr = (struct drx_common_attr *) demod->my_common_attr;
2755 if (cfg_data->enable_mpeg_output == true) {
2756 /* quick and dirty patch to set MPEG in case current std is not
2758 switch (ext_attr->standard) {
2759 case DRX_STANDARD_8VSB:
2760 case DRX_STANDARD_ITU_A:
2761 case DRX_STANDARD_ITU_B:
2762 case DRX_STANDARD_ITU_C:
2768 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0);
2770 pr_err("error %d\n", rc);
2773 switch (ext_attr->standard) {
2774 case DRX_STANDARD_8VSB:
2775 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0);
2777 pr_err("error %d\n", rc);
2779 } /* 2048 bytes fifo ram */
2780 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0);
2782 pr_err("error %d\n", rc);
2785 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0);
2787 pr_err("error %d\n", rc);
2790 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0);
2792 pr_err("error %d\n", rc);
2795 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0);
2797 pr_err("error %d\n", rc);
2800 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0);
2802 pr_err("error %d\n", rc);
2805 /* Low Water Mark for synchronization */
2806 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0);
2808 pr_err("error %d\n", rc);
2811 /* High Water Mark for synchronization */
2812 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0);
2814 pr_err("error %d\n", rc);
2818 case DRX_STANDARD_ITU_A:
2819 case DRX_STANDARD_ITU_C:
2820 switch (ext_attr->constellation) {
2821 case DRX_CONSTELLATION_QAM256:
2824 case DRX_CONSTELLATION_QAM128:
2827 case DRX_CONSTELLATION_QAM64:
2830 case DRX_CONSTELLATION_QAM32:
2833 case DRX_CONSTELLATION_QAM16:
2838 } /* ext_attr->constellation */
2839 /* max_bit_rate = symbol_rate * nr_bits * coef */
2840 /* coef = 188/204 */
2842 (ext_attr->curr_symbol_rate / 8) * nr_bits * 188;
2843 fallthrough; /* as b/c Annex A/C need following settings */
2844 case DRX_STANDARD_ITU_B:
2845 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);
2847 pr_err("error %d\n", rc);
2850 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0);
2852 pr_err("error %d\n", rc);
2855 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0);
2857 pr_err("error %d\n", rc);
2860 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0);
2862 pr_err("error %d\n", rc);
2865 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0);
2867 pr_err("error %d\n", rc);
2870 if (cfg_data->static_clk == true) {
2871 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0);
2873 pr_err("error %d\n", rc);
2877 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0);
2879 pr_err("error %d\n", rc);
2883 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0);
2885 pr_err("error %d\n", rc);
2888 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0);
2890 pr_err("error %d\n", rc);
2896 } /* switch (standard) */
2898 /* Check insertion of the Reed-Solomon parity bytes */
2899 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
2901 pr_err("error %d\n", rc);
2904 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0);
2906 pr_err("error %d\n", rc);
2909 if (cfg_data->insert_rs_byte == true) {
2910 /* enable parity symbol forward */
2911 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
2912 /* MVAL disable during parity bytes */
2913 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2914 switch (ext_attr->standard) {
2915 case DRX_STANDARD_8VSB:
2916 rcn_rate = 0x004854D3;
2918 case DRX_STANDARD_ITU_B:
2919 fec_oc_reg_mode |= FEC_OC_MODE_TRANSPARENT__M;
2920 switch (ext_attr->constellation) {
2921 case DRX_CONSTELLATION_QAM256:
2922 rcn_rate = 0x008945E7;
2924 case DRX_CONSTELLATION_QAM64:
2925 rcn_rate = 0x005F64D4;
2931 case DRX_STANDARD_ITU_A:
2932 case DRX_STANDARD_ITU_C:
2933 /* insert_rs_byte = true -> coef = 188/188 -> 1, RS bits are in MPEG output */
2937 (u32) (common_attr->sys_clock_freq / 8))) /
2942 } /* ext_attr->standard */
2943 } else { /* insert_rs_byte == false */
2945 /* disable parity symbol forward */
2946 fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
2947 /* MVAL enable during parity bytes */
2948 fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2949 switch (ext_attr->standard) {
2950 case DRX_STANDARD_8VSB:
2951 rcn_rate = 0x0041605C;
2953 case DRX_STANDARD_ITU_B:
2954 fec_oc_reg_mode &= (~FEC_OC_MODE_TRANSPARENT__M);
2955 switch (ext_attr->constellation) {
2956 case DRX_CONSTELLATION_QAM256:
2957 rcn_rate = 0x0082D6A0;
2959 case DRX_CONSTELLATION_QAM64:
2960 rcn_rate = 0x005AEC1A;
2966 case DRX_STANDARD_ITU_A:
2967 case DRX_STANDARD_ITU_C:
2968 /* insert_rs_byte = false -> coef = 188/204, RS bits not in MPEG output */
2972 (u32) (common_attr->sys_clock_freq / 8))) /
2977 } /* ext_attr->standard */
2980 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> clear ipr_mode[0] */
2981 fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2982 } else { /* MPEG data output is serial -> set ipr_mode[0] */
2983 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2986 /* Control slective inversion of output bits */
2987 if (cfg_data->invert_data == true)
2988 fec_oc_reg_ipr_invert |= invert_data_mask;
2990 fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2992 if (cfg_data->invert_err == true)
2993 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2995 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2997 if (cfg_data->invert_str == true)
2998 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
3000 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
3002 if (cfg_data->invert_val == true)
3003 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
3005 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
3007 if (cfg_data->invert_clk == true)
3008 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
3010 fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
3013 if (cfg_data->static_clk == true) { /* Static mode */
3016 u16 fec_oc_dto_burst_len = 0;
3017 u16 fec_oc_dto_period = 0;
3019 fec_oc_dto_burst_len = FEC_OC_DTO_BURST_LEN__PRE;
3021 switch (ext_attr->standard) {
3022 case DRX_STANDARD_8VSB:
3023 fec_oc_dto_period = 4;
3024 if (cfg_data->insert_rs_byte == true)
3025 fec_oc_dto_burst_len = 208;
3027 case DRX_STANDARD_ITU_A:
3029 u32 symbol_rate_th = 6400000;
3030 if (cfg_data->insert_rs_byte == true) {
3031 fec_oc_dto_burst_len = 204;
3032 symbol_rate_th = 5900000;
3034 if (ext_attr->curr_symbol_rate >=
3036 fec_oc_dto_period = 0;
3038 fec_oc_dto_period = 1;
3042 case DRX_STANDARD_ITU_B:
3043 fec_oc_dto_period = 1;
3044 if (cfg_data->insert_rs_byte == true)
3045 fec_oc_dto_burst_len = 128;
3047 case DRX_STANDARD_ITU_C:
3048 fec_oc_dto_period = 1;
3049 if (cfg_data->insert_rs_byte == true)
3050 fec_oc_dto_burst_len = 204;
3056 common_attr->sys_clock_freq * 1000 / (fec_oc_dto_period +
3059 frac28(bit_rate, common_attr->sys_clock_freq * 1000);
3061 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RATE_HI__M), 0);
3063 pr_err("error %d\n", rc);
3066 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RATE_LO__M), 0);
3068 pr_err("error %d\n", rc);
3071 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MODE_OFFSET_ENABLE__M, 0);
3073 pr_err("error %d\n", rc);
3076 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MODE_VIRT_ENA__M, 0);
3078 pr_err("error %d\n", rc);
3081 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0);
3083 pr_err("error %d\n", rc);
3086 if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO)
3087 fec_oc_dto_period = ext_attr->mpeg_output_clock_rate - 1;
3088 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0);
3090 pr_err("error %d\n", rc);
3093 } else { /* Dynamic mode */
3095 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0);
3097 pr_err("error %d\n", rc);
3100 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0);
3102 pr_err("error %d\n", rc);
3107 rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0);
3109 pr_err("error %d\n", rc);
3113 /* Write appropriate registers with requested configuration */
3114 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0);
3116 pr_err("error %d\n", rc);
3119 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0);
3121 pr_err("error %d\n", rc);
3124 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0);
3126 pr_err("error %d\n", rc);
3130 /* enabling for both parallel and serial now */
3131 /* Write magic word to enable pdr reg write */
3132 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3134 pr_err("error %d\n", rc);
3137 /* Set MPEG TS pads to outputmode */
3138 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0);
3140 pr_err("error %d\n", rc);
3143 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0);
3145 pr_err("error %d\n", rc);
3148 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR_MCLK_CFG_DRIVE__B | 0x03 << SIO_PDR_MCLK_CFG_MODE__B, 0);
3150 pr_err("error %d\n", rc);
3153 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0);
3155 pr_err("error %d\n", rc);
3159 MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH <<
3160 SIO_PDR_MD0_CFG_DRIVE__B | 0x03 << SIO_PDR_MD0_CFG_MODE__B;
3161 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3163 pr_err("error %d\n", rc);
3166 if (cfg_data->enable_parallel == true) { /* MPEG data output is parallel -> set MD1 to MD7 to output mode */
3168 MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH <<
3169 SIO_PDR_MD0_CFG_DRIVE__B | 0x03 <<
3170 SIO_PDR_MD0_CFG_MODE__B;
3171 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0);
3173 pr_err("error %d\n", rc);
3176 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0);
3178 pr_err("error %d\n", rc);
3181 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0);
3183 pr_err("error %d\n", rc);
3186 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0);
3188 pr_err("error %d\n", rc);
3191 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0);
3193 pr_err("error %d\n", rc);
3196 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0);
3198 pr_err("error %d\n", rc);
3201 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0);
3203 pr_err("error %d\n", rc);
3206 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0);
3208 pr_err("error %d\n", rc);
3211 } else { /* MPEG data output is serial -> set MD1 to MD7 to tri-state */
3212 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3214 pr_err("error %d\n", rc);
3217 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3219 pr_err("error %d\n", rc);
3222 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3224 pr_err("error %d\n", rc);
3227 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3229 pr_err("error %d\n", rc);
3232 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3234 pr_err("error %d\n", rc);
3237 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3239 pr_err("error %d\n", rc);
3242 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3244 pr_err("error %d\n", rc);
3248 /* Enable Monitor Bus output over MPEG pads and ctl input */
3249 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3251 pr_err("error %d\n", rc);
3254 /* Write nomagic word to enable pdr reg write */
3255 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3257 pr_err("error %d\n", rc);
3261 /* Write magic word to enable pdr reg write */
3262 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
3264 pr_err("error %d\n", rc);
3267 /* Set MPEG TS pads to inputmode */
3268 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0);
3270 pr_err("error %d\n", rc);
3273 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0);
3275 pr_err("error %d\n", rc);
3278 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0);
3280 pr_err("error %d\n", rc);
3283 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0);
3285 pr_err("error %d\n", rc);
3288 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0);
3290 pr_err("error %d\n", rc);
3293 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0);
3295 pr_err("error %d\n", rc);
3298 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0);
3300 pr_err("error %d\n", rc);
3303 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0);
3305 pr_err("error %d\n", rc);
3308 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0);
3310 pr_err("error %d\n", rc);
3313 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0);
3315 pr_err("error %d\n", rc);
3318 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0);
3320 pr_err("error %d\n", rc);
3323 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0);
3325 pr_err("error %d\n", rc);
3328 /* Enable Monitor Bus output over MPEG pads and ctl input */
3329 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0);
3331 pr_err("error %d\n", rc);
3334 /* Write nomagic word to enable pdr reg write */
3335 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3337 pr_err("error %d\n", rc);
3342 /* save values for restore after re-acquire */
3343 common_attr->mpeg_cfg.enable_mpeg_output = cfg_data->enable_mpeg_output;
3350 /*----------------------------------------------------------------------------*/
3353 /*----------------------------------------------------------------------------*/
3354 /* MPEG Output Configuration Functions - end */
3355 /*----------------------------------------------------------------------------*/
3357 /*----------------------------------------------------------------------------*/
3358 /* miscellaneous configurations - begin */
3359 /*----------------------------------------------------------------------------*/
3362 * \fn int set_mpegtei_handling()
3363 * \brief Activate MPEG TEI handling settings.
3364 * \param devmod Pointer to demodulator instance.
3367 * This routine should be called during a set channel of QAM/VSB
3370 static int set_mpegtei_handling(struct drx_demod_instance *demod)
3372 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3373 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3375 u16 fec_oc_dpr_mode = 0;
3376 u16 fec_oc_snc_mode = 0;
3377 u16 fec_oc_ems_mode = 0;
3379 dev_addr = demod->my_i2c_dev_addr;
3380 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3382 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0);
3384 pr_err("error %d\n", rc);
3387 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
3389 pr_err("error %d\n", rc);
3392 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0);
3394 pr_err("error %d\n", rc);
3398 /* reset to default, allow TEI bit to be changed */
3399 fec_oc_dpr_mode &= (~FEC_OC_DPR_MODE_ERR_DISABLE__M);
3400 fec_oc_snc_mode &= (~(FEC_OC_SNC_MODE_ERROR_CTL__M |
3401 FEC_OC_SNC_MODE_CORR_DISABLE__M));
3402 fec_oc_ems_mode &= (~FEC_OC_EMS_MODE_MODE__M);
3404 if (ext_attr->disable_te_ihandling) {
3405 /* do not change TEI bit */
3406 fec_oc_dpr_mode |= FEC_OC_DPR_MODE_ERR_DISABLE__M;
3407 fec_oc_snc_mode |= FEC_OC_SNC_MODE_CORR_DISABLE__M |
3408 ((0x2) << (FEC_OC_SNC_MODE_ERROR_CTL__B));
3409 fec_oc_ems_mode |= ((0x01) << (FEC_OC_EMS_MODE_MODE__B));
3412 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0);
3414 pr_err("error %d\n", rc);
3417 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0);
3419 pr_err("error %d\n", rc);
3422 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0);
3424 pr_err("error %d\n", rc);
3433 /*----------------------------------------------------------------------------*/
3435 * \fn int bit_reverse_mpeg_output()
3436 * \brief Set MPEG output bit-endian settings.
3437 * \param devmod Pointer to demodulator instance.
3440 * This routine should be called during a set channel of QAM/VSB
3443 static int bit_reverse_mpeg_output(struct drx_demod_instance *demod)
3445 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3446 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3448 u16 fec_oc_ipr_mode = 0;
3450 dev_addr = demod->my_i2c_dev_addr;
3451 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3453 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0);
3455 pr_err("error %d\n", rc);
3459 /* reset to default (normal bit order) */
3460 fec_oc_ipr_mode &= (~FEC_OC_IPR_MODE_REVERSE_ORDER__M);
3462 if (ext_attr->bit_reverse_mpeg_outout)
3463 fec_oc_ipr_mode |= FEC_OC_IPR_MODE_REVERSE_ORDER__M;
3465 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0);
3467 pr_err("error %d\n", rc);
3476 /*----------------------------------------------------------------------------*/
3478 * \fn int set_mpeg_start_width()
3479 * \brief Set MPEG start width.
3480 * \param devmod Pointer to demodulator instance.
3483 * This routine should be called during a set channel of QAM/VSB
3486 static int set_mpeg_start_width(struct drx_demod_instance *demod)
3488 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3489 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
3490 struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
3492 u16 fec_oc_comm_mb = 0;
3494 dev_addr = demod->my_i2c_dev_addr;
3495 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3496 common_attr = demod->my_common_attr;
3498 if ((common_attr->mpeg_cfg.static_clk == true)
3499 && (common_attr->mpeg_cfg.enable_parallel == false)) {
3500 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0);
3502 pr_err("error %d\n", rc);
3505 fec_oc_comm_mb &= ~FEC_OC_COMM_MB_CTL_ON;
3506 if (ext_attr->mpeg_start_width == DRXJ_MPEG_START_WIDTH_8CLKCYC)
3507 fec_oc_comm_mb |= FEC_OC_COMM_MB_CTL_ON;
3508 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0);
3510 pr_err("error %d\n", rc);
3520 /*----------------------------------------------------------------------------*/
3521 /* miscellaneous configurations - end */
3522 /*----------------------------------------------------------------------------*/
3524 /*----------------------------------------------------------------------------*/
3525 /* UIO Configuration Functions - begin */
3526 /*----------------------------------------------------------------------------*/
3528 * \fn int ctrl_set_uio_cfg()
3529 * \brief Configure modus oprandi UIO.
3530 * \param demod Pointer to demodulator instance.
3531 * \param uio_cfg Pointer to a configuration setting for a certain UIO.
3534 static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg)
3536 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3539 if ((uio_cfg == NULL) || (demod == NULL))
3542 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3544 /* Write magic word to enable pdr reg write */
3545 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3547 pr_err("error %d\n", rc);
3550 switch (uio_cfg->uio) {
3551 /*====================================================================*/
3553 /* DRX_UIO1: SMA_TX UIO-1 */
3554 if (!ext_attr->has_smatx)
3556 switch (uio_cfg->mode) {
3557 case DRX_UIO_MODE_FIRMWARE_SMA:
3558 case DRX_UIO_MODE_FIRMWARE_SAW:
3559 case DRX_UIO_MODE_READWRITE:
3560 ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3562 case DRX_UIO_MODE_DISABLE:
3563 ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3564 /* pad configuration register is set 0 - input mode */
3565 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0);
3567 pr_err("error %d\n", rc);
3573 } /* switch ( uio_cfg->mode ) */
3575 /*====================================================================*/
3577 /* DRX_UIO2: SMA_RX UIO-2 */
3578 if (!ext_attr->has_smarx)
3580 switch (uio_cfg->mode) {
3581 case DRX_UIO_MODE_FIRMWARE0:
3582 case DRX_UIO_MODE_READWRITE:
3583 ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3585 case DRX_UIO_MODE_DISABLE:
3586 ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3587 /* pad configuration register is set 0 - input mode */
3588 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0);
3590 pr_err("error %d\n", rc);
3596 } /* switch ( uio_cfg->mode ) */
3598 /*====================================================================*/
3600 /* DRX_UIO3: GPIO UIO-3 */
3601 if (!ext_attr->has_gpio)
3603 switch (uio_cfg->mode) {
3604 case DRX_UIO_MODE_FIRMWARE0:
3605 case DRX_UIO_MODE_READWRITE:
3606 ext_attr->uio_gpio_mode = uio_cfg->mode;
3608 case DRX_UIO_MODE_DISABLE:
3609 ext_attr->uio_gpio_mode = uio_cfg->mode;
3610 /* pad configuration register is set 0 - input mode */
3611 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0);
3613 pr_err("error %d\n", rc);
3619 } /* switch ( uio_cfg->mode ) */
3621 /*====================================================================*/
3623 /* DRX_UIO4: IRQN UIO-4 */
3624 if (!ext_attr->has_irqn)
3626 switch (uio_cfg->mode) {
3627 case DRX_UIO_MODE_READWRITE:
3628 ext_attr->uio_irqn_mode = uio_cfg->mode;
3630 case DRX_UIO_MODE_DISABLE:
3631 /* pad configuration register is set 0 - input mode */
3632 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0);
3634 pr_err("error %d\n", rc);
3637 ext_attr->uio_irqn_mode = uio_cfg->mode;
3639 case DRX_UIO_MODE_FIRMWARE0:
3642 } /* switch ( uio_cfg->mode ) */
3644 /*====================================================================*/
3647 } /* switch ( uio_cfg->uio ) */
3649 /* Write magic word to disable pdr reg write */
3650 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3652 pr_err("error %d\n", rc);
3662 * \fn int ctrl_uio_write()
3663 * \brief Write to a UIO.
3664 * \param demod Pointer to demodulator instance.
3665 * \param uio_data Pointer to data container for a certain UIO.
3669 ctrl_uio_write(struct drx_demod_instance *demod, struct drxuio_data *uio_data)
3671 struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
3673 u16 pin_cfg_value = 0;
3676 if ((uio_data == NULL) || (demod == NULL))
3679 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3681 /* Write magic word to enable pdr reg write */
3682 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3684 pr_err("error %d\n", rc);
3687 switch (uio_data->uio) {
3688 /*====================================================================*/
3690 /* DRX_UIO1: SMA_TX UIO-1 */
3691 if (!ext_attr->has_smatx)
3693 if ((ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE)
3694 && (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SAW)) {
3698 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3699 pin_cfg_value |= 0x0113;
3700 /* io_pad_cfg_mode output mode is drive always */
3701 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3703 /* write to io pad configuration register - output mode */
3704 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
3706 pr_err("error %d\n", rc);
3710 /* use corresponding bit in io data output registar */
3711 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3713 pr_err("error %d\n", rc);
3716 if (!uio_data->value)
3717 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
3719 value |= 0x8000; /* write one to 15th bit - 1st UIO */
3721 /* write back to io data output register */
3722 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3724 pr_err("error %d\n", rc);
3728 /*======================================================================*/
3730 /* DRX_UIO2: SMA_RX UIO-2 */
3731 if (!ext_attr->has_smarx)
3733 if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE)
3737 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3738 pin_cfg_value |= 0x0113;
3739 /* io_pad_cfg_mode output mode is drive always */
3740 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3742 /* write to io pad configuration register - output mode */
3743 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
3745 pr_err("error %d\n", rc);
3749 /* use corresponding bit in io data output registar */
3750 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3752 pr_err("error %d\n", rc);
3755 if (!uio_data->value)
3756 value &= 0xBFFF; /* write zero to 14th bit - 2nd UIO */
3758 value |= 0x4000; /* write one to 14th bit - 2nd UIO */
3760 /* write back to io data output register */
3761 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3763 pr_err("error %d\n", rc);
3767 /*====================================================================*/
3769 /* DRX_UIO3: ASEL UIO-3 */
3770 if (!ext_attr->has_gpio)
3772 if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE)
3776 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3777 pin_cfg_value |= 0x0113;
3778 /* io_pad_cfg_mode output mode is drive always */
3779 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3781 /* write to io pad configuration register - output mode */
3782 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);
3784 pr_err("error %d\n", rc);
3788 /* use corresponding bit in io data output registar */
3789 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0);
3791 pr_err("error %d\n", rc);
3794 if (!uio_data->value)
3795 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
3797 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
3799 /* write back to io data output register */
3800 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0);
3802 pr_err("error %d\n", rc);
3806 /*=====================================================================*/
3808 /* DRX_UIO4: IRQN UIO-4 */
3809 if (!ext_attr->has_irqn)
3812 if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE)
3816 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
3817 pin_cfg_value |= 0x0113;
3818 /* io_pad_cfg_mode output mode is drive always */
3819 /* io_pad_cfg_drive is set to power 2 (23 mA) */
3821 /* write to io pad configuration register - output mode */
3822 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);
3824 pr_err("error %d\n", rc);
3828 /* use corresponding bit in io data output registar */
3829 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0);
3831 pr_err("error %d\n", rc);
3834 if (uio_data->value == false)
3835 value &= 0xEFFF; /* write zero to 12th bit - 4th UIO */
3837 value |= 0x1000; /* write one to 12th bit - 4th UIO */
3839 /* write back to io data output register */
3840 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0);
3842 pr_err("error %d\n", rc);
3846 /*=====================================================================*/
3849 } /* switch ( uio_data->uio ) */
3851 /* Write magic word to disable pdr reg write */
3852 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3854 pr_err("error %d\n", rc);
3863 /*---------------------------------------------------------------------------*/
3864 /* UIO Configuration Functions - end */
3865 /*---------------------------------------------------------------------------*/
3867 /*----------------------------------------------------------------------------*/
3868 /* I2C Bridge Functions - begin */
3869 /*----------------------------------------------------------------------------*/
3871 * \fn int ctrl_i2c_bridge()
3872 * \brief Open or close the I2C switch to tuner.
3873 * \param demod Pointer to demodulator instance.
3874 * \param bridge_closed Pointer to bool indication if bridge is closed not.
3879 ctrl_i2c_bridge(struct drx_demod_instance *demod, bool *bridge_closed)
3881 struct drxj_hi_cmd hi_cmd;
3884 /* check arguments */
3885 if (bridge_closed == NULL)
3888 hi_cmd.cmd = SIO_HI_RA_RAM_CMD_BRDCTRL;
3889 hi_cmd.param1 = SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY;
3891 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED;
3893 hi_cmd.param2 = SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN;
3895 return hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result);
3898 /*----------------------------------------------------------------------------*/
3899 /* I2C Bridge Functions - end */
3900 /*----------------------------------------------------------------------------*/
3902 /*----------------------------------------------------------------------------*/
3903 /* Smart antenna Functions - begin */
3904 /*----------------------------------------------------------------------------*/
3906 * \fn int smart_ant_init()
3907 * \brief Initialize Smart Antenna.
3908 * \param pointer to struct drx_demod_instance.
3912 static int smart_ant_init(struct drx_demod_instance *demod)
3914 struct drxj_data *ext_attr = NULL;
3915 struct i2c_device_addr *dev_addr = NULL;
3916 struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SMA };
3920 dev_addr = demod->my_i2c_dev_addr;
3921 ext_attr = (struct drxj_data *) demod->my_ext_attr;
3923 /* Write magic word to enable pdr reg write */
3924 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
3926 pr_err("error %d\n", rc);
3929 /* init smart antenna */
3930 rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0);
3932 pr_err("error %d\n", rc);
3935 if (ext_attr->smart_ant_inverted) {
3936 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3938 pr_err("error %d\n", rc);
3942 rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M)) | SIO_SA_TX_COMMAND_TX_ENABLE__M, 0);
3944 pr_err("error %d\n", rc);
3949 /* config SMA_TX pin to smart antenna mode */
3950 rc = ctrl_set_uio_cfg(demod, &uio_cfg);
3952 pr_err("error %d\n", rc);
3955 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0);
3957 pr_err("error %d\n", rc);
3960 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0);
3962 pr_err("error %d\n", rc);
3966 /* Write magic word to disable pdr reg write */
3967 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
3969 pr_err("error %d\n", rc);
3978 static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd)
3982 unsigned long timeout;
3988 /* Wait until SCU command interface is ready to receive command */
3989 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
3991 pr_err("error %d\n", rc);
3994 if (cur_cmd != DRX_SCU_READY)
3997 switch (cmd->parameter_len) {
3999 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0);
4001 pr_err("error %d\n", rc);
4006 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
4008 pr_err("error %d\n", rc);
4013 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
4015 pr_err("error %d\n", rc);
4020 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
4022 pr_err("error %d\n", rc);
4027 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
4029 pr_err("error %d\n", rc);
4037 /* this number of parameters is not supported */
4040 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0);
4042 pr_err("error %d\n", rc);
4046 /* Wait until SCU has processed command */
4047 timeout = jiffies + msecs_to_jiffies(DRXJ_MAX_WAITTIME);
4048 while (time_is_after_jiffies(timeout)) {
4049 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0);
4051 pr_err("error %d\n", rc);
4054 if (cur_cmd == DRX_SCU_READY)
4056 usleep_range(1000, 2000);
4059 if (cur_cmd != DRX_SCU_READY)
4063 if ((cmd->result_len > 0) && (cmd->result != NULL)) {
4066 switch (cmd->result_len) {
4068 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0);
4070 pr_err("error %d\n", rc);
4075 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
4077 pr_err("error %d\n", rc);
4082 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
4084 pr_err("error %d\n", rc);
4089 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
4091 pr_err("error %d\n", rc);
4099 /* this number of parameters is not supported */
4103 /* Check if an error was reported by SCU */
4104 err = cmd->result[0];
4106 /* check a few fixed error codes */
4107 if ((err == (s16) SCU_RAM_PARAM_0_RESULT_UNKSTD)
4108 || (err == (s16) SCU_RAM_PARAM_0_RESULT_UNKCMD)
4109 || (err == (s16) SCU_RAM_PARAM_0_RESULT_INVPAR)
4110 || (err == (s16) SCU_RAM_PARAM_0_RESULT_SIZE)
4114 /* here it is assumed that negative means error, and positive no error */
4128 * \fn int DRXJ_DAP_SCUAtomicReadWriteBlock()
4129 * \brief Basic access routine for SCU atomic read or write access
4130 * \param dev_addr pointer to i2c dev address
4131 * \param addr destination/source address
4132 * \param datasize size of data buffer in bytes
4133 * \param data pointer to data buffer
4136 * \retval -EIO Timeout, I2C error, illegal bank
4139 #define ADDR_AT_SCU_SPACE(x) ((x - 0x82E000) * 2)
4141 int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */
4142 u8 *data, bool read_flag)
4144 struct drxjscu_cmd scu_cmd;
4146 u16 set_param_parameters[18];
4149 /* Parameter check */
4150 if (!data || !dev_addr || (datasize % 2) || ((datasize / 2) > 16))
4153 set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr);
4154 if (read_flag) { /* read */
4155 set_param_parameters[0] = ((~(0x0080)) & datasize);
4156 scu_cmd.parameter_len = 2;
4157 scu_cmd.result_len = datasize / 2 + 2;
4161 set_param_parameters[0] = 0x0080 | datasize;
4162 for (i = 0; i < (datasize / 2); i++) {
4163 set_param_parameters[i + 2] =
4164 (data[2 * i] | (data[(2 * i) + 1] << 8));
4166 scu_cmd.parameter_len = datasize / 2 + 2;
4167 scu_cmd.result_len = 1;
4171 SCU_RAM_COMMAND_STANDARD_TOP |
4172 SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS;
4173 scu_cmd.result = cmd_result;
4174 scu_cmd.parameter = set_param_parameters;
4175 rc = scu_command(dev_addr, &scu_cmd);
4177 pr_err("error %d\n", rc);
4183 /* read data from buffer */
4184 for (i = 0; i < (datasize / 2); i++) {
4185 data[2 * i] = (u8) (scu_cmd.result[i + 2] & 0xFF);
4186 data[(2 * i) + 1] = (u8) (scu_cmd.result[i + 2] >> 8);
4197 /*============================================================================*/
4200 * \fn int DRXJ_DAP_AtomicReadReg16()
4201 * \brief Atomic read of 16 bits words
4204 int drxj_dap_scu_atomic_read_reg16(struct i2c_device_addr *dev_addr,
4206 u16 *data, u32 flags)
4215 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true);
4219 word = (u16) (buf[0] + (buf[1] << 8));
4226 /*============================================================================*/
4228 * \fn int drxj_dap_scu_atomic_write_reg16()
4229 * \brief Atomic read of 16 bits words
4232 int drxj_dap_scu_atomic_write_reg16(struct i2c_device_addr *dev_addr,
4234 u16 data, u32 flags)
4239 buf[0] = (u8) (data & 0xff);
4240 buf[1] = (u8) ((data >> 8) & 0xff);
4242 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false);
4247 /* -------------------------------------------------------------------------- */
4249 * \brief Measure result of ADC synchronisation
4250 * \param demod demod instance
4251 * \param count (returned) count
4254 * \retval -EIO Failure: I2C error
4257 static int adc_sync_measurement(struct drx_demod_instance *demod, u16 *count)
4259 struct i2c_device_addr *dev_addr = NULL;
4263 dev_addr = demod->my_i2c_dev_addr;
4265 /* Start measurement */
4266 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0);
4268 pr_err("error %d\n", rc);
4271 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0);
4273 pr_err("error %d\n", rc);
4277 /* Wait at least 3*128*(1/sysclk) <<< 1 millisec */
4281 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0);
4283 pr_err("error %d\n", rc);
4287 *count = *count + 1;
4288 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0);
4290 pr_err("error %d\n", rc);
4294 *count = *count + 1;
4295 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0);
4297 pr_err("error %d\n", rc);
4301 *count = *count + 1;
4309 * \brief Synchronize analog and digital clock domains
4310 * \param demod demod instance
4313 * \retval -EIO Failure: I2C error or failure to synchronize
4315 * An IQM reset will also reset the results of this synchronization.
4316 * After an IQM reset this routine needs to be called again.
4320 static int adc_synchronization(struct drx_demod_instance *demod)
4322 struct i2c_device_addr *dev_addr = NULL;
4326 dev_addr = demod->my_i2c_dev_addr;
4328 rc = adc_sync_measurement(demod, &count);
4330 pr_err("error %d\n", rc);
4335 /* Try sampling on a different edge */
4338 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0);
4340 pr_err("error %d\n", rc);
4344 clk_neg ^= IQM_AF_CLKNEG_CLKNEGDATA__M;
4345 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0);
4347 pr_err("error %d\n", rc);
4351 rc = adc_sync_measurement(demod, &count);
4353 pr_err("error %d\n", rc);
4358 /* TODO: implement fallback scenarios */
4367 /*============================================================================*/
4368 /*== END AUXILIARY FUNCTIONS ==*/
4369 /*============================================================================*/
4371 /*============================================================================*/
4372 /*============================================================================*/
4373 /*== 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/
4374 /*============================================================================*/
4375 /*============================================================================*/
4377 * \fn int init_agc ()
4378 * \brief Initialize AGC for all standards.
4379 * \param demod instance of demodulator.
4380 * \param channel pointer to channel data.
4383 static int init_agc(struct drx_demod_instance *demod)
4385 struct i2c_device_addr *dev_addr = NULL;
4386 struct drx_common_attr *common_attr = NULL;
4387 struct drxj_data *ext_attr = NULL;
4388 struct drxj_cfg_agc *p_agc_rf_settings = NULL;
4389 struct drxj_cfg_agc *p_agc_if_settings = NULL;
4391 u16 ingain_tgt_max = 0;
4393 u16 sns_sum_max = 0;
4394 u16 clp_sum_max = 0;
4396 u16 ki_innergain_min = 0;
4399 u16 if_iaccu_hi_tgt_min = 0;
4401 u16 agc_ki_dgain = 0;
4403 u16 clp_ctrl_mode = 0;
4407 dev_addr = demod->my_i2c_dev_addr;
4408 common_attr = (struct drx_common_attr *) demod->my_common_attr;
4409 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4411 switch (ext_attr->standard) {
4412 case DRX_STANDARD_8VSB:
4414 clp_dir_to = (u16) (-9);
4416 sns_dir_to = (u16) (-9);
4417 ki_innergain_min = (u16) (-32768);
4420 if_iaccu_hi_tgt_min = 2047;
4422 ingain_tgt_max = 16383;
4424 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4426 pr_err("error %d\n", rc);
4429 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4431 pr_err("error %d\n", rc);
4434 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4436 pr_err("error %d\n", rc);
4439 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4441 pr_err("error %d\n", rc);
4444 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4446 pr_err("error %d\n", rc);
4449 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4451 pr_err("error %d\n", rc);
4454 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4456 pr_err("error %d\n", rc);
4459 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4461 pr_err("error %d\n", rc);
4464 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4466 pr_err("error %d\n", rc);
4469 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4471 pr_err("error %d\n", rc);
4474 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0);
4476 pr_err("error %d\n", rc);
4479 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0);
4481 pr_err("error %d\n", rc);
4484 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0);
4486 pr_err("error %d\n", rc);
4489 p_agc_if_settings = &(ext_attr->vsb_if_agc_cfg);
4490 p_agc_rf_settings = &(ext_attr->vsb_rf_agc_cfg);
4492 #ifndef DRXJ_VSB_ONLY
4493 case DRX_STANDARD_ITU_A:
4494 case DRX_STANDARD_ITU_C:
4495 case DRX_STANDARD_ITU_B:
4496 ingain_tgt_max = 5119;
4498 clp_dir_to = (u16) (-5);
4500 sns_dir_to = (u16) (-3);
4501 ki_innergain_min = 0;
4503 if_iaccu_hi_tgt_min = 2047;
4507 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0);
4509 pr_err("error %d\n", rc);
4512 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0);
4514 pr_err("error %d\n", rc);
4517 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0);
4519 pr_err("error %d\n", rc);
4522 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0);
4524 pr_err("error %d\n", rc);
4527 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0);
4529 pr_err("error %d\n", rc);
4532 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0);
4534 pr_err("error %d\n", rc);
4537 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0);
4539 pr_err("error %d\n", rc);
4542 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0);
4544 pr_err("error %d\n", rc);
4547 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0);
4549 pr_err("error %d\n", rc);
4552 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0);
4554 pr_err("error %d\n", rc);
4557 p_agc_if_settings = &(ext_attr->qam_if_agc_cfg);
4558 p_agc_rf_settings = &(ext_attr->qam_rf_agc_cfg);
4559 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0);
4561 pr_err("error %d\n", rc);
4565 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0);
4567 pr_err("error %d\n", rc);
4571 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0);
4573 pr_err("error %d\n", rc);
4582 /* for new AGC interface */
4583 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0);
4585 pr_err("error %d\n", rc);
4588 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0);
4590 pr_err("error %d\n", rc);
4592 } /* Gain fed from inner to outer AGC */
4593 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0);
4595 pr_err("error %d\n", rc);
4598 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0);
4600 pr_err("error %d\n", rc);
4603 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0);
4605 pr_err("error %d\n", rc);
4607 } /* set to p_agc_settings->top before */
4608 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0);
4610 pr_err("error %d\n", rc);
4613 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0);
4615 pr_err("error %d\n", rc);
4618 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0);
4620 pr_err("error %d\n", rc);
4623 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0);
4625 pr_err("error %d\n", rc);
4628 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0);
4630 pr_err("error %d\n", rc);
4633 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0);
4635 pr_err("error %d\n", rc);
4638 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0);
4640 pr_err("error %d\n", rc);
4643 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0);
4645 pr_err("error %d\n", rc);
4648 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0);
4650 pr_err("error %d\n", rc);
4653 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0);
4655 pr_err("error %d\n", rc);
4658 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0);
4660 pr_err("error %d\n", rc);
4663 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0);
4665 pr_err("error %d\n", rc);
4668 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0);
4670 pr_err("error %d\n", rc);
4673 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0);
4675 pr_err("error %d\n", rc);
4678 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0);
4680 pr_err("error %d\n", rc);
4683 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0);
4685 pr_err("error %d\n", rc);
4688 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0);
4690 pr_err("error %d\n", rc);
4693 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0);
4695 pr_err("error %d\n", rc);
4698 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0);
4700 pr_err("error %d\n", rc);
4703 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0);
4705 pr_err("error %d\n", rc);
4708 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0);
4710 pr_err("error %d\n", rc);
4714 agc_rf = 0x800 + p_agc_rf_settings->cut_off_current;
4715 if (common_attr->tuner_rf_agc_pol == true)
4716 agc_rf = 0x87ff - agc_rf;
4719 if (common_attr->tuner_if_agc_pol == true)
4720 agc_rf = 0x87ff - agc_rf;
4722 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0);
4724 pr_err("error %d\n", rc);
4727 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0);
4729 pr_err("error %d\n", rc);
4733 /* Set/restore Ki DGAIN factor */
4734 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4736 pr_err("error %d\n", rc);
4739 data &= ~SCU_RAM_AGC_KI_DGAIN__M;
4740 data |= (agc_ki_dgain << SCU_RAM_AGC_KI_DGAIN__B);
4741 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4743 pr_err("error %d\n", rc);
4753 * \fn int set_frequency ()
4754 * \brief Set frequency shift.
4755 * \param demod instance of demodulator.
4756 * \param channel pointer to channel data.
4757 * \param tuner_freq_offset residual frequency from tuner.
4761 set_frequency(struct drx_demod_instance *demod,
4762 struct drx_channel *channel, s32 tuner_freq_offset)
4764 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
4765 struct drxj_data *ext_attr = demod->my_ext_attr;
4767 s32 sampling_frequency = 0;
4768 s32 frequency_shift = 0;
4769 s32 if_freq_actual = 0;
4770 s32 rf_freq_residual = -1 * tuner_freq_offset;
4772 s32 intermediate_freq = 0;
4773 u32 iqm_fs_rate_ofs = 0;
4774 bool adc_flip = true;
4775 bool select_pos_image = false;
4778 bool image_to_select;
4779 s32 fm_frequency_shift = 0;
4781 rf_mirror = (ext_attr->mirror == DRX_MIRROR_YES) ? true : false;
4782 tuner_mirror = demod->my_common_attr->mirror_freq_spect ? false : true;
4784 Program frequency shifter
4785 No need to account for mirroring on RF
4787 switch (ext_attr->standard) {
4788 case DRX_STANDARD_ITU_A:
4789 case DRX_STANDARD_ITU_C:
4790 case DRX_STANDARD_PAL_SECAM_LP:
4791 case DRX_STANDARD_8VSB:
4792 select_pos_image = true;
4794 case DRX_STANDARD_FM:
4795 /* After IQM FS sound carrier must appear at 4 Mhz in spect.
4796 Sound carrier is already 3Mhz above centre frequency due
4797 to tuner setting so now add an extra shift of 1MHz... */
4798 fm_frequency_shift = 1000;
4800 case DRX_STANDARD_ITU_B:
4801 case DRX_STANDARD_NTSC:
4802 case DRX_STANDARD_PAL_SECAM_BG:
4803 case DRX_STANDARD_PAL_SECAM_DK:
4804 case DRX_STANDARD_PAL_SECAM_I:
4805 case DRX_STANDARD_PAL_SECAM_L:
4806 select_pos_image = false;
4811 intermediate_freq = demod->my_common_attr->intermediate_freq;
4812 sampling_frequency = demod->my_common_attr->sys_clock_freq / 3;
4814 if_freq_actual = intermediate_freq + rf_freq_residual + fm_frequency_shift;
4816 if_freq_actual = intermediate_freq - rf_freq_residual - fm_frequency_shift;
4817 if (if_freq_actual > sampling_frequency / 2) {
4819 adc_freq = sampling_frequency - if_freq_actual;
4822 /* adc doesn't mirror */
4823 adc_freq = if_freq_actual;
4827 frequency_shift = adc_freq;
4829 (bool) (rf_mirror ^ tuner_mirror ^ adc_flip ^ select_pos_image);
4830 iqm_fs_rate_ofs = frac28(frequency_shift, sampling_frequency);
4832 if (image_to_select)
4833 iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
4835 /* Program frequency shifter with tuner offset compensation */
4836 /* frequency_shift += tuner_freq_offset; TODO */
4837 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
4839 pr_err("error %d\n", rc);
4842 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
4843 ext_attr->pos_image = (bool) (rf_mirror ^ tuner_mirror ^ select_pos_image);
4851 * \fn int get_acc_pkt_err()
4852 * \brief Retrieve signal strength for VSB and QAM.
4853 * \param demod Pointer to demod instance
4854 * \param packet_err Pointer to packet error
4856 * \retval 0 sig_strength contains valid data.
4857 * \retval -EINVAL sig_strength is NULL.
4858 * \retval -EIO Erroneous data, sig_strength contains invalid data.
4860 #ifdef DRXJ_SIGNAL_ACCUM_ERR
4861 static int get_acc_pkt_err(struct drx_demod_instance *demod, u16 *packet_err)
4865 static u16 last_pkt_err;
4867 struct drxj_data *ext_attr = NULL;
4868 struct i2c_device_addr *dev_addr = NULL;
4870 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4871 dev_addr = demod->my_i2c_dev_addr;
4873 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0);
4875 pr_err("error %d\n", rc);
4878 if (ext_attr->reset_pkt_err_acc) {
4879 last_pkt_err = data;
4881 ext_attr->reset_pkt_err_acc = false;
4884 if (data < last_pkt_err) {
4885 pkt_err += 0xffff - last_pkt_err;
4888 pkt_err += (data - last_pkt_err);
4890 *packet_err = pkt_err;
4891 last_pkt_err = data;
4900 /*============================================================================*/
4903 * \fn int set_agc_rf ()
4904 * \brief Configure RF AGC
4905 * \param demod instance of demodulator.
4906 * \param agc_settings AGC configuration structure
4910 set_agc_rf(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
4912 struct i2c_device_addr *dev_addr = NULL;
4913 struct drxj_data *ext_attr = NULL;
4914 struct drxj_cfg_agc *p_agc_settings = NULL;
4915 struct drx_common_attr *common_attr = NULL;
4917 drx_write_reg16func_t scu_wr16 = NULL;
4918 drx_read_reg16func_t scu_rr16 = NULL;
4920 common_attr = (struct drx_common_attr *) demod->my_common_attr;
4921 dev_addr = demod->my_i2c_dev_addr;
4922 ext_attr = (struct drxj_data *) demod->my_ext_attr;
4925 scu_rr16 = drxj_dap_scu_atomic_read_reg16;
4926 scu_wr16 = drxj_dap_scu_atomic_write_reg16;
4928 scu_rr16 = drxj_dap_read_reg16;
4929 scu_wr16 = drxj_dap_write_reg16;
4932 /* Configure AGC only if standard is currently active */
4933 if ((ext_attr->standard == agc_settings->standard) ||
4934 (DRXJ_ISQAMSTD(ext_attr->standard) &&
4935 DRXJ_ISQAMSTD(agc_settings->standard)) ||
4936 (DRXJ_ISATVSTD(ext_attr->standard) &&
4937 DRXJ_ISATVSTD(agc_settings->standard))) {
4940 switch (agc_settings->ctrl_mode) {
4941 case DRX_AGC_CTRL_AUTO:
4943 /* Enable RF AGC DAC */
4944 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
4946 pr_err("error %d\n", rc);
4949 data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
4950 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
4952 pr_err("error %d\n", rc);
4956 /* Enable SCU RF AGC loop */
4957 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
4959 pr_err("error %d\n", rc);
4962 data &= ~SCU_RAM_AGC_KI_RF__M;
4963 if (ext_attr->standard == DRX_STANDARD_8VSB)
4964 data |= (2 << SCU_RAM_AGC_KI_RF__B);
4965 else if (DRXJ_ISQAMSTD(ext_attr->standard))
4966 data |= (5 << SCU_RAM_AGC_KI_RF__B);
4968 data |= (4 << SCU_RAM_AGC_KI_RF__B);
4970 if (common_attr->tuner_rf_agc_pol)
4971 data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
4973 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
4974 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
4976 pr_err("error %d\n", rc);
4980 /* Set speed ( using complementary reduction value ) */
4981 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
4983 pr_err("error %d\n", rc);
4986 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
4987 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAGC_RED__B) & SCU_RAM_AGC_KI_RED_RAGC_RED__M) | data, 0);
4989 pr_err("error %d\n", rc);
4993 if (agc_settings->standard == DRX_STANDARD_8VSB)
4994 p_agc_settings = &(ext_attr->vsb_if_agc_cfg);
4995 else if (DRXJ_ISQAMSTD(agc_settings->standard))
4996 p_agc_settings = &(ext_attr->qam_if_agc_cfg);
4997 else if (DRXJ_ISATVSTD(agc_settings->standard))
4998 p_agc_settings = &(ext_attr->atv_if_agc_cfg);
5002 /* Set TOP, only if IF-AGC is in AUTO mode */
5003 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
5004 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0);
5006 pr_err("error %d\n", rc);
5009 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0);
5011 pr_err("error %d\n", rc);
5016 /* Cut-Off current */
5017 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0);
5019 pr_err("error %d\n", rc);
5023 case DRX_AGC_CTRL_USER:
5025 /* Enable RF AGC DAC */
5026 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5028 pr_err("error %d\n", rc);
5031 data |= IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE;
5032 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5034 pr_err("error %d\n", rc);
5038 /* Disable SCU RF AGC loop */
5039 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5041 pr_err("error %d\n", rc);
5044 data &= ~SCU_RAM_AGC_KI_RF__M;
5045 if (common_attr->tuner_rf_agc_pol)
5046 data |= SCU_RAM_AGC_KI_INV_RF_POL__M;
5048 data &= ~SCU_RAM_AGC_KI_INV_RF_POL__M;
5049 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5051 pr_err("error %d\n", rc);
5055 /* Write value to output pin */
5056 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0);
5058 pr_err("error %d\n", rc);
5062 case DRX_AGC_CTRL_OFF:
5064 /* Disable RF AGC DAC */
5065 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5067 pr_err("error %d\n", rc);
5070 data &= (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5071 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5073 pr_err("error %d\n", rc);
5077 /* Disable SCU RF AGC loop */
5078 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5080 pr_err("error %d\n", rc);
5083 data &= ~SCU_RAM_AGC_KI_RF__M;
5084 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5086 pr_err("error %d\n", rc);
5092 } /* switch ( agcsettings->ctrl_mode ) */
5095 /* Store rf agc settings */
5096 switch (agc_settings->standard) {
5097 case DRX_STANDARD_8VSB:
5098 ext_attr->vsb_rf_agc_cfg = *agc_settings;
5100 #ifndef DRXJ_VSB_ONLY
5101 case DRX_STANDARD_ITU_A:
5102 case DRX_STANDARD_ITU_B:
5103 case DRX_STANDARD_ITU_C:
5104 ext_attr->qam_rf_agc_cfg = *agc_settings;
5117 * \fn int set_agc_if ()
5118 * \brief Configure If AGC
5119 * \param demod instance of demodulator.
5120 * \param agc_settings AGC configuration structure
5124 set_agc_if(struct drx_demod_instance *demod, struct drxj_cfg_agc *agc_settings, bool atomic)
5126 struct i2c_device_addr *dev_addr = NULL;
5127 struct drxj_data *ext_attr = NULL;
5128 struct drxj_cfg_agc *p_agc_settings = NULL;
5129 struct drx_common_attr *common_attr = NULL;
5130 drx_write_reg16func_t scu_wr16 = NULL;
5131 drx_read_reg16func_t scu_rr16 = NULL;
5134 common_attr = (struct drx_common_attr *) demod->my_common_attr;
5135 dev_addr = demod->my_i2c_dev_addr;
5136 ext_attr = (struct drxj_data *) demod->my_ext_attr;
5139 scu_rr16 = drxj_dap_scu_atomic_read_reg16;
5140 scu_wr16 = drxj_dap_scu_atomic_write_reg16;
5142 scu_rr16 = drxj_dap_read_reg16;
5143 scu_wr16 = drxj_dap_write_reg16;
5146 /* Configure AGC only if standard is currently active */
5147 if ((ext_attr->standard == agc_settings->standard) ||
5148 (DRXJ_ISQAMSTD(ext_attr->standard) &&
5149 DRXJ_ISQAMSTD(agc_settings->standard)) ||
5150 (DRXJ_ISATVSTD(ext_attr->standard) &&
5151 DRXJ_ISATVSTD(agc_settings->standard))) {
5154 switch (agc_settings->ctrl_mode) {
5155 case DRX_AGC_CTRL_AUTO:
5156 /* Enable IF AGC DAC */
5157 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5159 pr_err("error %d\n", rc);
5162 data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5163 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5165 pr_err("error %d\n", rc);
5169 /* Enable SCU IF AGC loop */
5170 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5172 pr_err("error %d\n", rc);
5175 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5176 data &= ~SCU_RAM_AGC_KI_IF__M;
5177 if (ext_attr->standard == DRX_STANDARD_8VSB)
5178 data |= (3 << SCU_RAM_AGC_KI_IF__B);
5179 else if (DRXJ_ISQAMSTD(ext_attr->standard))
5180 data |= (6 << SCU_RAM_AGC_KI_IF__B);
5182 data |= (5 << SCU_RAM_AGC_KI_IF__B);
5184 if (common_attr->tuner_if_agc_pol)
5185 data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5187 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5188 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5190 pr_err("error %d\n", rc);
5194 /* Set speed (using complementary reduction value) */
5195 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0);
5197 pr_err("error %d\n", rc);
5200 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
5201 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IAGC_RED__B) & SCU_RAM_AGC_KI_RED_IAGC_RED__M) | data, 0);
5203 pr_err("error %d\n", rc);
5207 if (agc_settings->standard == DRX_STANDARD_8VSB)
5208 p_agc_settings = &(ext_attr->vsb_rf_agc_cfg);
5209 else if (DRXJ_ISQAMSTD(agc_settings->standard))
5210 p_agc_settings = &(ext_attr->qam_rf_agc_cfg);
5211 else if (DRXJ_ISATVSTD(agc_settings->standard))
5212 p_agc_settings = &(ext_attr->atv_rf_agc_cfg);
5217 if (p_agc_settings->ctrl_mode == DRX_AGC_CTRL_AUTO) {
5218 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0);
5220 pr_err("error %d\n", rc);
5223 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0);
5225 pr_err("error %d\n", rc);
5229 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0);
5231 pr_err("error %d\n", rc);
5234 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0);
5236 pr_err("error %d\n", rc);
5242 case DRX_AGC_CTRL_USER:
5244 /* Enable IF AGC DAC */
5245 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5247 pr_err("error %d\n", rc);
5250 data |= IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE;
5251 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5253 pr_err("error %d\n", rc);
5257 /* Disable SCU IF AGC loop */
5258 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5260 pr_err("error %d\n", rc);
5263 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5264 data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5265 if (common_attr->tuner_if_agc_pol)
5266 data |= SCU_RAM_AGC_KI_INV_IF_POL__M;
5268 data &= ~SCU_RAM_AGC_KI_INV_IF_POL__M;
5269 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5271 pr_err("error %d\n", rc);
5275 /* Write value to output pin */
5276 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0);
5278 pr_err("error %d\n", rc);
5283 case DRX_AGC_CTRL_OFF:
5285 /* Disable If AGC DAC */
5286 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5288 pr_err("error %d\n", rc);
5291 data &= (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE);
5292 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5294 pr_err("error %d\n", rc);
5298 /* Disable SCU IF AGC loop */
5299 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0);
5301 pr_err("error %d\n", rc);
5304 data &= ~SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5305 data |= SCU_RAM_AGC_KI_IF_AGC_DISABLE__M;
5306 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0);
5308 pr_err("error %d\n", rc);
5314 } /* switch ( agcsettings->ctrl_mode ) */
5316 /* always set the top to support configurations without if-loop */
5317 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0);
5319 pr_err("error %d\n", rc);
5324 /* Store if agc settings */
5325 switch (agc_settings->standard) {
5326 case DRX_STANDARD_8VSB:
5327 ext_attr->vsb_if_agc_cfg = *agc_settings;
5329 #ifndef DRXJ_VSB_ONLY
5330 case DRX_STANDARD_ITU_A:
5331 case DRX_STANDARD_ITU_B:
5332 case DRX_STANDARD_ITU_C:
5333 ext_attr->qam_if_agc_cfg = *agc_settings;
5346 * \fn int set_iqm_af ()
5347 * \brief Configure IQM AF registers
5348 * \param demod instance of demodulator.
5352 static int set_iqm_af(struct drx_demod_instance *demod, bool active)
5355 struct i2c_device_addr *dev_addr = NULL;
5358 dev_addr = demod->my_i2c_dev_addr;
5361 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
5363 pr_err("error %d\n", rc);
5367 data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE));
5369 data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
5370 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
5372 pr_err("error %d\n", rc);
5381 /*============================================================================*/
5382 /*== END 8VSB & QAM COMMON DATAPATH FUNCTIONS ==*/
5383 /*============================================================================*/
5385 /*============================================================================*/
5386 /*============================================================================*/
5387 /*== 8VSB DATAPATH FUNCTIONS ==*/
5388 /*============================================================================*/
5389 /*============================================================================*/
5392 * \fn int power_down_vsb ()
5393 * \brief Powr down QAM related blocks.
5394 * \param demod instance of demodulator.
5395 * \param channel pointer to channel data.
5398 static int power_down_vsb(struct drx_demod_instance *demod, bool primary)
5400 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
5401 struct drxjscu_cmd cmd_scu = { /* command */ 0,
5402 /* parameter_len */ 0,
5404 /* *parameter */ NULL,
5407 struct drx_cfg_mpeg_output cfg_mpeg_output;
5413 reset of FEC and VSB HW
5415 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
5416 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
5417 cmd_scu.parameter_len = 0;
5418 cmd_scu.result_len = 1;
5419 cmd_scu.parameter = NULL;
5420 cmd_scu.result = &cmd_result;
5421 rc = scu_command(dev_addr, &cmd_scu);
5423 pr_err("error %d\n", rc);
5427 /* stop all comm_exec */
5428 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5430 pr_err("error %d\n", rc);
5433 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5435 pr_err("error %d\n", rc);
5439 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
5441 pr_err("error %d\n", rc);
5444 rc = set_iqm_af(demod, false);
5446 pr_err("error %d\n", rc);
5450 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5452 pr_err("error %d\n", rc);
5455 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5457 pr_err("error %d\n", rc);
5460 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5462 pr_err("error %d\n", rc);
5465 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5467 pr_err("error %d\n", rc);
5470 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5472 pr_err("error %d\n", rc);
5477 cfg_mpeg_output.enable_mpeg_output = false;
5478 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
5480 pr_err("error %d\n", rc);
5490 * \fn int set_vsb_leak_n_gain ()
5491 * \brief Set ATSC demod.
5492 * \param demod instance of demodulator.
5495 static int set_vsb_leak_n_gain(struct drx_demod_instance *demod)
5497 struct i2c_device_addr *dev_addr = NULL;
5500 static const u8 vsb_ffe_leak_gain_ram0[] = {
5501 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO1 */
5502 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO2 */
5503 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO3 */
5504 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO4 */
5505 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO5 */
5506 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO6 */
5507 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO7 */
5508 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO8 */
5509 DRXJ_16TO8(0xf), /* FFETRAINLKRATIO9 */
5510 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO10 */
5511 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO11 */
5512 DRXJ_16TO8(0x8), /* FFETRAINLKRATIO12 */
5513 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO1 */
5514 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO2 */
5515 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO3 */
5516 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO4 */
5517 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO5 */
5518 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO6 */
5519 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO7 */
5520 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO8 */
5521 DRXJ_16TO8(0x20), /* FFERCA1TRAINLKRATIO9 */
5522 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO10 */
5523 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO11 */
5524 DRXJ_16TO8(0x10), /* FFERCA1TRAINLKRATIO12 */
5525 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO1 */
5526 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO2 */
5527 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO3 */
5528 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO4 */
5529 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO5 */
5530 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO6 */
5531 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO7 */
5532 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO8 */
5533 DRXJ_16TO8(0x20), /* FFERCA1DATALKRATIO9 */
5534 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO10 */
5535 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO11 */
5536 DRXJ_16TO8(0x10), /* FFERCA1DATALKRATIO12 */
5537 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO1 */
5538 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO2 */
5539 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO3 */
5540 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO4 */
5541 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO5 */
5542 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO6 */
5543 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO7 */
5544 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO8 */
5545 DRXJ_16TO8(0x20), /* FFERCA2TRAINLKRATIO9 */
5546 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO10 */
5547 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO11 */
5548 DRXJ_16TO8(0x10), /* FFERCA2TRAINLKRATIO12 */
5549 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO1 */
5550 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO2 */
5551 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO3 */
5552 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO4 */
5553 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO5 */
5554 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO6 */
5555 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO7 */
5556 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO8 */
5557 DRXJ_16TO8(0x20), /* FFERCA2DATALKRATIO9 */
5558 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO10 */
5559 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO11 */
5560 DRXJ_16TO8(0x10), /* FFERCA2DATALKRATIO12 */
5561 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO1 */
5562 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO2 */
5563 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO3 */
5564 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO4 */
5565 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO5 */
5566 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO6 */
5567 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO7 */
5568 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO8 */
5569 DRXJ_16TO8(0x0e), /* FFEDDM1TRAINLKRATIO9 */
5570 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO10 */
5571 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO11 */
5572 DRXJ_16TO8(0x07), /* FFEDDM1TRAINLKRATIO12 */
5573 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO1 */
5574 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO2 */
5575 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO3 */
5576 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO4 */
5577 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO5 */
5578 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO6 */
5579 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO7 */
5580 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO8 */
5581 DRXJ_16TO8(0x0e), /* FFEDDM1DATALKRATIO9 */
5582 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO10 */
5583 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO11 */
5584 DRXJ_16TO8(0x07), /* FFEDDM1DATALKRATIO12 */
5585 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO1 */
5586 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO2 */
5587 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO3 */
5588 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO4 */
5589 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO5 */
5590 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO6 */
5591 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO7 */
5592 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO8 */
5593 DRXJ_16TO8(0x0c), /* FFEDDM2TRAINLKRATIO9 */
5594 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO10 */
5595 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO11 */
5596 DRXJ_16TO8(0x06), /* FFEDDM2TRAINLKRATIO12 */
5597 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO1 */
5598 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO2 */
5599 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO3 */
5600 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO4 */
5601 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO5 */
5602 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO6 */
5603 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO7 */
5604 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO8 */
5605 DRXJ_16TO8(0x0c), /* FFEDDM2DATALKRATIO9 */
5606 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO10 */
5607 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO11 */
5608 DRXJ_16TO8(0x06), /* FFEDDM2DATALKRATIO12 */
5609 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN1 */
5610 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN2 */
5611 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN3 */
5612 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN4 */
5613 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN5 */
5614 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN6 */
5615 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN7 */
5616 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN8 */
5617 DRXJ_16TO8(0x4040), /* FIRTRAINGAIN9 */
5618 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN10 */
5619 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN11 */
5620 DRXJ_16TO8(0x2020), /* FIRTRAINGAIN12 */
5621 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN1 */
5622 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN2 */
5623 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN3 */
5624 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN4 */
5625 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN5 */
5626 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN6 */
5627 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN7 */
5628 DRXJ_16TO8(0x1010) /* FIRRCA1GAIN8 */
5631 static const u8 vsb_ffe_leak_gain_ram1[] = {
5632 DRXJ_16TO8(0x1010), /* FIRRCA1GAIN9 */
5633 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN10 */
5634 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN11 */
5635 DRXJ_16TO8(0x0808), /* FIRRCA1GAIN12 */
5636 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN1 */
5637 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN2 */
5638 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN3 */
5639 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN4 */
5640 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN5 */
5641 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN6 */
5642 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN7 */
5643 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN8 */
5644 DRXJ_16TO8(0x1010), /* FIRRCA2GAIN9 */
5645 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN10 */
5646 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN11 */
5647 DRXJ_16TO8(0x0808), /* FIRRCA2GAIN12 */
5648 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN1 */
5649 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN2 */
5650 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN3 */
5651 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN4 */
5652 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN5 */
5653 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN6 */
5654 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN7 */
5655 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN8 */
5656 DRXJ_16TO8(0x0606), /* FIRDDM1GAIN9 */
5657 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN10 */
5658 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN11 */
5659 DRXJ_16TO8(0x0303), /* FIRDDM1GAIN12 */
5660 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN1 */
5661 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN2 */
5662 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN3 */
5663 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN4 */
5664 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN5 */
5665 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN6 */
5666 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN7 */
5667 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN8 */
5668 DRXJ_16TO8(0x0505), /* FIRDDM2GAIN9 */
5669 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN10 */
5670 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN11 */
5671 DRXJ_16TO8(0x0303), /* FIRDDM2GAIN12 */
5672 DRXJ_16TO8(0x001f), /* DFETRAINLKRATIO */
5673 DRXJ_16TO8(0x01ff), /* DFERCA1TRAINLKRATIO */
5674 DRXJ_16TO8(0x01ff), /* DFERCA1DATALKRATIO */
5675 DRXJ_16TO8(0x004f), /* DFERCA2TRAINLKRATIO */
5676 DRXJ_16TO8(0x004f), /* DFERCA2DATALKRATIO */
5677 DRXJ_16TO8(0x01ff), /* DFEDDM1TRAINLKRATIO */
5678 DRXJ_16TO8(0x01ff), /* DFEDDM1DATALKRATIO */
5679 DRXJ_16TO8(0x0352), /* DFEDDM2TRAINLKRATIO */
5680 DRXJ_16TO8(0x0352), /* DFEDDM2DATALKRATIO */
5681 DRXJ_16TO8(0x0000), /* DFETRAINGAIN */
5682 DRXJ_16TO8(0x2020), /* DFERCA1GAIN */
5683 DRXJ_16TO8(0x1010), /* DFERCA2GAIN */
5684 DRXJ_16TO8(0x1818), /* DFEDDM1GAIN */
5685 DRXJ_16TO8(0x1212) /* DFEDDM2GAIN */
5688 dev_addr = demod->my_i2c_dev_addr;
5689 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_gain_ram0), ((u8 *)vsb_ffe_leak_gain_ram0), 0);
5691 pr_err("error %d\n", rc);
5694 rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_ram1), ((u8 *)vsb_ffe_leak_gain_ram1), 0);
5696 pr_err("error %d\n", rc);
5707 * \brief Set 8VSB demod.
5708 * \param demod instance of demodulator.
5712 static int set_vsb(struct drx_demod_instance *demod)
5714 struct i2c_device_addr *dev_addr = NULL;
5716 struct drx_common_attr *common_attr = NULL;
5717 struct drxjscu_cmd cmd_scu;
5718 struct drxj_data *ext_attr = NULL;
5721 static const u8 vsb_taps_re[] = {
5722 DRXJ_16TO8(-2), /* re0 */
5723 DRXJ_16TO8(4), /* re1 */
5724 DRXJ_16TO8(1), /* re2 */
5725 DRXJ_16TO8(-4), /* re3 */
5726 DRXJ_16TO8(1), /* re4 */
5727 DRXJ_16TO8(4), /* re5 */
5728 DRXJ_16TO8(-3), /* re6 */
5729 DRXJ_16TO8(-3), /* re7 */
5730 DRXJ_16TO8(6), /* re8 */
5731 DRXJ_16TO8(1), /* re9 */
5732 DRXJ_16TO8(-9), /* re10 */
5733 DRXJ_16TO8(3), /* re11 */
5734 DRXJ_16TO8(12), /* re12 */
5735 DRXJ_16TO8(-9), /* re13 */
5736 DRXJ_16TO8(-15), /* re14 */
5737 DRXJ_16TO8(17), /* re15 */
5738 DRXJ_16TO8(19), /* re16 */
5739 DRXJ_16TO8(-29), /* re17 */
5740 DRXJ_16TO8(-22), /* re18 */
5741 DRXJ_16TO8(45), /* re19 */
5742 DRXJ_16TO8(25), /* re20 */
5743 DRXJ_16TO8(-70), /* re21 */
5744 DRXJ_16TO8(-28), /* re22 */
5745 DRXJ_16TO8(111), /* re23 */
5746 DRXJ_16TO8(30), /* re24 */
5747 DRXJ_16TO8(-201), /* re25 */
5748 DRXJ_16TO8(-31), /* re26 */
5749 DRXJ_16TO8(629) /* re27 */
5752 dev_addr = demod->my_i2c_dev_addr;
5753 common_attr = (struct drx_common_attr *) demod->my_common_attr;
5754 ext_attr = (struct drxj_data *) demod->my_ext_attr;
5756 /* stop all comm_exec */
5757 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
5759 pr_err("error %d\n", rc);
5762 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0);
5764 pr_err("error %d\n", rc);
5767 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
5769 pr_err("error %d\n", rc);
5772 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
5774 pr_err("error %d\n", rc);
5777 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
5779 pr_err("error %d\n", rc);
5782 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
5784 pr_err("error %d\n", rc);
5787 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
5789 pr_err("error %d\n", rc);
5793 /* reset demodulator */
5794 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
5795 | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
5796 cmd_scu.parameter_len = 0;
5797 cmd_scu.result_len = 1;
5798 cmd_scu.parameter = NULL;
5799 cmd_scu.result = &cmd_result;
5800 rc = scu_command(dev_addr, &cmd_scu);
5802 pr_err("error %d\n", rc);
5806 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0);
5808 pr_err("error %d\n", rc);
5811 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0);
5813 pr_err("error %d\n", rc);
5816 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0);
5818 pr_err("error %d\n", rc);
5821 ext_attr->iqm_rc_rate_ofs = 0x00AD0D79;
5822 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0);
5824 pr_err("error %d\n", rc);
5827 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0);
5829 pr_err("error %d\n", rc);
5832 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0);
5834 pr_err("error %d\n", rc);
5838 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0);
5840 pr_err("error %d\n", rc);
5843 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0);
5845 pr_err("error %d\n", rc);
5848 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0);
5850 pr_err("error %d\n", rc);
5853 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
5855 pr_err("error %d\n", rc);
5858 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
5860 pr_err("error %d\n", rc);
5863 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0);
5865 pr_err("error %d\n", rc);
5868 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0);
5870 pr_err("error %d\n", rc);
5873 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
5875 pr_err("error %d\n", rc);
5878 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
5880 pr_err("error %d\n", rc);
5884 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5886 pr_err("error %d\n", rc);
5889 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re), 0);
5891 pr_err("error %d\n", rc);
5895 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0);
5897 pr_err("error %d\n", rc);
5899 } /* set higher threshold */
5900 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0);
5902 pr_err("error %d\n", rc);
5904 } /* burst detection on */
5905 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0);
5907 pr_err("error %d\n", rc);
5909 } /* drop thresholds by 1 dB */
5910 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0);
5912 pr_err("error %d\n", rc);
5914 } /* drop thresholds by 2 dB */
5915 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0);
5917 pr_err("error %d\n", rc);
5920 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
5922 pr_err("error %d\n", rc);
5926 /* Initialize the FEC Subsystem */
5927 rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0);
5929 pr_err("error %d\n", rc);
5933 u16 fec_oc_snc_mode = 0;
5934 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0);
5936 pr_err("error %d\n", rc);
5939 /* output data even when not locked */
5940 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_ENABLE__M, 0);
5942 pr_err("error %d\n", rc);
5948 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
5950 pr_err("error %d\n", rc);
5953 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0);
5955 pr_err("error %d\n", rc);
5958 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
5960 pr_err("error %d\n", rc);
5963 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0);
5965 pr_err("error %d\n", rc);
5968 /* no transparent, no A&C framing; parity is set in mpegoutput */
5970 u16 fec_oc_reg_mode = 0;
5971 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0);
5973 pr_err("error %d\n", rc);
5976 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__M | FEC_OC_MODE_CLEAR__M | FEC_OC_MODE_RETAIN_FRAMING__M)), 0);
5978 pr_err("error %d\n", rc);
5983 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0);
5985 pr_err("error %d\n", rc);
5987 } /* timeout counter for restarting */
5988 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0);
5990 pr_err("error %d\n", rc);
5993 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0);
5995 pr_err("error %d\n", rc);
5997 } /* bypass disabled */
5998 /* initialize RS packet error measurement parameters */
5999 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0);
6001 pr_err("error %d\n", rc);
6004 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0);
6006 pr_err("error %d\n", rc);
6010 /* init measurement period of MER/SER */
6011 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0);
6013 pr_err("error %d\n", rc);
6016 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6018 pr_err("error %d\n", rc);
6021 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6023 pr_err("error %d\n", rc);
6026 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6028 pr_err("error %d\n", rc);
6032 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0);
6034 pr_err("error %d\n", rc);
6037 /* B-Input to ADC, PGA+filter in standby */
6038 if (!ext_attr->has_lna) {
6039 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
6041 pr_err("error %d\n", rc);
6046 /* turn on IQMAF. It has to be in front of setAgc**() */
6047 rc = set_iqm_af(demod, true);
6049 pr_err("error %d\n", rc);
6052 rc = adc_synchronization(demod);
6054 pr_err("error %d\n", rc);
6058 rc = init_agc(demod);
6060 pr_err("error %d\n", rc);
6063 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false);
6065 pr_err("error %d\n", rc);
6068 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false);
6070 pr_err("error %d\n", rc);
6074 /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
6076 struct drxj_cfg_afe_gain vsb_pga_cfg = { DRX_STANDARD_8VSB, 0 };
6078 vsb_pga_cfg.gain = ext_attr->vsb_pga_cfg;
6079 rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg);
6081 pr_err("error %d\n", rc);
6085 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg));
6087 pr_err("error %d\n", rc);
6091 /* Mpeg output has to be in front of FEC active */
6092 rc = set_mpegtei_handling(demod);
6094 pr_err("error %d\n", rc);
6097 rc = bit_reverse_mpeg_output(demod);
6099 pr_err("error %d\n", rc);
6102 rc = set_mpeg_start_width(demod);
6104 pr_err("error %d\n", rc);
6108 /* TODO: move to set_standard after hardware reset value problem is solved */
6109 /* Configure initial MPEG output */
6110 struct drx_cfg_mpeg_output cfg_mpeg_output;
6112 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6113 cfg_mpeg_output.enable_mpeg_output = true;
6115 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6117 pr_err("error %d\n", rc);
6122 /* TBD: what parameters should be set */
6123 cmd_param = 0x00; /* Default mode AGC on, etc */
6124 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
6125 | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
6126 cmd_scu.parameter_len = 1;
6127 cmd_scu.result_len = 1;
6128 cmd_scu.parameter = &cmd_param;
6129 cmd_scu.result = &cmd_result;
6130 rc = scu_command(dev_addr, &cmd_scu);
6132 pr_err("error %d\n", rc);
6136 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0);
6138 pr_err("error %d\n", rc);
6141 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0);
6143 pr_err("error %d\n", rc);
6146 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M, 0);
6148 pr_err("error %d\n", rc);
6151 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0);
6153 pr_err("error %d\n", rc);
6156 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0);
6158 pr_err("error %d\n", rc);
6161 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0);
6163 pr_err("error %d\n", rc);
6166 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0);
6168 pr_err("error %d\n", rc);
6171 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0);
6173 pr_err("error %d\n", rc);
6177 /* start demodulator */
6178 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB
6179 | SCU_RAM_COMMAND_CMD_DEMOD_START;
6180 cmd_scu.parameter_len = 0;
6181 cmd_scu.result_len = 1;
6182 cmd_scu.parameter = NULL;
6183 cmd_scu.result = &cmd_result;
6184 rc = scu_command(dev_addr, &cmd_scu);
6186 pr_err("error %d\n", rc);
6190 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
6192 pr_err("error %d\n", rc);
6195 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0);
6197 pr_err("error %d\n", rc);
6200 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
6202 pr_err("error %d\n", rc);
6212 * \fn static short get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr, u16 *PckErrs)
6213 * \brief Get the values of packet error in 8VSB mode
6214 * \return Error code
6216 static int get_vsb_post_rs_pck_err(struct i2c_device_addr *dev_addr,
6217 u32 *pck_errs, u32 *pck_count)
6223 u16 packet_errors_mant = 0;
6224 u16 packet_errors_exp = 0;
6226 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0);
6228 pr_err("error %d\n", rc);
6231 packet_errors_mant = data & FEC_RS_NR_FAILURES_FIXED_MANT__M;
6232 packet_errors_exp = (data & FEC_RS_NR_FAILURES_EXP__M)
6233 >> FEC_RS_NR_FAILURES_EXP__B;
6234 period = FEC_RS_MEASUREMENT_PERIOD;
6235 prescale = FEC_RS_MEASUREMENT_PRESCALE;
6236 /* packet error rate = (error packet number) per second */
6237 /* 77.3 us is time for per packet */
6238 if (period * prescale == 0) {
6239 pr_err("error: period and/or prescale is zero!\n");
6242 *pck_errs = packet_errors_mant * (1 << packet_errors_exp);
6243 *pck_count = period * prescale * 77;
6251 * \fn static short GetVSBBer(struct i2c_device_addr *dev_addr, u32 *ber)
6252 * \brief Get the values of ber in VSB mode
6253 * \return Error code
6255 static int get_vs_bpost_viterbi_ber(struct i2c_device_addr *dev_addr,
6262 u16 bit_errors_mant = 0;
6263 u16 bit_errors_exp = 0;
6265 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0);
6267 pr_err("error %d\n", rc);
6270 period = FEC_RS_MEASUREMENT_PERIOD;
6271 prescale = FEC_RS_MEASUREMENT_PRESCALE;
6273 bit_errors_mant = data & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M;
6274 bit_errors_exp = (data & FEC_RS_NR_BIT_ERRORS_EXP__M)
6275 >> FEC_RS_NR_BIT_ERRORS_EXP__B;
6277 *cnt = period * prescale * 207 * ((bit_errors_exp > 2) ? 1 : 8);
6279 if (((bit_errors_mant << bit_errors_exp) >> 3) > 68700)
6280 *ber = (*cnt) * 26570;
6282 if (period * prescale == 0) {
6283 pr_err("error: period and/or prescale is zero!\n");
6286 *ber = bit_errors_mant << ((bit_errors_exp > 2) ?
6287 (bit_errors_exp - 3) : bit_errors_exp);
6296 * \fn static short get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr, u32 *ber)
6297 * \brief Get the values of ber in VSB mode
6298 * \return Error code
6300 static int get_vs_bpre_viterbi_ber(struct i2c_device_addr *dev_addr,
6306 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0);
6308 pr_err("error %d\n", rc);
6312 *cnt = VSB_TOP_MEASUREMENT_PERIOD * SYMBOLS_PER_SEGMENT;
6318 * \fn static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
6319 * \brief Get the values of MER
6320 * \return Error code
6322 static int get_vsbmer(struct i2c_device_addr *dev_addr, u16 *mer)
6327 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0);
6329 pr_err("error %d\n", rc);
6333 (u16) (log1_times100(21504) - log1_times100((data_hi << 6) / 52));
6341 /*============================================================================*/
6342 /*== END 8VSB DATAPATH FUNCTIONS ==*/
6343 /*============================================================================*/
6345 /*============================================================================*/
6346 /*============================================================================*/
6347 /*== QAM DATAPATH FUNCTIONS ==*/
6348 /*============================================================================*/
6349 /*============================================================================*/
6352 * \fn int power_down_qam ()
6353 * \brief Powr down QAM related blocks.
6354 * \param demod instance of demodulator.
6355 * \param channel pointer to channel data.
6358 static int power_down_qam(struct drx_demod_instance *demod, bool primary)
6360 struct drxjscu_cmd cmd_scu = { /* command */ 0,
6361 /* parameter_len */ 0,
6363 /* *parameter */ NULL,
6367 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6368 struct drx_cfg_mpeg_output cfg_mpeg_output;
6369 struct drx_common_attr *common_attr = demod->my_common_attr;
6374 resets IQM, QAM and FEC HW blocks
6376 /* stop all comm_exec */
6377 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
6379 pr_err("error %d\n", rc);
6382 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
6384 pr_err("error %d\n", rc);
6388 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
6389 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
6390 cmd_scu.parameter_len = 0;
6391 cmd_scu.result_len = 1;
6392 cmd_scu.parameter = NULL;
6393 cmd_scu.result = &cmd_result;
6394 rc = scu_command(dev_addr, &cmd_scu);
6396 pr_err("error %d\n", rc);
6401 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
6403 pr_err("error %d\n", rc);
6406 rc = set_iqm_af(demod, false);
6408 pr_err("error %d\n", rc);
6412 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
6414 pr_err("error %d\n", rc);
6417 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
6419 pr_err("error %d\n", rc);
6422 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
6424 pr_err("error %d\n", rc);
6427 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
6429 pr_err("error %d\n", rc);
6432 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
6434 pr_err("error %d\n", rc);
6439 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
6440 cfg_mpeg_output.enable_mpeg_output = false;
6442 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
6444 pr_err("error %d\n", rc);
6453 /*============================================================================*/
6456 * \fn int set_qam_measurement ()
6457 * \brief Setup of the QAM Measuremnt intervals for signal quality
6458 * \param demod instance of demod.
6459 * \param constellation current constellation.
6463 * Take into account that for certain settings the errorcounters can overflow.
6464 * The implementation does not check this.
6466 * TODO: overriding the ext_attr->fec_bits_desired by constellation dependent
6467 * constants to get a measurement period of approx. 1 sec. Remove fec_bits_desired
6471 #ifndef DRXJ_VSB_ONLY
6473 set_qam_measurement(struct drx_demod_instance *demod,
6474 enum drx_modulation constellation, u32 symbol_rate)
6476 struct i2c_device_addr *dev_addr = NULL; /* device address for I2C writes */
6477 struct drxj_data *ext_attr = NULL; /* Global data container for DRXJ specific data */
6479 u32 fec_bits_desired = 0; /* BER accounting period */
6480 u16 fec_rs_plen = 0; /* defines RS BER measurement period */
6481 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
6482 u32 fec_rs_period = 0; /* Value for corresponding I2C register */
6483 u32 fec_rs_bit_cnt = 0; /* Actual precise amount of bits */
6484 u32 fec_oc_snc_fail_period = 0; /* Value for corresponding I2C register */
6485 u32 qam_vd_period = 0; /* Value for corresponding I2C register */
6486 u32 qam_vd_bit_cnt = 0; /* Actual precise amount of bits */
6487 u16 fec_vd_plen = 0; /* no of trellis symbols: VD SER measur period */
6488 u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */
6490 dev_addr = demod->my_i2c_dev_addr;
6491 ext_attr = (struct drxj_data *) demod->my_ext_attr;
6493 fec_bits_desired = ext_attr->fec_bits_desired;
6494 fec_rs_prescale = ext_attr->fec_rs_prescale;
6496 switch (constellation) {
6497 case DRX_CONSTELLATION_QAM16:
6498 fec_bits_desired = 4 * symbol_rate;
6500 case DRX_CONSTELLATION_QAM32:
6501 fec_bits_desired = 5 * symbol_rate;
6503 case DRX_CONSTELLATION_QAM64:
6504 fec_bits_desired = 6 * symbol_rate;
6506 case DRX_CONSTELLATION_QAM128:
6507 fec_bits_desired = 7 * symbol_rate;
6509 case DRX_CONSTELLATION_QAM256:
6510 fec_bits_desired = 8 * symbol_rate;
6516 /* Parameters for Reed-Solomon Decoder */
6517 /* fecrs_period = (int)ceil(FEC_BITS_DESIRED/(fecrs_prescale*plen)) */
6518 /* rs_bit_cnt = fecrs_period*fecrs_prescale*plen */
6519 /* result is within 32 bit arithmetic -> */
6520 /* no need for mult or frac functions */
6522 /* TODO: use constant instead of calculation and remove the fec_rs_plen in ext_attr */
6523 switch (ext_attr->standard) {
6524 case DRX_STANDARD_ITU_A:
6525 case DRX_STANDARD_ITU_C:
6526 fec_rs_plen = 204 * 8;
6528 case DRX_STANDARD_ITU_B:
6529 fec_rs_plen = 128 * 7;
6535 ext_attr->fec_rs_plen = fec_rs_plen; /* for getSigQual */
6536 fec_rs_bit_cnt = fec_rs_prescale * fec_rs_plen; /* temp storage */
6537 if (fec_rs_bit_cnt == 0) {
6538 pr_err("error: fec_rs_bit_cnt is zero!\n");
6541 fec_rs_period = fec_bits_desired / fec_rs_bit_cnt + 1; /* ceil */
6542 if (ext_attr->standard != DRX_STANDARD_ITU_B)
6543 fec_oc_snc_fail_period = fec_rs_period;
6545 /* limit to max 16 bit value (I2C register width) if needed */
6546 if (fec_rs_period > 0xFFFF)
6547 fec_rs_period = 0xFFFF;
6549 /* write corresponding registers */
6550 switch (ext_attr->standard) {
6551 case DRX_STANDARD_ITU_A:
6552 case DRX_STANDARD_ITU_C:
6554 case DRX_STANDARD_ITU_B:
6555 switch (constellation) {
6556 case DRX_CONSTELLATION_QAM64:
6557 fec_rs_period = 31581;
6558 fec_oc_snc_fail_period = 17932;
6560 case DRX_CONSTELLATION_QAM256:
6561 fec_rs_period = 45446;
6562 fec_oc_snc_fail_period = 25805;
6572 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0);
6574 pr_err("error %d\n", rc);
6577 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0);
6579 pr_err("error %d\n", rc);
6582 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0);
6584 pr_err("error %d\n", rc);
6587 ext_attr->fec_rs_period = (u16) fec_rs_period;
6588 ext_attr->fec_rs_prescale = fec_rs_prescale;
6589 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0);
6591 pr_err("error %d\n", rc);
6594 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0);
6596 pr_err("error %d\n", rc);
6599 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0);
6601 pr_err("error %d\n", rc);
6605 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
6606 /* Parameters for Viterbi Decoder */
6607 /* qamvd_period = (int)ceil(FEC_BITS_DESIRED/ */
6608 /* (qamvd_prescale*plen*(qam_constellation+1))) */
6609 /* vd_bit_cnt = qamvd_period*qamvd_prescale*plen */
6610 /* result is within 32 bit arithmetic -> */
6611 /* no need for mult or frac functions */
6613 /* a(8 bit) * b(8 bit) = 16 bit result => mult32 not needed */
6614 fec_vd_plen = ext_attr->fec_vd_plen;
6615 qam_vd_prescale = ext_attr->qam_vd_prescale;
6616 qam_vd_bit_cnt = qam_vd_prescale * fec_vd_plen; /* temp storage */
6618 switch (constellation) {
6619 case DRX_CONSTELLATION_QAM64:
6620 /* a(16 bit) * b(4 bit) = 20 bit result => mult32 not needed */
6622 qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM64 + 1)
6623 * (QAM_TOP_CONSTELLATION_QAM64 + 1);
6625 case DRX_CONSTELLATION_QAM256:
6626 /* a(16 bit) * b(5 bit) = 21 bit result => mult32 not needed */
6628 qam_vd_bit_cnt * (QAM_TOP_CONSTELLATION_QAM256 + 1)
6629 * (QAM_TOP_CONSTELLATION_QAM256 + 1);
6634 if (qam_vd_period == 0) {
6635 pr_err("error: qam_vd_period is zero!\n");
6638 qam_vd_period = fec_bits_desired / qam_vd_period;
6639 /* limit to max 16 bit value (I2C register width) if needed */
6640 if (qam_vd_period > 0xFFFF)
6641 qam_vd_period = 0xFFFF;
6643 /* a(16 bit) * b(16 bit) = 32 bit result => mult32 not needed */
6644 qam_vd_bit_cnt *= qam_vd_period;
6646 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0);
6648 pr_err("error %d\n", rc);
6651 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0);
6653 pr_err("error %d\n", rc);
6656 ext_attr->qam_vd_period = (u16) qam_vd_period;
6657 ext_attr->qam_vd_prescale = qam_vd_prescale;
6665 /*============================================================================*/
6668 * \fn int set_qam16 ()
6669 * \brief QAM16 specific setup
6670 * \param demod instance of demod.
6673 static int set_qam16(struct drx_demod_instance *demod)
6675 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6677 static const u8 qam_dq_qual_fun[] = {
6678 DRXJ_16TO8(2), /* fun0 */
6679 DRXJ_16TO8(2), /* fun1 */
6680 DRXJ_16TO8(2), /* fun2 */
6681 DRXJ_16TO8(2), /* fun3 */
6682 DRXJ_16TO8(3), /* fun4 */
6683 DRXJ_16TO8(3), /* fun5 */
6685 static const u8 qam_eq_cma_rad[] = {
6686 DRXJ_16TO8(13517), /* RAD0 */
6687 DRXJ_16TO8(13517), /* RAD1 */
6688 DRXJ_16TO8(13517), /* RAD2 */
6689 DRXJ_16TO8(13517), /* RAD3 */
6690 DRXJ_16TO8(13517), /* RAD4 */
6691 DRXJ_16TO8(13517), /* RAD5 */
6694 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6696 pr_err("error %d\n", rc);
6699 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6701 pr_err("error %d\n", rc);
6705 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0);
6707 pr_err("error %d\n", rc);
6710 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6712 pr_err("error %d\n", rc);
6715 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0);
6717 pr_err("error %d\n", rc);
6720 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0);
6722 pr_err("error %d\n", rc);
6725 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0);
6727 pr_err("error %d\n", rc);
6730 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0);
6732 pr_err("error %d\n", rc);
6736 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6738 pr_err("error %d\n", rc);
6741 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6743 pr_err("error %d\n", rc);
6746 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6748 pr_err("error %d\n", rc);
6752 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0);
6754 pr_err("error %d\n", rc);
6757 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0);
6759 pr_err("error %d\n", rc);
6762 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0);
6764 pr_err("error %d\n", rc);
6767 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0);
6769 pr_err("error %d\n", rc);
6772 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0);
6774 pr_err("error %d\n", rc);
6777 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0);
6779 pr_err("error %d\n", rc);
6782 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0);
6784 pr_err("error %d\n", rc);
6788 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
6790 pr_err("error %d\n", rc);
6793 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
6795 pr_err("error %d\n", rc);
6798 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
6800 pr_err("error %d\n", rc);
6803 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
6805 pr_err("error %d\n", rc);
6808 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
6810 pr_err("error %d\n", rc);
6813 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
6815 pr_err("error %d\n", rc);
6818 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
6820 pr_err("error %d\n", rc);
6823 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
6825 pr_err("error %d\n", rc);
6828 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
6830 pr_err("error %d\n", rc);
6833 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
6835 pr_err("error %d\n", rc);
6838 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
6840 pr_err("error %d\n", rc);
6843 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
6845 pr_err("error %d\n", rc);
6848 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
6850 pr_err("error %d\n", rc);
6853 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
6855 pr_err("error %d\n", rc);
6858 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
6860 pr_err("error %d\n", rc);
6863 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
6865 pr_err("error %d\n", rc);
6868 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0);
6870 pr_err("error %d\n", rc);
6873 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
6875 pr_err("error %d\n", rc);
6878 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
6880 pr_err("error %d\n", rc);
6883 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
6885 pr_err("error %d\n", rc);
6889 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0);
6891 pr_err("error %d\n", rc);
6900 /*============================================================================*/
6903 * \fn int set_qam32 ()
6904 * \brief QAM32 specific setup
6905 * \param demod instance of demod.
6908 static int set_qam32(struct drx_demod_instance *demod)
6910 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
6912 static const u8 qam_dq_qual_fun[] = {
6913 DRXJ_16TO8(3), /* fun0 */
6914 DRXJ_16TO8(3), /* fun1 */
6915 DRXJ_16TO8(3), /* fun2 */
6916 DRXJ_16TO8(3), /* fun3 */
6917 DRXJ_16TO8(4), /* fun4 */
6918 DRXJ_16TO8(4), /* fun5 */
6920 static const u8 qam_eq_cma_rad[] = {
6921 DRXJ_16TO8(6707), /* RAD0 */
6922 DRXJ_16TO8(6707), /* RAD1 */
6923 DRXJ_16TO8(6707), /* RAD2 */
6924 DRXJ_16TO8(6707), /* RAD3 */
6925 DRXJ_16TO8(6707), /* RAD4 */
6926 DRXJ_16TO8(6707), /* RAD5 */
6929 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
6931 pr_err("error %d\n", rc);
6934 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
6936 pr_err("error %d\n", rc);
6940 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0);
6942 pr_err("error %d\n", rc);
6945 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0);
6947 pr_err("error %d\n", rc);
6950 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
6952 pr_err("error %d\n", rc);
6955 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0);
6957 pr_err("error %d\n", rc);
6960 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
6962 pr_err("error %d\n", rc);
6965 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
6967 pr_err("error %d\n", rc);
6971 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
6973 pr_err("error %d\n", rc);
6976 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0);
6978 pr_err("error %d\n", rc);
6981 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
6983 pr_err("error %d\n", rc);
6987 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
6989 pr_err("error %d\n", rc);
6992 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0);
6994 pr_err("error %d\n", rc);
6997 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0);
6999 pr_err("error %d\n", rc);
7002 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0);
7004 pr_err("error %d\n", rc);
7007 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0);
7009 pr_err("error %d\n", rc);
7012 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0);
7014 pr_err("error %d\n", rc);
7017 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0);
7019 pr_err("error %d\n", rc);
7023 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7025 pr_err("error %d\n", rc);
7028 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7030 pr_err("error %d\n", rc);
7033 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7035 pr_err("error %d\n", rc);
7038 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0);
7040 pr_err("error %d\n", rc);
7043 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7045 pr_err("error %d\n", rc);
7048 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7050 pr_err("error %d\n", rc);
7053 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0);
7055 pr_err("error %d\n", rc);
7058 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0);
7060 pr_err("error %d\n", rc);
7063 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7065 pr_err("error %d\n", rc);
7068 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7070 pr_err("error %d\n", rc);
7073 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7075 pr_err("error %d\n", rc);
7078 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7080 pr_err("error %d\n", rc);
7083 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7085 pr_err("error %d\n", rc);
7088 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7090 pr_err("error %d\n", rc);
7093 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7095 pr_err("error %d\n", rc);
7098 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7100 pr_err("error %d\n", rc);
7103 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0);
7105 pr_err("error %d\n", rc);
7108 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7110 pr_err("error %d\n", rc);
7113 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7115 pr_err("error %d\n", rc);
7118 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0);
7120 pr_err("error %d\n", rc);
7124 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0);
7126 pr_err("error %d\n", rc);
7135 /*============================================================================*/
7138 * \fn int set_qam64 ()
7139 * \brief QAM64 specific setup
7140 * \param demod instance of demod.
7143 static int set_qam64(struct drx_demod_instance *demod)
7145 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7147 static const u8 qam_dq_qual_fun[] = {
7148 /* this is hw reset value. no necessary to re-write */
7149 DRXJ_16TO8(4), /* fun0 */
7150 DRXJ_16TO8(4), /* fun1 */
7151 DRXJ_16TO8(4), /* fun2 */
7152 DRXJ_16TO8(4), /* fun3 */
7153 DRXJ_16TO8(6), /* fun4 */
7154 DRXJ_16TO8(6), /* fun5 */
7156 static const u8 qam_eq_cma_rad[] = {
7157 DRXJ_16TO8(13336), /* RAD0 */
7158 DRXJ_16TO8(12618), /* RAD1 */
7159 DRXJ_16TO8(11988), /* RAD2 */
7160 DRXJ_16TO8(13809), /* RAD3 */
7161 DRXJ_16TO8(13809), /* RAD4 */
7162 DRXJ_16TO8(15609), /* RAD5 */
7165 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7167 pr_err("error %d\n", rc);
7170 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7172 pr_err("error %d\n", rc);
7176 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0);
7178 pr_err("error %d\n", rc);
7181 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7183 pr_err("error %d\n", rc);
7186 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7188 pr_err("error %d\n", rc);
7191 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0);
7193 pr_err("error %d\n", rc);
7196 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7198 pr_err("error %d\n", rc);
7201 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0);
7203 pr_err("error %d\n", rc);
7207 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7209 pr_err("error %d\n", rc);
7212 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7214 pr_err("error %d\n", rc);
7217 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7219 pr_err("error %d\n", rc);
7223 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0);
7225 pr_err("error %d\n", rc);
7228 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0);
7230 pr_err("error %d\n", rc);
7233 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0);
7235 pr_err("error %d\n", rc);
7238 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0);
7240 pr_err("error %d\n", rc);
7243 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0);
7245 pr_err("error %d\n", rc);
7248 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0);
7250 pr_err("error %d\n", rc);
7253 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0);
7255 pr_err("error %d\n", rc);
7259 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7261 pr_err("error %d\n", rc);
7264 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7266 pr_err("error %d\n", rc);
7269 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7271 pr_err("error %d\n", rc);
7274 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0);
7276 pr_err("error %d\n", rc);
7279 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7281 pr_err("error %d\n", rc);
7284 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7286 pr_err("error %d\n", rc);
7289 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0);
7291 pr_err("error %d\n", rc);
7294 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7296 pr_err("error %d\n", rc);
7299 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7301 pr_err("error %d\n", rc);
7304 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7306 pr_err("error %d\n", rc);
7309 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7311 pr_err("error %d\n", rc);
7314 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7316 pr_err("error %d\n", rc);
7319 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7321 pr_err("error %d\n", rc);
7324 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7326 pr_err("error %d\n", rc);
7329 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7331 pr_err("error %d\n", rc);
7334 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7336 pr_err("error %d\n", rc);
7339 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0);
7341 pr_err("error %d\n", rc);
7344 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7346 pr_err("error %d\n", rc);
7349 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7351 pr_err("error %d\n", rc);
7354 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0);
7356 pr_err("error %d\n", rc);
7360 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0);
7362 pr_err("error %d\n", rc);
7371 /*============================================================================*/
7374 * \fn int set_qam128 ()
7375 * \brief QAM128 specific setup
7376 * \param demod: instance of demod.
7379 static int set_qam128(struct drx_demod_instance *demod)
7381 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7383 static const u8 qam_dq_qual_fun[] = {
7384 DRXJ_16TO8(6), /* fun0 */
7385 DRXJ_16TO8(6), /* fun1 */
7386 DRXJ_16TO8(6), /* fun2 */
7387 DRXJ_16TO8(6), /* fun3 */
7388 DRXJ_16TO8(9), /* fun4 */
7389 DRXJ_16TO8(9), /* fun5 */
7391 static const u8 qam_eq_cma_rad[] = {
7392 DRXJ_16TO8(6164), /* RAD0 */
7393 DRXJ_16TO8(6598), /* RAD1 */
7394 DRXJ_16TO8(6394), /* RAD2 */
7395 DRXJ_16TO8(6409), /* RAD3 */
7396 DRXJ_16TO8(6656), /* RAD4 */
7397 DRXJ_16TO8(7238), /* RAD5 */
7400 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7402 pr_err("error %d\n", rc);
7405 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7407 pr_err("error %d\n", rc);
7411 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7413 pr_err("error %d\n", rc);
7416 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7418 pr_err("error %d\n", rc);
7421 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7423 pr_err("error %d\n", rc);
7426 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0);
7428 pr_err("error %d\n", rc);
7431 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7433 pr_err("error %d\n", rc);
7436 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0);
7438 pr_err("error %d\n", rc);
7442 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7444 pr_err("error %d\n", rc);
7447 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0);
7449 pr_err("error %d\n", rc);
7452 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7454 pr_err("error %d\n", rc);
7458 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7460 pr_err("error %d\n", rc);
7463 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0);
7465 pr_err("error %d\n", rc);
7468 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0);
7470 pr_err("error %d\n", rc);
7473 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0);
7475 pr_err("error %d\n", rc);
7478 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0);
7480 pr_err("error %d\n", rc);
7483 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0);
7485 pr_err("error %d\n", rc);
7488 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0);
7490 pr_err("error %d\n", rc);
7494 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7496 pr_err("error %d\n", rc);
7499 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7501 pr_err("error %d\n", rc);
7504 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7506 pr_err("error %d\n", rc);
7509 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0);
7511 pr_err("error %d\n", rc);
7514 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7516 pr_err("error %d\n", rc);
7519 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7521 pr_err("error %d\n", rc);
7524 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0);
7526 pr_err("error %d\n", rc);
7529 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7531 pr_err("error %d\n", rc);
7534 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7536 pr_err("error %d\n", rc);
7539 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7541 pr_err("error %d\n", rc);
7544 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7546 pr_err("error %d\n", rc);
7549 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7551 pr_err("error %d\n", rc);
7554 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7556 pr_err("error %d\n", rc);
7559 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7561 pr_err("error %d\n", rc);
7564 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7566 pr_err("error %d\n", rc);
7569 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0);
7571 pr_err("error %d\n", rc);
7574 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0);
7576 pr_err("error %d\n", rc);
7579 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7581 pr_err("error %d\n", rc);
7584 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7586 pr_err("error %d\n", rc);
7589 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7591 pr_err("error %d\n", rc);
7595 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0);
7597 pr_err("error %d\n", rc);
7606 /*============================================================================*/
7609 * \fn int set_qam256 ()
7610 * \brief QAM256 specific setup
7611 * \param demod: instance of demod.
7614 static int set_qam256(struct drx_demod_instance *demod)
7616 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
7618 static const u8 qam_dq_qual_fun[] = {
7619 DRXJ_16TO8(8), /* fun0 */
7620 DRXJ_16TO8(8), /* fun1 */
7621 DRXJ_16TO8(8), /* fun2 */
7622 DRXJ_16TO8(8), /* fun3 */
7623 DRXJ_16TO8(12), /* fun4 */
7624 DRXJ_16TO8(12), /* fun5 */
7626 static const u8 qam_eq_cma_rad[] = {
7627 DRXJ_16TO8(12345), /* RAD0 */
7628 DRXJ_16TO8(12345), /* RAD1 */
7629 DRXJ_16TO8(13626), /* RAD2 */
7630 DRXJ_16TO8(12931), /* RAD3 */
7631 DRXJ_16TO8(14719), /* RAD4 */
7632 DRXJ_16TO8(15356), /* RAD5 */
7635 rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq_qual_fun), 0);
7637 pr_err("error %d\n", rc);
7640 rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)qam_eq_cma_rad), 0);
7642 pr_err("error %d\n", rc);
7646 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0);
7648 pr_err("error %d\n", rc);
7651 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0);
7653 pr_err("error %d\n", rc);
7656 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0);
7658 pr_err("error %d\n", rc);
7661 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0);
7663 pr_err("error %d\n", rc);
7666 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0);
7668 pr_err("error %d\n", rc);
7671 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0);
7673 pr_err("error %d\n", rc);
7677 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0);
7679 pr_err("error %d\n", rc);
7682 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0);
7684 pr_err("error %d\n", rc);
7687 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0);
7689 pr_err("error %d\n", rc);
7693 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0);
7695 pr_err("error %d\n", rc);
7698 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0);
7700 pr_err("error %d\n", rc);
7703 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0);
7705 pr_err("error %d\n", rc);
7708 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0);
7710 pr_err("error %d\n", rc);
7713 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0);
7715 pr_err("error %d\n", rc);
7718 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0);
7720 pr_err("error %d\n", rc);
7723 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0);
7725 pr_err("error %d\n", rc);
7729 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0);
7731 pr_err("error %d\n", rc);
7734 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0);
7736 pr_err("error %d\n", rc);
7739 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0);
7741 pr_err("error %d\n", rc);
7744 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0);
7746 pr_err("error %d\n", rc);
7749 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0);
7751 pr_err("error %d\n", rc);
7754 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0);
7756 pr_err("error %d\n", rc);
7759 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0);
7761 pr_err("error %d\n", rc);
7764 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0);
7766 pr_err("error %d\n", rc);
7769 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0);
7771 pr_err("error %d\n", rc);
7774 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0);
7776 pr_err("error %d\n", rc);
7779 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0);
7781 pr_err("error %d\n", rc);
7784 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0);
7786 pr_err("error %d\n", rc);
7789 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0);
7791 pr_err("error %d\n", rc);
7794 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0);
7796 pr_err("error %d\n", rc);
7799 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0);
7801 pr_err("error %d\n", rc);
7804 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0);
7806 pr_err("error %d\n", rc);
7809 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0);
7811 pr_err("error %d\n", rc);
7814 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0);
7816 pr_err("error %d\n", rc);
7819 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0);
7821 pr_err("error %d\n", rc);
7824 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0);
7826 pr_err("error %d\n", rc);
7830 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0);
7832 pr_err("error %d\n", rc);
7841 /*============================================================================*/
7842 #define QAM_SET_OP_ALL 0x1
7843 #define QAM_SET_OP_CONSTELLATION 0x2
7844 #define QAM_SET_OP_SPECTRUM 0X4
7847 * \fn int set_qam ()
7848 * \brief Set QAM demod.
7849 * \param demod: instance of demod.
7850 * \param channel: pointer to channel data.
7854 set_qam(struct drx_demod_instance *demod,
7855 struct drx_channel *channel, s32 tuner_freq_offset, u32 op)
7857 struct i2c_device_addr *dev_addr = NULL;
7858 struct drxj_data *ext_attr = NULL;
7859 struct drx_common_attr *common_attr = NULL;
7861 u32 adc_frequency = 0;
7862 u32 iqm_rc_rate = 0;
7864 u16 lc_symbol_freq = 0;
7865 u16 iqm_rc_stretch = 0;
7866 u16 set_env_parameters = 0;
7867 u16 set_param_parameters[2] = { 0 };
7868 struct drxjscu_cmd cmd_scu = { /* command */ 0,
7869 /* parameter_len */ 0,
7871 /* parameter */ NULL,
7874 static const u8 qam_a_taps[] = {
7875 DRXJ_16TO8(-1), /* re0 */
7876 DRXJ_16TO8(1), /* re1 */
7877 DRXJ_16TO8(1), /* re2 */
7878 DRXJ_16TO8(-1), /* re3 */
7879 DRXJ_16TO8(-1), /* re4 */
7880 DRXJ_16TO8(2), /* re5 */
7881 DRXJ_16TO8(1), /* re6 */
7882 DRXJ_16TO8(-2), /* re7 */
7883 DRXJ_16TO8(0), /* re8 */
7884 DRXJ_16TO8(3), /* re9 */
7885 DRXJ_16TO8(-1), /* re10 */
7886 DRXJ_16TO8(-3), /* re11 */
7887 DRXJ_16TO8(4), /* re12 */
7888 DRXJ_16TO8(1), /* re13 */
7889 DRXJ_16TO8(-8), /* re14 */
7890 DRXJ_16TO8(4), /* re15 */
7891 DRXJ_16TO8(13), /* re16 */
7892 DRXJ_16TO8(-13), /* re17 */
7893 DRXJ_16TO8(-19), /* re18 */
7894 DRXJ_16TO8(28), /* re19 */
7895 DRXJ_16TO8(25), /* re20 */
7896 DRXJ_16TO8(-53), /* re21 */
7897 DRXJ_16TO8(-31), /* re22 */
7898 DRXJ_16TO8(96), /* re23 */
7899 DRXJ_16TO8(37), /* re24 */
7900 DRXJ_16TO8(-190), /* re25 */
7901 DRXJ_16TO8(-40), /* re26 */
7902 DRXJ_16TO8(619) /* re27 */
7904 static const u8 qam_b64_taps[] = {
7905 DRXJ_16TO8(0), /* re0 */
7906 DRXJ_16TO8(-2), /* re1 */
7907 DRXJ_16TO8(1), /* re2 */
7908 DRXJ_16TO8(2), /* re3 */
7909 DRXJ_16TO8(-2), /* re4 */
7910 DRXJ_16TO8(0), /* re5 */
7911 DRXJ_16TO8(4), /* re6 */
7912 DRXJ_16TO8(-2), /* re7 */
7913 DRXJ_16TO8(-4), /* re8 */
7914 DRXJ_16TO8(4), /* re9 */
7915 DRXJ_16TO8(3), /* re10 */
7916 DRXJ_16TO8(-6), /* re11 */
7917 DRXJ_16TO8(0), /* re12 */
7918 DRXJ_16TO8(6), /* re13 */
7919 DRXJ_16TO8(-5), /* re14 */
7920 DRXJ_16TO8(-3), /* re15 */
7921 DRXJ_16TO8(11), /* re16 */
7922 DRXJ_16TO8(-4), /* re17 */
7923 DRXJ_16TO8(-19), /* re18 */
7924 DRXJ_16TO8(19), /* re19 */
7925 DRXJ_16TO8(28), /* re20 */
7926 DRXJ_16TO8(-45), /* re21 */
7927 DRXJ_16TO8(-36), /* re22 */
7928 DRXJ_16TO8(90), /* re23 */
7929 DRXJ_16TO8(42), /* re24 */
7930 DRXJ_16TO8(-185), /* re25 */
7931 DRXJ_16TO8(-46), /* re26 */
7932 DRXJ_16TO8(614) /* re27 */
7934 static const u8 qam_b256_taps[] = {
7935 DRXJ_16TO8(-2), /* re0 */
7936 DRXJ_16TO8(4), /* re1 */
7937 DRXJ_16TO8(1), /* re2 */
7938 DRXJ_16TO8(-4), /* re3 */
7939 DRXJ_16TO8(0), /* re4 */
7940 DRXJ_16TO8(4), /* re5 */
7941 DRXJ_16TO8(-2), /* re6 */
7942 DRXJ_16TO8(-4), /* re7 */
7943 DRXJ_16TO8(5), /* re8 */
7944 DRXJ_16TO8(2), /* re9 */
7945 DRXJ_16TO8(-8), /* re10 */
7946 DRXJ_16TO8(2), /* re11 */
7947 DRXJ_16TO8(11), /* re12 */
7948 DRXJ_16TO8(-8), /* re13 */
7949 DRXJ_16TO8(-15), /* re14 */
7950 DRXJ_16TO8(16), /* re15 */
7951 DRXJ_16TO8(19), /* re16 */
7952 DRXJ_16TO8(-27), /* re17 */
7953 DRXJ_16TO8(-22), /* re18 */
7954 DRXJ_16TO8(44), /* re19 */
7955 DRXJ_16TO8(26), /* re20 */
7956 DRXJ_16TO8(-69), /* re21 */
7957 DRXJ_16TO8(-28), /* re22 */
7958 DRXJ_16TO8(110), /* re23 */
7959 DRXJ_16TO8(31), /* re24 */
7960 DRXJ_16TO8(-201), /* re25 */
7961 DRXJ_16TO8(-32), /* re26 */
7962 DRXJ_16TO8(628) /* re27 */
7964 static const u8 qam_c_taps[] = {
7965 DRXJ_16TO8(-3), /* re0 */
7966 DRXJ_16TO8(3), /* re1 */
7967 DRXJ_16TO8(2), /* re2 */
7968 DRXJ_16TO8(-4), /* re3 */
7969 DRXJ_16TO8(0), /* re4 */
7970 DRXJ_16TO8(4), /* re5 */
7971 DRXJ_16TO8(-1), /* re6 */
7972 DRXJ_16TO8(-4), /* re7 */
7973 DRXJ_16TO8(3), /* re8 */
7974 DRXJ_16TO8(3), /* re9 */
7975 DRXJ_16TO8(-5), /* re10 */
7976 DRXJ_16TO8(0), /* re11 */
7977 DRXJ_16TO8(9), /* re12 */
7978 DRXJ_16TO8(-4), /* re13 */
7979 DRXJ_16TO8(-12), /* re14 */
7980 DRXJ_16TO8(10), /* re15 */
7981 DRXJ_16TO8(16), /* re16 */
7982 DRXJ_16TO8(-21), /* re17 */
7983 DRXJ_16TO8(-20), /* re18 */
7984 DRXJ_16TO8(37), /* re19 */
7985 DRXJ_16TO8(25), /* re20 */
7986 DRXJ_16TO8(-62), /* re21 */
7987 DRXJ_16TO8(-28), /* re22 */
7988 DRXJ_16TO8(105), /* re23 */
7989 DRXJ_16TO8(31), /* re24 */
7990 DRXJ_16TO8(-197), /* re25 */
7991 DRXJ_16TO8(-33), /* re26 */
7992 DRXJ_16TO8(626) /* re27 */
7995 dev_addr = demod->my_i2c_dev_addr;
7996 ext_attr = (struct drxj_data *) demod->my_ext_attr;
7997 common_attr = (struct drx_common_attr *) demod->my_common_attr;
7999 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8000 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8001 switch (channel->constellation) {
8002 case DRX_CONSTELLATION_QAM256:
8003 iqm_rc_rate = 0x00AE3562;
8005 QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256;
8006 channel->symbolrate = 5360537;
8007 iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_256;
8009 case DRX_CONSTELLATION_QAM64:
8010 iqm_rc_rate = 0x00C05A0E;
8011 lc_symbol_freq = 409;
8012 channel->symbolrate = 5056941;
8013 iqm_rc_stretch = IQM_RC_STRETCH_QAM_B_64;
8019 adc_frequency = (common_attr->sys_clock_freq * 1000) / 3;
8020 if (channel->symbolrate == 0) {
8021 pr_err("error: channel symbolrate is zero!\n");
8025 (adc_frequency / channel->symbolrate) * (1 << 21) +
8027 ((adc_frequency % channel->symbolrate),
8028 channel->symbolrate) >> 7) - (1 << 23);
8031 (channel->symbolrate +
8032 (adc_frequency >> 13),
8033 adc_frequency) >> 16);
8034 if (lc_symbol_freq > 511)
8035 lc_symbol_freq = 511;
8037 iqm_rc_stretch = 21;
8040 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8041 set_env_parameters = QAM_TOP_ANNEX_A; /* annex */
8042 set_param_parameters[0] = channel->constellation; /* constellation */
8043 set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */
8044 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8045 set_env_parameters = QAM_TOP_ANNEX_B; /* annex */
8046 set_param_parameters[0] = channel->constellation; /* constellation */
8047 set_param_parameters[1] = channel->interleavemode; /* interleave mode */
8048 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8049 set_env_parameters = QAM_TOP_ANNEX_C; /* annex */
8050 set_param_parameters[0] = channel->constellation; /* constellation */
8051 set_param_parameters[1] = DRX_INTERLEAVEMODE_I12_J17; /* interleave mode */
8057 if (op & QAM_SET_OP_ALL) {
8059 STEP 1: reset demodulator
8060 resets IQM, QAM and FEC HW blocks
8061 resets SCU variables
8063 /* stop all comm_exec */
8064 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0);
8066 pr_err("error %d\n", rc);
8069 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0);
8071 pr_err("error %d\n", rc);
8074 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
8076 pr_err("error %d\n", rc);
8079 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
8081 pr_err("error %d\n", rc);
8084 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
8086 pr_err("error %d\n", rc);
8089 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
8091 pr_err("error %d\n", rc);
8094 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
8096 pr_err("error %d\n", rc);
8100 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8101 SCU_RAM_COMMAND_CMD_DEMOD_RESET;
8102 cmd_scu.parameter_len = 0;
8103 cmd_scu.result_len = 1;
8104 cmd_scu.parameter = NULL;
8105 cmd_scu.result = &cmd_result;
8106 rc = scu_command(dev_addr, &cmd_scu);
8108 pr_err("error %d\n", rc);
8113 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8115 STEP 2: configure demodulator
8117 -set params (resets IQM,QAM,FEC HW; initializes some SCU variables )
8119 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8120 SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
8121 cmd_scu.parameter_len = 1;
8122 cmd_scu.result_len = 1;
8123 cmd_scu.parameter = &set_env_parameters;
8124 cmd_scu.result = &cmd_result;
8125 rc = scu_command(dev_addr, &cmd_scu);
8127 pr_err("error %d\n", rc);
8131 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8132 SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM;
8133 cmd_scu.parameter_len = 2;
8134 cmd_scu.result_len = 1;
8135 cmd_scu.parameter = set_param_parameters;
8136 cmd_scu.result = &cmd_result;
8137 rc = scu_command(dev_addr, &cmd_scu);
8139 pr_err("error %d\n", rc);
8142 /* set symbol rate */
8143 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0);
8145 pr_err("error %d\n", rc);
8148 ext_attr->iqm_rc_rate_ofs = iqm_rc_rate;
8149 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate);
8151 pr_err("error %d\n", rc);
8155 /* STEP 3: enable the system in a mode where the ADC provides valid signal
8156 setup constellation independent registers */
8157 /* from qam_cmd.py script (qam_driver_b) */
8158 /* TODO: remove re-writes of HW reset values */
8159 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_SPECTRUM)) {
8160 rc = set_frequency(demod, channel, tuner_freq_offset);
8162 pr_err("error %d\n", rc);
8167 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8169 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0);
8171 pr_err("error %d\n", rc);
8174 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0);
8176 pr_err("error %d\n", rc);
8181 if (op & QAM_SET_OP_ALL) {
8182 if (!ext_attr->has_lna) {
8183 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0);
8185 pr_err("error %d\n", rc);
8189 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0);
8191 pr_err("error %d\n", rc);
8194 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0);
8196 pr_err("error %d\n", rc);
8199 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0);
8201 pr_err("error %d\n", rc);
8205 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0);
8207 pr_err("error %d\n", rc);
8209 } /* scu temporary shut down agc */
8211 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0);
8213 pr_err("error %d\n", rc);
8216 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0);
8218 pr_err("error %d\n", rc);
8221 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0);
8223 pr_err("error %d\n", rc);
8226 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0);
8228 pr_err("error %d\n", rc);
8231 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0);
8233 pr_err("error %d\n", rc);
8236 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0);
8238 pr_err("error %d\n", rc);
8241 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0);
8243 pr_err("error %d\n", rc);
8247 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0);
8249 pr_err("error %d\n", rc);
8252 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0);
8254 pr_err("error %d\n", rc);
8256 } /*! reset default val ! */
8258 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0);
8260 pr_err("error %d\n", rc);
8262 } /*! reset default val ! */
8263 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8264 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0);
8266 pr_err("error %d\n", rc);
8268 } /*! reset default val ! */
8269 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0);
8271 pr_err("error %d\n", rc);
8273 } /*! reset default val ! */
8274 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8276 pr_err("error %d\n", rc);
8278 } /*! reset default val ! */
8280 switch (channel->constellation) {
8281 case DRX_CONSTELLATION_QAM16:
8282 case DRX_CONSTELLATION_QAM64:
8283 case DRX_CONSTELLATION_QAM256:
8284 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8286 pr_err("error %d\n", rc);
8289 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0);
8291 pr_err("error %d\n", rc);
8294 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0);
8296 pr_err("error %d\n", rc);
8298 } /*! reset default val ! */
8300 case DRX_CONSTELLATION_QAM32:
8301 case DRX_CONSTELLATION_QAM128:
8302 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0);
8304 pr_err("error %d\n", rc);
8307 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0);
8309 pr_err("error %d\n", rc);
8312 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0);
8314 pr_err("error %d\n", rc);
8323 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0);
8325 pr_err("error %d\n", rc);
8327 } /*! reset default val ! */
8328 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0);
8330 pr_err("error %d\n", rc);
8333 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0);
8335 pr_err("error %d\n", rc);
8338 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0);
8340 pr_err("error %d\n", rc);
8343 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0);
8345 pr_err("error %d\n", rc);
8348 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0);
8350 pr_err("error %d\n", rc);
8353 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0);
8355 pr_err("error %d\n", rc);
8358 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0);
8360 pr_err("error %d\n", rc);
8363 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0);
8365 pr_err("error %d\n", rc);
8368 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0);
8370 pr_err("error %d\n", rc);
8373 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0);
8375 pr_err("error %d\n", rc);
8378 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0);
8380 pr_err("error %d\n", rc);
8383 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0);
8385 pr_err("error %d\n", rc);
8388 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0);
8390 pr_err("error %d\n", rc);
8393 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0);
8395 pr_err("error %d\n", rc);
8398 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0);
8400 pr_err("error %d\n", rc);
8403 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0);
8405 pr_err("error %d\n", rc);
8408 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0);
8410 pr_err("error %d\n", rc);
8413 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0);
8415 pr_err("error %d\n", rc);
8418 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0);
8420 pr_err("error %d\n", rc);
8424 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0);
8426 pr_err("error %d\n", rc);
8429 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0);
8431 pr_err("error %d\n", rc);
8434 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0);
8436 pr_err("error %d\n", rc);
8439 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0);
8441 pr_err("error %d\n", rc);
8444 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0);
8446 pr_err("error %d\n", rc);
8450 /* No more resets of the IQM, current standard correctly set =>
8451 now AGCs can be configured. */
8452 /* turn on IQMAF. It has to be in front of setAgc**() */
8453 rc = set_iqm_af(demod, true);
8455 pr_err("error %d\n", rc);
8458 rc = adc_synchronization(demod);
8460 pr_err("error %d\n", rc);
8464 rc = init_agc(demod);
8466 pr_err("error %d\n", rc);
8469 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false);
8471 pr_err("error %d\n", rc);
8474 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false);
8476 pr_err("error %d\n", rc);
8480 /* TODO fix this, store a struct drxj_cfg_afe_gain structure in struct drxj_data instead
8482 struct drxj_cfg_afe_gain qam_pga_cfg = { DRX_STANDARD_ITU_B, 0 };
8484 qam_pga_cfg.gain = ext_attr->qam_pga_cfg;
8485 rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg);
8487 pr_err("error %d\n", rc);
8491 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg));
8493 pr_err("error %d\n", rc);
8498 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8499 if (ext_attr->standard == DRX_STANDARD_ITU_A) {
8500 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8502 pr_err("error %d\n", rc);
8505 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), 0);
8507 pr_err("error %d\n", rc);
8510 } else if (ext_attr->standard == DRX_STANDARD_ITU_B) {
8511 switch (channel->constellation) {
8512 case DRX_CONSTELLATION_QAM64:
8513 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8515 pr_err("error %d\n", rc);
8518 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_taps), 0);
8520 pr_err("error %d\n", rc);
8524 case DRX_CONSTELLATION_QAM256:
8525 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8527 pr_err("error %d\n", rc);
8530 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_taps), 0);
8532 pr_err("error %d\n", rc);
8539 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
8540 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8542 pr_err("error %d\n", rc);
8545 rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), 0);
8547 pr_err("error %d\n", rc);
8552 /* SETP 4: constellation specific setup */
8553 switch (channel->constellation) {
8554 case DRX_CONSTELLATION_QAM16:
8555 rc = set_qam16(demod);
8557 pr_err("error %d\n", rc);
8561 case DRX_CONSTELLATION_QAM32:
8562 rc = set_qam32(demod);
8564 pr_err("error %d\n", rc);
8568 case DRX_CONSTELLATION_QAM64:
8569 rc = set_qam64(demod);
8571 pr_err("error %d\n", rc);
8575 case DRX_CONSTELLATION_QAM128:
8576 rc = set_qam128(demod);
8578 pr_err("error %d\n", rc);
8582 case DRX_CONSTELLATION_QAM256:
8583 rc = set_qam256(demod);
8585 pr_err("error %d\n", rc);
8594 if ((op & QAM_SET_OP_ALL)) {
8595 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0);
8597 pr_err("error %d\n", rc);
8601 /* Mpeg output has to be in front of FEC active */
8602 rc = set_mpegtei_handling(demod);
8604 pr_err("error %d\n", rc);
8607 rc = bit_reverse_mpeg_output(demod);
8609 pr_err("error %d\n", rc);
8612 rc = set_mpeg_start_width(demod);
8614 pr_err("error %d\n", rc);
8618 /* TODO: move to set_standard after hardware reset value problem is solved */
8619 /* Configure initial MPEG output */
8620 struct drx_cfg_mpeg_output cfg_mpeg_output;
8622 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
8623 cfg_mpeg_output.enable_mpeg_output = true;
8625 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
8627 pr_err("error %d\n", rc);
8633 if ((op & QAM_SET_OP_ALL) || (op & QAM_SET_OP_CONSTELLATION)) {
8635 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
8636 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
8637 SCU_RAM_COMMAND_CMD_DEMOD_START;
8638 cmd_scu.parameter_len = 0;
8639 cmd_scu.result_len = 1;
8640 cmd_scu.parameter = NULL;
8641 cmd_scu.result = &cmd_result;
8642 rc = scu_command(dev_addr, &cmd_scu);
8644 pr_err("error %d\n", rc);
8649 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0);
8651 pr_err("error %d\n", rc);
8654 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0);
8656 pr_err("error %d\n", rc);
8659 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0);
8661 pr_err("error %d\n", rc);
8670 /*============================================================================*/
8671 static int ctrl_get_qam_sig_quality(struct drx_demod_instance *demod);
8673 static int qam_flip_spec(struct drx_demod_instance *demod, struct drx_channel *channel)
8675 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8676 struct drxj_data *ext_attr = demod->my_ext_attr;
8678 u32 iqm_fs_rate_ofs = 0;
8679 u32 iqm_fs_rate_lo = 0;
8680 u16 qam_ctl_ena = 0;
8687 /* Silence the controlling of lc, equ, and the acquisition state machine */
8688 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0);
8690 pr_err("error %d\n", rc);
8693 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_ACQ__M | SCU_RAM_QAM_CTL_ENA_EQU__M | SCU_RAM_QAM_CTL_ENA_LC__M), 0);
8695 pr_err("error %d\n", rc);
8699 /* freeze the frequency control loop */
8700 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0);
8702 pr_err("error %d\n", rc);
8705 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0);
8707 pr_err("error %d\n", rc);
8711 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0);
8713 pr_err("error %d\n", rc);
8716 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0);
8718 pr_err("error %d\n", rc);
8721 ofsofs = iqm_fs_rate_lo - iqm_fs_rate_ofs;
8722 iqm_fs_rate_ofs = ~iqm_fs_rate_ofs + 1;
8723 iqm_fs_rate_ofs -= 2 * ofsofs;
8725 /* freeze dq/fq updating */
8726 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8728 pr_err("error %d\n", rc);
8731 data = (data & 0xfff9);
8732 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8734 pr_err("error %d\n", rc);
8737 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8739 pr_err("error %d\n", rc);
8743 /* lc_cp / _ci / _ca */
8744 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0);
8746 pr_err("error %d\n", rc);
8749 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0);
8751 pr_err("error %d\n", rc);
8754 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0);
8756 pr_err("error %d\n", rc);
8761 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0);
8763 pr_err("error %d\n", rc);
8766 ext_attr->iqm_fs_rate_ofs = iqm_fs_rate_ofs;
8767 ext_attr->pos_image = (ext_attr->pos_image) ? false : true;
8769 /* freeze dq/fq updating */
8770 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0);
8772 pr_err("error %d\n", rc);
8776 data = (data & 0xfff9);
8777 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8779 pr_err("error %d\n", rc);
8782 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8784 pr_err("error %d\n", rc);
8788 for (i = 0; i < 28; i++) {
8789 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8791 pr_err("error %d\n", rc);
8794 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8796 pr_err("error %d\n", rc);
8801 for (i = 0; i < 24; i++) {
8802 rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0);
8804 pr_err("error %d\n", rc);
8807 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0);
8809 pr_err("error %d\n", rc);
8815 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0);
8817 pr_err("error %d\n", rc);
8820 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0);
8822 pr_err("error %d\n", rc);
8826 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0);
8828 pr_err("error %d\n", rc);
8833 while ((fsm_state != 4) && (i++ < 100)) {
8834 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0);
8836 pr_err("error %d\n", rc);
8840 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0);
8842 pr_err("error %d\n", rc);
8853 #define DEMOD_LOCKED 0x1
8854 #define SYNC_FLIPPED 0x2
8855 #define SPEC_MIRRORED 0x4
8857 * \fn int qam64auto ()
8858 * \brief auto do sync pattern switching and mirroring.
8859 * \param demod: instance of demod.
8860 * \param channel: pointer to channel data.
8861 * \param tuner_freq_offset: tuner frequency offset.
8862 * \param lock_status: pointer to lock status.
8866 qam64auto(struct drx_demod_instance *demod,
8867 struct drx_channel *channel,
8868 s32 tuner_freq_offset, enum drx_lock_status *lock_status)
8870 struct drxj_data *ext_attr = demod->my_ext_attr;
8871 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
8872 struct drx39xxj_state *state = dev_addr->user_data;
8873 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
8875 u32 lck_state = NO_LOCK;
8877 u32 d_locked_time = 0;
8878 u32 timeout_ofs = 0;
8881 /* external attributes for storing acquired channel constellation */
8882 *lock_status = DRX_NOT_LOCKED;
8883 start_time = jiffies_to_msecs(jiffies);
8884 lck_state = NO_LOCK;
8886 rc = ctrl_lock_status(demod, lock_status);
8888 pr_err("error %d\n", rc);
8892 switch (lck_state) {
8894 if (*lock_status == DRXJ_DEMOD_LOCK) {
8895 rc = ctrl_get_qam_sig_quality(demod);
8897 pr_err("error %d\n", rc);
8900 if (p->cnr.stat[0].svalue > 20800) {
8901 lck_state = DEMOD_LOCKED;
8902 /* some delay to see if fec_lock possible TODO find the right value */
8903 timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, waiting longer */
8904 d_locked_time = jiffies_to_msecs(jiffies);
8909 if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */
8910 ((jiffies_to_msecs(jiffies) - d_locked_time) >
8911 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
8912 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8914 pr_err("error %d\n", rc);
8917 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8919 pr_err("error %d\n", rc);
8922 lck_state = SYNC_FLIPPED;
8927 if (*lock_status == DRXJ_DEMOD_LOCK) {
8928 if (channel->mirror == DRX_MIRROR_AUTO) {
8929 /* flip sync pattern back */
8930 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8932 pr_err("error %d\n", rc);
8935 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0);
8937 pr_err("error %d\n", rc);
8941 ext_attr->mirror = DRX_MIRROR_YES;
8942 rc = qam_flip_spec(demod, channel);
8944 pr_err("error %d\n", rc);
8947 lck_state = SPEC_MIRRORED;
8948 /* reset timer TODO: still need 500ms? */
8949 start_time = d_locked_time =
8950 jiffies_to_msecs(jiffies);
8952 } else { /* no need to wait lock */
8955 jiffies_to_msecs(jiffies) -
8956 DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8961 if ((*lock_status == DRXJ_DEMOD_LOCK) && /* still demod_lock in 150ms */
8962 ((jiffies_to_msecs(jiffies) - d_locked_time) >
8963 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
8964 rc = ctrl_get_qam_sig_quality(demod);
8966 pr_err("error %d\n", rc);
8969 if (p->cnr.stat[0].svalue > 20800) {
8970 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0);
8972 pr_err("error %d\n", rc);
8975 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0);
8977 pr_err("error %d\n", rc);
8980 /* no need to wait lock */
8982 jiffies_to_msecs(jiffies) -
8983 DRXJ_QAM_MAX_WAITTIME - timeout_ofs;
8992 ((*lock_status != DRX_LOCKED) &&
8993 (*lock_status != DRX_NEVER_LOCK) &&
8994 ((jiffies_to_msecs(jiffies) - start_time) <
8995 (DRXJ_QAM_MAX_WAITTIME + timeout_ofs))
8997 /* Returning control to application ... */
9005 * \fn int qam256auto ()
9006 * \brief auto do sync pattern switching and mirroring.
9007 * \param demod: instance of demod.
9008 * \param channel: pointer to channel data.
9009 * \param tuner_freq_offset: tuner frequency offset.
9010 * \param lock_status: pointer to lock status.
9014 qam256auto(struct drx_demod_instance *demod,
9015 struct drx_channel *channel,
9016 s32 tuner_freq_offset, enum drx_lock_status *lock_status)
9018 struct drxj_data *ext_attr = demod->my_ext_attr;
9019 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9020 struct drx39xxj_state *state = dev_addr->user_data;
9021 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9023 u32 lck_state = NO_LOCK;
9025 u32 d_locked_time = 0;
9026 u32 timeout_ofs = DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME;
9028 /* external attributes for storing acquired channel constellation */
9029 *lock_status = DRX_NOT_LOCKED;
9030 start_time = jiffies_to_msecs(jiffies);
9031 lck_state = NO_LOCK;
9033 rc = ctrl_lock_status(demod, lock_status);
9035 pr_err("error %d\n", rc);
9038 switch (lck_state) {
9040 if (*lock_status == DRXJ_DEMOD_LOCK) {
9041 rc = ctrl_get_qam_sig_quality(demod);
9043 pr_err("error %d\n", rc);
9046 if (p->cnr.stat[0].svalue > 26800) {
9047 lck_state = DEMOD_LOCKED;
9048 timeout_ofs += DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME; /* see something, wait longer */
9049 d_locked_time = jiffies_to_msecs(jiffies);
9054 if (*lock_status == DRXJ_DEMOD_LOCK) {
9055 if ((channel->mirror == DRX_MIRROR_AUTO) &&
9056 ((jiffies_to_msecs(jiffies) - d_locked_time) >
9057 DRXJ_QAM_FEC_LOCK_WAITTIME)) {
9058 ext_attr->mirror = DRX_MIRROR_YES;
9059 rc = qam_flip_spec(demod, channel);
9061 pr_err("error %d\n", rc);
9064 lck_state = SPEC_MIRRORED;
9065 /* reset timer TODO: still need 300ms? */
9066 start_time = jiffies_to_msecs(jiffies);
9067 timeout_ofs = -DRXJ_QAM_MAX_WAITTIME / 2;
9078 ((*lock_status < DRX_LOCKED) &&
9079 (*lock_status != DRX_NEVER_LOCK) &&
9080 ((jiffies_to_msecs(jiffies) - start_time) <
9081 (DRXJ_QAM_MAX_WAITTIME + timeout_ofs)));
9089 * \fn int set_qam_channel ()
9090 * \brief Set QAM channel according to the requested constellation.
9091 * \param demod: instance of demod.
9092 * \param channel: pointer to channel data.
9096 set_qam_channel(struct drx_demod_instance *demod,
9097 struct drx_channel *channel, s32 tuner_freq_offset)
9099 struct drxj_data *ext_attr = NULL;
9101 enum drx_lock_status lock_status = DRX_NOT_LOCKED;
9102 bool auto_flag = false;
9104 /* external attributes for storing acquired channel constellation */
9105 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9107 /* set QAM channel constellation */
9108 switch (channel->constellation) {
9109 case DRX_CONSTELLATION_QAM16:
9110 case DRX_CONSTELLATION_QAM32:
9111 case DRX_CONSTELLATION_QAM128:
9113 case DRX_CONSTELLATION_QAM64:
9114 case DRX_CONSTELLATION_QAM256:
9115 if (ext_attr->standard != DRX_STANDARD_ITU_B)
9118 ext_attr->constellation = channel->constellation;
9119 if (channel->mirror == DRX_MIRROR_AUTO)
9120 ext_attr->mirror = DRX_MIRROR_NO;
9122 ext_attr->mirror = channel->mirror;
9124 rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL);
9126 pr_err("error %d\n", rc);
9130 if (channel->constellation == DRX_CONSTELLATION_QAM64)
9131 rc = qam64auto(demod, channel, tuner_freq_offset,
9134 rc = qam256auto(demod, channel, tuner_freq_offset,
9137 pr_err("error %d\n", rc);
9141 case DRX_CONSTELLATION_AUTO: /* for channel scan */
9142 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9143 u16 qam_ctl_ena = 0;
9147 /* try to lock default QAM constellation: QAM256 */
9148 channel->constellation = DRX_CONSTELLATION_QAM256;
9149 ext_attr->constellation = DRX_CONSTELLATION_QAM256;
9150 if (channel->mirror == DRX_MIRROR_AUTO)
9151 ext_attr->mirror = DRX_MIRROR_NO;
9153 ext_attr->mirror = channel->mirror;
9154 rc = set_qam(demod, channel, tuner_freq_offset,
9157 pr_err("error %d\n", rc);
9160 rc = qam256auto(demod, channel, tuner_freq_offset,
9163 pr_err("error %d\n", rc);
9167 if (lock_status >= DRX_LOCKED) {
9168 channel->constellation = DRX_CONSTELLATION_AUTO;
9172 /* QAM254 not locked. Try QAM64 constellation */
9173 channel->constellation = DRX_CONSTELLATION_QAM64;
9174 ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9175 if (channel->mirror == DRX_MIRROR_AUTO)
9176 ext_attr->mirror = DRX_MIRROR_NO;
9178 ext_attr->mirror = channel->mirror;
9180 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9181 SCU_RAM_QAM_CTL_ENA__A,
9184 pr_err("error %d\n", rc);
9187 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9188 SCU_RAM_QAM_CTL_ENA__A,
9189 qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
9191 pr_err("error %d\n", rc);
9194 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9195 SCU_RAM_QAM_FSM_STATE_TGT__A,
9198 pr_err("error %d\n", rc);
9200 } /* force to rate hunting */
9202 rc = set_qam(demod, channel, tuner_freq_offset,
9203 QAM_SET_OP_CONSTELLATION);
9205 pr_err("error %d\n", rc);
9208 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9209 SCU_RAM_QAM_CTL_ENA__A,
9212 pr_err("error %d\n", rc);
9216 rc = qam64auto(demod, channel, tuner_freq_offset,
9219 pr_err("error %d\n", rc);
9223 channel->constellation = DRX_CONSTELLATION_AUTO;
9224 } else if (ext_attr->standard == DRX_STANDARD_ITU_C) {
9225 u16 qam_ctl_ena = 0;
9227 channel->constellation = DRX_CONSTELLATION_QAM64;
9228 ext_attr->constellation = DRX_CONSTELLATION_QAM64;
9231 if (channel->mirror == DRX_MIRROR_AUTO)
9232 ext_attr->mirror = DRX_MIRROR_NO;
9234 ext_attr->mirror = channel->mirror;
9235 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr,
9236 SCU_RAM_QAM_CTL_ENA__A,
9239 pr_err("error %d\n", rc);
9242 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9243 SCU_RAM_QAM_CTL_ENA__A,
9244 qam_ctl_ena & ~SCU_RAM_QAM_CTL_ENA_ACQ__M, 0);
9246 pr_err("error %d\n", rc);
9249 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9250 SCU_RAM_QAM_FSM_STATE_TGT__A,
9253 pr_err("error %d\n", rc);
9255 } /* force to rate hunting */
9257 rc = set_qam(demod, channel, tuner_freq_offset,
9258 QAM_SET_OP_CONSTELLATION);
9260 pr_err("error %d\n", rc);
9263 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr,
9264 SCU_RAM_QAM_CTL_ENA__A,
9267 pr_err("error %d\n", rc);
9270 rc = qam64auto(demod, channel, tuner_freq_offset,
9273 pr_err("error %d\n", rc);
9276 channel->constellation = DRX_CONSTELLATION_AUTO;
9287 /* restore starting value */
9289 channel->constellation = DRX_CONSTELLATION_AUTO;
9293 /*============================================================================*/
9296 * \fn static short get_qamrs_err_count(struct i2c_device_addr *dev_addr)
9297 * \brief Get RS error count in QAM mode (used for post RS BER calculation)
9298 * \return Error code
9300 * precondition: measurement period & measurement prescale must be set
9304 get_qamrs_err_count(struct i2c_device_addr *dev_addr,
9305 struct drxjrs_errors *rs_errors)
9308 u16 nr_bit_errors = 0,
9309 nr_symbol_errors = 0,
9310 nr_packet_errors = 0, nr_failures = 0, nr_snc_par_fail_count = 0;
9312 /* check arguments */
9313 if (dev_addr == NULL)
9316 /* all reported errors are received in the */
9317 /* most recently finished measurement period */
9318 /* no of pre RS bit errors */
9319 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0);
9321 pr_err("error %d\n", rc);
9324 /* no of symbol errors */
9325 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0);
9327 pr_err("error %d\n", rc);
9330 /* no of packet errors */
9331 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0);
9333 pr_err("error %d\n", rc);
9336 /* no of failures to decode */
9337 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0);
9339 pr_err("error %d\n", rc);
9342 /* no of post RS bit erros */
9343 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0);
9345 pr_err("error %d\n", rc);
9349 /* These register values are fetched in non-atomic fashion */
9350 /* It is possible that the read values contain unrelated information */
9352 rs_errors->nr_bit_errors = nr_bit_errors & FEC_RS_NR_BIT_ERRORS__M;
9353 rs_errors->nr_symbol_errors = nr_symbol_errors & FEC_RS_NR_SYMBOL_ERRORS__M;
9354 rs_errors->nr_packet_errors = nr_packet_errors & FEC_RS_NR_PACKET_ERRORS__M;
9355 rs_errors->nr_failures = nr_failures & FEC_RS_NR_FAILURES__M;
9356 rs_errors->nr_snc_par_fail_count =
9357 nr_snc_par_fail_count & FEC_OC_SNC_FAIL_COUNT__M;
9364 /*============================================================================*/
9367 * \fn int get_sig_strength()
9368 * \brief Retrieve signal strength for VSB and QAM.
9369 * \param demod Pointer to demod instance
9370 * \param u16-t Pointer to signal strength data; range 0, .. , 100.
9372 * \retval 0 sig_strength contains valid data.
9373 * \retval -EINVAL sig_strength is NULL.
9374 * \retval -EIO Erroneous data, sig_strength contains invalid data.
9376 #define DRXJ_AGC_TOP 0x2800
9377 #define DRXJ_AGC_SNS 0x1600
9378 #define DRXJ_RFAGC_MAX 0x3fff
9379 #define DRXJ_RFAGC_MIN 0x800
9381 static int get_sig_strength(struct drx_demod_instance *demod, u16 *sig_strength)
9383 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9392 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0);
9394 pr_err("error %d\n", rc);
9397 if_gain &= IQM_AF_AGC_IF__M;
9398 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0);
9400 pr_err("error %d\n", rc);
9403 rf_gain &= IQM_AF_AGC_RF__M;
9405 if_agc_sns = DRXJ_AGC_SNS;
9406 if_agc_top = DRXJ_AGC_TOP;
9407 rf_agc_max = DRXJ_RFAGC_MAX;
9408 rf_agc_min = DRXJ_RFAGC_MIN;
9410 if (if_gain > if_agc_top) {
9411 if (rf_gain > rf_agc_max)
9412 *sig_strength = 100;
9413 else if (rf_gain > rf_agc_min) {
9414 if (rf_agc_max == rf_agc_min) {
9415 pr_err("error: rf_agc_max == rf_agc_min\n");
9419 75 + 25 * (rf_gain - rf_agc_min) / (rf_agc_max -
9423 } else if (if_gain > if_agc_sns) {
9424 if (if_agc_top == if_agc_sns) {
9425 pr_err("error: if_agc_top == if_agc_sns\n");
9429 20 + 55 * (if_gain - if_agc_sns) / (if_agc_top - if_agc_sns);
9432 pr_err("error: if_agc_sns is zero!\n");
9435 *sig_strength = (20 * if_gain / if_agc_sns);
9438 if (*sig_strength <= 7)
9447 * \fn int ctrl_get_qam_sig_quality()
9448 * \brief Retrieve QAM signal quality from device.
9449 * \param devmod Pointer to demodulator instance.
9450 * \param sig_quality Pointer to signal quality data.
9452 * \retval 0 sig_quality contains valid data.
9453 * \retval -EINVAL sig_quality is NULL.
9454 * \retval -EIO Erroneous data, sig_quality contains invalid data.
9456 * Pre-condition: Device must be started and in lock.
9459 ctrl_get_qam_sig_quality(struct drx_demod_instance *demod)
9461 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9462 struct drxj_data *ext_attr = demod->my_ext_attr;
9463 struct drx39xxj_state *state = dev_addr->user_data;
9464 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
9465 struct drxjrs_errors measuredrs_errors = { 0, 0, 0, 0, 0 };
9466 enum drx_modulation constellation = ext_attr->constellation;
9469 u32 pre_bit_err_rs = 0; /* pre RedSolomon Bit Error Rate */
9470 u32 post_bit_err_rs = 0; /* post RedSolomon Bit Error Rate */
9471 u32 pkt_errs = 0; /* no of packet errors in RS */
9472 u16 qam_sl_err_power = 0; /* accumulated error between raw and sliced symbols */
9473 u16 qsym_err_vd = 0; /* quadrature symbol errors in QAM_VD */
9474 u16 fec_oc_period = 0; /* SNC sync failure measurement period */
9475 u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */
9476 u16 fec_rs_period = 0; /* Value for corresponding I2C register */
9477 /* calculation constants */
9478 u32 rs_bit_cnt = 0; /* RedSolomon Bit Count */
9479 u32 qam_sl_sig_power = 0; /* used for MER, depends of QAM constellation */
9480 /* intermediate results */
9481 u32 e = 0; /* exponent value used for QAM BER/SER */
9482 u32 m = 0; /* mantisa value used for QAM BER/SER */
9483 u32 ber_cnt = 0; /* BER count */
9484 /* signal quality info */
9485 u32 qam_sl_mer = 0; /* QAM MER */
9486 u32 qam_pre_rs_ber = 0; /* Pre RedSolomon BER */
9487 u32 qam_post_rs_ber = 0; /* Post RedSolomon BER */
9488 u32 qam_vd_ser = 0; /* ViterbiDecoder SER */
9489 u16 qam_vd_prescale = 0; /* Viterbi Measurement Prescale */
9490 u16 qam_vd_period = 0; /* Viterbi Measurement period */
9491 u32 vd_bit_cnt = 0; /* ViterbiDecoder Bit Count */
9493 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9495 /* read the physical registers */
9496 /* Get the RS error data */
9497 rc = get_qamrs_err_count(dev_addr, &measuredrs_errors);
9499 pr_err("error %d\n", rc);
9502 /* get the register value needed for MER */
9503 rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0);
9505 pr_err("error %d\n", rc);
9508 /* get the register value needed for post RS BER */
9509 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0);
9511 pr_err("error %d\n", rc);
9515 /* get constants needed for signal quality calculation */
9516 fec_rs_period = ext_attr->fec_rs_period;
9517 fec_rs_prescale = ext_attr->fec_rs_prescale;
9518 rs_bit_cnt = fec_rs_period * fec_rs_prescale * ext_attr->fec_rs_plen;
9519 qam_vd_period = ext_attr->qam_vd_period;
9520 qam_vd_prescale = ext_attr->qam_vd_prescale;
9521 vd_bit_cnt = qam_vd_period * qam_vd_prescale * ext_attr->fec_vd_plen;
9523 /* DRXJ_QAM_SL_SIG_POWER_QAMxxx * 4 */
9524 switch (constellation) {
9525 case DRX_CONSTELLATION_QAM16:
9526 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM16 << 2;
9528 case DRX_CONSTELLATION_QAM32:
9529 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM32 << 2;
9531 case DRX_CONSTELLATION_QAM64:
9532 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM64 << 2;
9534 case DRX_CONSTELLATION_QAM128:
9535 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM128 << 2;
9537 case DRX_CONSTELLATION_QAM256:
9538 qam_sl_sig_power = DRXJ_QAM_SL_SIG_POWER_QAM256 << 2;
9544 /* ------------------------------ */
9545 /* MER Calculation */
9546 /* ------------------------------ */
9547 /* MER is good if it is above 27.5 for QAM256 or 21.5 for QAM64 */
9549 /* 10.0*log10(qam_sl_sig_power * 4.0 / qam_sl_err_power); */
9550 if (qam_sl_err_power == 0)
9553 qam_sl_mer = log1_times100(qam_sl_sig_power) - log1_times100((u32)qam_sl_err_power);
9555 /* ----------------------------------------- */
9556 /* Pre Viterbi Symbol Error Rate Calculation */
9557 /* ----------------------------------------- */
9558 /* pre viterbi SER is good if it is below 0.025 */
9560 /* get the register value */
9561 /* no of quadrature symbol errors */
9562 rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0);
9564 pr_err("error %d\n", rc);
9567 /* Extract the Exponent and the Mantisa */
9568 /* of number of quadrature symbol errors */
9569 e = (qsym_err_vd & QAM_VD_NR_QSYM_ERRORS_EXP__M) >>
9570 QAM_VD_NR_QSYM_ERRORS_EXP__B;
9571 m = (qsym_err_vd & QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M) >>
9572 QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B;
9574 if ((m << e) >> 3 > 549752)
9575 qam_vd_ser = 500000 * vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
9577 qam_vd_ser = m << ((e > 2) ? (e - 3) : e);
9579 /* --------------------------------------- */
9580 /* pre and post RedSolomon BER Calculation */
9581 /* --------------------------------------- */
9582 /* pre RS BER is good if it is below 3.5e-4 */
9584 /* get the register values */
9585 pre_bit_err_rs = (u32) measuredrs_errors.nr_bit_errors;
9586 pkt_errs = post_bit_err_rs = (u32) measuredrs_errors.nr_snc_par_fail_count;
9588 /* Extract the Exponent and the Mantisa of the */
9589 /* pre Reed-Solomon bit error count */
9590 e = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_EXP__M) >>
9591 FEC_RS_NR_BIT_ERRORS_EXP__B;
9592 m = (pre_bit_err_rs & FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M) >>
9593 FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B;
9597 /*qam_pre_rs_ber = frac_times1e6( ber_cnt, rs_bit_cnt ); */
9598 if (m > (rs_bit_cnt >> (e + 1)) || (rs_bit_cnt >> e) == 0)
9599 qam_pre_rs_ber = 500000 * rs_bit_cnt >> e;
9601 qam_pre_rs_ber = ber_cnt;
9603 /* post RS BER = 1000000* (11.17 * FEC_OC_SNC_FAIL_COUNT__A) / */
9604 /* (1504.0 * FEC_OC_SNC_FAIL_PERIOD__A) */
9606 => c = (1000000*100*11.17)/1504 =
9607 post RS BER = (( c* FEC_OC_SNC_FAIL_COUNT__A) /
9608 (100 * FEC_OC_SNC_FAIL_PERIOD__A)
9609 *100 and /100 is for more precision.
9610 => (20 bits * 12 bits) /(16 bits * 7 bits) => safe in 32 bits computation
9612 Precision errors still possible.
9614 if (!fec_oc_period) {
9615 qam_post_rs_ber = 0xFFFFFFFF;
9617 e = post_bit_err_rs * 742686;
9618 m = fec_oc_period * 100;
9619 qam_post_rs_ber = e / m;
9622 /* fill signal quality data structure */
9623 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9624 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
9625 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9626 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
9627 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
9628 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
9630 p->cnr.stat[0].svalue = ((u16) qam_sl_mer) * 100;
9631 if (ext_attr->standard == DRX_STANDARD_ITU_B) {
9632 p->pre_bit_error.stat[0].uvalue += qam_vd_ser;
9633 p->pre_bit_count.stat[0].uvalue += vd_bit_cnt * ((e > 2) ? 1 : 8) / 8;
9635 p->pre_bit_error.stat[0].uvalue += qam_pre_rs_ber;
9636 p->pre_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9639 p->post_bit_error.stat[0].uvalue += qam_post_rs_ber;
9640 p->post_bit_count.stat[0].uvalue += rs_bit_cnt >> e;
9642 p->block_error.stat[0].uvalue += pkt_errs;
9644 #ifdef DRXJ_SIGNAL_ACCUM_ERR
9645 rc = get_acc_pkt_err(demod, &sig_quality->packet_error);
9647 pr_err("error %d\n", rc);
9654 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9655 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9656 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9657 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9658 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9659 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
9664 #endif /* #ifndef DRXJ_VSB_ONLY */
9666 /*============================================================================*/
9667 /*== END QAM DATAPATH FUNCTIONS ==*/
9668 /*============================================================================*/
9670 /*============================================================================*/
9671 /*============================================================================*/
9672 /*== ATV DATAPATH FUNCTIONS ==*/
9673 /*============================================================================*/
9674 /*============================================================================*/
9677 Implementation notes.
9681 Four AGCs are used for NTSC:
9682 (1) RF (used to attenuate the input signal in case of to much power)
9683 (2) IF (used to attenuate the input signal in case of to much power)
9684 (3) Video AGC (used to amplify the output signal in case input to low)
9685 (4) SIF AGC (used to amplify the output signal in case input to low)
9687 Video AGC is coupled to RF and IF. SIF AGC is not coupled. It is assumed
9688 that the coupling between Video AGC and the RF and IF AGCs also works in
9689 favor of the SIF AGC.
9691 Three AGCs are used for FM:
9692 (1) RF (used to attenuate the input signal in case of to much power)
9693 (2) IF (used to attenuate the input signal in case of to much power)
9694 (3) SIF AGC (used to amplify the output signal in case input to low)
9696 The SIF AGC is now coupled to the RF/IF AGCs.
9697 The SIF AGC is needed for both SIF output and the internal SIF signal to
9700 RF and IF AGCs DACs are part of AFE, Video and SIF AGC DACs are part of
9701 the ATV block. The AGC control algorithms are all implemented in
9706 (Shadow settings will not be used for now, they will be implemented
9707 later on because of the schedule)
9709 Several HW/SCU "settings" can be used for ATV. The standard selection
9710 will reset most of these settings. To avoid that the end user application
9711 has to perform these settings each time the ATV or FM standards is
9712 selected the driver will shadow these settings. This enables the end user
9713 to perform the settings only once after a drx_open(). The driver must
9714 write the shadow settings to HW/SCU in case:
9715 ( setstandard FM/ATV) ||
9716 ( settings have changed && FM/ATV standard is active)
9717 The shadow settings will be stored in the device specific data container.
9718 A set of flags will be defined to flag changes in shadow settings.
9719 A routine will be implemented to write all changed shadow settings to
9722 The "settings" will consist of: AGC settings, filter settings etc.
9724 Disadvantage of use of shadow settings:
9725 Direct changes in HW/SCU registers will not be reflected in the
9726 shadow settings and these changes will be overwritten during a next
9727 update. This can happen during evaluation. This will not be a problem
9728 for normal customer usage.
9730 /* -------------------------------------------------------------------------- */
9733 * \fn int power_down_atv ()
9734 * \brief Power down ATV.
9735 * \param demod instance of demodulator
9736 * \param standard either NTSC or FM (sub strandard for ATV )
9739 * Stops and thus resets ATV and IQM block
9740 * SIF and CVBS ADC are powered down
9741 * Calls audio power down
9744 power_down_atv(struct drx_demod_instance *demod, enum drx_standard standard, bool primary)
9746 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9747 struct drxjscu_cmd cmd_scu = { /* command */ 0,
9748 /* parameter_len */ 0,
9750 /* *parameter */ NULL,
9758 /* Stop ATV SCU (will reset ATV and IQM hardware */
9759 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_ATV |
9760 SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9761 cmd_scu.parameter_len = 0;
9762 cmd_scu.result_len = 1;
9763 cmd_scu.parameter = NULL;
9764 cmd_scu.result = &cmd_result;
9765 rc = scu_command(dev_addr, &cmd_scu);
9767 pr_err("error %d\n", rc);
9770 /* Disable ATV outputs (ATV reset enables CVBS, undo this) */
9771 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0);
9773 pr_err("error %d\n", rc);
9777 rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0);
9779 pr_err("error %d\n", rc);
9783 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0);
9785 pr_err("error %d\n", rc);
9788 rc = set_iqm_af(demod, false);
9790 pr_err("error %d\n", rc);
9794 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0);
9796 pr_err("error %d\n", rc);
9799 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0);
9801 pr_err("error %d\n", rc);
9804 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0);
9806 pr_err("error %d\n", rc);
9809 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0);
9811 pr_err("error %d\n", rc);
9814 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0);
9816 pr_err("error %d\n", rc);
9820 rc = power_down_aud(demod);
9822 pr_err("error %d\n", rc);
9831 /*============================================================================*/
9834 * \brief Power up AUD.
9835 * \param demod instance of demodulator
9839 static int power_down_aud(struct drx_demod_instance *demod)
9841 struct i2c_device_addr *dev_addr = NULL;
9842 struct drxj_data *ext_attr = NULL;
9845 dev_addr = (struct i2c_device_addr *)demod->my_i2c_dev_addr;
9846 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9848 rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0);
9850 pr_err("error %d\n", rc);
9854 ext_attr->aud_data.audio_is_active = false;
9862 * \fn int set_orx_nsu_aox()
9863 * \brief Configure OrxNsuAox for OOB
9864 * \param demod instance of demodulator.
9868 static int set_orx_nsu_aox(struct drx_demod_instance *demod, bool active)
9870 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
9874 /* Configure NSU_AOX */
9875 rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0);
9877 pr_err("error %d\n", rc);
9881 data &= ((~ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON) & (~ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON));
9883 data |= (ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON | ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON);
9884 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0);
9886 pr_err("error %d\n", rc);
9896 * \fn int ctrl_set_oob()
9897 * \brief Set OOB channel to be used.
9898 * \param demod instance of demodulator
9899 * \param oob_param OOB parameters for channel setting.
9900 * \frequency should be in KHz
9903 * Accepts only. Returns error otherwise.
9904 * Demapper value is written after scu_command START
9905 * because START command causes COMM_EXEC transition
9906 * from 0 to 1 which causes all registers to be
9907 * overwritten with initial value
9911 /* Nyquist filter impulse response */
9912 #define IMPULSE_COSINE_ALPHA_0_3 {-3, -4, -1, 6, 10, 7, -5, -20, -25, -10, 29, 79, 123, 140} /*sqrt raised-cosine filter with alpha=0.3 */
9913 #define IMPULSE_COSINE_ALPHA_0_5 { 2, 0, -2, -2, 2, 5, 2, -10, -20, -14, 20, 74, 125, 145} /*sqrt raised-cosine filter with alpha=0.5 */
9914 #define IMPULSE_COSINE_ALPHA_RO_0_5 { 0, 0, 1, 2, 3, 0, -7, -15, -16, 0, 34, 77, 114, 128} /*full raised-cosine filter with alpha=0.5 (receiver only) */
9916 /* Coefficients for the nyquist filter (total: 27 taps) */
9917 #define NYQFILTERLEN 27
9919 static int ctrl_set_oob(struct drx_demod_instance *demod, struct drxoob *oob_param)
9922 s32 freq = 0; /* KHz */
9923 struct i2c_device_addr *dev_addr = NULL;
9924 struct drxj_data *ext_attr = NULL;
9926 bool mirror_freq_spect_oob = false;
9927 u16 trk_filter_value = 0;
9928 struct drxjscu_cmd scu_cmd;
9929 u16 set_param_parameters[3];
9930 u16 cmd_result[2] = { 0, 0 };
9931 s16 nyquist_coeffs[4][(NYQFILTERLEN + 1) / 2] = {
9932 IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 0 */
9933 IMPULSE_COSINE_ALPHA_0_3, /* Target Mode 1 */
9934 IMPULSE_COSINE_ALPHA_0_5, /* Target Mode 2 */
9935 IMPULSE_COSINE_ALPHA_RO_0_5 /* Target Mode 3 */
9937 u8 mode_val[4] = { 2, 2, 0, 1 };
9938 u8 pfi_coeffs[4][6] = {
9939 {DRXJ_16TO8(-92), DRXJ_16TO8(-108), DRXJ_16TO8(100)}, /* TARGET_MODE = 0: PFI_A = -23/32; PFI_B = -54/32; PFI_C = 25/32; fg = 0.5 MHz (Att=26dB) */
9940 {DRXJ_16TO8(-64), DRXJ_16TO8(-80), DRXJ_16TO8(80)}, /* TARGET_MODE = 1: PFI_A = -16/32; PFI_B = -40/32; PFI_C = 20/32; fg = 1.0 MHz (Att=28dB) */
9941 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)}, /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
9942 {DRXJ_16TO8(-80), DRXJ_16TO8(-98), DRXJ_16TO8(92)} /* TARGET_MODE = 2, 3: PFI_A = -20/32; PFI_B = -49/32; PFI_C = 23/32; fg = 0.8 MHz (Att=25dB) */
9946 dev_addr = demod->my_i2c_dev_addr;
9947 ext_attr = (struct drxj_data *) demod->my_ext_attr;
9948 mirror_freq_spect_oob = ext_attr->mirror_freq_spect_oob;
9950 /* Check parameters */
9951 if (oob_param == NULL) {
9952 /* power off oob module */
9953 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
9954 | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
9955 scu_cmd.parameter_len = 0;
9956 scu_cmd.result_len = 1;
9957 scu_cmd.result = cmd_result;
9958 rc = scu_command(dev_addr, &scu_cmd);
9960 pr_err("error %d\n", rc);
9963 rc = set_orx_nsu_aox(demod, false);
9965 pr_err("error %d\n", rc);
9968 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
9970 pr_err("error %d\n", rc);
9974 ext_attr->oob_power_on = false;
9978 freq = oob_param->frequency;
9979 if ((freq < 70000) || (freq > 130000))
9981 freq = (freq - 50000) / 50;
9986 u16 *trk_filtercfg = ext_attr->oob_trk_filter_cfg;
9988 index = (u16) ((freq - 400) / 200);
9989 remainder = (u16) ((freq - 400) % 200);
9991 trk_filtercfg[index] - (trk_filtercfg[index] -
9992 trk_filtercfg[index +
9993 1]) / 10 * remainder /
10000 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0);
10002 pr_err("error %d\n", rc);
10005 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10006 | SCU_RAM_COMMAND_CMD_DEMOD_STOP;
10007 scu_cmd.parameter_len = 0;
10008 scu_cmd.result_len = 1;
10009 scu_cmd.result = cmd_result;
10010 rc = scu_command(dev_addr, &scu_cmd);
10012 pr_err("error %d\n", rc);
10018 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10019 | SCU_RAM_COMMAND_CMD_DEMOD_RESET;
10020 scu_cmd.parameter_len = 0;
10021 scu_cmd.result_len = 1;
10022 scu_cmd.result = cmd_result;
10023 rc = scu_command(dev_addr, &scu_cmd);
10025 pr_err("error %d\n", rc);
10031 /* set frequency, spectrum inversion and data rate */
10032 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10033 | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV;
10034 scu_cmd.parameter_len = 3;
10035 /* 1-data rate;2-frequency */
10036 switch (oob_param->standard) {
10037 case DRX_OOB_MODE_A:
10039 /* signal is transmitted inverted */
10040 ((oob_param->spectrum_inverted == true) &&
10041 /* and tuner is not mirroring the signal */
10042 (!mirror_freq_spect_oob)) |
10044 /* signal is transmitted noninverted */
10045 ((oob_param->spectrum_inverted == false) &&
10046 /* and tuner is mirroring the signal */
10047 (mirror_freq_spect_oob))
10049 set_param_parameters[0] =
10050 SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC;
10052 set_param_parameters[0] =
10053 SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC;
10055 case DRX_OOB_MODE_B_GRADE_A:
10057 /* signal is transmitted inverted */
10058 ((oob_param->spectrum_inverted == true) &&
10059 /* and tuner is not mirroring the signal */
10060 (!mirror_freq_spect_oob)) |
10062 /* signal is transmitted noninverted */
10063 ((oob_param->spectrum_inverted == false) &&
10064 /* and tuner is mirroring the signal */
10065 (mirror_freq_spect_oob))
10067 set_param_parameters[0] =
10068 SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC;
10070 set_param_parameters[0] =
10071 SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC;
10073 case DRX_OOB_MODE_B_GRADE_B:
10076 /* signal is transmitted inverted */
10077 ((oob_param->spectrum_inverted == true) &&
10078 /* and tuner is not mirroring the signal */
10079 (!mirror_freq_spect_oob)) |
10081 /* signal is transmitted noninverted */
10082 ((oob_param->spectrum_inverted == false) &&
10083 /* and tuner is mirroring the signal */
10084 (mirror_freq_spect_oob))
10086 set_param_parameters[0] =
10087 SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC;
10089 set_param_parameters[0] =
10090 SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC;
10093 set_param_parameters[1] = (u16) (freq & 0xFFFF);
10094 set_param_parameters[2] = trk_filter_value;
10095 scu_cmd.parameter = set_param_parameters;
10096 scu_cmd.result_len = 1;
10097 scu_cmd.result = cmd_result;
10098 mode_index = mode_val[(set_param_parameters[0] & 0xC0) >> 6];
10099 rc = scu_command(dev_addr, &scu_cmd);
10101 pr_err("error %d\n", rc);
10105 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
10107 pr_err("error %d\n", rc);
10109 } /* Write magic word to enable pdr reg write */
10110 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_CRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_CRX_CFG_MODE__B, 0);
10112 pr_err("error %d\n", rc);
10115 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_DRX_CFG_DRIVE__B | 0x03 << SIO_PDR_OOB_DRX_CFG_MODE__B, 0);
10117 pr_err("error %d\n", rc);
10120 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
10122 pr_err("error %d\n", rc);
10124 } /* Write magic word to disable pdr reg write */
10126 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0);
10128 pr_err("error %d\n", rc);
10131 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0);
10133 pr_err("error %d\n", rc);
10136 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0);
10138 pr_err("error %d\n", rc);
10143 rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0);
10145 pr_err("error %d\n", rc);
10150 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0);
10152 pr_err("error %d\n", rc);
10156 /* initialization for target mode */
10157 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT, 0);
10159 pr_err("error %d\n", rc);
10162 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS, 0);
10164 pr_err("error %d\n", rc);
10168 /* Reset bits for timing and freq. recovery */
10169 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0);
10171 pr_err("error %d\n", rc);
10174 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0);
10176 pr_err("error %d\n", rc);
10179 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0);
10181 pr_err("error %d\n", rc);
10184 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0);
10186 pr_err("error %d\n", rc);
10190 /* AGN_LOCK = {2048>>3, -2048, 8, -8, 0, 1}; */
10191 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0);
10193 pr_err("error %d\n", rc);
10196 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0);
10198 pr_err("error %d\n", rc);
10201 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0);
10203 pr_err("error %d\n", rc);
10206 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0);
10208 pr_err("error %d\n", rc);
10211 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0);
10213 pr_err("error %d\n", rc);
10217 /* DGN_LOCK = {10, -2048, 8, -8, 0, 1<<1}; */
10218 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0);
10220 pr_err("error %d\n", rc);
10223 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0);
10225 pr_err("error %d\n", rc);
10228 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0);
10230 pr_err("error %d\n", rc);
10233 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0);
10235 pr_err("error %d\n", rc);
10238 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0);
10240 pr_err("error %d\n", rc);
10244 /* FRQ_LOCK = {15,-2048, 8, -8, 0, 1<<2}; */
10245 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0);
10247 pr_err("error %d\n", rc);
10250 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0);
10252 pr_err("error %d\n", rc);
10255 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0);
10257 pr_err("error %d\n", rc);
10260 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0);
10262 pr_err("error %d\n", rc);
10265 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0);
10267 pr_err("error %d\n", rc);
10271 /* PHA_LOCK = {5000, -2048, 8, -8, 0, 1<<3}; */
10272 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0);
10274 pr_err("error %d\n", rc);
10277 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0);
10279 pr_err("error %d\n", rc);
10282 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0);
10284 pr_err("error %d\n", rc);
10287 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0);
10289 pr_err("error %d\n", rc);
10292 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0);
10294 pr_err("error %d\n", rc);
10298 /* TIM_LOCK = {300, -2048, 8, -8, 0, 1<<4}; */
10299 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0);
10301 pr_err("error %d\n", rc);
10304 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0);
10306 pr_err("error %d\n", rc);
10309 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0);
10311 pr_err("error %d\n", rc);
10314 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0);
10316 pr_err("error %d\n", rc);
10319 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0);
10321 pr_err("error %d\n", rc);
10325 /* EQU_LOCK = {20, -2048, 8, -8, 0, 1<<5}; */
10326 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0);
10328 pr_err("error %d\n", rc);
10331 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0);
10333 pr_err("error %d\n", rc);
10336 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0);
10338 pr_err("error %d\n", rc);
10341 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0);
10343 pr_err("error %d\n", rc);
10346 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0);
10348 pr_err("error %d\n", rc);
10352 /* PRE-Filter coefficients (PFI) */
10353 rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)pfi_coeffs[mode_index]), 0);
10355 pr_err("error %d\n", rc);
10358 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0);
10360 pr_err("error %d\n", rc);
10364 /* NYQUIST-Filter coefficients (NYQ) */
10365 for (i = 0; i < (NYQFILTERLEN + 1) / 2; i++) {
10366 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0);
10368 pr_err("error %d\n", rc);
10371 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0);
10373 pr_err("error %d\n", rc);
10377 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0);
10379 pr_err("error %d\n", rc);
10382 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0);
10384 pr_err("error %d\n", rc);
10390 scu_cmd.command = SCU_RAM_COMMAND_STANDARD_OOB
10391 | SCU_RAM_COMMAND_CMD_DEMOD_START;
10392 scu_cmd.parameter_len = 0;
10393 scu_cmd.result_len = 1;
10394 scu_cmd.result = cmd_result;
10395 rc = scu_command(dev_addr, &scu_cmd);
10397 pr_err("error %d\n", rc);
10401 rc = set_orx_nsu_aox(demod, true);
10403 pr_err("error %d\n", rc);
10406 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0);
10408 pr_err("error %d\n", rc);
10412 ext_attr->oob_power_on = true;
10419 /*============================================================================*/
10420 /*== END OOB DATAPATH FUNCTIONS ==*/
10421 /*============================================================================*/
10423 /*=============================================================================
10424 ===== MC command related functions ==========================================
10425 ===========================================================================*/
10427 /*=============================================================================
10428 ===== ctrl_set_channel() ==========================================================
10429 ===========================================================================*/
10431 * \fn int ctrl_set_channel()
10432 * \brief Select a new transmission channel.
10433 * \param demod instance of demod.
10434 * \param channel Pointer to channel data.
10437 * In case the tuner module is not used and in case of NTSC/FM the pogrammer
10438 * must tune the tuner to the centre frequency of the NTSC/FM channel.
10442 ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel)
10445 s32 tuner_freq_offset = 0;
10446 struct drxj_data *ext_attr = NULL;
10447 struct i2c_device_addr *dev_addr = NULL;
10448 enum drx_standard standard = DRX_STANDARD_UNKNOWN;
10449 #ifndef DRXJ_VSB_ONLY
10450 u32 min_symbol_rate = 0;
10451 u32 max_symbol_rate = 0;
10452 int bandwidth_temp = 0;
10455 /*== check arguments ======================================================*/
10456 if ((demod == NULL) || (channel == NULL))
10459 dev_addr = demod->my_i2c_dev_addr;
10460 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10461 standard = ext_attr->standard;
10463 /* check valid standards */
10464 switch (standard) {
10465 case DRX_STANDARD_8VSB:
10466 #ifndef DRXJ_VSB_ONLY
10467 case DRX_STANDARD_ITU_A:
10468 case DRX_STANDARD_ITU_B:
10469 case DRX_STANDARD_ITU_C:
10470 #endif /* DRXJ_VSB_ONLY */
10472 case DRX_STANDARD_UNKNOWN:
10477 /* check bandwidth QAM annex B, NTSC and 8VSB */
10478 if ((standard == DRX_STANDARD_ITU_B) ||
10479 (standard == DRX_STANDARD_8VSB) ||
10480 (standard == DRX_STANDARD_NTSC)) {
10481 switch (channel->bandwidth) {
10482 case DRX_BANDWIDTH_6MHZ:
10483 case DRX_BANDWIDTH_UNKNOWN:
10484 channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10486 case DRX_BANDWIDTH_8MHZ:
10487 case DRX_BANDWIDTH_7MHZ:
10493 /* For QAM annex A and annex C:
10494 -check symbolrate and constellation
10495 -derive bandwidth from symbolrate (input bandwidth is ignored)
10497 #ifndef DRXJ_VSB_ONLY
10498 if ((standard == DRX_STANDARD_ITU_A) ||
10499 (standard == DRX_STANDARD_ITU_C)) {
10500 struct drxuio_cfg uio_cfg = { DRX_UIO1, DRX_UIO_MODE_FIRMWARE_SAW };
10501 int bw_rolloff_factor = 0;
10503 bw_rolloff_factor = (standard == DRX_STANDARD_ITU_A) ? 115 : 113;
10504 min_symbol_rate = DRXJ_QAM_SYMBOLRATE_MIN;
10505 max_symbol_rate = DRXJ_QAM_SYMBOLRATE_MAX;
10506 /* config SMA_TX pin to SAW switch mode */
10507 rc = ctrl_set_uio_cfg(demod, &uio_cfg);
10509 pr_err("error %d\n", rc);
10513 if (channel->symbolrate < min_symbol_rate ||
10514 channel->symbolrate > max_symbol_rate) {
10518 switch (channel->constellation) {
10519 case DRX_CONSTELLATION_QAM16:
10520 case DRX_CONSTELLATION_QAM32:
10521 case DRX_CONSTELLATION_QAM64:
10522 case DRX_CONSTELLATION_QAM128:
10523 case DRX_CONSTELLATION_QAM256:
10524 bandwidth_temp = channel->symbolrate * bw_rolloff_factor;
10525 bandwidth = bandwidth_temp / 100;
10527 if ((bandwidth_temp % 100) >= 50)
10530 if (bandwidth <= 6100000) {
10531 channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10532 } else if ((bandwidth > 6100000)
10533 && (bandwidth <= 7100000)) {
10534 channel->bandwidth = DRX_BANDWIDTH_7MHZ;
10535 } else if (bandwidth > 7100000) {
10536 channel->bandwidth = DRX_BANDWIDTH_8MHZ;
10544 /* For QAM annex B:
10545 -check constellation
10547 if (standard == DRX_STANDARD_ITU_B) {
10548 switch (channel->constellation) {
10549 case DRX_CONSTELLATION_AUTO:
10550 case DRX_CONSTELLATION_QAM256:
10551 case DRX_CONSTELLATION_QAM64:
10557 switch (channel->interleavemode) {
10558 case DRX_INTERLEAVEMODE_I128_J1:
10559 case DRX_INTERLEAVEMODE_I128_J1_V2:
10560 case DRX_INTERLEAVEMODE_I128_J2:
10561 case DRX_INTERLEAVEMODE_I64_J2:
10562 case DRX_INTERLEAVEMODE_I128_J3:
10563 case DRX_INTERLEAVEMODE_I32_J4:
10564 case DRX_INTERLEAVEMODE_I128_J4:
10565 case DRX_INTERLEAVEMODE_I16_J8:
10566 case DRX_INTERLEAVEMODE_I128_J5:
10567 case DRX_INTERLEAVEMODE_I8_J16:
10568 case DRX_INTERLEAVEMODE_I128_J6:
10569 case DRX_INTERLEAVEMODE_I128_J7:
10570 case DRX_INTERLEAVEMODE_I128_J8:
10571 case DRX_INTERLEAVEMODE_I12_J17:
10572 case DRX_INTERLEAVEMODE_I5_J4:
10573 case DRX_INTERLEAVEMODE_B52_M240:
10574 case DRX_INTERLEAVEMODE_B52_M720:
10575 case DRX_INTERLEAVEMODE_UNKNOWN:
10576 case DRX_INTERLEAVEMODE_AUTO:
10583 if ((ext_attr->uio_sma_tx_mode) == DRX_UIO_MODE_FIRMWARE_SAW) {
10584 /* SAW SW, user UIO is used for switchable SAW */
10585 struct drxuio_data uio1 = { DRX_UIO1, false };
10587 switch (channel->bandwidth) {
10588 case DRX_BANDWIDTH_8MHZ:
10591 case DRX_BANDWIDTH_7MHZ:
10592 uio1.value = false;
10594 case DRX_BANDWIDTH_6MHZ:
10595 uio1.value = false;
10597 case DRX_BANDWIDTH_UNKNOWN:
10602 rc = ctrl_uio_write(demod, &uio1);
10604 pr_err("error %d\n", rc);
10608 #endif /* DRXJ_VSB_ONLY */
10609 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
10611 pr_err("error %d\n", rc);
10615 tuner_freq_offset = 0;
10617 /*== Setup demod for specific standard ====================================*/
10618 switch (standard) {
10619 case DRX_STANDARD_8VSB:
10620 if (channel->mirror == DRX_MIRROR_AUTO)
10621 ext_attr->mirror = DRX_MIRROR_NO;
10623 ext_attr->mirror = channel->mirror;
10624 rc = set_vsb(demod);
10626 pr_err("error %d\n", rc);
10629 rc = set_frequency(demod, channel, tuner_freq_offset);
10631 pr_err("error %d\n", rc);
10635 #ifndef DRXJ_VSB_ONLY
10636 case DRX_STANDARD_ITU_A:
10637 case DRX_STANDARD_ITU_B:
10638 case DRX_STANDARD_ITU_C:
10639 rc = set_qam_channel(demod, channel, tuner_freq_offset);
10641 pr_err("error %d\n", rc);
10646 case DRX_STANDARD_UNKNOWN:
10651 /* flag the packet error counter reset */
10652 ext_attr->reset_pkt_err_acc = true;
10659 /*=============================================================================
10660 ===== SigQuality() ==========================================================
10661 ===========================================================================*/
10664 * \fn int ctrl_sig_quality()
10665 * \brief Retrieve signal quality form device.
10666 * \param devmod Pointer to demodulator instance.
10667 * \param sig_quality Pointer to signal quality data.
10669 * \retval 0 sig_quality contains valid data.
10670 * \retval -EINVAL sig_quality is NULL.
10671 * \retval -EIO Erroneous data, sig_quality contains invalid data.
10675 ctrl_sig_quality(struct drx_demod_instance *demod,
10676 enum drx_lock_status lock_status)
10678 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
10679 struct drxj_data *ext_attr = demod->my_ext_attr;
10680 struct drx39xxj_state *state = dev_addr->user_data;
10681 struct dtv_frontend_properties *p = &state->frontend.dtv_property_cache;
10682 enum drx_standard standard = ext_attr->standard;
10684 u32 ber, cnt, err, pkt;
10685 u16 mer, strength = 0;
10687 rc = get_sig_strength(demod, &strength);
10689 pr_err("error getting signal strength %d\n", rc);
10690 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10692 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
10693 p->strength.stat[0].uvalue = 65535UL * strength/ 100;
10696 switch (standard) {
10697 case DRX_STANDARD_8VSB:
10698 #ifdef DRXJ_SIGNAL_ACCUM_ERR
10699 rc = get_acc_pkt_err(demod, &pkt);
10701 pr_err("error %d\n", rc);
10705 if (lock_status != DRXJ_DEMOD_LOCK && lock_status != DRX_LOCKED) {
10706 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10707 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10708 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10709 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10710 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10711 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10712 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10714 rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt);
10716 pr_err("error %d getting UCB\n", rc);
10717 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10719 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
10720 p->block_error.stat[0].uvalue += err;
10721 p->block_count.stat[0].scale = FE_SCALE_COUNTER;
10722 p->block_count.stat[0].uvalue += pkt;
10725 /* PostViterbi is compute in steps of 10^(-6) */
10726 rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt);
10728 pr_err("error %d getting pre-ber\n", rc);
10729 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10731 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10732 p->pre_bit_error.stat[0].uvalue += ber;
10733 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10734 p->pre_bit_count.stat[0].uvalue += cnt;
10737 rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt);
10739 pr_err("error %d getting post-ber\n", rc);
10740 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10742 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
10743 p->post_bit_error.stat[0].uvalue += ber;
10744 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
10745 p->post_bit_count.stat[0].uvalue += cnt;
10747 rc = get_vsbmer(dev_addr, &mer);
10749 pr_err("error %d getting MER\n", rc);
10750 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
10752 p->cnr.stat[0].svalue = mer * 100;
10753 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
10757 #ifndef DRXJ_VSB_ONLY
10758 case DRX_STANDARD_ITU_A:
10759 case DRX_STANDARD_ITU_B:
10760 case DRX_STANDARD_ITU_C:
10761 rc = ctrl_get_qam_sig_quality(demod);
10763 pr_err("error %d\n", rc);
10777 /*============================================================================*/
10780 * \fn int ctrl_lock_status()
10781 * \brief Retrieve lock status .
10782 * \param dev_addr Pointer to demodulator device address.
10783 * \param lock_stat Pointer to lock status structure.
10788 ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_stat)
10790 enum drx_standard standard = DRX_STANDARD_UNKNOWN;
10791 struct drxj_data *ext_attr = NULL;
10792 struct i2c_device_addr *dev_addr = NULL;
10793 struct drxjscu_cmd cmd_scu = { /* command */ 0,
10794 /* parameter_len */ 0,
10795 /* result_len */ 0,
10796 /* *parameter */ NULL,
10800 u16 cmd_result[2] = { 0, 0 };
10801 u16 demod_lock = SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED;
10803 /* check arguments */
10804 if ((demod == NULL) || (lock_stat == NULL))
10807 dev_addr = demod->my_i2c_dev_addr;
10808 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10809 standard = ext_attr->standard;
10811 *lock_stat = DRX_NOT_LOCKED;
10813 /* define the SCU command code */
10814 switch (standard) {
10815 case DRX_STANDARD_8VSB:
10816 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_VSB |
10817 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
10820 #ifndef DRXJ_VSB_ONLY
10821 case DRX_STANDARD_ITU_A:
10822 case DRX_STANDARD_ITU_B:
10823 case DRX_STANDARD_ITU_C:
10824 cmd_scu.command = SCU_RAM_COMMAND_STANDARD_QAM |
10825 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
10828 case DRX_STANDARD_UNKNOWN:
10833 /* define the SCU command parameters and execute the command */
10834 cmd_scu.parameter_len = 0;
10835 cmd_scu.result_len = 2;
10836 cmd_scu.parameter = NULL;
10837 cmd_scu.result = cmd_result;
10838 rc = scu_command(dev_addr, &cmd_scu);
10840 pr_err("error %d\n", rc);
10844 /* set the lock status */
10845 if (cmd_scu.result[1] < demod_lock) {
10846 /* 0x0000 NOT LOCKED */
10847 *lock_stat = DRX_NOT_LOCKED;
10848 } else if (cmd_scu.result[1] < SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED) {
10849 *lock_stat = DRXJ_DEMOD_LOCK;
10850 } else if (cmd_scu.result[1] <
10851 SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK) {
10852 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
10853 *lock_stat = DRX_LOCKED;
10855 /* 0xC000 NEVER LOCKED */
10856 /* (system will never be able to lock to the signal) */
10857 *lock_stat = DRX_NEVER_LOCK;
10865 /*============================================================================*/
10868 * \fn int ctrl_set_standard()
10869 * \brief Set modulation standard to be used.
10870 * \param standard Modulation standard.
10873 * Setup stuff for the desired demodulation standard.
10874 * Disable and power down the previous selected demodulation standard
10878 ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard)
10880 struct drxj_data *ext_attr = NULL;
10882 enum drx_standard prev_standard;
10884 /* check arguments */
10885 if ((standard == NULL) || (demod == NULL))
10888 ext_attr = (struct drxj_data *) demod->my_ext_attr;
10889 prev_standard = ext_attr->standard;
10892 Stop and power down previous standard
10894 switch (prev_standard) {
10895 #ifndef DRXJ_VSB_ONLY
10896 case DRX_STANDARD_ITU_A:
10897 case DRX_STANDARD_ITU_B:
10898 case DRX_STANDARD_ITU_C:
10899 rc = power_down_qam(demod, false);
10901 pr_err("error %d\n", rc);
10906 case DRX_STANDARD_8VSB:
10907 rc = power_down_vsb(demod, false);
10909 pr_err("error %d\n", rc);
10913 case DRX_STANDARD_UNKNOWN:
10916 case DRX_STANDARD_AUTO:
10922 Initialize channel independent registers
10923 Power up new standard
10925 ext_attr->standard = *standard;
10927 switch (*standard) {
10928 #ifndef DRXJ_VSB_ONLY
10929 case DRX_STANDARD_ITU_A:
10930 case DRX_STANDARD_ITU_B:
10931 case DRX_STANDARD_ITU_C:
10934 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0);
10936 pr_err("error %d\n", rc);
10942 case DRX_STANDARD_8VSB:
10943 rc = set_vsb_leak_n_gain(demod);
10945 pr_err("error %d\n", rc);
10950 ext_attr->standard = DRX_STANDARD_UNKNOWN;
10956 /* Don't know what the standard is now ... try again */
10957 ext_attr->standard = DRX_STANDARD_UNKNOWN;
10961 /*============================================================================*/
10963 static void drxj_reset_mode(struct drxj_data *ext_attr)
10965 /* Initialize default AFE configuration for QAM */
10966 if (ext_attr->has_lna) {
10967 /* IF AGC off, PGA active */
10968 #ifndef DRXJ_VSB_ONLY
10969 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10970 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10971 ext_attr->qam_pga_cfg = 140 + (11 * 13);
10973 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10974 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_OFF;
10975 ext_attr->vsb_pga_cfg = 140 + (11 * 13);
10977 /* IF AGC on, PGA not active */
10978 #ifndef DRXJ_VSB_ONLY
10979 ext_attr->qam_if_agc_cfg.standard = DRX_STANDARD_ITU_B;
10980 ext_attr->qam_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10981 ext_attr->qam_if_agc_cfg.min_output_level = 0;
10982 ext_attr->qam_if_agc_cfg.max_output_level = 0x7FFF;
10983 ext_attr->qam_if_agc_cfg.speed = 3;
10984 ext_attr->qam_if_agc_cfg.top = 1297;
10985 ext_attr->qam_pga_cfg = 140;
10987 ext_attr->vsb_if_agc_cfg.standard = DRX_STANDARD_8VSB;
10988 ext_attr->vsb_if_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
10989 ext_attr->vsb_if_agc_cfg.min_output_level = 0;
10990 ext_attr->vsb_if_agc_cfg.max_output_level = 0x7FFF;
10991 ext_attr->vsb_if_agc_cfg.speed = 3;
10992 ext_attr->vsb_if_agc_cfg.top = 1024;
10993 ext_attr->vsb_pga_cfg = 140;
10995 /* TODO: remove min_output_level and max_output_level for both QAM and VSB after */
10996 /* mc has not used them */
10997 #ifndef DRXJ_VSB_ONLY
10998 ext_attr->qam_rf_agc_cfg.standard = DRX_STANDARD_ITU_B;
10999 ext_attr->qam_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
11000 ext_attr->qam_rf_agc_cfg.min_output_level = 0;
11001 ext_attr->qam_rf_agc_cfg.max_output_level = 0x7FFF;
11002 ext_attr->qam_rf_agc_cfg.speed = 3;
11003 ext_attr->qam_rf_agc_cfg.top = 9500;
11004 ext_attr->qam_rf_agc_cfg.cut_off_current = 4000;
11005 ext_attr->qam_pre_saw_cfg.standard = DRX_STANDARD_ITU_B;
11006 ext_attr->qam_pre_saw_cfg.reference = 0x07;
11007 ext_attr->qam_pre_saw_cfg.use_pre_saw = true;
11009 /* Initialize default AFE configuration for VSB */
11010 ext_attr->vsb_rf_agc_cfg.standard = DRX_STANDARD_8VSB;
11011 ext_attr->vsb_rf_agc_cfg.ctrl_mode = DRX_AGC_CTRL_AUTO;
11012 ext_attr->vsb_rf_agc_cfg.min_output_level = 0;
11013 ext_attr->vsb_rf_agc_cfg.max_output_level = 0x7FFF;
11014 ext_attr->vsb_rf_agc_cfg.speed = 3;
11015 ext_attr->vsb_rf_agc_cfg.top = 9500;
11016 ext_attr->vsb_rf_agc_cfg.cut_off_current = 4000;
11017 ext_attr->vsb_pre_saw_cfg.standard = DRX_STANDARD_8VSB;
11018 ext_attr->vsb_pre_saw_cfg.reference = 0x07;
11019 ext_attr->vsb_pre_saw_cfg.use_pre_saw = true;
11023 * \fn int ctrl_power_mode()
11024 * \brief Set the power mode of the device to the specified power mode
11025 * \param demod Pointer to demodulator instance.
11026 * \param mode Pointer to new power mode.
11028 * \retval 0 Success
11029 * \retval -EIO I2C error or other failure
11030 * \retval -EINVAL Invalid mode argument.
11035 ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode)
11037 struct drx_common_attr *common_attr = (struct drx_common_attr *) NULL;
11038 struct drxj_data *ext_attr = (struct drxj_data *) NULL;
11039 struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)NULL;
11041 u16 sio_cc_pwd_mode = 0;
11043 common_attr = (struct drx_common_attr *) demod->my_common_attr;
11044 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11045 dev_addr = demod->my_i2c_dev_addr;
11047 /* Check arguments */
11051 /* If already in requested power mode, do nothing */
11052 if (common_attr->current_power_mode == *mode)
11057 case DRXJ_POWER_DOWN_MAIN_PATH:
11058 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
11060 case DRXJ_POWER_DOWN_CORE:
11061 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
11063 case DRXJ_POWER_DOWN_PLL:
11064 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
11066 case DRX_POWER_DOWN:
11067 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
11070 /* Unknow sleep mode */
11074 /* Check if device needs to be powered up */
11075 if ((common_attr->current_power_mode != DRX_POWER_UP)) {
11076 rc = power_up_device(demod);
11078 pr_err("error %d\n", rc);
11083 if (*mode == DRX_POWER_UP) {
11084 /* Restore analog & pin configuration */
11086 /* Initialize default AFE configuration for VSB */
11087 drxj_reset_mode(ext_attr);
11089 /* Power down to requested mode */
11090 /* Backup some register settings */
11091 /* Set pins with possible pull-ups connected to them in input mode */
11092 /* Analog power down */
11093 /* ADC power down */
11094 /* Power down device */
11095 /* stop all comm_exec */
11097 Stop and power down previous standard
11100 switch (ext_attr->standard) {
11101 case DRX_STANDARD_ITU_A:
11102 case DRX_STANDARD_ITU_B:
11103 case DRX_STANDARD_ITU_C:
11104 rc = power_down_qam(demod, true);
11106 pr_err("error %d\n", rc);
11110 case DRX_STANDARD_8VSB:
11111 rc = power_down_vsb(demod, true);
11113 pr_err("error %d\n", rc);
11117 case DRX_STANDARD_PAL_SECAM_BG:
11118 case DRX_STANDARD_PAL_SECAM_DK:
11119 case DRX_STANDARD_PAL_SECAM_I:
11120 case DRX_STANDARD_PAL_SECAM_L:
11121 case DRX_STANDARD_PAL_SECAM_LP:
11122 case DRX_STANDARD_NTSC:
11123 case DRX_STANDARD_FM:
11124 rc = power_down_atv(demod, ext_attr->standard, true);
11126 pr_err("error %d\n", rc);
11130 case DRX_STANDARD_UNKNOWN:
11133 case DRX_STANDARD_AUTO:
11137 ext_attr->standard = DRX_STANDARD_UNKNOWN;
11140 if (*mode != DRXJ_POWER_DOWN_MAIN_PATH) {
11141 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0);
11143 pr_err("error %d\n", rc);
11146 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11148 pr_err("error %d\n", rc);
11152 if ((*mode != DRX_POWER_UP)) {
11153 /* Initialize HI, wakeup key especially before put IC to sleep */
11154 rc = init_hi(demod);
11156 pr_err("error %d\n", rc);
11160 ext_attr->hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
11161 rc = hi_cfg_command(demod);
11163 pr_err("error %d\n", rc);
11169 common_attr->current_power_mode = *mode;
11176 /*============================================================================*/
11177 /*== CTRL Set/Get Config related functions ===================================*/
11178 /*============================================================================*/
11181 * \fn int ctrl_set_cfg_pre_saw()
11182 * \brief Set Pre-saw reference.
11183 * \param demod demod instance
11188 * Dispatch handling to standard specific function.
11192 ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw)
11194 struct i2c_device_addr *dev_addr = NULL;
11195 struct drxj_data *ext_attr = NULL;
11198 dev_addr = demod->my_i2c_dev_addr;
11199 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11201 /* check arguments */
11202 if ((pre_saw == NULL) || (pre_saw->reference > IQM_AF_PDREF__M)
11207 /* Only if standard is currently active */
11208 if ((ext_attr->standard == pre_saw->standard) ||
11209 (DRXJ_ISQAMSTD(ext_attr->standard) &&
11210 DRXJ_ISQAMSTD(pre_saw->standard)) ||
11211 (DRXJ_ISATVSTD(ext_attr->standard) &&
11212 DRXJ_ISATVSTD(pre_saw->standard))) {
11213 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0);
11215 pr_err("error %d\n", rc);
11220 /* Store pre-saw settings */
11221 switch (pre_saw->standard) {
11222 case DRX_STANDARD_8VSB:
11223 ext_attr->vsb_pre_saw_cfg = *pre_saw;
11225 #ifndef DRXJ_VSB_ONLY
11226 case DRX_STANDARD_ITU_A:
11227 case DRX_STANDARD_ITU_B:
11228 case DRX_STANDARD_ITU_C:
11229 ext_attr->qam_pre_saw_cfg = *pre_saw;
11241 /*============================================================================*/
11244 * \fn int ctrl_set_cfg_afe_gain()
11245 * \brief Set AFE Gain.
11246 * \param demod demod instance
11251 * Dispatch handling to standard specific function.
11255 ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain *afe_gain)
11257 struct i2c_device_addr *dev_addr = NULL;
11258 struct drxj_data *ext_attr = NULL;
11262 /* check arguments */
11263 if (afe_gain == NULL)
11266 dev_addr = demod->my_i2c_dev_addr;
11267 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11269 switch (afe_gain->standard) {
11270 case DRX_STANDARD_8VSB: fallthrough;
11271 #ifndef DRXJ_VSB_ONLY
11272 case DRX_STANDARD_ITU_A:
11273 case DRX_STANDARD_ITU_B:
11274 case DRX_STANDARD_ITU_C:
11282 /* TODO PGA gain is also written by microcode (at least by QAM and VSB)
11283 So I (PJ) think interface requires choice between auto, user mode */
11285 if (afe_gain->gain >= 329)
11287 else if (afe_gain->gain <= 147)
11290 gain = (afe_gain->gain - 140 + 6) / 13;
11292 /* Only if standard is currently active */
11293 if (ext_attr->standard == afe_gain->standard) {
11294 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0);
11296 pr_err("error %d\n", rc);
11301 /* Store AFE Gain settings */
11302 switch (afe_gain->standard) {
11303 case DRX_STANDARD_8VSB:
11304 ext_attr->vsb_pga_cfg = gain * 13 + 140;
11306 #ifndef DRXJ_VSB_ONLY
11307 case DRX_STANDARD_ITU_A:
11308 case DRX_STANDARD_ITU_B:
11309 case DRX_STANDARD_ITU_C:
11310 ext_attr->qam_pga_cfg = gain * 13 + 140;
11322 /*============================================================================*/
11325 /*=============================================================================
11326 ===== EXPORTED FUNCTIONS ====================================================*/
11328 static int drx_ctrl_u_code(struct drx_demod_instance *demod,
11329 struct drxu_code_info *mc_info,
11330 enum drxu_code_action action);
11331 static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state);
11335 * \brief Open the demod instance, configure device, configure drxdriver
11336 * \return Status_t Return status.
11338 * drxj_open() can be called with a NULL ucode image => no ucode upload.
11339 * This means that drxj_open() must NOT contain SCU commands or, in general,
11340 * rely on SCU or AUD ucode to be present.
11344 static int drxj_open(struct drx_demod_instance *demod)
11346 struct i2c_device_addr *dev_addr = NULL;
11347 struct drxj_data *ext_attr = NULL;
11348 struct drx_common_attr *common_attr = NULL;
11349 u32 driver_version = 0;
11350 struct drxu_code_info ucode_info;
11351 struct drx_cfg_mpeg_output cfg_mpeg_output;
11353 enum drx_power_mode power_mode = DRX_POWER_UP;
11355 if ((demod == NULL) ||
11356 (demod->my_common_attr == NULL) ||
11357 (demod->my_ext_attr == NULL) ||
11358 (demod->my_i2c_dev_addr == NULL) ||
11359 (demod->my_common_attr->is_opened)) {
11363 /* Check arguments */
11364 if (demod->my_ext_attr == NULL)
11367 dev_addr = demod->my_i2c_dev_addr;
11368 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11369 common_attr = (struct drx_common_attr *) demod->my_common_attr;
11371 rc = ctrl_power_mode(demod, &power_mode);
11373 pr_err("error %d\n", rc);
11376 if (power_mode != DRX_POWER_UP) {
11378 pr_err("failed to powerup device\n");
11382 /* has to be in front of setIqmAf and setOrxNsuAox */
11383 rc = get_device_capabilities(demod);
11385 pr_err("error %d\n", rc);
11390 * Soft reset of sys- and osc-clockdomain
11392 * HACK: On windows, it writes a 0x07 here, instead of just 0x03.
11393 * As we didn't load the firmware here yet, we should do the same.
11394 * Btw, this is coherent with DRX-K, where we send reset codes
11395 * for modulation (OFTM, in DRX-k), SYS and OSC clock domains.
11397 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M), 0);
11399 pr_err("error %d\n", rc);
11402 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0);
11404 pr_err("error %d\n", rc);
11409 /* TODO first make sure that everything keeps working before enabling this */
11410 /* PowerDownAnalogBlocks() */
11411 rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_TOP_STDBY_SIF_STDBY_STANDBY, 0);
11413 pr_err("error %d\n", rc);
11417 rc = set_iqm_af(demod, false);
11419 pr_err("error %d\n", rc);
11422 rc = set_orx_nsu_aox(demod, false);
11424 pr_err("error %d\n", rc);
11428 rc = init_hi(demod);
11430 pr_err("error %d\n", rc);
11434 /* disable mpegoutput pins */
11435 memcpy(&cfg_mpeg_output, &common_attr->mpeg_cfg, sizeof(cfg_mpeg_output));
11436 cfg_mpeg_output.enable_mpeg_output = false;
11438 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output);
11440 pr_err("error %d\n", rc);
11443 /* Stop AUD Inform SetAudio it will need to do all setting */
11444 rc = power_down_aud(demod);
11446 pr_err("error %d\n", rc);
11450 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0);
11452 pr_err("error %d\n", rc);
11456 /* Upload microcode */
11457 if (common_attr->microcode_file != NULL) {
11458 /* Dirty trick to use common ucode upload & verify,
11459 pretend device is already open */
11460 common_attr->is_opened = true;
11461 ucode_info.mc_file = common_attr->microcode_file;
11463 if (DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode)) {
11464 pr_err("Should powerup before loading the firmware.");
11468 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD);
11470 pr_err("error %d while uploading the firmware\n", rc);
11473 if (common_attr->verify_microcode == true) {
11474 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY);
11476 pr_err("error %d while verifying the firmware\n",
11481 common_attr->is_opened = false;
11484 /* Run SCU for a little while to initialize microcode version numbers */
11485 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11487 pr_err("error %d\n", rc);
11491 /* Initialize scan timeout */
11492 common_attr->scan_demod_lock_timeout = DRXJ_SCAN_TIMEOUT;
11493 common_attr->scan_desired_lock = DRX_LOCKED;
11495 drxj_reset_mode(ext_attr);
11496 ext_attr->standard = DRX_STANDARD_UNKNOWN;
11498 rc = smart_ant_init(demod);
11500 pr_err("error %d\n", rc);
11504 /* Stamp driver version number in SCU data RAM in BCD code
11505 Done to enable field application engineers to retrieve drxdriver version
11506 via I2C from SCU RAM
11508 driver_version = (VERSION_MAJOR / 100) % 10;
11509 driver_version <<= 4;
11510 driver_version += (VERSION_MAJOR / 10) % 10;
11511 driver_version <<= 4;
11512 driver_version += (VERSION_MAJOR % 10);
11513 driver_version <<= 4;
11514 driver_version += (VERSION_MINOR % 10);
11515 driver_version <<= 4;
11516 driver_version += (VERSION_PATCH / 1000) % 10;
11517 driver_version <<= 4;
11518 driver_version += (VERSION_PATCH / 100) % 10;
11519 driver_version <<= 4;
11520 driver_version += (VERSION_PATCH / 10) % 10;
11521 driver_version <<= 4;
11522 driver_version += (VERSION_PATCH % 10);
11523 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0);
11525 pr_err("error %d\n", rc);
11528 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0);
11530 pr_err("error %d\n", rc);
11534 rc = ctrl_set_oob(demod, NULL);
11536 pr_err("error %d\n", rc);
11540 /* refresh the audio data structure with default */
11541 ext_attr->aud_data = drxj_default_aud_data_g;
11543 demod->my_common_attr->is_opened = true;
11544 drxj_set_lna_state(demod, false);
11547 common_attr->is_opened = false;
11551 /*============================================================================*/
11554 * \brief Close the demod instance, power down the device
11555 * \return Status_t Return status.
11558 static int drxj_close(struct drx_demod_instance *demod)
11560 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11562 enum drx_power_mode power_mode = DRX_POWER_UP;
11564 if ((demod->my_common_attr == NULL) ||
11565 (demod->my_ext_attr == NULL) ||
11566 (demod->my_i2c_dev_addr == NULL) ||
11567 (!demod->my_common_attr->is_opened)) {
11572 rc = ctrl_power_mode(demod, &power_mode);
11574 pr_err("error %d\n", rc);
11578 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0);
11580 pr_err("error %d\n", rc);
11583 power_mode = DRX_POWER_DOWN;
11584 rc = ctrl_power_mode(demod, &power_mode);
11586 pr_err("error %d\n", rc);
11590 DRX_ATTR_ISOPENED(demod) = false;
11594 DRX_ATTR_ISOPENED(demod) = false;
11600 * Microcode related functions
11604 * drx_u_code_compute_crc - Compute CRC of block of microcode data.
11605 * @block_data: Pointer to microcode data.
11606 * @nr_words: Size of microcode block (number of 16 bits words).
11608 * returns The computed CRC residue.
11610 static u16 drx_u_code_compute_crc(u8 *block_data, u16 nr_words)
11617 while (i < nr_words) {
11618 crc_word |= (u32)be16_to_cpu(*(__be16 *)(block_data));
11619 for (j = 0; j < 16; j++) {
11622 crc_word ^= 0x80050000UL;
11623 carry = crc_word & 0x80000000UL;
11626 block_data += (sizeof(u16));
11628 return (u16)(crc_word >> 16);
11632 * drx_check_firmware - checks if the loaded firmware is valid
11634 * @demod: demod structure
11635 * @mc_data: pointer to the start of the firmware
11636 * @size: firmware size
11638 static int drx_check_firmware(struct drx_demod_instance *demod, u8 *mc_data,
11641 struct drxu_code_block_hdr block_hdr;
11643 unsigned count = 2 * sizeof(u16);
11644 u32 mc_dev_type, mc_version, mc_base_version;
11645 u16 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data + sizeof(u16)));
11648 * Scan microcode blocks first for version info
11649 * and firmware check
11652 /* Clear version block */
11653 DRX_ATTR_MCRECORD(demod).aux_type = 0;
11654 DRX_ATTR_MCRECORD(demod).mc_dev_type = 0;
11655 DRX_ATTR_MCRECORD(demod).mc_version = 0;
11656 DRX_ATTR_MCRECORD(demod).mc_base_version = 0;
11658 for (i = 0; i < mc_nr_of_blks; i++) {
11659 if (count + 3 * sizeof(u16) + sizeof(u32) > size)
11662 /* Process block header */
11663 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data + count));
11664 count += sizeof(u32);
11665 block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data + count));
11666 count += sizeof(u16);
11667 block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data + count));
11668 count += sizeof(u16);
11669 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data + count));
11670 count += sizeof(u16);
11672 pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11673 count, block_hdr.addr, block_hdr.size, block_hdr.flags,
11676 if (block_hdr.flags & 0x8) {
11677 u8 *auxblk = ((void *)mc_data) + block_hdr.addr;
11680 if (block_hdr.addr + sizeof(u16) > size)
11683 auxtype = be16_to_cpu(*(__be16 *)(auxblk));
11685 /* Aux block. Check type */
11686 if (DRX_ISMCVERTYPE(auxtype)) {
11687 if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size)
11690 auxblk += sizeof(u16);
11691 mc_dev_type = be32_to_cpu(*(__be32 *)(auxblk));
11692 auxblk += sizeof(u32);
11693 mc_version = be32_to_cpu(*(__be32 *)(auxblk));
11694 auxblk += sizeof(u32);
11695 mc_base_version = be32_to_cpu(*(__be32 *)(auxblk));
11697 DRX_ATTR_MCRECORD(demod).aux_type = auxtype;
11698 DRX_ATTR_MCRECORD(demod).mc_dev_type = mc_dev_type;
11699 DRX_ATTR_MCRECORD(demod).mc_version = mc_version;
11700 DRX_ATTR_MCRECORD(demod).mc_base_version = mc_base_version;
11702 pr_info("Firmware dev %x, ver %x, base ver %x\n",
11703 mc_dev_type, mc_version, mc_base_version);
11706 } else if (count + block_hdr.size * sizeof(u16) > size)
11709 count += block_hdr.size * sizeof(u16);
11713 pr_err("Firmware is truncated at pos %u/%u\n", count, size);
11718 * drx_ctrl_u_code - Handle microcode upload or verify.
11719 * @dev_addr: Address of device.
11720 * @mc_info: Pointer to information about microcode data.
11721 * @action: Either UCODE_UPLOAD or UCODE_VERIFY
11723 * This function returns:
11725 * - In case of UCODE_UPLOAD: code is successfully uploaded.
11726 * - In case of UCODE_VERIFY: image on device is equal to
11727 * image provided to this control function.
11729 * - In case of UCODE_UPLOAD: I2C error.
11730 * - In case of UCODE_VERIFY: I2C error or image on device
11731 * is not equal to image provided to this control function.
11733 * - Invalid arguments.
11734 * - Provided image is corrupt
11736 static int drx_ctrl_u_code(struct drx_demod_instance *demod,
11737 struct drxu_code_info *mc_info,
11738 enum drxu_code_action action)
11740 struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
11743 u16 mc_nr_of_blks = 0;
11744 u16 mc_magic_word = 0;
11745 const u8 *mc_data_init = NULL;
11746 u8 *mc_data = NULL;
11750 /* Check arguments */
11751 if (!mc_info || !mc_info->mc_file)
11754 mc_file = mc_info->mc_file;
11756 if (!demod->firmware) {
11757 const struct firmware *fw = NULL;
11759 rc = reject_firmware(&fw, mc_file, demod->i2c->dev.parent);
11761 pr_err("Couldn't read firmware %s\n", mc_file);
11764 demod->firmware = fw;
11766 if (demod->firmware->size < 2 * sizeof(u16)) {
11768 pr_err("Firmware is too short!\n");
11772 pr_info("Firmware %s, size %zu\n",
11773 mc_file, demod->firmware->size);
11776 mc_data_init = demod->firmware->data;
11777 size = demod->firmware->size;
11779 mc_data = (void *)mc_data_init;
11781 mc_magic_word = be16_to_cpu(*(__be16 *)(mc_data));
11782 mc_data += sizeof(u16);
11783 mc_nr_of_blks = be16_to_cpu(*(__be16 *)(mc_data));
11784 mc_data += sizeof(u16);
11786 if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) {
11788 pr_err("Firmware magic word doesn't match\n");
11792 if (action == UCODE_UPLOAD) {
11793 rc = drx_check_firmware(demod, (u8 *)mc_data_init, size);
11796 pr_info("Uploading firmware %s\n", mc_file);
11798 pr_info("Verifying if firmware upload was ok.\n");
11801 /* Process microcode blocks */
11802 for (i = 0; i < mc_nr_of_blks; i++) {
11803 struct drxu_code_block_hdr block_hdr;
11804 u16 mc_block_nr_bytes = 0;
11806 /* Process block header */
11807 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data));
11808 mc_data += sizeof(u32);
11809 block_hdr.size = be16_to_cpu(*(__be16 *)(mc_data));
11810 mc_data += sizeof(u16);
11811 block_hdr.flags = be16_to_cpu(*(__be16 *)(mc_data));
11812 mc_data += sizeof(u16);
11813 block_hdr.CRC = be16_to_cpu(*(__be16 *)(mc_data));
11814 mc_data += sizeof(u16);
11816 pr_debug("%zd: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11817 (mc_data - mc_data_init), block_hdr.addr,
11818 block_hdr.size, block_hdr.flags, block_hdr.CRC);
11820 /* Check block header on:
11821 - data larger than 64Kb
11822 - if CRC enabled check CRC
11824 if ((block_hdr.size > 0x7FFF) ||
11825 (((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) &&
11826 (block_hdr.CRC != drx_u_code_compute_crc(mc_data, block_hdr.size)))
11830 pr_err("firmware CRC is wrong\n");
11834 if (!block_hdr.size)
11837 mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16));
11839 /* Perform the desired action */
11841 case UCODE_UPLOAD: /* Upload microcode */
11842 if (drxdap_fasi_write_block(dev_addr,
11845 mc_data, 0x0000)) {
11847 pr_err("error writing firmware at pos %zd\n",
11848 mc_data - mc_data_init);
11852 case UCODE_VERIFY: { /* Verify uploaded microcode */
11854 u8 mc_data_buffer[DRX_UCODE_MAX_BUF_SIZE];
11855 u32 bytes_to_comp = 0;
11856 u32 bytes_left = mc_block_nr_bytes;
11857 u32 curr_addr = block_hdr.addr;
11858 u8 *curr_ptr = mc_data;
11860 while (bytes_left != 0) {
11861 if (bytes_left > DRX_UCODE_MAX_BUF_SIZE)
11862 bytes_to_comp = DRX_UCODE_MAX_BUF_SIZE;
11864 bytes_to_comp = bytes_left;
11866 if (drxdap_fasi_read_block(dev_addr,
11868 (u16)bytes_to_comp,
11869 (u8 *)mc_data_buffer,
11871 pr_err("error reading firmware at pos %zd\n",
11872 mc_data - mc_data_init);
11876 result = memcmp(curr_ptr, mc_data_buffer,
11880 pr_err("error verifying firmware at pos %zd\n",
11881 mc_data - mc_data_init);
11885 curr_addr += ((dr_xaddr_t)(bytes_to_comp / 2));
11886 curr_ptr =&(curr_ptr[bytes_to_comp]);
11887 bytes_left -=((u32) bytes_to_comp);
11895 mc_data += mc_block_nr_bytes;
11901 release_firmware(demod->firmware);
11902 demod->firmware = NULL;
11907 /* caller is expected to check if lna is supported before enabling */
11908 static int drxj_set_lna_state(struct drx_demod_instance *demod, bool state)
11910 struct drxuio_cfg uio_cfg;
11911 struct drxuio_data uio_data;
11914 uio_cfg.uio = DRX_UIO1;
11915 uio_cfg.mode = DRX_UIO_MODE_READWRITE;
11916 /* Configure user-I/O #3: enable read/write */
11917 result = ctrl_set_uio_cfg(demod, &uio_cfg);
11919 pr_err("Failed to setup LNA GPIO!\n");
11923 uio_data.uio = DRX_UIO1;
11924 uio_data.value = state;
11925 result = ctrl_uio_write(demod, &uio_data);
11927 pr_err("Failed to %sable LNA!\n",
11928 state ? "en" : "dis");
11935 * The Linux DVB Driver for Micronas DRX39xx family (drx3933j)
11937 * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
11940 static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
11942 struct drx39xxj_state *state = fe->demodulator_priv;
11943 struct drx_demod_instance *demod = state->demod;
11945 enum drx_power_mode power_mode;
11948 power_mode = DRX_POWER_UP;
11950 power_mode = DRX_POWER_DOWN;
11952 result = ctrl_power_mode(demod, &power_mode);
11954 pr_err("Power state change failed\n");
11961 static int drx39xxj_read_status(struct dvb_frontend *fe, enum fe_status *status)
11963 struct drx39xxj_state *state = fe->demodulator_priv;
11964 struct drx_demod_instance *demod = state->demod;
11966 enum drx_lock_status lock_status;
11970 result = ctrl_lock_status(demod, &lock_status);
11972 pr_err("drx39xxj: could not get lock status!\n");
11976 switch (lock_status) {
11977 case DRX_NEVER_LOCK:
11979 pr_err("drx says NEVER_LOCK\n");
11981 case DRX_NOT_LOCKED:
11984 case DRX_LOCK_STATE_1:
11985 case DRX_LOCK_STATE_2:
11986 case DRX_LOCK_STATE_3:
11987 case DRX_LOCK_STATE_4:
11988 case DRX_LOCK_STATE_5:
11989 case DRX_LOCK_STATE_6:
11990 case DRX_LOCK_STATE_7:
11991 case DRX_LOCK_STATE_8:
11992 case DRX_LOCK_STATE_9:
11993 *status = FE_HAS_SIGNAL
11994 | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
11997 *status = FE_HAS_SIGNAL
11999 | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
12002 pr_err("Lock state unknown %d\n", lock_status);
12004 ctrl_sig_quality(demod, lock_status);
12009 static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber)
12011 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12013 if (p->pre_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12018 if (!p->pre_bit_count.stat[0].uvalue) {
12019 if (!p->pre_bit_error.stat[0].uvalue)
12024 *ber = frac_times1e6(p->pre_bit_error.stat[0].uvalue,
12025 p->pre_bit_count.stat[0].uvalue);
12030 static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
12033 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12035 if (p->strength.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12040 *strength = p->strength.stat[0].uvalue;
12044 static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr)
12046 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12049 if (p->cnr.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12054 tmp64 = p->cnr.stat[0].svalue;
12060 static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucb)
12062 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12064 if (p->block_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
12069 *ucb = p->block_error.stat[0].uvalue;
12073 static int drx39xxj_set_frontend(struct dvb_frontend *fe)
12078 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
12079 struct drx39xxj_state *state = fe->demodulator_priv;
12080 struct drx_demod_instance *demod = state->demod;
12081 enum drx_standard standard = DRX_STANDARD_8VSB;
12082 struct drx_channel channel;
12084 static const struct drx_channel def_channel = {
12086 /* bandwidth */ DRX_BANDWIDTH_6MHZ,
12087 /* mirror */ DRX_MIRROR_NO,
12088 /* constellation */ DRX_CONSTELLATION_AUTO,
12089 /* hierarchy */ DRX_HIERARCHY_UNKNOWN,
12090 /* priority */ DRX_PRIORITY_UNKNOWN,
12091 /* coderate */ DRX_CODERATE_UNKNOWN,
12092 /* guard */ DRX_GUARD_UNKNOWN,
12093 /* fftmode */ DRX_FFTMODE_UNKNOWN,
12094 /* classification */ DRX_CLASSIFICATION_AUTO,
12095 /* symbolrate */ 5057000,
12096 /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN,
12097 /* ldpc */ DRX_LDPC_UNKNOWN,
12098 /* carrier */ DRX_CARRIER_UNKNOWN,
12099 /* frame mode */ DRX_FRAMEMODE_UNKNOWN
12101 u32 constellation = DRX_CONSTELLATION_AUTO;
12103 /* Bring the demod out of sleep */
12104 drx39xxj_set_powerstate(fe, 1);
12106 if (fe->ops.tuner_ops.set_params) {
12109 if (fe->ops.i2c_gate_ctrl)
12110 fe->ops.i2c_gate_ctrl(fe, 1);
12112 /* Set tuner to desired frequency and standard */
12113 fe->ops.tuner_ops.set_params(fe);
12115 /* Use the tuner's IF */
12116 if (fe->ops.tuner_ops.get_if_frequency) {
12117 fe->ops.tuner_ops.get_if_frequency(fe, &int_freq);
12118 demod->my_common_attr->intermediate_freq = int_freq / 1000;
12121 if (fe->ops.i2c_gate_ctrl)
12122 fe->ops.i2c_gate_ctrl(fe, 0);
12125 switch (p->delivery_system) {
12127 standard = DRX_STANDARD_8VSB;
12129 case SYS_DVBC_ANNEX_B:
12130 standard = DRX_STANDARD_ITU_B;
12132 switch (p->modulation) {
12134 constellation = DRX_CONSTELLATION_QAM64;
12137 constellation = DRX_CONSTELLATION_QAM256;
12140 constellation = DRX_CONSTELLATION_AUTO;
12147 /* Set the standard (will be powered up if necessary */
12148 result = ctrl_set_standard(demod, &standard);
12150 pr_err("Failed to set standard! result=%02x\n",
12155 /* set channel parameters */
12156 channel = def_channel;
12157 channel.frequency = p->frequency / 1000;
12158 channel.bandwidth = DRX_BANDWIDTH_6MHZ;
12159 channel.constellation = constellation;
12161 /* program channel */
12162 result = ctrl_set_channel(demod, &channel);
12164 pr_err("Failed to set channel!\n");
12167 /* Just for giggles, let's shut off the LNA again.... */
12168 drxj_set_lna_state(demod, false);
12170 /* After set_frontend, except for strength, stats aren't available */
12171 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12176 static int drx39xxj_sleep(struct dvb_frontend *fe)
12178 /* power-down the demodulator */
12179 return drx39xxj_set_powerstate(fe, 0);
12182 static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
12184 struct drx39xxj_state *state = fe->demodulator_priv;
12185 struct drx_demod_instance *demod = state->demod;
12186 bool i2c_gate_state;
12190 pr_debug("i2c gate call: enable=%d state=%d\n", enable,
12191 state->i2c_gate_open);
12195 i2c_gate_state = true;
12197 i2c_gate_state = false;
12199 if (state->i2c_gate_open == enable) {
12200 /* We're already in the desired state */
12204 result = ctrl_i2c_bridge(demod, &i2c_gate_state);
12206 pr_err("drx39xxj: could not open i2c gate [%d]\n",
12210 state->i2c_gate_open = enable;
12215 static int drx39xxj_init(struct dvb_frontend *fe)
12217 struct drx39xxj_state *state = fe->demodulator_priv;
12218 struct drx_demod_instance *demod = state->demod;
12221 if (fe->exit == DVB_FE_DEVICE_RESUME) {
12222 /* so drxj_open() does what it needs to do */
12223 demod->my_common_attr->is_opened = false;
12224 rc = drxj_open(demod);
12226 pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc);
12228 drx39xxj_set_powerstate(fe, 1);
12233 static int drx39xxj_set_lna(struct dvb_frontend *fe)
12235 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
12236 struct drx39xxj_state *state = fe->demodulator_priv;
12237 struct drx_demod_instance *demod = state->demod;
12238 struct drxj_data *ext_attr = demod->my_ext_attr;
12241 if (!ext_attr->has_lna) {
12242 pr_err("LNA is not supported on this device!\n");
12248 return drxj_set_lna_state(demod, c->lna);
12251 static int drx39xxj_get_tune_settings(struct dvb_frontend *fe,
12252 struct dvb_frontend_tune_settings *tune)
12254 tune->min_delay_ms = 1000;
12258 static void drx39xxj_release(struct dvb_frontend *fe)
12260 struct drx39xxj_state *state = fe->demodulator_priv;
12261 struct drx_demod_instance *demod = state->demod;
12263 /* if device is removed don't access it */
12264 if (fe->exit != DVB_FE_DEVICE_REMOVED)
12267 kfree(demod->my_ext_attr);
12268 kfree(demod->my_common_attr);
12269 kfree(demod->my_i2c_dev_addr);
12270 release_firmware(demod->firmware);
12275 static const struct dvb_frontend_ops drx39xxj_ops;
12277 struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
12279 struct drx39xxj_state *state = NULL;
12280 struct i2c_device_addr *demod_addr = NULL;
12281 struct drx_common_attr *demod_comm_attr = NULL;
12282 struct drxj_data *demod_ext_attr = NULL;
12283 struct drx_demod_instance *demod = NULL;
12284 struct dtv_frontend_properties *p;
12287 /* allocate memory for the internal state */
12288 state = kzalloc(sizeof(struct drx39xxj_state), GFP_KERNEL);
12292 demod = kmemdup(&drxj_default_demod_g,
12293 sizeof(struct drx_demod_instance), GFP_KERNEL);
12297 demod_addr = kmemdup(&drxj_default_addr_g,
12298 sizeof(struct i2c_device_addr), GFP_KERNEL);
12299 if (demod_addr == NULL)
12302 demod_comm_attr = kmemdup(&drxj_default_comm_attr_g,
12303 sizeof(struct drx_common_attr), GFP_KERNEL);
12304 if (demod_comm_attr == NULL)
12307 demod_ext_attr = kmemdup(&drxj_data_g, sizeof(struct drxj_data),
12309 if (demod_ext_attr == NULL)
12312 /* setup the state */
12314 state->demod = demod;
12316 /* setup the demod data */
12317 demod->my_i2c_dev_addr = demod_addr;
12318 demod->my_common_attr = demod_comm_attr;
12319 demod->my_i2c_dev_addr->user_data = state;
12320 demod->my_common_attr->microcode_file = DRX39XX_MAIN_FIRMWARE;
12321 demod->my_common_attr->verify_microcode = true;
12322 demod->my_common_attr->intermediate_freq = 5000;
12323 demod->my_common_attr->current_power_mode = DRX_POWER_DOWN;
12324 demod->my_ext_attr = demod_ext_attr;
12325 ((struct drxj_data *)demod_ext_attr)->uio_sma_tx_mode = DRX_UIO_MODE_READWRITE;
12328 result = drxj_open(demod);
12330 pr_err("DRX open failed! Aborting\n");
12334 /* create dvb_frontend */
12335 memcpy(&state->frontend.ops, &drx39xxj_ops,
12336 sizeof(struct dvb_frontend_ops));
12338 state->frontend.demodulator_priv = state;
12340 /* Initialize stats - needed for DVBv5 stats to work */
12341 p = &state->frontend.dtv_property_cache;
12342 p->strength.len = 1;
12343 p->pre_bit_count.len = 1;
12344 p->pre_bit_error.len = 1;
12345 p->post_bit_count.len = 1;
12346 p->post_bit_error.len = 1;
12347 p->block_count.len = 1;
12348 p->block_error.len = 1;
12351 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
12352 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12353 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12354 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12355 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12356 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12357 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12358 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
12360 return &state->frontend;
12363 kfree(demod_ext_attr);
12364 kfree(demod_comm_attr);
12371 EXPORT_SYMBOL_GPL(drx39xxj_attach);
12373 static const struct dvb_frontend_ops drx39xxj_ops = {
12374 .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B },
12376 .name = "Micronas DRX39xxj family Frontend",
12377 .frequency_min_hz = 51 * MHz,
12378 .frequency_max_hz = 858 * MHz,
12379 .frequency_stepsize_hz = 62500,
12380 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
12383 .init = drx39xxj_init,
12384 .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl,
12385 .sleep = drx39xxj_sleep,
12386 .set_frontend = drx39xxj_set_frontend,
12387 .get_tune_settings = drx39xxj_get_tune_settings,
12388 .read_status = drx39xxj_read_status,
12389 .read_ber = drx39xxj_read_ber,
12390 .read_signal_strength = drx39xxj_read_signal_strength,
12391 .read_snr = drx39xxj_read_snr,
12392 .read_ucblocks = drx39xxj_read_ucblocks,
12393 .release = drx39xxj_release,
12394 .set_lna = drx39xxj_set_lna,
12397 MODULE_DESCRIPTION("Micronas DRX39xxj Frontend");
12398 MODULE_AUTHOR("Devin Heitmueller");
12399 MODULE_LICENSE("GPL");