1 // SPDX-License-Identifier: GPL-2.0
4 * Sony CXD2880 DVB-T2/T tuner + demodulator driver
6 * Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
9 #define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__
11 #include <linux/spi/spi.h>
13 #include <media/dvb_frontend.h>
14 #include <media/dvb_math.h>
17 #include "cxd2880_tnrdmd_mon.h"
18 #include "cxd2880_tnrdmd_dvbt2_mon.h"
19 #include "cxd2880_tnrdmd_dvbt_mon.h"
20 #include "cxd2880_integ.h"
21 #include "cxd2880_tnrdmd_dvbt2.h"
22 #include "cxd2880_tnrdmd_dvbt.h"
23 #include "cxd2880_devio_spi.h"
24 #include "cxd2880_spi_device.h"
25 #include "cxd2880_tnrdmd_driver_version.h"
28 struct cxd2880_tnrdmd tnrdmd;
29 struct spi_device *spi;
30 struct cxd2880_io regio;
31 struct cxd2880_spi_device spi_device;
32 struct cxd2880_spi cxd2880_spi;
33 struct cxd2880_dvbt_tune_param dvbt_tune_param;
34 struct cxd2880_dvbt2_tune_param dvbt2_tune_param;
35 struct mutex *spi_mutex; /* For SPI access exclusive control */
36 unsigned long pre_ber_update;
37 unsigned long pre_ber_interval;
38 unsigned long post_ber_update;
39 unsigned long post_ber_interval;
40 unsigned long ucblock_update;
41 unsigned long ucblock_interval;
45 static int cxd2880_pre_bit_err_t(struct cxd2880_tnrdmd *tnrdmd,
46 u32 *pre_bit_err, u32 *pre_bit_count)
51 if (!tnrdmd || !pre_bit_err || !pre_bit_count)
54 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
57 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
60 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
63 ret = slvt_freeze_reg(tnrdmd);
67 ret = tnrdmd->io->write_reg(tnrdmd->io,
71 slvt_unfreeze_reg(tnrdmd);
75 ret = tnrdmd->io->read_regs(tnrdmd->io,
79 slvt_unfreeze_reg(tnrdmd);
83 if ((rdata[0] & 0x01) == 0) {
84 slvt_unfreeze_reg(tnrdmd);
88 ret = tnrdmd->io->read_regs(tnrdmd->io,
92 slvt_unfreeze_reg(tnrdmd);
96 *pre_bit_err = (rdata[0] << 8) | rdata[1];
98 ret = tnrdmd->io->read_regs(tnrdmd->io,
102 slvt_unfreeze_reg(tnrdmd);
106 slvt_unfreeze_reg(tnrdmd);
108 *pre_bit_count = ((rdata[0] & 0x07) == 0) ?
109 256 : (0x1000 << (rdata[0] & 0x07));
114 static int cxd2880_pre_bit_err_t2(struct cxd2880_tnrdmd *tnrdmd,
123 if (!tnrdmd || !pre_bit_err || !pre_bit_count)
126 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
129 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
132 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
135 ret = slvt_freeze_reg(tnrdmd);
139 ret = tnrdmd->io->write_reg(tnrdmd->io,
143 slvt_unfreeze_reg(tnrdmd);
147 ret = tnrdmd->io->read_regs(tnrdmd->io,
149 0x3c, data, sizeof(data));
151 slvt_unfreeze_reg(tnrdmd);
155 if (!(data[0] & 0x01)) {
156 slvt_unfreeze_reg(tnrdmd);
160 ((data[1] & 0x0f) << 24) | (data[2] << 16) | (data[3] << 8) | data[4];
162 ret = tnrdmd->io->read_regs(tnrdmd->io,
166 slvt_unfreeze_reg(tnrdmd);
170 if (((enum cxd2880_dvbt2_plp_fec)(data[0] & 0x03)) ==
171 CXD2880_DVBT2_FEC_LDPC_16K)
175 slvt_unfreeze_reg(tnrdmd);
177 ret = tnrdmd->io->write_reg(tnrdmd->io,
183 ret = tnrdmd->io->read_regs(tnrdmd->io,
189 period_exp = data[0] & 0x0f;
191 *pre_bit_count = (1U << period_exp) * n_ldpc;
196 static int cxd2880_post_bit_err_t(struct cxd2880_tnrdmd *tnrdmd,
205 if (!tnrdmd || !post_bit_err || !post_bit_count)
208 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
211 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
214 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
217 ret = tnrdmd->io->write_reg(tnrdmd->io,
223 ret = tnrdmd->io->read_regs(tnrdmd->io,
229 if ((rdata[0] & 0x40) == 0)
232 *post_bit_err = ((rdata[0] & 0x3f) << 16) | (rdata[1] << 8) | rdata[2];
234 ret = tnrdmd->io->write_reg(tnrdmd->io,
240 ret = tnrdmd->io->read_regs(tnrdmd->io,
246 period_exp = (rdata[0] & 0x1f);
248 if (period_exp <= 11 && (bit_error > (1U << period_exp) * 204 * 8))
251 *post_bit_count = (1U << period_exp) * 204 * 8;
256 static int cxd2880_post_bit_err_t2(struct cxd2880_tnrdmd *tnrdmd,
263 enum cxd2880_dvbt2_plp_fec plp_fec_type =
264 CXD2880_DVBT2_FEC_LDPC_16K;
265 enum cxd2880_dvbt2_plp_code_rate plp_code_rate =
268 static const u16 n_bch_bits_lookup[2][8] = {
269 {7200, 9720, 10800, 11880, 12600, 13320, 5400, 6480},
270 {32400, 38880, 43200, 48600, 51840, 54000, 21600, 25920}
273 if (!tnrdmd || !post_bit_err || !post_bit_count)
276 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
279 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
282 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
285 ret = slvt_freeze_reg(tnrdmd);
289 ret = tnrdmd->io->write_reg(tnrdmd->io,
293 slvt_unfreeze_reg(tnrdmd);
297 ret = tnrdmd->io->read_regs(tnrdmd->io,
301 slvt_unfreeze_reg(tnrdmd);
305 if (!(data[0] & 0x40)) {
306 slvt_unfreeze_reg(tnrdmd);
311 ((data[0] & 0x3f) << 16) | (data[1] << 8) | data[2];
313 ret = tnrdmd->io->read_regs(tnrdmd->io,
317 slvt_unfreeze_reg(tnrdmd);
322 (enum cxd2880_dvbt2_plp_code_rate)(data[0] & 0x07);
324 ret = tnrdmd->io->read_regs(tnrdmd->io,
328 slvt_unfreeze_reg(tnrdmd);
332 plp_fec_type = (enum cxd2880_dvbt2_plp_fec)(data[0] & 0x03);
334 slvt_unfreeze_reg(tnrdmd);
336 ret = tnrdmd->io->write_reg(tnrdmd->io,
342 ret = tnrdmd->io->read_regs(tnrdmd->io,
348 period_exp = data[0] & 0x0f;
350 if (plp_fec_type > CXD2880_DVBT2_FEC_LDPC_64K ||
351 plp_code_rate > CXD2880_DVBT2_R2_5)
354 n_bch = n_bch_bits_lookup[plp_fec_type][plp_code_rate];
356 if (*post_bit_err > ((1U << period_exp) * n_bch))
359 *post_bit_count = (1U << period_exp) * n_bch;
364 static int cxd2880_read_block_err_t(struct cxd2880_tnrdmd *tnrdmd,
371 if (!tnrdmd || !block_err || !block_count)
374 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
377 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
380 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT)
383 ret = tnrdmd->io->write_reg(tnrdmd->io,
389 ret = tnrdmd->io->read_regs(tnrdmd->io,
395 if ((rdata[0] & 0x01) == 0)
398 *block_err = (rdata[1] << 8) | rdata[2];
400 ret = tnrdmd->io->write_reg(tnrdmd->io,
406 ret = tnrdmd->io->read_regs(tnrdmd->io,
412 *block_count = 1U << (rdata[0] & 0x0f);
414 if ((*block_count == 0) || (*block_err > *block_count))
420 static int cxd2880_read_block_err_t2(struct cxd2880_tnrdmd *tnrdmd,
427 if (!tnrdmd || !block_err || !block_count)
430 if (tnrdmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
433 if (tnrdmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
435 if (tnrdmd->sys != CXD2880_DTV_SYS_DVBT2)
438 ret = tnrdmd->io->write_reg(tnrdmd->io,
444 ret = tnrdmd->io->read_regs(tnrdmd->io,
450 if ((rdata[0] & 0x01) == 0)
453 *block_err = (rdata[1] << 8) | rdata[2];
455 ret = tnrdmd->io->write_reg(tnrdmd->io,
461 ret = tnrdmd->io->read_regs(tnrdmd->io,
467 *block_count = 1U << (rdata[0] & 0x0f);
469 if ((*block_count == 0) || (*block_err > *block_count))
475 static void cxd2880_release(struct dvb_frontend *fe)
477 struct cxd2880_priv *priv = NULL;
480 pr_err("invalid arg.\n");
483 priv = fe->demodulator_priv;
487 static int cxd2880_init(struct dvb_frontend *fe)
490 struct cxd2880_priv *priv = NULL;
491 struct cxd2880_tnrdmd_create_param create_param;
494 pr_err("invalid arg.\n");
498 priv = fe->demodulator_priv;
500 create_param.ts_output_if = CXD2880_TNRDMD_TSOUT_IF_SPI;
501 create_param.xtal_share_type = CXD2880_TNRDMD_XTAL_SHARE_NONE;
502 create_param.en_internal_ldo = 1;
503 create_param.xosc_cap = 18;
504 create_param.xosc_i = 8;
505 create_param.stationary_use = 1;
507 mutex_lock(priv->spi_mutex);
508 if (priv->tnrdmd.io != &priv->regio) {
509 ret = cxd2880_tnrdmd_create(&priv->tnrdmd,
510 &priv->regio, &create_param);
512 mutex_unlock(priv->spi_mutex);
513 pr_info("cxd2880 tnrdmd create failed %d\n", ret);
517 ret = cxd2880_integ_init(&priv->tnrdmd);
519 mutex_unlock(priv->spi_mutex);
520 pr_err("cxd2880 integ init failed %d\n", ret);
524 ret = cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
525 CXD2880_TNRDMD_CFG_TSPIN_CURRENT,
528 mutex_unlock(priv->spi_mutex);
529 pr_err("cxd2880 set config failed %d\n", ret);
532 mutex_unlock(priv->spi_mutex);
539 static int cxd2880_sleep(struct dvb_frontend *fe)
542 struct cxd2880_priv *priv = NULL;
545 pr_err("invalid arg\n");
549 priv = fe->demodulator_priv;
551 mutex_lock(priv->spi_mutex);
552 ret = cxd2880_tnrdmd_sleep(&priv->tnrdmd);
553 mutex_unlock(priv->spi_mutex);
555 pr_debug("tnrdmd_sleep ret %d\n", ret);
560 static int cxd2880_read_signal_strength(struct dvb_frontend *fe,
564 struct cxd2880_priv *priv = NULL;
565 struct dtv_frontend_properties *c = NULL;
568 if (!fe || !strength) {
569 pr_err("invalid arg\n");
573 priv = fe->demodulator_priv;
574 c = &fe->dtv_property_cache;
576 mutex_lock(priv->spi_mutex);
577 if (c->delivery_system == SYS_DVBT ||
578 c->delivery_system == SYS_DVBT2) {
579 ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &level);
581 pr_debug("invalid system\n");
582 mutex_unlock(priv->spi_mutex);
585 mutex_unlock(priv->spi_mutex);
589 * level should be between -105dBm and -30dBm.
590 * E.g. they should be between:
591 * -105000/125 = -840 and -30000/125 = -240
593 level = clamp(level, -840, -240);
594 /* scale value to 0x0000-0xffff */
595 *strength = ((level + 840) * 0xffff) / (-240 + 840);
598 pr_debug("ret = %d\n", ret);
603 static int cxd2880_read_snr(struct dvb_frontend *fe, u16 *snr)
607 struct cxd2880_priv *priv = NULL;
608 struct dtv_frontend_properties *c = NULL;
611 pr_err("invalid arg\n");
615 priv = fe->demodulator_priv;
616 c = &fe->dtv_property_cache;
618 mutex_lock(priv->spi_mutex);
619 if (c->delivery_system == SYS_DVBT) {
620 ret = cxd2880_tnrdmd_dvbt_mon_snr(&priv->tnrdmd,
622 } else if (c->delivery_system == SYS_DVBT2) {
623 ret = cxd2880_tnrdmd_dvbt2_mon_snr(&priv->tnrdmd,
626 pr_err("invalid system\n");
627 mutex_unlock(priv->spi_mutex);
630 mutex_unlock(priv->spi_mutex);
637 pr_debug("ret = %d\n", ret);
642 static int cxd2880_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
645 struct cxd2880_priv *priv = NULL;
646 struct dtv_frontend_properties *c = NULL;
648 if (!fe || !ucblocks) {
649 pr_err("invalid arg\n");
653 priv = fe->demodulator_priv;
654 c = &fe->dtv_property_cache;
656 mutex_lock(priv->spi_mutex);
657 if (c->delivery_system == SYS_DVBT) {
658 ret = cxd2880_tnrdmd_dvbt_mon_packet_error_number(&priv->tnrdmd,
660 } else if (c->delivery_system == SYS_DVBT2) {
661 ret = cxd2880_tnrdmd_dvbt2_mon_packet_error_number(&priv->tnrdmd,
664 pr_err("invalid system\n");
665 mutex_unlock(priv->spi_mutex);
668 mutex_unlock(priv->spi_mutex);
671 pr_debug("ret = %d\n", ret);
676 static int cxd2880_read_ber(struct dvb_frontend *fe, u32 *ber)
683 static int cxd2880_set_ber_per_period_t(struct dvb_frontend *fe)
686 struct cxd2880_priv *priv;
687 struct cxd2880_dvbt_tpsinfo info;
688 enum cxd2880_dtv_bandwidth bw;
689 u32 pre_ber_rate = 0;
690 u32 post_ber_rate = 0;
691 u32 ucblock_rate = 0;
693 static const int cr_table[5] = {31500, 42000, 47250, 52500, 55125};
694 static const int denominator_tbl[4] = {125664, 129472, 137088, 152320};
697 pr_err("invalid arg\n");
701 priv = fe->demodulator_priv;
702 bw = priv->dvbt_tune_param.bandwidth;
704 ret = cxd2880_tnrdmd_dvbt_mon_tps_info(&priv->tnrdmd,
707 pr_err("tps monitor error ret = %d\n", ret);
708 info.hierarchy = CXD2880_DVBT_HIERARCHY_NON;
709 info.constellation = CXD2880_DVBT_CONSTELLATION_QPSK;
710 info.guard = CXD2880_DVBT_GUARD_1_4;
711 info.rate_hp = CXD2880_DVBT_CODERATE_1_2;
712 info.rate_lp = CXD2880_DVBT_CODERATE_1_2;
715 if (info.hierarchy == CXD2880_DVBT_HIERARCHY_NON) {
716 pre_ber_rate = 63000000 * bw * (info.constellation * 2 + 2) /
717 denominator_tbl[info.guard];
719 post_ber_rate = 1000 * cr_table[info.rate_hp] * bw *
720 (info.constellation * 2 + 2) /
721 denominator_tbl[info.guard];
723 ucblock_rate = 875 * cr_table[info.rate_hp] * bw *
724 (info.constellation * 2 + 2) /
725 denominator_tbl[info.guard];
728 struct cxd2880_tnrdmd *tnrdmd = &priv->tnrdmd;
730 ret = tnrdmd->io->write_reg(tnrdmd->io,
734 ret = tnrdmd->io->read_regs(tnrdmd->io,
743 if (data & 0x01) { /* Low priority */
745 63000000 * bw * (info.constellation * 2 + 2) /
746 denominator_tbl[info.guard];
748 post_ber_rate = 1000 * cr_table[info.rate_lp] * bw *
749 (info.constellation * 2 + 2) /
750 denominator_tbl[info.guard];
752 ucblock_rate = (1000 * 7 / 8) * cr_table[info.rate_lp] *
753 bw * (info.constellation * 2 + 2) /
754 denominator_tbl[info.guard];
755 } else { /* High priority */
757 63000000 * bw * 2 / denominator_tbl[info.guard];
759 post_ber_rate = 1000 * cr_table[info.rate_hp] * bw * 2 /
760 denominator_tbl[info.guard];
762 ucblock_rate = (1000 * 7 / 8) * cr_table[info.rate_hp] *
763 bw * 2 / denominator_tbl[info.guard];
767 mes_exp = pre_ber_rate < 8192 ? 8 : intlog2(pre_ber_rate) >> 24;
768 priv->pre_ber_interval =
769 ((1U << mes_exp) * 1000 + (pre_ber_rate / 2)) /
771 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
772 CXD2880_TNRDMD_CFG_DVBT_VBER_PERIOD,
773 mes_exp == 8 ? 0 : mes_exp - 12);
775 mes_exp = intlog2(post_ber_rate) >> 24;
776 priv->post_ber_interval =
777 ((1U << mes_exp) * 1000 + (post_ber_rate / 2)) /
779 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
780 CXD2880_TNRDMD_CFG_DVBT_BERN_PERIOD,
783 mes_exp = intlog2(ucblock_rate) >> 24;
784 priv->ucblock_interval =
785 ((1U << mes_exp) * 1000 + (ucblock_rate / 2)) /
787 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
788 CXD2880_TNRDMD_CFG_DVBT_PER_MES,
794 static int cxd2880_set_ber_per_period_t2(struct dvb_frontend *fe)
797 struct cxd2880_priv *priv;
798 struct cxd2880_dvbt2_l1pre l1pre;
799 struct cxd2880_dvbt2_l1post l1post;
800 struct cxd2880_dvbt2_plp plp;
801 struct cxd2880_dvbt2_bbheader bbheader;
802 enum cxd2880_dtv_bandwidth bw = CXD2880_DTV_BW_1_7_MHZ;
803 u32 pre_ber_rate = 0;
804 u32 post_ber_rate = 0;
805 u32 ucblock_rate = 0;
810 static const u32 gi_tbl[7] = {32, 64, 128, 256, 8, 152, 76};
811 static const u8 n_tbl[6] = {8, 2, 4, 16, 1, 1};
812 static const u8 mode_tbl[6] = {2, 8, 4, 1, 16, 32};
813 static const u32 kbch_tbl[2][8] = {
814 {6952, 9472, 10552, 11632, 12352, 13072, 5152, 6232},
815 {32128, 38608, 42960, 48328, 51568, 53760, 0, 0}
819 pr_err("invalid arg\n");
823 priv = fe->demodulator_priv;
824 bw = priv->dvbt2_tune_param.bandwidth;
826 ret = cxd2880_tnrdmd_dvbt2_mon_l1_pre(&priv->tnrdmd, &l1pre);
828 pr_info("l1 pre error\n");
829 goto error_ber_setting;
832 ret = cxd2880_tnrdmd_dvbt2_mon_active_plp(&priv->tnrdmd,
833 CXD2880_DVBT2_PLP_DATA, &plp);
835 pr_info("plp info error\n");
836 goto error_ber_setting;
839 ret = cxd2880_tnrdmd_dvbt2_mon_l1_post(&priv->tnrdmd, &l1post);
841 pr_info("l1 post error\n");
842 goto error_ber_setting;
846 (mode_tbl[l1pre.fft_mode] * (1024 + gi_tbl[l1pre.gi])) *
847 (l1pre.num_symbols + n_tbl[l1pre.fft_mode]) + 2048;
849 if (l1pre.mixed && l1post.fef_intvl) {
850 term_b = (l1post.fef_length + (l1post.fef_intvl / 2)) /
857 case CXD2880_DTV_BW_1_7_MHZ:
858 denominator = ((term_a + term_b) * 71 + (131 / 2)) / 131;
860 case CXD2880_DTV_BW_5_MHZ:
861 denominator = ((term_a + term_b) * 7 + 20) / 40;
863 case CXD2880_DTV_BW_6_MHZ:
864 denominator = ((term_a + term_b) * 7 + 24) / 48;
866 case CXD2880_DTV_BW_7_MHZ:
867 denominator = ((term_a + term_b) + 4) / 8;
869 case CXD2880_DTV_BW_8_MHZ:
871 denominator = ((term_a + term_b) * 7 + 32) / 64;
875 if (plp.til_type && plp.til_len) {
877 (plp.num_blocks_max * 1000000 + (denominator / 2)) /
879 pre_ber_rate = (pre_ber_rate + (plp.til_len / 2)) /
883 (plp.num_blocks_max * 1000000 + (denominator / 2)) /
887 post_ber_rate = pre_ber_rate;
889 mes_exp = intlog2(pre_ber_rate) >> 24;
890 priv->pre_ber_interval =
891 ((1U << mes_exp) * 1000 + (pre_ber_rate / 2)) /
893 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
894 CXD2880_TNRDMD_CFG_DVBT2_LBER_MES,
897 mes_exp = intlog2(post_ber_rate) >> 24;
898 priv->post_ber_interval =
899 ((1U << mes_exp) * 1000 + (post_ber_rate / 2)) /
901 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
902 CXD2880_TNRDMD_CFG_DVBT2_BBER_MES,
905 ret = cxd2880_tnrdmd_dvbt2_mon_bbheader(&priv->tnrdmd,
906 CXD2880_DVBT2_PLP_DATA,
909 pr_info("bb header error\n");
910 goto error_ucblock_setting;
913 if (bbheader.plp_mode == CXD2880_DVBT2_PLP_MODE_NM) {
914 if (!bbheader.issy_indicator) {
916 (pre_ber_rate * kbch_tbl[plp.fec][plp.plp_cr] +
920 (pre_ber_rate * kbch_tbl[plp.fec][plp.plp_cr] +
923 } else if (bbheader.plp_mode == CXD2880_DVBT2_PLP_MODE_HEM) {
925 (pre_ber_rate * kbch_tbl[plp.fec][plp.plp_cr] + 748) /
928 pr_info("plp mode is not Normal or HEM\n");
929 goto error_ucblock_setting;
932 mes_exp = intlog2(ucblock_rate) >> 24;
933 priv->ucblock_interval =
934 ((1U << mes_exp) * 1000 + (ucblock_rate / 2)) /
936 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
937 CXD2880_TNRDMD_CFG_DVBT2_PER_MES,
943 priv->pre_ber_interval = 1000;
944 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
945 CXD2880_TNRDMD_CFG_DVBT2_LBER_MES, 0);
947 priv->post_ber_interval = 1000;
948 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
949 CXD2880_TNRDMD_CFG_DVBT2_BBER_MES, 0);
951 error_ucblock_setting:
952 priv->ucblock_interval = 1000;
953 cxd2880_tnrdmd_set_cfg(&priv->tnrdmd,
954 CXD2880_TNRDMD_CFG_DVBT2_PER_MES, 8);
959 static int cxd2880_dvbt_tune(struct cxd2880_tnrdmd *tnr_dmd,
960 struct cxd2880_dvbt_tune_param
965 if (!tnr_dmd || !tune_param)
968 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
971 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
972 tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
975 atomic_set(&tnr_dmd->cancel, 0);
977 if (tune_param->bandwidth != CXD2880_DTV_BW_5_MHZ &&
978 tune_param->bandwidth != CXD2880_DTV_BW_6_MHZ &&
979 tune_param->bandwidth != CXD2880_DTV_BW_7_MHZ &&
980 tune_param->bandwidth != CXD2880_DTV_BW_8_MHZ) {
984 ret = cxd2880_tnrdmd_dvbt_tune1(tnr_dmd, tune_param);
988 usleep_range(CXD2880_TNRDMD_WAIT_AGC_STABLE * 10000,
989 CXD2880_TNRDMD_WAIT_AGC_STABLE * 10000 + 1000);
991 return cxd2880_tnrdmd_dvbt_tune2(tnr_dmd, tune_param);
994 static int cxd2880_dvbt2_tune(struct cxd2880_tnrdmd *tnr_dmd,
995 struct cxd2880_dvbt2_tune_param
1000 if (!tnr_dmd || !tune_param)
1003 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
1006 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
1007 tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
1010 atomic_set(&tnr_dmd->cancel, 0);
1012 if (tune_param->bandwidth != CXD2880_DTV_BW_1_7_MHZ &&
1013 tune_param->bandwidth != CXD2880_DTV_BW_5_MHZ &&
1014 tune_param->bandwidth != CXD2880_DTV_BW_6_MHZ &&
1015 tune_param->bandwidth != CXD2880_DTV_BW_7_MHZ &&
1016 tune_param->bandwidth != CXD2880_DTV_BW_8_MHZ) {
1020 if (tune_param->profile != CXD2880_DVBT2_PROFILE_BASE &&
1021 tune_param->profile != CXD2880_DVBT2_PROFILE_LITE)
1024 ret = cxd2880_tnrdmd_dvbt2_tune1(tnr_dmd, tune_param);
1028 usleep_range(CXD2880_TNRDMD_WAIT_AGC_STABLE * 10000,
1029 CXD2880_TNRDMD_WAIT_AGC_STABLE * 10000 + 1000);
1031 return cxd2880_tnrdmd_dvbt2_tune2(tnr_dmd, tune_param);
1034 static int cxd2880_set_frontend(struct dvb_frontend *fe)
1037 struct dtv_frontend_properties *c;
1038 struct cxd2880_priv *priv;
1039 enum cxd2880_dtv_bandwidth bw = CXD2880_DTV_BW_1_7_MHZ;
1042 pr_err("invalid arg\n");
1046 priv = fe->demodulator_priv;
1047 c = &fe->dtv_property_cache;
1049 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1050 c->pre_bit_error.stat[0].uvalue = 0;
1051 c->pre_bit_error.len = 1;
1052 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1053 c->pre_bit_count.stat[0].uvalue = 0;
1054 c->pre_bit_count.len = 1;
1055 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1056 c->post_bit_error.stat[0].uvalue = 0;
1057 c->post_bit_error.len = 1;
1058 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1059 c->post_bit_count.stat[0].uvalue = 0;
1060 c->post_bit_count.len = 1;
1061 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1062 c->block_error.stat[0].uvalue = 0;
1063 c->block_error.len = 1;
1064 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1065 c->block_count.stat[0].uvalue = 0;
1066 c->block_count.len = 1;
1068 switch (c->bandwidth_hz) {
1070 bw = CXD2880_DTV_BW_1_7_MHZ;
1073 bw = CXD2880_DTV_BW_5_MHZ;
1076 bw = CXD2880_DTV_BW_6_MHZ;
1079 bw = CXD2880_DTV_BW_7_MHZ;
1082 bw = CXD2880_DTV_BW_8_MHZ;
1090 pr_info("sys:%d freq:%d bw:%d\n",
1091 c->delivery_system, c->frequency, bw);
1092 mutex_lock(priv->spi_mutex);
1093 if (c->delivery_system == SYS_DVBT) {
1094 priv->tnrdmd.sys = CXD2880_DTV_SYS_DVBT;
1095 priv->dvbt_tune_param.center_freq_khz = c->frequency / 1000;
1096 priv->dvbt_tune_param.bandwidth = bw;
1097 priv->dvbt_tune_param.profile = CXD2880_DVBT_PROFILE_HP;
1098 ret = cxd2880_dvbt_tune(&priv->tnrdmd,
1099 &priv->dvbt_tune_param);
1100 } else if (c->delivery_system == SYS_DVBT2) {
1101 priv->tnrdmd.sys = CXD2880_DTV_SYS_DVBT2;
1102 priv->dvbt2_tune_param.center_freq_khz = c->frequency / 1000;
1103 priv->dvbt2_tune_param.bandwidth = bw;
1104 priv->dvbt2_tune_param.data_plp_id = (u16)c->stream_id;
1105 priv->dvbt2_tune_param.profile = CXD2880_DVBT2_PROFILE_BASE;
1106 ret = cxd2880_dvbt2_tune(&priv->tnrdmd,
1107 &priv->dvbt2_tune_param);
1109 pr_err("invalid system\n");
1110 mutex_unlock(priv->spi_mutex);
1113 mutex_unlock(priv->spi_mutex);
1115 pr_info("tune result %d\n", ret);
1120 static int cxd2880_get_stats(struct dvb_frontend *fe,
1121 enum fe_status status)
1123 struct cxd2880_priv *priv = NULL;
1124 struct dtv_frontend_properties *c = NULL;
1125 u32 pre_bit_err = 0, pre_bit_count = 0;
1126 u32 post_bit_err = 0, post_bit_count = 0;
1127 u32 block_err = 0, block_count = 0;
1131 pr_err("invalid arg\n");
1135 priv = fe->demodulator_priv;
1136 c = &fe->dtv_property_cache;
1138 if (!(status & FE_HAS_LOCK) || !(status & FE_HAS_CARRIER)) {
1139 c->pre_bit_error.len = 1;
1140 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1141 c->pre_bit_count.len = 1;
1142 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1143 c->post_bit_error.len = 1;
1144 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1145 c->post_bit_count.len = 1;
1146 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1147 c->block_error.len = 1;
1148 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1149 c->block_count.len = 1;
1150 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1155 if (time_after(jiffies, priv->pre_ber_update)) {
1156 priv->pre_ber_update =
1157 jiffies + msecs_to_jiffies(priv->pre_ber_interval);
1158 if (c->delivery_system == SYS_DVBT) {
1159 mutex_lock(priv->spi_mutex);
1160 ret = cxd2880_pre_bit_err_t(&priv->tnrdmd,
1163 mutex_unlock(priv->spi_mutex);
1164 } else if (c->delivery_system == SYS_DVBT2) {
1165 mutex_lock(priv->spi_mutex);
1166 ret = cxd2880_pre_bit_err_t2(&priv->tnrdmd,
1169 mutex_unlock(priv->spi_mutex);
1175 c->pre_bit_error.len = 1;
1176 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1177 c->pre_bit_error.stat[0].uvalue += pre_bit_err;
1178 c->pre_bit_count.len = 1;
1179 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1180 c->pre_bit_count.stat[0].uvalue += pre_bit_count;
1182 c->pre_bit_error.len = 1;
1183 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1184 c->pre_bit_count.len = 1;
1185 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1186 pr_debug("pre_bit_error_t failed %d\n", ret);
1190 if (time_after(jiffies, priv->post_ber_update)) {
1191 priv->post_ber_update =
1192 jiffies + msecs_to_jiffies(priv->post_ber_interval);
1193 if (c->delivery_system == SYS_DVBT) {
1194 mutex_lock(priv->spi_mutex);
1195 ret = cxd2880_post_bit_err_t(&priv->tnrdmd,
1198 mutex_unlock(priv->spi_mutex);
1199 } else if (c->delivery_system == SYS_DVBT2) {
1200 mutex_lock(priv->spi_mutex);
1201 ret = cxd2880_post_bit_err_t2(&priv->tnrdmd,
1204 mutex_unlock(priv->spi_mutex);
1210 c->post_bit_error.len = 1;
1211 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1212 c->post_bit_error.stat[0].uvalue += post_bit_err;
1213 c->post_bit_count.len = 1;
1214 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1215 c->post_bit_count.stat[0].uvalue += post_bit_count;
1217 c->post_bit_error.len = 1;
1218 c->post_bit_error.stat[0].scale =
1219 FE_SCALE_NOT_AVAILABLE;
1220 c->post_bit_count.len = 1;
1221 c->post_bit_count.stat[0].scale =
1222 FE_SCALE_NOT_AVAILABLE;
1223 pr_debug("post_bit_err_t %d\n", ret);
1227 if (time_after(jiffies, priv->ucblock_update)) {
1228 priv->ucblock_update =
1229 jiffies + msecs_to_jiffies(priv->ucblock_interval);
1230 if (c->delivery_system == SYS_DVBT) {
1231 mutex_lock(priv->spi_mutex);
1232 ret = cxd2880_read_block_err_t(&priv->tnrdmd,
1235 mutex_unlock(priv->spi_mutex);
1236 } else if (c->delivery_system == SYS_DVBT2) {
1237 mutex_lock(priv->spi_mutex);
1238 ret = cxd2880_read_block_err_t2(&priv->tnrdmd,
1241 mutex_unlock(priv->spi_mutex);
1246 c->block_error.len = 1;
1247 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
1248 c->block_error.stat[0].uvalue += block_err;
1249 c->block_count.len = 1;
1250 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
1251 c->block_count.stat[0].uvalue += block_count;
1253 c->block_error.len = 1;
1254 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1255 c->block_count.len = 1;
1256 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1257 pr_debug("read_block_err_t %d\n", ret);
1264 static int cxd2880_check_l1post_plp(struct dvb_frontend *fe)
1269 struct cxd2880_priv *priv = NULL;
1272 pr_err("invalid arg\n");
1276 priv = fe->demodulator_priv;
1278 ret = cxd2880_tnrdmd_dvbt2_check_l1post_valid(&priv->tnrdmd,
1286 ret = cxd2880_tnrdmd_dvbt2_mon_data_plp_error(&priv->tnrdmd,
1291 if (plp_not_found) {
1292 priv->dvbt2_tune_param.tune_info =
1293 CXD2880_TNRDMD_DVBT2_TUNE_INFO_INVALID_PLP_ID;
1295 priv->dvbt2_tune_param.tune_info =
1296 CXD2880_TNRDMD_DVBT2_TUNE_INFO_OK;
1302 static int cxd2880_read_status(struct dvb_frontend *fe,
1303 enum fe_status *status)
1309 struct cxd2880_priv *priv = NULL;
1310 struct dtv_frontend_properties *c = NULL;
1312 if (!fe || !status) {
1313 pr_err("invalid arg\n");
1317 priv = fe->demodulator_priv;
1318 c = &fe->dtv_property_cache;
1321 if (priv->tnrdmd.state == CXD2880_TNRDMD_STATE_ACTIVE) {
1322 mutex_lock(priv->spi_mutex);
1323 if (c->delivery_system == SYS_DVBT) {
1324 ret = cxd2880_tnrdmd_dvbt_mon_sync_stat(&priv->tnrdmd,
1328 } else if (c->delivery_system == SYS_DVBT2) {
1329 ret = cxd2880_tnrdmd_dvbt2_mon_sync_stat(&priv->tnrdmd,
1334 pr_err("invalid system");
1335 mutex_unlock(priv->spi_mutex);
1339 mutex_unlock(priv->spi_mutex);
1341 pr_err("failed. sys = %d\n", priv->tnrdmd.sys);
1346 *status = FE_HAS_SIGNAL |
1350 *status |= FE_HAS_VITERBI |
1355 pr_debug("status %d\n", *status);
1357 if (priv->s == 0 && (*status & FE_HAS_LOCK) &&
1358 (*status & FE_HAS_CARRIER)) {
1359 mutex_lock(priv->spi_mutex);
1360 if (c->delivery_system == SYS_DVBT) {
1361 ret = cxd2880_set_ber_per_period_t(fe);
1363 } else if (c->delivery_system == SYS_DVBT2) {
1364 ret = cxd2880_check_l1post_plp(fe);
1366 ret = cxd2880_set_ber_per_period_t2(fe);
1370 pr_err("invalid system\n");
1371 mutex_unlock(priv->spi_mutex);
1374 mutex_unlock(priv->spi_mutex);
1377 cxd2880_get_stats(fe, *status);
1381 static int cxd2880_tune(struct dvb_frontend *fe,
1383 unsigned int mode_flags,
1384 unsigned int *delay,
1385 enum fe_status *status)
1389 if (!fe || !delay || !status) {
1390 pr_err("invalid arg.");
1395 ret = cxd2880_set_frontend(fe);
1397 pr_err("cxd2880_set_frontend failed %d\n", ret);
1404 return cxd2880_read_status(fe, status);
1407 static int cxd2880_get_frontend_t(struct dvb_frontend *fe,
1408 struct dtv_frontend_properties *c)
1411 struct cxd2880_priv *priv = NULL;
1412 enum cxd2880_dvbt_mode mode = CXD2880_DVBT_MODE_2K;
1413 enum cxd2880_dvbt_guard guard = CXD2880_DVBT_GUARD_1_32;
1414 struct cxd2880_dvbt_tpsinfo tps;
1415 enum cxd2880_tnrdmd_spectrum_sense sense;
1420 pr_err("invalid arg\n");
1424 priv = fe->demodulator_priv;
1426 mutex_lock(priv->spi_mutex);
1427 ret = cxd2880_tnrdmd_dvbt_mon_mode_guard(&priv->tnrdmd,
1429 mutex_unlock(priv->spi_mutex);
1432 case CXD2880_DVBT_MODE_2K:
1433 c->transmission_mode = TRANSMISSION_MODE_2K;
1435 case CXD2880_DVBT_MODE_8K:
1436 c->transmission_mode = TRANSMISSION_MODE_8K;
1439 c->transmission_mode = TRANSMISSION_MODE_2K;
1440 pr_debug("transmission mode is invalid %d\n", mode);
1444 case CXD2880_DVBT_GUARD_1_32:
1445 c->guard_interval = GUARD_INTERVAL_1_32;
1447 case CXD2880_DVBT_GUARD_1_16:
1448 c->guard_interval = GUARD_INTERVAL_1_16;
1450 case CXD2880_DVBT_GUARD_1_8:
1451 c->guard_interval = GUARD_INTERVAL_1_8;
1453 case CXD2880_DVBT_GUARD_1_4:
1454 c->guard_interval = GUARD_INTERVAL_1_4;
1457 c->guard_interval = GUARD_INTERVAL_1_32;
1458 pr_debug("guard interval is invalid %d\n",
1463 c->transmission_mode = TRANSMISSION_MODE_2K;
1464 c->guard_interval = GUARD_INTERVAL_1_32;
1465 pr_debug("ModeGuard err %d\n", ret);
1468 mutex_lock(priv->spi_mutex);
1469 ret = cxd2880_tnrdmd_dvbt_mon_tps_info(&priv->tnrdmd, &tps);
1470 mutex_unlock(priv->spi_mutex);
1472 switch (tps.hierarchy) {
1473 case CXD2880_DVBT_HIERARCHY_NON:
1474 c->hierarchy = HIERARCHY_NONE;
1476 case CXD2880_DVBT_HIERARCHY_1:
1477 c->hierarchy = HIERARCHY_1;
1479 case CXD2880_DVBT_HIERARCHY_2:
1480 c->hierarchy = HIERARCHY_2;
1482 case CXD2880_DVBT_HIERARCHY_4:
1483 c->hierarchy = HIERARCHY_4;
1486 c->hierarchy = HIERARCHY_NONE;
1487 pr_debug("TPSInfo hierarchy is invalid %d\n",
1492 switch (tps.rate_hp) {
1493 case CXD2880_DVBT_CODERATE_1_2:
1494 c->code_rate_HP = FEC_1_2;
1496 case CXD2880_DVBT_CODERATE_2_3:
1497 c->code_rate_HP = FEC_2_3;
1499 case CXD2880_DVBT_CODERATE_3_4:
1500 c->code_rate_HP = FEC_3_4;
1502 case CXD2880_DVBT_CODERATE_5_6:
1503 c->code_rate_HP = FEC_5_6;
1505 case CXD2880_DVBT_CODERATE_7_8:
1506 c->code_rate_HP = FEC_7_8;
1509 c->code_rate_HP = FEC_NONE;
1510 pr_debug("TPSInfo rateHP is invalid %d\n",
1514 switch (tps.rate_lp) {
1515 case CXD2880_DVBT_CODERATE_1_2:
1516 c->code_rate_LP = FEC_1_2;
1518 case CXD2880_DVBT_CODERATE_2_3:
1519 c->code_rate_LP = FEC_2_3;
1521 case CXD2880_DVBT_CODERATE_3_4:
1522 c->code_rate_LP = FEC_3_4;
1524 case CXD2880_DVBT_CODERATE_5_6:
1525 c->code_rate_LP = FEC_5_6;
1527 case CXD2880_DVBT_CODERATE_7_8:
1528 c->code_rate_LP = FEC_7_8;
1531 c->code_rate_LP = FEC_NONE;
1532 pr_debug("TPSInfo rateLP is invalid %d\n",
1536 switch (tps.constellation) {
1537 case CXD2880_DVBT_CONSTELLATION_QPSK:
1538 c->modulation = QPSK;
1540 case CXD2880_DVBT_CONSTELLATION_16QAM:
1541 c->modulation = QAM_16;
1543 case CXD2880_DVBT_CONSTELLATION_64QAM:
1544 c->modulation = QAM_64;
1547 c->modulation = QPSK;
1548 pr_debug("TPSInfo constellation is invalid %d\n",
1553 c->hierarchy = HIERARCHY_NONE;
1554 c->code_rate_HP = FEC_NONE;
1555 c->code_rate_LP = FEC_NONE;
1556 c->modulation = QPSK;
1557 pr_debug("TPS info err %d\n", ret);
1560 mutex_lock(priv->spi_mutex);
1561 ret = cxd2880_tnrdmd_dvbt_mon_spectrum_sense(&priv->tnrdmd, &sense);
1562 mutex_unlock(priv->spi_mutex);
1565 case CXD2880_TNRDMD_SPECTRUM_NORMAL:
1566 c->inversion = INVERSION_OFF;
1568 case CXD2880_TNRDMD_SPECTRUM_INV:
1569 c->inversion = INVERSION_ON;
1572 c->inversion = INVERSION_OFF;
1573 pr_debug("spectrum sense is invalid %d\n", sense);
1577 c->inversion = INVERSION_OFF;
1578 pr_debug("spectrum_sense %d\n", ret);
1581 mutex_lock(priv->spi_mutex);
1582 ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);
1583 mutex_unlock(priv->spi_mutex);
1585 c->strength.len = 1;
1586 c->strength.stat[0].scale = FE_SCALE_DECIBEL;
1587 c->strength.stat[0].svalue = strength;
1589 c->strength.len = 1;
1590 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1591 pr_debug("mon_rf_lvl %d\n", ret);
1594 ret = cxd2880_read_snr(fe, &snr);
1597 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1598 c->cnr.stat[0].svalue = snr;
1601 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1602 pr_debug("read_snr %d\n", ret);
1608 static int cxd2880_get_frontend_t2(struct dvb_frontend *fe,
1609 struct dtv_frontend_properties *c)
1612 struct cxd2880_priv *priv = NULL;
1613 struct cxd2880_dvbt2_l1pre l1pre;
1614 enum cxd2880_dvbt2_plp_code_rate coderate;
1615 enum cxd2880_dvbt2_plp_constell qam;
1616 enum cxd2880_tnrdmd_spectrum_sense sense;
1621 pr_err("invalid arg.\n");
1625 priv = fe->demodulator_priv;
1627 mutex_lock(priv->spi_mutex);
1628 ret = cxd2880_tnrdmd_dvbt2_mon_l1_pre(&priv->tnrdmd, &l1pre);
1629 mutex_unlock(priv->spi_mutex);
1631 switch (l1pre.fft_mode) {
1632 case CXD2880_DVBT2_M2K:
1633 c->transmission_mode = TRANSMISSION_MODE_2K;
1635 case CXD2880_DVBT2_M8K:
1636 c->transmission_mode = TRANSMISSION_MODE_8K;
1638 case CXD2880_DVBT2_M4K:
1639 c->transmission_mode = TRANSMISSION_MODE_4K;
1641 case CXD2880_DVBT2_M1K:
1642 c->transmission_mode = TRANSMISSION_MODE_1K;
1644 case CXD2880_DVBT2_M16K:
1645 c->transmission_mode = TRANSMISSION_MODE_16K;
1647 case CXD2880_DVBT2_M32K:
1648 c->transmission_mode = TRANSMISSION_MODE_32K;
1651 c->transmission_mode = TRANSMISSION_MODE_2K;
1652 pr_debug("L1Pre fft_mode is invalid %d\n",
1657 case CXD2880_DVBT2_G1_32:
1658 c->guard_interval = GUARD_INTERVAL_1_32;
1660 case CXD2880_DVBT2_G1_16:
1661 c->guard_interval = GUARD_INTERVAL_1_16;
1663 case CXD2880_DVBT2_G1_8:
1664 c->guard_interval = GUARD_INTERVAL_1_8;
1666 case CXD2880_DVBT2_G1_4:
1667 c->guard_interval = GUARD_INTERVAL_1_4;
1669 case CXD2880_DVBT2_G1_128:
1670 c->guard_interval = GUARD_INTERVAL_1_128;
1672 case CXD2880_DVBT2_G19_128:
1673 c->guard_interval = GUARD_INTERVAL_19_128;
1675 case CXD2880_DVBT2_G19_256:
1676 c->guard_interval = GUARD_INTERVAL_19_256;
1679 c->guard_interval = GUARD_INTERVAL_1_32;
1680 pr_debug("L1Pre guard interval is invalid %d\n",
1685 c->transmission_mode = TRANSMISSION_MODE_2K;
1686 c->guard_interval = GUARD_INTERVAL_1_32;
1687 pr_debug("L1Pre err %d\n", ret);
1690 mutex_lock(priv->spi_mutex);
1691 ret = cxd2880_tnrdmd_dvbt2_mon_code_rate(&priv->tnrdmd,
1692 CXD2880_DVBT2_PLP_DATA,
1694 mutex_unlock(priv->spi_mutex);
1697 case CXD2880_DVBT2_R1_2:
1698 c->fec_inner = FEC_1_2;
1700 case CXD2880_DVBT2_R3_5:
1701 c->fec_inner = FEC_3_5;
1703 case CXD2880_DVBT2_R2_3:
1704 c->fec_inner = FEC_2_3;
1706 case CXD2880_DVBT2_R3_4:
1707 c->fec_inner = FEC_3_4;
1709 case CXD2880_DVBT2_R4_5:
1710 c->fec_inner = FEC_4_5;
1712 case CXD2880_DVBT2_R5_6:
1713 c->fec_inner = FEC_5_6;
1716 c->fec_inner = FEC_NONE;
1717 pr_debug("CodeRate is invalid %d\n", coderate);
1721 c->fec_inner = FEC_NONE;
1722 pr_debug("CodeRate %d\n", ret);
1725 mutex_lock(priv->spi_mutex);
1726 ret = cxd2880_tnrdmd_dvbt2_mon_qam(&priv->tnrdmd,
1727 CXD2880_DVBT2_PLP_DATA,
1729 mutex_unlock(priv->spi_mutex);
1732 case CXD2880_DVBT2_QPSK:
1733 c->modulation = QPSK;
1735 case CXD2880_DVBT2_QAM16:
1736 c->modulation = QAM_16;
1738 case CXD2880_DVBT2_QAM64:
1739 c->modulation = QAM_64;
1741 case CXD2880_DVBT2_QAM256:
1742 c->modulation = QAM_256;
1745 c->modulation = QPSK;
1746 pr_debug("QAM is invalid %d\n", qam);
1750 c->modulation = QPSK;
1751 pr_debug("QAM %d\n", ret);
1754 mutex_lock(priv->spi_mutex);
1755 ret = cxd2880_tnrdmd_dvbt2_mon_spectrum_sense(&priv->tnrdmd, &sense);
1756 mutex_unlock(priv->spi_mutex);
1759 case CXD2880_TNRDMD_SPECTRUM_NORMAL:
1760 c->inversion = INVERSION_OFF;
1762 case CXD2880_TNRDMD_SPECTRUM_INV:
1763 c->inversion = INVERSION_ON;
1766 c->inversion = INVERSION_OFF;
1767 pr_debug("spectrum sense is invalid %d\n", sense);
1771 c->inversion = INVERSION_OFF;
1772 pr_debug("SpectrumSense %d\n", ret);
1775 mutex_lock(priv->spi_mutex);
1776 ret = cxd2880_tnrdmd_mon_rf_lvl(&priv->tnrdmd, &strength);
1777 mutex_unlock(priv->spi_mutex);
1779 c->strength.len = 1;
1780 c->strength.stat[0].scale = FE_SCALE_DECIBEL;
1781 c->strength.stat[0].svalue = strength;
1783 c->strength.len = 1;
1784 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1785 pr_debug("mon_rf_lvl %d\n", ret);
1788 ret = cxd2880_read_snr(fe, &snr);
1791 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
1792 c->cnr.stat[0].svalue = snr;
1795 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1796 pr_debug("read_snr %d\n", ret);
1802 static int cxd2880_get_frontend(struct dvb_frontend *fe,
1803 struct dtv_frontend_properties *props)
1807 if (!fe || !props) {
1808 pr_err("invalid arg.");
1812 pr_debug("system=%d\n", fe->dtv_property_cache.delivery_system);
1813 switch (fe->dtv_property_cache.delivery_system) {
1815 ret = cxd2880_get_frontend_t(fe, props);
1818 ret = cxd2880_get_frontend_t2(fe, props);
1828 static enum dvbfe_algo cxd2880_get_frontend_algo(struct dvb_frontend *fe)
1830 return DVBFE_ALGO_HW;
1833 static struct dvb_frontend_ops cxd2880_dvbt_t2_ops = {
1835 .name = "Sony CXD2880",
1836 .frequency_min_hz = 174 * MHz,
1837 .frequency_max_hz = 862 * MHz,
1838 .frequency_stepsize_hz = 1 * kHz,
1839 .caps = FE_CAN_INVERSION_AUTO |
1854 FE_CAN_TRANSMISSION_MODE_AUTO |
1855 FE_CAN_GUARD_INTERVAL_AUTO |
1856 FE_CAN_2G_MODULATION |
1860 .delsys = { SYS_DVBT, SYS_DVBT2 },
1862 .release = cxd2880_release,
1863 .init = cxd2880_init,
1864 .sleep = cxd2880_sleep,
1865 .tune = cxd2880_tune,
1866 .set_frontend = cxd2880_set_frontend,
1867 .get_frontend = cxd2880_get_frontend,
1868 .read_status = cxd2880_read_status,
1869 .read_ber = cxd2880_read_ber,
1870 .read_signal_strength = cxd2880_read_signal_strength,
1871 .read_snr = cxd2880_read_snr,
1872 .read_ucblocks = cxd2880_read_ucblocks,
1873 .get_frontend_algo = cxd2880_get_frontend_algo,
1876 struct dvb_frontend *cxd2880_attach(struct dvb_frontend *fe,
1877 struct cxd2880_config *cfg)
1880 enum cxd2880_tnrdmd_chip_id chipid =
1881 CXD2880_TNRDMD_CHIP_ID_UNKNOWN;
1882 static struct cxd2880_priv *priv;
1886 pr_err("invalid arg.\n");
1890 priv = kzalloc(sizeof(struct cxd2880_priv), GFP_KERNEL);
1894 priv->spi = cfg->spi;
1895 priv->spi_mutex = cfg->spi_mutex;
1896 priv->spi_device.spi = cfg->spi;
1898 memcpy(&fe->ops, &cxd2880_dvbt_t2_ops,
1899 sizeof(struct dvb_frontend_ops));
1901 ret = cxd2880_spi_device_initialize(&priv->spi_device,
1905 pr_err("spi_device_initialize failed. %d\n", ret);
1910 ret = cxd2880_spi_device_create_spi(&priv->cxd2880_spi,
1913 pr_err("spi_device_create_spi failed. %d\n", ret);
1918 ret = cxd2880_io_spi_create(&priv->regio, &priv->cxd2880_spi, 0);
1920 pr_err("io_spi_create failed. %d\n", ret);
1924 ret = priv->regio.write_reg(&priv->regio,
1925 CXD2880_IO_TGT_SYS, 0x00, 0x00);
1927 pr_err("set bank to 0x00 failed.\n");
1931 ret = priv->regio.read_regs(&priv->regio,
1932 CXD2880_IO_TGT_SYS, 0xfd, &data, 1);
1934 pr_err("read chip id failed.\n");
1939 chipid = (enum cxd2880_tnrdmd_chip_id)data;
1940 if (chipid != CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_0X &&
1941 chipid != CXD2880_TNRDMD_CHIP_ID_CXD2880_ES1_11) {
1942 pr_err("chip id invalid.\n");
1947 fe->demodulator_priv = priv;
1948 pr_info("CXD2880 driver version: Ver %s\n",
1949 CXD2880_TNRDMD_DRIVER_VERSION);
1953 EXPORT_SYMBOL_GPL(cxd2880_attach);
1955 MODULE_DESCRIPTION("Sony CXD2880 DVB-T2/T tuner + demod driver");
1956 MODULE_AUTHOR("Sony Semiconductor Solutions Corporation");
1957 MODULE_LICENSE("GPL v2");