1 // SPDX-License-Identifier: GPL-2.0
3 * cxd2880_tnrdmd_dvbt2.c
4 * Sony CXD2880 DVB-T2/T tuner + demodulator driver
5 * control functions for DVB-T2
7 * Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
10 #include <media/dvb_frontend.h>
12 #include "cxd2880_tnrdmd_dvbt2.h"
13 #include "cxd2880_tnrdmd_dvbt2_mon.h"
15 static const struct cxd2880_reg_value tune_dmd_setting_seq1[] = {
16 {0x00, 0x00}, {0x31, 0x02},
19 static const struct cxd2880_reg_value tune_dmd_setting_seq2[] = {
20 {0x00, 0x04}, {0x5d, 0x0b},
23 static int x_tune_dvbt2_demod_setting(struct cxd2880_tnrdmd
25 enum cxd2880_dtv_bandwidth
27 enum cxd2880_tnrdmd_clockmode
30 static const u8 tsif_settings[2] = { 0x01, 0x01 };
31 static const u8 init_settings[14] = {
32 0x07, 0x06, 0x01, 0xf0, 0x00, 0x00, 0x04, 0xb0, 0x00, 0x00,
33 0x09, 0x9c, 0x0e, 0x4c
35 static const u8 clk_mode_settings_a1[9] = {
36 0x52, 0x49, 0x2c, 0x51, 0x51, 0x3d, 0x15, 0x29, 0x0c
39 static const u8 clk_mode_settings_b1[9] = {
40 0x5d, 0x55, 0x32, 0x5c, 0x5c, 0x45, 0x17, 0x2e, 0x0d
43 static const u8 clk_mode_settings_c1[9] = {
44 0x60, 0x00, 0x34, 0x5e, 0x5e, 0x47, 0x18, 0x2f, 0x0e
47 static const u8 clk_mode_settings_a2[13] = {
48 0x04, 0xe7, 0x94, 0x92, 0x09, 0xcf, 0x7e, 0xd0, 0x49,
49 0xcd, 0xcd, 0x1f, 0x5b
52 static const u8 clk_mode_settings_b2[13] = {
53 0x05, 0x90, 0x27, 0x55, 0x0b, 0x20, 0x8f, 0xd6, 0xea,
54 0xc8, 0xc8, 0x23, 0x91
57 static const u8 clk_mode_settings_c2[13] = {
58 0x05, 0xb8, 0xd8, 0x00, 0x0b, 0x72, 0x93, 0xf3, 0x00,
59 0xcd, 0xcd, 0x24, 0x95
62 static const u8 clk_mode_settings_a3[5] = {
63 0x0b, 0x6a, 0xc9, 0x03, 0x33
65 static const u8 clk_mode_settings_b3[5] = {
66 0x01, 0x02, 0xe4, 0x03, 0x39
68 static const u8 clk_mode_settings_c3[5] = {
69 0x01, 0x02, 0xeb, 0x03, 0x3b
72 static const u8 gtdofst[2] = { 0x3f, 0xff };
74 static const u8 bw8_gtdofst_a[2] = { 0x19, 0xd2 };
75 static const u8 bw8_nomi_ac[6] = { 0x15, 0x00, 0x00, 0x00, 0x00, 0x00 };
76 static const u8 bw8_nomi_b[6] = { 0x14, 0x6a, 0xaa, 0xaa, 0xab, 0x00 };
77 static const u8 bw8_sst_a[2] = { 0x06, 0x2a };
78 static const u8 bw8_sst_b[2] = { 0x06, 0x29 };
79 static const u8 bw8_sst_c[2] = { 0x06, 0x28 };
80 static const u8 bw8_mrc_a[9] = {
81 0x28, 0x00, 0x50, 0x00, 0x60, 0x00, 0x00, 0x90, 0x00
83 static const u8 bw8_mrc_b[9] = {
84 0x2d, 0x5e, 0x5a, 0xbd, 0x6c, 0xe3, 0x00, 0xa3, 0x55
86 static const u8 bw8_mrc_c[9] = {
87 0x2e, 0xaa, 0x5d, 0x55, 0x70, 0x00, 0x00, 0xa8, 0x00
90 static const u8 bw7_nomi_ac[6] = { 0x18, 0x00, 0x00, 0x00, 0x00, 0x00 };
91 static const u8 bw7_nomi_b[6] = { 0x17, 0x55, 0x55, 0x55, 0x55, 0x00 };
92 static const u8 bw7_sst_a[2] = { 0x06, 0x23 };
93 static const u8 bw7_sst_b[2] = { 0x06, 0x22 };
94 static const u8 bw7_sst_c[2] = { 0x06, 0x21 };
95 static const u8 bw7_mrc_a[9] = {
96 0x2d, 0xb6, 0x5b, 0x6d, 0x6d, 0xb6, 0x00, 0xa4, 0x92
98 static const u8 bw7_mrc_b[9] = {
99 0x33, 0xda, 0x67, 0xb4, 0x7c, 0x71, 0x00, 0xba, 0xaa
101 static const u8 bw7_mrc_c[9] = {
102 0x35, 0x55, 0x6a, 0xaa, 0x80, 0x00, 0x00, 0xc0, 0x00
105 static const u8 bw6_nomi_ac[6] = { 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00 };
106 static const u8 bw6_nomi_b[6] = { 0x1b, 0x38, 0xe3, 0x8e, 0x39, 0x00 };
107 static const u8 bw6_sst_a[2] = { 0x06, 0x1c };
108 static const u8 bw6_sst_b[2] = { 0x06, 0x1b };
109 static const u8 bw6_sst_c[2] = { 0x06, 0x1a };
110 static const u8 bw6_mrc_a[9] = {
111 0x35, 0x55, 0x6a, 0xaa, 0x80, 0x00, 0x00, 0xc0, 0x00
113 static const u8 bw6_mrc_b[9] = {
114 0x3c, 0x7e, 0x78, 0xfc, 0x91, 0x2f, 0x00, 0xd9, 0xc7
116 static const u8 bw6_mrc_c[9] = {
117 0x3e, 0x38, 0x7c, 0x71, 0x95, 0x55, 0x00, 0xdf, 0xff
120 static const u8 bw5_nomi_ac[6] = { 0x21, 0x99, 0x99, 0x99, 0x9a, 0x00 };
121 static const u8 bw5_nomi_b[6] = { 0x20, 0xaa, 0xaa, 0xaa, 0xab, 0x00 };
122 static const u8 bw5_sst_a[2] = { 0x06, 0x15 };
123 static const u8 bw5_sst_b[2] = { 0x06, 0x15 };
124 static const u8 bw5_sst_c[2] = { 0x06, 0x14 };
125 static const u8 bw5_mrc_a[9] = {
126 0x40, 0x00, 0x6a, 0xaa, 0x80, 0x00, 0x00, 0xe6, 0x66
128 static const u8 bw5_mrc_b[9] = {
129 0x48, 0x97, 0x78, 0xfc, 0x91, 0x2f, 0x01, 0x05, 0x55
131 static const u8 bw5_mrc_c[9] = {
132 0x4a, 0xaa, 0x7c, 0x71, 0x95, 0x55, 0x01, 0x0c, 0xcc
135 static const u8 bw1_7_nomi_a[6] = {
136 0x68, 0x0f, 0xa2, 0x32, 0xcf, 0x03
138 static const u8 bw1_7_nomi_c[6] = {
139 0x68, 0x0f, 0xa2, 0x32, 0xcf, 0x03
141 static const u8 bw1_7_nomi_b[6] = {
142 0x65, 0x2b, 0xa4, 0xcd, 0xd8, 0x03
144 static const u8 bw1_7_sst_a[2] = { 0x06, 0x0c };
145 static const u8 bw1_7_sst_b[2] = { 0x06, 0x0c };
146 static const u8 bw1_7_sst_c[2] = { 0x06, 0x0b };
147 static const u8 bw1_7_mrc_a[9] = {
148 0x40, 0x00, 0x6a, 0xaa, 0x80, 0x00, 0x02, 0xc9, 0x8f
150 static const u8 bw1_7_mrc_b[9] = {
151 0x48, 0x97, 0x78, 0xfc, 0x91, 0x2f, 0x03, 0x29, 0x5d
153 static const u8 bw1_7_mrc_c[9] = {
154 0x4a, 0xaa, 0x7c, 0x71, 0x95, 0x55, 0x03, 0x40, 0x7d
157 const u8 *data = NULL;
158 const u8 *data2 = NULL;
159 const u8 *data3 = NULL;
165 ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
167 tune_dmd_setting_seq1,
168 ARRAY_SIZE(tune_dmd_setting_seq1));
172 ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
174 tune_dmd_setting_seq2,
175 ARRAY_SIZE(tune_dmd_setting_seq2));
179 if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_SUB) {
180 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
186 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
188 0xce, tsif_settings, 2);
193 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
199 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
201 0x8a, init_settings[0]);
205 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
207 0x90, init_settings[1]);
211 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
217 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
219 0xf0, &init_settings[2], 2);
223 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
229 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
231 0xdc, init_settings[4]);
235 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
237 0xde, init_settings[5]);
241 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
247 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
249 0x73, &init_settings[6], 4);
253 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
255 0x8f, &init_settings[10], 4);
260 case CXD2880_TNRDMD_CLOCKMODE_A:
261 data = clk_mode_settings_a1;
262 data2 = clk_mode_settings_a2;
263 data3 = clk_mode_settings_a3;
265 case CXD2880_TNRDMD_CLOCKMODE_B:
266 data = clk_mode_settings_b1;
267 data2 = clk_mode_settings_b2;
268 data3 = clk_mode_settings_b3;
270 case CXD2880_TNRDMD_CLOCKMODE_C:
271 data = clk_mode_settings_c1;
272 data2 = clk_mode_settings_c2;
273 data3 = clk_mode_settings_c3;
279 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
285 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
291 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
297 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
303 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
309 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
315 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
321 if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_SUB) {
322 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
328 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
335 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
341 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
348 case CXD2880_DTV_BW_8_MHZ:
350 case CXD2880_TNRDMD_CLOCKMODE_A:
351 case CXD2880_TNRDMD_CLOCKMODE_C:
354 case CXD2880_TNRDMD_CLOCKMODE_B:
361 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
367 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
374 case CXD2880_TNRDMD_CLOCKMODE_A:
375 data = bw8_gtdofst_a;
377 case CXD2880_TNRDMD_CLOCKMODE_B:
378 case CXD2880_TNRDMD_CLOCKMODE_C:
385 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
392 case CXD2880_TNRDMD_CLOCKMODE_A:
395 case CXD2880_TNRDMD_CLOCKMODE_B:
398 case CXD2880_TNRDMD_CLOCKMODE_C:
405 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
411 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
413 case CXD2880_TNRDMD_CLOCKMODE_A:
416 case CXD2880_TNRDMD_CLOCKMODE_B:
419 case CXD2880_TNRDMD_CLOCKMODE_C:
426 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
434 case CXD2880_DTV_BW_7_MHZ:
436 case CXD2880_TNRDMD_CLOCKMODE_A:
437 case CXD2880_TNRDMD_CLOCKMODE_C:
440 case CXD2880_TNRDMD_CLOCKMODE_B:
447 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
453 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
459 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
466 case CXD2880_TNRDMD_CLOCKMODE_A:
469 case CXD2880_TNRDMD_CLOCKMODE_B:
472 case CXD2880_TNRDMD_CLOCKMODE_C:
479 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
485 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
487 case CXD2880_TNRDMD_CLOCKMODE_A:
490 case CXD2880_TNRDMD_CLOCKMODE_B:
493 case CXD2880_TNRDMD_CLOCKMODE_C:
500 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
508 case CXD2880_DTV_BW_6_MHZ:
510 case CXD2880_TNRDMD_CLOCKMODE_A:
511 case CXD2880_TNRDMD_CLOCKMODE_C:
514 case CXD2880_TNRDMD_CLOCKMODE_B:
521 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
527 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
533 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
540 case CXD2880_TNRDMD_CLOCKMODE_A:
543 case CXD2880_TNRDMD_CLOCKMODE_B:
546 case CXD2880_TNRDMD_CLOCKMODE_C:
553 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
559 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
561 case CXD2880_TNRDMD_CLOCKMODE_A:
564 case CXD2880_TNRDMD_CLOCKMODE_B:
567 case CXD2880_TNRDMD_CLOCKMODE_C:
574 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
582 case CXD2880_DTV_BW_5_MHZ:
584 case CXD2880_TNRDMD_CLOCKMODE_A:
585 case CXD2880_TNRDMD_CLOCKMODE_C:
588 case CXD2880_TNRDMD_CLOCKMODE_B:
595 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
601 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
607 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
614 case CXD2880_TNRDMD_CLOCKMODE_A:
617 case CXD2880_TNRDMD_CLOCKMODE_B:
620 case CXD2880_TNRDMD_CLOCKMODE_C:
627 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
633 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
635 case CXD2880_TNRDMD_CLOCKMODE_A:
638 case CXD2880_TNRDMD_CLOCKMODE_B:
641 case CXD2880_TNRDMD_CLOCKMODE_C:
648 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
656 case CXD2880_DTV_BW_1_7_MHZ:
659 case CXD2880_TNRDMD_CLOCKMODE_A:
662 case CXD2880_TNRDMD_CLOCKMODE_C:
665 case CXD2880_TNRDMD_CLOCKMODE_B:
672 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
678 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
684 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
691 case CXD2880_TNRDMD_CLOCKMODE_A:
694 case CXD2880_TNRDMD_CLOCKMODE_B:
697 case CXD2880_TNRDMD_CLOCKMODE_C:
704 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
710 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
712 case CXD2880_TNRDMD_CLOCKMODE_A:
715 case CXD2880_TNRDMD_CLOCKMODE_B:
718 case CXD2880_TNRDMD_CLOCKMODE_C:
725 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
737 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
743 return tnr_dmd->io->write_reg(tnr_dmd->io,
748 static int x_sleep_dvbt2_demod_setting(struct cxd2880_tnrdmd
751 static const u8 difint_clip[] = {
752 0, 1, 0, 2, 0, 4, 0, 8, 0, 16, 0, 32
759 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
760 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
766 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
768 0x47, difint_clip, 12);
774 static int dvbt2_set_profile(struct cxd2880_tnrdmd *tnr_dmd,
775 enum cxd2880_dvbt2_profile profile)
777 u8 t2_mode_tune_mode = 0;
778 u8 seq_not2_dtime = 0;
786 switch (tnr_dmd->clk_mode) {
787 case CXD2880_TNRDMD_CLOCKMODE_A:
791 case CXD2880_TNRDMD_CLOCKMODE_B:
795 case CXD2880_TNRDMD_CLOCKMODE_C:
804 case CXD2880_DVBT2_PROFILE_BASE:
805 t2_mode_tune_mode = 0x01;
806 seq_not2_dtime = dtime2;
809 case CXD2880_DVBT2_PROFILE_LITE:
810 t2_mode_tune_mode = 0x05;
811 seq_not2_dtime = dtime1;
814 case CXD2880_DVBT2_PROFILE_ANY:
815 t2_mode_tune_mode = 0x00;
816 seq_not2_dtime = dtime1;
823 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
829 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
831 0x10, t2_mode_tune_mode);
835 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
841 return tnr_dmd->io->write_reg(tnr_dmd->io,
843 0x2c, seq_not2_dtime);
846 int cxd2880_tnrdmd_dvbt2_tune1(struct cxd2880_tnrdmd *tnr_dmd,
847 struct cxd2880_dvbt2_tune_param
852 if (!tnr_dmd || !tune_param)
855 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
858 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
859 tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
862 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN &&
863 tune_param->profile == CXD2880_DVBT2_PROFILE_ANY)
867 cxd2880_tnrdmd_common_tune_setting1(tnr_dmd, CXD2880_DTV_SYS_DVBT2,
868 tune_param->center_freq_khz,
869 tune_param->bandwidth, 0, 0);
874 x_tune_dvbt2_demod_setting(tnr_dmd, tune_param->bandwidth,
879 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
881 x_tune_dvbt2_demod_setting(tnr_dmd->diver_sub,
882 tune_param->bandwidth,
883 tnr_dmd->diver_sub->clk_mode);
888 ret = dvbt2_set_profile(tnr_dmd, tune_param->profile);
892 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
894 dvbt2_set_profile(tnr_dmd->diver_sub, tune_param->profile);
899 if (tune_param->data_plp_id == CXD2880_DVBT2_TUNE_PARAM_PLPID_AUTO)
900 ret = cxd2880_tnrdmd_dvbt2_set_plp_cfg(tnr_dmd, 1, 0);
903 cxd2880_tnrdmd_dvbt2_set_plp_cfg(tnr_dmd, 0,
904 (u8)(tune_param->data_plp_id));
909 int cxd2880_tnrdmd_dvbt2_tune2(struct cxd2880_tnrdmd *tnr_dmd,
910 struct cxd2880_dvbt2_tune_param
913 u8 en_fef_intmtnt_ctrl = 1;
916 if (!tnr_dmd || !tune_param)
919 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
922 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
923 tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
926 switch (tune_param->profile) {
927 case CXD2880_DVBT2_PROFILE_BASE:
928 en_fef_intmtnt_ctrl = tnr_dmd->en_fef_intmtnt_base;
930 case CXD2880_DVBT2_PROFILE_LITE:
931 en_fef_intmtnt_ctrl = tnr_dmd->en_fef_intmtnt_lite;
933 case CXD2880_DVBT2_PROFILE_ANY:
934 if (tnr_dmd->en_fef_intmtnt_base &&
935 tnr_dmd->en_fef_intmtnt_lite)
936 en_fef_intmtnt_ctrl = 1;
938 en_fef_intmtnt_ctrl = 0;
945 cxd2880_tnrdmd_common_tune_setting2(tnr_dmd,
946 CXD2880_DTV_SYS_DVBT2,
947 en_fef_intmtnt_ctrl);
951 tnr_dmd->state = CXD2880_TNRDMD_STATE_ACTIVE;
952 tnr_dmd->frequency_khz = tune_param->center_freq_khz;
953 tnr_dmd->sys = CXD2880_DTV_SYS_DVBT2;
954 tnr_dmd->bandwidth = tune_param->bandwidth;
956 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
957 tnr_dmd->diver_sub->state = CXD2880_TNRDMD_STATE_ACTIVE;
958 tnr_dmd->diver_sub->frequency_khz = tune_param->center_freq_khz;
959 tnr_dmd->diver_sub->sys = CXD2880_DTV_SYS_DVBT2;
960 tnr_dmd->diver_sub->bandwidth = tune_param->bandwidth;
966 int cxd2880_tnrdmd_dvbt2_sleep_setting(struct cxd2880_tnrdmd
974 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
977 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
978 tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
981 ret = x_sleep_dvbt2_demod_setting(tnr_dmd);
985 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
986 ret = x_sleep_dvbt2_demod_setting(tnr_dmd->diver_sub);
991 int cxd2880_tnrdmd_dvbt2_check_demod_lock(struct cxd2880_tnrdmd
994 cxd2880_tnrdmd_lock_result
1001 u8 unlock_detected = 0;
1002 u8 unlock_detected_sub = 0;
1004 if (!tnr_dmd || !lock)
1007 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
1010 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
1014 cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_stat, &ts_lock,
1019 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
1021 *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
1022 else if (unlock_detected)
1023 *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
1025 *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
1030 if (sync_stat == 6) {
1031 *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
1036 cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub(tnr_dmd, &sync_stat,
1037 &unlock_detected_sub);
1042 *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
1043 else if (unlock_detected && unlock_detected_sub)
1044 *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
1046 *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
1051 int cxd2880_tnrdmd_dvbt2_check_ts_lock(struct cxd2880_tnrdmd
1054 cxd2880_tnrdmd_lock_result
1061 u8 unlock_detected = 0;
1062 u8 unlock_detected_sub = 0;
1064 if (!tnr_dmd || !lock)
1067 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
1070 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
1074 cxd2880_tnrdmd_dvbt2_mon_sync_stat(tnr_dmd, &sync_stat, &ts_lock,
1079 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
1081 *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
1082 else if (unlock_detected)
1083 *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
1085 *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
1091 *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
1093 } else if (!unlock_detected) {
1094 *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
1099 cxd2880_tnrdmd_dvbt2_mon_sync_stat_sub(tnr_dmd, &sync_stat,
1100 &unlock_detected_sub);
1104 if (unlock_detected && unlock_detected_sub)
1105 *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
1107 *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
1112 int cxd2880_tnrdmd_dvbt2_set_plp_cfg(struct cxd2880_tnrdmd
1113 *tnr_dmd, u8 auto_plp,
1121 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
1124 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
1125 tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
1128 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
1135 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
1142 return tnr_dmd->io->write_reg(tnr_dmd->io,
1144 0xad, auto_plp ? 0x00 : 0x01);
1147 int cxd2880_tnrdmd_dvbt2_diver_fef_setting(struct cxd2880_tnrdmd
1150 struct cxd2880_dvbt2_ofdm ofdm;
1151 static const u8 data[] = { 0, 8, 0, 16, 0, 32, 0, 64, 0, 128, 1, 0};
1157 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
1160 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
1163 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE)
1166 ret = cxd2880_tnrdmd_dvbt2_mon_ofdm(tnr_dmd, &ofdm);
1173 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
1179 return tnr_dmd->io->write_regs(tnr_dmd->io,
1184 int cxd2880_tnrdmd_dvbt2_check_l1post_valid(struct cxd2880_tnrdmd
1192 if (!tnr_dmd || !l1_post_valid)
1195 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
1198 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
1199 tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
1202 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
1208 ret = tnr_dmd->io->read_regs(tnr_dmd->io,
1214 *l1_post_valid = data & 0x01;