1 // SPDX-License-Identifier: GPL-2.0
3 * cxd2880_tnrdmd_dvbt.c
4 * Sony CXD2880 DVB-T2/T tuner + demodulator driver
5 * control functions for DVB-T
7 * Copyright (C) 2016, 2017, 2018 Sony Semiconductor Solutions Corporation
10 #include <media/dvb_frontend.h>
12 #include "cxd2880_tnrdmd_dvbt.h"
13 #include "cxd2880_tnrdmd_dvbt_mon.h"
15 static const struct cxd2880_reg_value tune_dmd_setting_seq1[] = {
16 {0x00, 0x00}, {0x31, 0x01},
19 static const struct cxd2880_reg_value tune_dmd_setting_seq2[] = {
20 {0x00, 0x04}, {0x5c, 0xfb}, {0x00, 0x10}, {0xa4, 0x03},
21 {0x00, 0x14}, {0xb0, 0x00}, {0x00, 0x25},
24 static const struct cxd2880_reg_value tune_dmd_setting_seq3[] = {
25 {0x00, 0x12}, {0x44, 0x00},
28 static const struct cxd2880_reg_value tune_dmd_setting_seq4[] = {
29 {0x00, 0x11}, {0x87, 0xd2},
32 static const struct cxd2880_reg_value tune_dmd_setting_seq5[] = {
33 {0x00, 0x00}, {0xfd, 0x01},
36 static const struct cxd2880_reg_value sleep_dmd_setting_seq1[] = {
37 {0x00, 0x04}, {0x5c, 0xd8}, {0x00, 0x10}, {0xa4, 0x00},
40 static const struct cxd2880_reg_value sleep_dmd_setting_seq2[] = {
41 {0x00, 0x11}, {0x87, 0x04},
44 static int x_tune_dvbt_demod_setting(struct cxd2880_tnrdmd
46 enum cxd2880_dtv_bandwidth
48 enum cxd2880_tnrdmd_clockmode
51 static const u8 clk_mode_ckffrq_a[2] = { 0x52, 0x49 };
52 static const u8 clk_mode_ckffrq_b[2] = { 0x5d, 0x55 };
53 static const u8 clk_mode_ckffrq_c[2] = { 0x60, 0x00 };
54 static const u8 ratectl_margin[2] = { 0x01, 0xf0 };
55 static const u8 maxclkcnt_a[3] = { 0x73, 0xca, 0x49 };
56 static const u8 maxclkcnt_b[3] = { 0xc8, 0x13, 0xaa };
57 static const u8 maxclkcnt_c[3] = { 0xdc, 0x6c, 0x00 };
59 static const u8 bw8_nomi_ac[5] = { 0x15, 0x00, 0x00, 0x00, 0x00};
60 static const u8 bw8_nomi_b[5] = { 0x14, 0x6a, 0xaa, 0xaa, 0xaa};
61 static const u8 bw8_gtdofst_a[2] = { 0x01, 0x28 };
62 static const u8 bw8_gtdofst_b[2] = { 0x11, 0x44 };
63 static const u8 bw8_gtdofst_c[2] = { 0x15, 0x28 };
64 static const u8 bw8_mrc_a[5] = { 0x30, 0x00, 0x00, 0x90, 0x00 };
65 static const u8 bw8_mrc_b[5] = { 0x36, 0x71, 0x00, 0xa3, 0x55 };
66 static const u8 bw8_mrc_c[5] = { 0x38, 0x00, 0x00, 0xa8, 0x00 };
67 static const u8 bw8_notch[4] = { 0xb3, 0x00, 0x01, 0x02 };
69 static const u8 bw7_nomi_ac[5] = { 0x18, 0x00, 0x00, 0x00, 0x00};
70 static const u8 bw7_nomi_b[5] = { 0x17, 0x55, 0x55, 0x55, 0x55};
71 static const u8 bw7_gtdofst_a[2] = { 0x12, 0x4c };
72 static const u8 bw7_gtdofst_b[2] = { 0x1f, 0x15 };
73 static const u8 bw7_gtdofst_c[2] = { 0x1f, 0xf8 };
74 static const u8 bw7_mrc_a[5] = { 0x36, 0xdb, 0x00, 0xa4, 0x92 };
75 static const u8 bw7_mrc_b[5] = { 0x3e, 0x38, 0x00, 0xba, 0xaa };
76 static const u8 bw7_mrc_c[5] = { 0x40, 0x00, 0x00, 0xc0, 0x00 };
77 static const u8 bw7_notch[4] = { 0xb8, 0x00, 0x00, 0x03 };
79 static const u8 bw6_nomi_ac[5] = { 0x1c, 0x00, 0x00, 0x00, 0x00};
80 static const u8 bw6_nomi_b[5] = { 0x1b, 0x38, 0xe3, 0x8e, 0x38};
81 static const u8 bw6_gtdofst_a[2] = { 0x1f, 0xf8 };
82 static const u8 bw6_gtdofst_b[2] = { 0x24, 0x43 };
83 static const u8 bw6_gtdofst_c[2] = { 0x25, 0x4c };
84 static const u8 bw6_mrc_a[5] = { 0x40, 0x00, 0x00, 0xc0, 0x00 };
85 static const u8 bw6_mrc_b[5] = { 0x48, 0x97, 0x00, 0xd9, 0xc7 };
86 static const u8 bw6_mrc_c[5] = { 0x4a, 0xaa, 0x00, 0xdf, 0xff };
87 static const u8 bw6_notch[4] = { 0xbe, 0xab, 0x00, 0x03 };
89 static const u8 bw5_nomi_ac[5] = { 0x21, 0x99, 0x99, 0x99, 0x99};
90 static const u8 bw5_nomi_b[5] = { 0x20, 0xaa, 0xaa, 0xaa, 0xaa};
91 static const u8 bw5_gtdofst_a[2] = { 0x26, 0x5d };
92 static const u8 bw5_gtdofst_b[2] = { 0x2b, 0x84 };
93 static const u8 bw5_gtdofst_c[2] = { 0x2c, 0xc2 };
94 static const u8 bw5_mrc_a[5] = { 0x4c, 0xcc, 0x00, 0xe6, 0x66 };
95 static const u8 bw5_mrc_b[5] = { 0x57, 0x1c, 0x01, 0x05, 0x55 };
96 static const u8 bw5_mrc_c[5] = { 0x59, 0x99, 0x01, 0x0c, 0xcc };
97 static const u8 bw5_notch[4] = { 0xc8, 0x01, 0x00, 0x03 };
98 const u8 *data = NULL;
105 ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
107 tune_dmd_setting_seq1,
108 ARRAY_SIZE(tune_dmd_setting_seq1));
112 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
119 case CXD2880_TNRDMD_CLOCKMODE_A:
120 data = clk_mode_ckffrq_a;
122 case CXD2880_TNRDMD_CLOCKMODE_B:
123 data = clk_mode_ckffrq_b;
125 case CXD2880_TNRDMD_CLOCKMODE_C:
126 data = clk_mode_ckffrq_c;
132 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
138 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
144 if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_SUB) {
145 u8 data[2] = { 0x01, 0x01 };
147 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
153 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
160 ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
162 tune_dmd_setting_seq2,
163 ARRAY_SIZE(tune_dmd_setting_seq2));
167 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
169 0xf0, ratectl_margin, 2);
173 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN ||
174 tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB) {
175 ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
177 tune_dmd_setting_seq3,
178 ARRAY_SIZE(tune_dmd_setting_seq3));
183 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB) {
184 ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
186 tune_dmd_setting_seq4,
187 ARRAY_SIZE(tune_dmd_setting_seq4));
192 if (tnr_dmd->diver_mode != CXD2880_TNRDMD_DIVERMODE_SUB) {
193 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
200 case CXD2880_TNRDMD_CLOCKMODE_A:
203 case CXD2880_TNRDMD_CLOCKMODE_B:
206 case CXD2880_TNRDMD_CLOCKMODE_C:
213 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
220 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
227 case CXD2880_DTV_BW_8_MHZ:
229 case CXD2880_TNRDMD_CLOCKMODE_A:
230 case CXD2880_TNRDMD_CLOCKMODE_C:
233 case CXD2880_TNRDMD_CLOCKMODE_B:
240 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
246 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
253 case CXD2880_TNRDMD_CLOCKMODE_A:
254 data = bw8_gtdofst_a;
256 case CXD2880_TNRDMD_CLOCKMODE_B:
257 data = bw8_gtdofst_b;
259 case CXD2880_TNRDMD_CLOCKMODE_C:
260 data = bw8_gtdofst_c;
266 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
273 case CXD2880_TNRDMD_CLOCKMODE_A:
274 case CXD2880_TNRDMD_CLOCKMODE_B:
277 case CXD2880_TNRDMD_CLOCKMODE_C:
284 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
290 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
292 case CXD2880_TNRDMD_CLOCKMODE_A:
295 case CXD2880_TNRDMD_CLOCKMODE_B:
298 case CXD2880_TNRDMD_CLOCKMODE_C:
305 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
311 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
318 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
320 0x72, &bw8_notch[0], 2);
324 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
326 0x6b, &bw8_notch[2], 2);
331 case CXD2880_DTV_BW_7_MHZ:
333 case CXD2880_TNRDMD_CLOCKMODE_A:
334 case CXD2880_TNRDMD_CLOCKMODE_C:
337 case CXD2880_TNRDMD_CLOCKMODE_B:
344 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
350 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
357 case CXD2880_TNRDMD_CLOCKMODE_A:
358 data = bw7_gtdofst_a;
360 case CXD2880_TNRDMD_CLOCKMODE_B:
361 data = bw7_gtdofst_b;
363 case CXD2880_TNRDMD_CLOCKMODE_C:
364 data = bw7_gtdofst_c;
370 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
377 case CXD2880_TNRDMD_CLOCKMODE_A:
378 case CXD2880_TNRDMD_CLOCKMODE_B:
381 case CXD2880_TNRDMD_CLOCKMODE_C:
388 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
394 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
396 case CXD2880_TNRDMD_CLOCKMODE_A:
399 case CXD2880_TNRDMD_CLOCKMODE_B:
402 case CXD2880_TNRDMD_CLOCKMODE_C:
409 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
415 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
422 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
424 0x72, &bw7_notch[0], 2);
428 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
430 0x6b, &bw7_notch[2], 2);
435 case CXD2880_DTV_BW_6_MHZ:
437 case CXD2880_TNRDMD_CLOCKMODE_A:
438 case CXD2880_TNRDMD_CLOCKMODE_C:
441 case CXD2880_TNRDMD_CLOCKMODE_B:
448 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
454 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
461 case CXD2880_TNRDMD_CLOCKMODE_A:
462 data = bw6_gtdofst_a;
464 case CXD2880_TNRDMD_CLOCKMODE_B:
465 data = bw6_gtdofst_b;
467 case CXD2880_TNRDMD_CLOCKMODE_C:
468 data = bw6_gtdofst_c;
474 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
481 case CXD2880_TNRDMD_CLOCKMODE_A:
482 case CXD2880_TNRDMD_CLOCKMODE_C:
485 case CXD2880_TNRDMD_CLOCKMODE_B:
492 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
498 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
500 case CXD2880_TNRDMD_CLOCKMODE_A:
503 case CXD2880_TNRDMD_CLOCKMODE_B:
506 case CXD2880_TNRDMD_CLOCKMODE_C:
513 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
519 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
526 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
528 0x72, &bw6_notch[0], 2);
532 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
534 0x6b, &bw6_notch[2], 2);
539 case CXD2880_DTV_BW_5_MHZ:
541 case CXD2880_TNRDMD_CLOCKMODE_A:
542 case CXD2880_TNRDMD_CLOCKMODE_C:
545 case CXD2880_TNRDMD_CLOCKMODE_B:
552 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
558 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
565 case CXD2880_TNRDMD_CLOCKMODE_A:
566 data = bw5_gtdofst_a;
568 case CXD2880_TNRDMD_CLOCKMODE_B:
569 data = bw5_gtdofst_b;
571 case CXD2880_TNRDMD_CLOCKMODE_C:
572 data = bw5_gtdofst_c;
578 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
585 case CXD2880_TNRDMD_CLOCKMODE_A:
586 case CXD2880_TNRDMD_CLOCKMODE_B:
589 case CXD2880_TNRDMD_CLOCKMODE_C:
596 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
602 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
604 case CXD2880_TNRDMD_CLOCKMODE_A:
607 case CXD2880_TNRDMD_CLOCKMODE_B:
610 case CXD2880_TNRDMD_CLOCKMODE_C:
617 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
623 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
630 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
632 0x72, &bw5_notch[0], 2);
636 ret = tnr_dmd->io->write_regs(tnr_dmd->io,
638 0x6b, &bw5_notch[2], 2);
647 return cxd2880_io_write_multi_regs(tnr_dmd->io,
649 tune_dmd_setting_seq5,
650 ARRAY_SIZE(tune_dmd_setting_seq5));
653 static int x_sleep_dvbt_demod_setting(struct cxd2880_tnrdmd
661 ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
663 sleep_dmd_setting_seq1,
664 ARRAY_SIZE(sleep_dmd_setting_seq1));
668 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
669 ret = cxd2880_io_write_multi_regs(tnr_dmd->io,
671 sleep_dmd_setting_seq2,
672 ARRAY_SIZE(sleep_dmd_setting_seq2));
677 static int dvbt_set_profile(struct cxd2880_tnrdmd *tnr_dmd,
678 enum cxd2880_dvbt_profile profile)
685 ret = tnr_dmd->io->write_reg(tnr_dmd->io,
691 return tnr_dmd->io->write_reg(tnr_dmd->io,
694 (profile == CXD2880_DVBT_PROFILE_HP)
698 int cxd2880_tnrdmd_dvbt_tune1(struct cxd2880_tnrdmd *tnr_dmd,
699 struct cxd2880_dvbt_tune_param
704 if (!tnr_dmd || !tune_param)
707 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
710 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
711 tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
715 cxd2880_tnrdmd_common_tune_setting1(tnr_dmd, CXD2880_DTV_SYS_DVBT,
716 tune_param->center_freq_khz,
717 tune_param->bandwidth, 0, 0);
722 x_tune_dvbt_demod_setting(tnr_dmd, tune_param->bandwidth,
727 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
729 x_tune_dvbt_demod_setting(tnr_dmd->diver_sub,
730 tune_param->bandwidth,
731 tnr_dmd->diver_sub->clk_mode);
736 return dvbt_set_profile(tnr_dmd, tune_param->profile);
739 int cxd2880_tnrdmd_dvbt_tune2(struct cxd2880_tnrdmd *tnr_dmd,
740 struct cxd2880_dvbt_tune_param
745 if (!tnr_dmd || !tune_param)
748 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
751 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
752 tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
756 cxd2880_tnrdmd_common_tune_setting2(tnr_dmd, CXD2880_DTV_SYS_DVBT,
761 tnr_dmd->state = CXD2880_TNRDMD_STATE_ACTIVE;
762 tnr_dmd->frequency_khz = tune_param->center_freq_khz;
763 tnr_dmd->sys = CXD2880_DTV_SYS_DVBT;
764 tnr_dmd->bandwidth = tune_param->bandwidth;
766 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN) {
767 tnr_dmd->diver_sub->state = CXD2880_TNRDMD_STATE_ACTIVE;
768 tnr_dmd->diver_sub->frequency_khz = tune_param->center_freq_khz;
769 tnr_dmd->diver_sub->sys = CXD2880_DTV_SYS_DVBT;
770 tnr_dmd->diver_sub->bandwidth = tune_param->bandwidth;
776 int cxd2880_tnrdmd_dvbt_sleep_setting(struct cxd2880_tnrdmd *tnr_dmd)
783 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
786 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_SLEEP &&
787 tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
790 ret = x_sleep_dvbt_demod_setting(tnr_dmd);
794 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_MAIN)
795 ret = x_sleep_dvbt_demod_setting(tnr_dmd->diver_sub);
800 int cxd2880_tnrdmd_dvbt_check_demod_lock(struct cxd2880_tnrdmd
803 cxd2880_tnrdmd_lock_result
810 u8 unlock_detected = 0;
811 u8 unlock_detected_sub = 0;
813 if (!tnr_dmd || !lock)
816 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
819 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
823 cxd2880_tnrdmd_dvbt_mon_sync_stat(tnr_dmd, &sync_stat, &ts_lock,
828 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
830 *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
831 else if (unlock_detected)
832 *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
834 *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
839 if (sync_stat == 6) {
840 *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
845 cxd2880_tnrdmd_dvbt_mon_sync_stat_sub(tnr_dmd, &sync_stat,
846 &unlock_detected_sub);
851 *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
852 else if (unlock_detected && unlock_detected_sub)
853 *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
855 *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
860 int cxd2880_tnrdmd_dvbt_check_ts_lock(struct cxd2880_tnrdmd
863 cxd2880_tnrdmd_lock_result
870 u8 unlock_detected = 0;
871 u8 unlock_detected_sub = 0;
873 if (!tnr_dmd || !lock)
876 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SUB)
879 if (tnr_dmd->state != CXD2880_TNRDMD_STATE_ACTIVE)
883 cxd2880_tnrdmd_dvbt_mon_sync_stat(tnr_dmd, &sync_stat, &ts_lock,
888 if (tnr_dmd->diver_mode == CXD2880_TNRDMD_DIVERMODE_SINGLE) {
890 *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
891 else if (unlock_detected)
892 *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
894 *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
900 *lock = CXD2880_TNRDMD_LOCK_RESULT_LOCKED;
902 } else if (!unlock_detected) {
903 *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;
908 cxd2880_tnrdmd_dvbt_mon_sync_stat_sub(tnr_dmd, &sync_stat,
909 &unlock_detected_sub);
913 if (unlock_detected && unlock_detected_sub)
914 *lock = CXD2880_TNRDMD_LOCK_RESULT_UNLOCKED;
916 *lock = CXD2880_TNRDMD_LOCK_RESULT_NOTDETECT;