drivers/media/dvb-frontends/cxd2841er.c

   1 /*
   2  * cxd2841er.c
   3  *
   4  * Sony digital demodulator driver for
   5  *      CXD2841ER - DVB-S/S2/T/T2/C/C2
   6  *      CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
   7  *
   8  * Copyright 2012 Sony Corporation
   9  * Copyright (C) 2014 NetUP Inc.
  10  * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
  11  * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22   */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/string.h>
  27 #include <linux/slab.h>
  28 #include <linux/bitops.h>
  29 #include <linux/math64.h>
  30 #include <linux/log2.h>
  31 #include <linux/dynamic_debug.h>
  32
  33 #include "dvb_math.h"
  34 #include "dvb_frontend.h"
  35 #include "cxd2841er.h"
  36 #include "cxd2841er_priv.h"
  37
  38 #define MAX_WRITE_REGSIZE       16
  39 #define LOG2_E_100X 144
  40
  41 #define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24))
  42
  43 /* DVB-C constellation */
  44 enum sony_dvbc_constellation_t {
  45         SONY_DVBC_CONSTELLATION_16QAM,
  46         SONY_DVBC_CONSTELLATION_32QAM,
  47         SONY_DVBC_CONSTELLATION_64QAM,
  48         SONY_DVBC_CONSTELLATION_128QAM,
  49         SONY_DVBC_CONSTELLATION_256QAM
  50 };
  51
  52 enum cxd2841er_state {
  53         STATE_SHUTDOWN = 0,
  54         STATE_SLEEP_S,
  55         STATE_ACTIVE_S,
  56         STATE_SLEEP_TC,
  57         STATE_ACTIVE_TC
  58 };
  59
  60 struct cxd2841er_priv {
  61         struct dvb_frontend             frontend;
  62         struct i2c_adapter              *i2c;
  63         u8                              i2c_addr_slvx;
  64         u8                              i2c_addr_slvt;
  65         const struct cxd2841er_config   *config;
  66         enum cxd2841er_state            state;
  67         u8                              system;
  68         enum cxd2841er_xtal             xtal;
  69         enum fe_caps caps;
  70         u32                             flags;
  71 };
  72
  73 static const struct cxd2841er_cnr_data s_cn_data[] = {
  74         { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
  75         { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
  76         { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
  77         { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
  78         { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
  79         { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
  80         { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
  81         { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
  82         { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
  83         { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
  84         { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
  85         { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
  86         { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
  87         { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
  88         { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
  89         { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
  90         { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
  91         { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
  92         { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
  93         { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
  94         { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
  95         { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
  96         { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
  97         { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
  98         { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
  99         { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
 100         { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
 101         { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
 102         { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
 103         { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
 104         { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
 105         { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
 106         { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
 107         { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
 108         { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
 109         { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
 110         { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
 111         { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
 112         { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
 113         { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
 114         { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
 115         { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
 116         { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
 117         { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
 118         { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
 119         { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
 120         { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
 121         { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 122         { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 123         { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
 124         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 125         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 126         { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
 127         { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
 128         { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
 129         { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
 130         { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
 131         { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
 132         { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
 133         { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
 134         { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
 135         { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
 136         { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
 137         { 0x0015, 19900 }, { 0x0014, 20000 },
 138 };
 139
 140 static const struct cxd2841er_cnr_data s2_cn_data[] = {
 141         { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
 142         { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
 143         { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
 144         { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
 145         { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
 146         { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
 147         { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
 148         { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
 149         { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
 150         { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
 151         { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
 152         { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
 153         { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
 154         { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
 155         { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
 156         { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
 157         { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
 158         { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
 159         { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
 160         { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
 161         { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
 162         { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
 163         { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
 164         { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
 165         { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
 166         { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
 167         { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
 168         { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
 169         { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
 170         { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
 171         { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
 172         { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
 173         { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
 174         { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
 175         { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
 176         { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
 177         { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
 178         { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
 179         { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
 180         { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
 181         { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
 182         { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
 183         { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
 184         { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
 185         { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
 186         { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
 187         { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
 188         { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 189         { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 190         { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
 191         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 192         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 193         { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
 194         { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
 195         { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
 196         { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
 197         { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
 198         { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
 199         { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
 200         { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
 201         { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
 202         { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
 203         { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
 204         { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
 205 };
 206
 207 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv);
 208 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv);
 209
 210 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
 211                                 u8 addr, u8 reg, u8 write,
 212                                 const u8 *data, u32 len)
 213 {
 214         dev_dbg(&priv->i2c->dev,
 215                 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d data %*ph\n",
 216                 (write == 0 ? "read" : "write"), addr, reg, len, len, data);
 217 }
 218
 219 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
 220                                 u8 addr, u8 reg, const u8 *data, u32 len)
 221 {
 222         int ret;
 223         u8 buf[MAX_WRITE_REGSIZE + 1];
 224         u8 i2c_addr = (addr == I2C_SLVX ?
 225                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 226         struct i2c_msg msg[1] = {
 227                 {
 228                         .addr = i2c_addr,
 229                         .flags = 0,
 230                         .len = len + 1,
 231                         .buf = buf,
 232                 }
 233         };
 234
 235         if (len + 1 >= sizeof(buf)) {
 236                 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
 237                          reg, len + 1);
 238                 return -E2BIG;
 239         }
 240
 241         cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
 242         buf[0] = reg;
 243         memcpy(&buf[1], data, len);
 244
 245         ret = i2c_transfer(priv->i2c, msg, 1);
 246         if (ret >= 0 && ret != 1)
 247                 ret = -EIO;
 248         if (ret < 0) {
 249                 dev_warn(&priv->i2c->dev,
 250                         "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
 251                         KBUILD_MODNAME, ret, i2c_addr, reg, len);
 252                 return ret;
 253         }
 254         return 0;
 255 }
 256
 257 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
 258                                u8 addr, u8 reg, u8 val)
 259 {
 260         u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
 261
 262         return cxd2841er_write_regs(priv, addr, reg, &tmp, 1);
 263 }
 264
 265 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
 266                                u8 addr, u8 reg, u8 *val, u32 len)
 267 {
 268         int ret;
 269         u8 i2c_addr = (addr == I2C_SLVX ?
 270                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 271         struct i2c_msg msg[2] = {
 272                 {
 273                         .addr = i2c_addr,
 274                         .flags = 0,
 275                         .len = 1,
 276                         .buf = &reg,
 277                 }, {
 278                         .addr = i2c_addr,
 279                         .flags = I2C_M_RD,
 280                         .len = len,
 281                         .buf = val,
 282                 }
 283         };
 284
 285         ret = i2c_transfer(priv->i2c, msg, 2);
 286         if (ret >= 0 && ret != 2)
 287                 ret = -EIO;
 288         if (ret < 0) {
 289                 dev_warn(&priv->i2c->dev,
 290                         "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
 291                         KBUILD_MODNAME, ret, i2c_addr, reg);
 292                 return ret;
 293         }
 294         cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
 295         return 0;
 296 }
 297
 298 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
 299                               u8 addr, u8 reg, u8 *val)
 300 {
 301         return cxd2841er_read_regs(priv, addr, reg, val, 1);
 302 }
 303
 304 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
 305                                   u8 addr, u8 reg, u8 data, u8 mask)
 306 {
 307         int res;
 308         u8 rdata;
 309
 310         if (mask != 0xff) {
 311                 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
 312                 if (res)
 313                         return res;
 314                 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
 315         }
 316         return cxd2841er_write_reg(priv, addr, reg, data);
 317 }
 318
 319 static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz)
 320 {
 321         u64 tmp;
 322
 323         tmp = (u64) ifhz * 16777216;
 324         do_div(tmp, ((xtal == SONY_XTAL_24000) ? 48000000 : 41000000));
 325
 326         return (u32) tmp;
 327 }
 328
 329 static u32 cxd2841er_calc_iffreq(u32 ifhz)
 330 {
 331         return cxd2841er_calc_iffreq_xtal(SONY_XTAL_20500, ifhz);
 332 }
 333
 334 static int cxd2841er_get_if_hz(struct cxd2841er_priv *priv, u32 def_hz)
 335 {
 336         u32 hz;
 337
 338         if (priv->frontend.ops.tuner_ops.get_if_frequency
 339                         && (priv->flags & CXD2841ER_AUTO_IFHZ))
 340                 priv->frontend.ops.tuner_ops.get_if_frequency(
 341                         &priv->frontend, &hz);
 342         else
 343                 hz = def_hz;
 344
 345         return hz;
 346 }
 347
 348 static int cxd2841er_tuner_set(struct dvb_frontend *fe)
 349 {
 350         struct cxd2841er_priv *priv = fe->demodulator_priv;
 351
 352         if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
 353                 fe->ops.i2c_gate_ctrl(fe, 1);
 354         if (fe->ops.tuner_ops.set_params)
 355                 fe->ops.tuner_ops.set_params(fe);
 356         if ((priv->flags & CXD2841ER_USE_GATECTRL) && fe->ops.i2c_gate_ctrl)
 357                 fe->ops.i2c_gate_ctrl(fe, 0);
 358
 359         return 0;
 360 }
 361
 362 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
 363                                            u32 symbol_rate)
 364 {
 365         u32 reg_value = 0;
 366         u8 data[3] = {0, 0, 0};
 367
 368         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 369         /*
 370          * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
 371          *          = ((symbolRateKSps * 2^14) + 500) / 1000
 372          *          = ((symbolRateKSps * 16384) + 500) / 1000
 373          */
 374         reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
 375         if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
 376                 dev_err(&priv->i2c->dev,
 377                         "%s(): reg_value is out of range\n", __func__);
 378                 return -EINVAL;
 379         }
 380         data[0] = (u8)((reg_value >> 16) & 0x0F);
 381         data[1] = (u8)((reg_value >>  8) & 0xFF);
 382         data[2] = (u8)(reg_value & 0xFF);
 383         /* Set SLV-T Bank : 0xAE */
 384         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 385         cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
 386         return 0;
 387 }
 388
 389 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 390                                         u8 system);
 391
 392 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
 393                                          u8 system, u32 symbol_rate)
 394 {
 395         int ret;
 396         u8 data[4] = { 0, 0, 0, 0 };
 397
 398         if (priv->state != STATE_SLEEP_S) {
 399                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 400                         __func__, (int)priv->state);
 401                 return -EINVAL;
 402         }
 403         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 404         cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
 405         /* Set demod mode */
 406         if (system == SYS_DVBS) {
 407                 data[0] = 0x0A;
 408         } else if (system == SYS_DVBS2) {
 409                 data[0] = 0x0B;
 410         } else {
 411                 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
 412                         __func__, system);
 413                 return -EINVAL;
 414         }
 415         /* Set SLV-X Bank : 0x00 */
 416         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 417         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
 418         /* DVB-S/S2 */
 419         data[0] = 0x00;
 420         /* Set SLV-T Bank : 0x00 */
 421         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 422         /* Enable S/S2 auto detection 1 */
 423         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
 424         /* Set SLV-T Bank : 0xAE */
 425         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 426         /* Enable S/S2 auto detection 2 */
 427         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
 428         /* Set SLV-T Bank : 0x00 */
 429         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 430         /* Enable demod clock */
 431         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
 432         /* Enable ADC clock */
 433         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
 434         /* Enable ADC 1 */
 435         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 436         /* Enable ADC 2 */
 437         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
 438         /* Set SLV-X Bank : 0x00 */
 439         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 440         /* Enable ADC 3 */
 441         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
 442         /* Set SLV-T Bank : 0xA3 */
 443         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
 444         cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
 445         data[0] = 0x07;
 446         data[1] = 0x3B;
 447         data[2] = 0x08;
 448         data[3] = 0xC5;
 449         /* Set SLV-T Bank : 0xAB */
 450         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
 451         cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
 452         data[0] = 0x05;
 453         data[1] = 0x80;
 454         data[2] = 0x0A;
 455         data[3] = 0x80;
 456         cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
 457         data[0] = 0x0C;
 458         data[1] = 0xCC;
 459         cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
 460         /* Set demod parameter */
 461         ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
 462         if (ret != 0)
 463                 return ret;
 464         /* Set SLV-T Bank : 0x00 */
 465         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 466         /* disable Hi-Z setting 1 */
 467         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
 468         /* disable Hi-Z setting 2 */
 469         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
 470         priv->state = STATE_ACTIVE_S;
 471         return 0;
 472 }
 473
 474 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
 475                                                u32 bandwidth);
 476
 477 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
 478                                                 u32 bandwidth);
 479
 480 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
 481                                                u32 bandwidth);
 482
 483 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
 484                 u32 bandwidth);
 485
 486 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
 487
 488 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
 489
 490 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
 491
 492 static int cxd2841er_sleep_tc(struct dvb_frontend *fe);
 493
 494 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
 495                                    struct dtv_frontend_properties *p)
 496 {
 497         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 498         if (priv->state != STATE_ACTIVE_S &&
 499                         priv->state != STATE_ACTIVE_TC) {
 500                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
 501                         __func__, priv->state);
 502                 return -EINVAL;
 503         }
 504         /* Set SLV-T Bank : 0x00 */
 505         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 506         /* disable TS output */
 507         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 508         if (priv->state == STATE_ACTIVE_S)
 509                 return cxd2841er_dvbs2_set_symbol_rate(
 510                                 priv, p->symbol_rate / 1000);
 511         else if (priv->state == STATE_ACTIVE_TC) {
 512                 switch (priv->system) {
 513                 case SYS_DVBT:
 514                         return cxd2841er_sleep_tc_to_active_t_band(
 515                                         priv, p->bandwidth_hz);
 516                 case SYS_DVBT2:
 517                         return cxd2841er_sleep_tc_to_active_t2_band(
 518                                         priv, p->bandwidth_hz);
 519                 case SYS_DVBC_ANNEX_A:
 520                         return cxd2841er_sleep_tc_to_active_c_band(
 521                                         priv, p->bandwidth_hz);
 522                 case SYS_ISDBT:
 523                         cxd2841er_active_i_to_sleep_tc(priv);
 524                         cxd2841er_sleep_tc_to_shutdown(priv);
 525                         cxd2841er_shutdown_to_sleep_tc(priv);
 526                         return cxd2841er_sleep_tc_to_active_i(
 527                                         priv, p->bandwidth_hz);
 528                 }
 529         }
 530         dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
 531                 __func__, priv->system);
 532         return -EINVAL;
 533 }
 534
 535 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
 536 {
 537         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 538         if (priv->state != STATE_ACTIVE_S) {
 539                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 540                         __func__, priv->state);
 541                 return -EINVAL;
 542         }
 543         /* Set SLV-T Bank : 0x00 */
 544         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 545         /* disable TS output */
 546         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 547         /* enable Hi-Z setting 1 */
 548         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
 549         /* enable Hi-Z setting 2 */
 550         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 551         /* Set SLV-X Bank : 0x00 */
 552         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 553         /* disable ADC 1 */
 554         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 555         /* Set SLV-T Bank : 0x00 */
 556         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 557         /* disable ADC clock */
 558         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
 559         /* disable ADC 2 */
 560         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 561         /* disable ADC 3 */
 562         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 563         /* SADC Bias ON */
 564         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 565         /* disable demod clock */
 566         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 567         /* Set SLV-T Bank : 0xAE */
 568         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 569         /* disable S/S2 auto detection1 */
 570         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 571         /* Set SLV-T Bank : 0x00 */
 572         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 573         /* disable S/S2 auto detection2 */
 574         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
 575         priv->state = STATE_SLEEP_S;
 576         return 0;
 577 }
 578
 579 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
 580 {
 581         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 582         if (priv->state != STATE_SLEEP_S) {
 583                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 584                         __func__, priv->state);
 585                 return -EINVAL;
 586         }
 587         /* Set SLV-T Bank : 0x00 */
 588         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 589         /* Disable DSQOUT */
 590         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 591         /* Disable DSQIN */
 592         cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
 593         /* Set SLV-X Bank : 0x00 */
 594         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 595         /* Disable oscillator */
 596         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 597         /* Set demod mode */
 598         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 599         priv->state = STATE_SHUTDOWN;
 600         return 0;
 601 }
 602
 603 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
 604 {
 605         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 606         if (priv->state != STATE_SLEEP_TC) {
 607                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 608                         __func__, priv->state);
 609                 return -EINVAL;
 610         }
 611         /* Set SLV-X Bank : 0x00 */
 612         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 613         /* Disable oscillator */
 614         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 615         /* Set demod mode */
 616         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 617         priv->state = STATE_SHUTDOWN;
 618         return 0;
 619 }
 620
 621 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
 622 {
 623         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 624         if (priv->state != STATE_ACTIVE_TC) {
 625                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 626                         __func__, priv->state);
 627                 return -EINVAL;
 628         }
 629         /* Set SLV-T Bank : 0x00 */
 630         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 631         /* disable TS output */
 632         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 633         /* enable Hi-Z setting 1 */
 634         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 635         /* enable Hi-Z setting 2 */
 636         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 637         /* Set SLV-X Bank : 0x00 */
 638         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 639         /* disable ADC 1 */
 640         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 641         /* Set SLV-T Bank : 0x00 */
 642         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 643         /* Disable ADC 2 */
 644         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 645         /* Disable ADC 3 */
 646         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 647         /* Disable ADC clock */
 648         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 649         /* Disable RF level monitor */
 650         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 651         /* Disable demod clock */
 652         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 653         priv->state = STATE_SLEEP_TC;
 654         return 0;
 655 }
 656
 657 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
 658 {
 659         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 660         if (priv->state != STATE_ACTIVE_TC) {
 661                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 662                         __func__, priv->state);
 663                 return -EINVAL;
 664         }
 665         /* Set SLV-T Bank : 0x00 */
 666         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 667         /* disable TS output */
 668         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 669         /* enable Hi-Z setting 1 */
 670         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 671         /* enable Hi-Z setting 2 */
 672         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 673         /* Cancel DVB-T2 setting */
 674         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
 675         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
 676         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
 677         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
 678         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
 679         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
 680         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
 681         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
 682         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
 683         /* Set SLV-X Bank : 0x00 */
 684         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 685         /* disable ADC 1 */
 686         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 687         /* Set SLV-T Bank : 0x00 */
 688         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 689         /* Disable ADC 2 */
 690         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 691         /* Disable ADC 3 */
 692         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 693         /* Disable ADC clock */
 694         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 695         /* Disable RF level monitor */
 696         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 697         /* Disable demod clock */
 698         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 699         priv->state = STATE_SLEEP_TC;
 700         return 0;
 701 }
 702
 703 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
 704 {
 705         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 706         if (priv->state != STATE_ACTIVE_TC) {
 707                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 708                         __func__, priv->state);
 709                 return -EINVAL;
 710         }
 711         /* Set SLV-T Bank : 0x00 */
 712         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 713         /* disable TS output */
 714         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 715         /* enable Hi-Z setting 1 */
 716         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 717         /* enable Hi-Z setting 2 */
 718         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 719         /* Cancel DVB-C setting */
 720         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
 721         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
 722         /* Set SLV-X Bank : 0x00 */
 723         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 724         /* disable ADC 1 */
 725         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 726         /* Set SLV-T Bank : 0x00 */
 727         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 728         /* Disable ADC 2 */
 729         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 730         /* Disable ADC 3 */
 731         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 732         /* Disable ADC clock */
 733         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 734         /* Disable RF level monitor */
 735         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 736         /* Disable demod clock */
 737         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 738         priv->state = STATE_SLEEP_TC;
 739         return 0;
 740 }
 741
 742 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
 743 {
 744         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 745         if (priv->state != STATE_ACTIVE_TC) {
 746                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 747                                 __func__, priv->state);
 748                 return -EINVAL;
 749         }
 750         /* Set SLV-T Bank : 0x00 */
 751         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 752         /* disable TS output */
 753         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 754         /* enable Hi-Z setting 1 */
 755         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 756         /* enable Hi-Z setting 2 */
 757         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 758
 759         /* TODO: Cancel demod parameter */
 760
 761         /* Set SLV-X Bank : 0x00 */
 762         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 763         /* disable ADC 1 */
 764         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 765         /* Set SLV-T Bank : 0x00 */
 766         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 767         /* Disable ADC 2 */
 768         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 769         /* Disable ADC 3 */
 770         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 771         /* Disable ADC clock */
 772         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 773         /* Disable RF level monitor */
 774         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 775         /* Disable demod clock */
 776         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 777         priv->state = STATE_SLEEP_TC;
 778         return 0;
 779 }
 780
 781 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
 782 {
 783         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 784         if (priv->state != STATE_SHUTDOWN) {
 785                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 786                         __func__, priv->state);
 787                 return -EINVAL;
 788         }
 789         /* Set SLV-X Bank : 0x00 */
 790         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 791         /* Clear all demodulator registers */
 792         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 793         usleep_range(3000, 5000);
 794         /* Set SLV-X Bank : 0x00 */
 795         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 796         /* Set demod SW reset */
 797         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 798
 799         switch (priv->xtal) {
 800         case SONY_XTAL_20500:
 801                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
 802                 break;
 803         case SONY_XTAL_24000:
 804                 /* Select demod frequency */
 805                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 806                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
 807                 break;
 808         case SONY_XTAL_41000:
 809                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
 810                 break;
 811         default:
 812                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
 813                                 __func__, priv->xtal);
 814                 return -EINVAL;
 815         }
 816
 817         /* Set demod mode */
 818         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
 819         /* Clear demod SW reset */
 820         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 821         usleep_range(1000, 2000);
 822         /* Set SLV-T Bank : 0x00 */
 823         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 824         /* enable DSQOUT */
 825         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
 826         /* enable DSQIN */
 827         cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
 828         /* TADC Bias On */
 829         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 830         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 831         /* SADC Bias On */
 832         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 833         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 834         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 835         priv->state = STATE_SLEEP_S;
 836         return 0;
 837 }
 838
 839 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
 840 {
 841         u8 data = 0;
 842
 843         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 844         if (priv->state != STATE_SHUTDOWN) {
 845                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 846                         __func__, priv->state);
 847                 return -EINVAL;
 848         }
 849         /* Set SLV-X Bank : 0x00 */
 850         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 851         /* Clear all demodulator registers */
 852         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 853         usleep_range(3000, 5000);
 854         /* Set SLV-X Bank : 0x00 */
 855         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 856         /* Set demod SW reset */
 857         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 858   /* Select ADC clock mode */
 859         cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
 860
 861         switch (priv->xtal) {
 862         case SONY_XTAL_20500:
 863                 data = 0x0;
 864                 break;
 865         case SONY_XTAL_24000:
 866                 /* Select demod frequency */
 867                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 868                 data = 0x3;
 869                 break;
 870         case SONY_XTAL_41000:
 871                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 872                 data = 0x1;
 873                 break;
 874         }
 875         cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
 876         /* Clear demod SW reset */
 877         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 878         usleep_range(1000, 2000);
 879         /* Set SLV-T Bank : 0x00 */
 880         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 881         /* TADC Bias On */
 882         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 883         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 884         /* SADC Bias On */
 885         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 886         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 887         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 888         priv->state = STATE_SLEEP_TC;
 889         return 0;
 890 }
 891
 892 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
 893 {
 894         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 895         /* Set SLV-T Bank : 0x00 */
 896         cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
 897         /* SW Reset */
 898         cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
 899         /* Enable TS output */
 900         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
 901         return 0;
 902 }
 903
 904 /* Set TS parallel mode */
 905 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 906                                         u8 system)
 907 {
 908         u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
 909
 910         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 911         /* Set SLV-T Bank : 0x00 */
 912         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 913         cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
 914         cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
 915         cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
 916         dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
 917                 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
 918
 919         /*
 920          * slave    Bank    Addr    Bit    default    Name
 921          * <SLV-T>  00h     C4h     [1:0]  2'b??      OSERCKMODE
 922          */
 923         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
 924                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
 925         /*
 926          * slave    Bank    Addr    Bit    default    Name
 927          * <SLV-T>  00h     D1h     [1:0]  2'b??      OSERDUTYMODE
 928          */
 929         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd1,
 930                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
 931         /*
 932          * slave    Bank    Addr    Bit    default    Name
 933          * <SLV-T>  00h     D9h     [7:0]  8'h08      OTSCKPERIOD
 934          */
 935         cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
 936         /*
 937          * Disable TS IF Clock
 938          * slave    Bank    Addr    Bit    default    Name
 939          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 940          */
 941         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
 942         /*
 943          * slave    Bank    Addr    Bit    default    Name
 944          * <SLV-T>  00h     33h     [1:0]  2'b01      OREG_CKSEL_TSIF
 945          */
 946         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33,
 947                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x01 : 0x00), 0x03);
 948         /*
 949          * Enable TS IF Clock
 950          * slave    Bank    Addr    Bit    default    Name
 951          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 952          */
 953         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
 954
 955         if (system == SYS_DVBT) {
 956                 /* Enable parity period for DVB-T */
 957                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 958                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 959         } else if (system == SYS_DVBC_ANNEX_A) {
 960                 /* Enable parity period for DVB-C */
 961                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 962                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 963         }
 964 }
 965
 966 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
 967 {
 968         u8 chip_id = 0;
 969
 970         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 971         if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
 972                 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
 973         else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
 974                 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
 975
 976         return chip_id;
 977 }
 978
 979 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
 980                                    enum fe_status *status)
 981 {
 982         u8 reg = 0;
 983         struct cxd2841er_priv *priv = fe->demodulator_priv;
 984
 985         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 986         *status = 0;
 987         if (priv->state != STATE_ACTIVE_S) {
 988                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 989                         __func__, priv->state);
 990                 return -EINVAL;
 991         }
 992         /* Set SLV-T Bank : 0xA0 */
 993         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
 994         /*
 995          *  slave     Bank      Addr      Bit      Signal name
 996          * <SLV-T>    A0h       11h       [2]      ITSLOCK
 997          */
 998         cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
 999         if (reg & 0x04) {
1000                 *status = FE_HAS_SIGNAL
1001                         | FE_HAS_CARRIER
1002                         | FE_HAS_VITERBI
1003                         | FE_HAS_SYNC
1004                         | FE_HAS_LOCK;
1005         }
1006         dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
1007         return 0;
1008 }
1009
1010 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
1011                                       u8 *sync, u8 *tslock, u8 *unlock)
1012 {
1013         u8 data = 0;
1014
1015         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1016         if (priv->state != STATE_ACTIVE_TC)
1017                 return -EINVAL;
1018         if (priv->system == SYS_DVBT) {
1019                 /* Set SLV-T Bank : 0x10 */
1020                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1021         } else {
1022                 /* Set SLV-T Bank : 0x20 */
1023                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1024         }
1025         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1026         if ((data & 0x07) == 0x07) {
1027                 dev_dbg(&priv->i2c->dev,
1028                         "%s(): invalid hardware state detected\n", __func__);
1029                 *sync = 0;
1030                 *tslock = 0;
1031                 *unlock = 0;
1032         } else {
1033                 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
1034                 *tslock = ((data & 0x20) ? 1 : 0);
1035                 *unlock = ((data & 0x10) ? 1 : 0);
1036         }
1037         return 0;
1038 }
1039
1040 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
1041 {
1042         u8 data;
1043
1044         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1045         if (priv->state != STATE_ACTIVE_TC)
1046                 return -EINVAL;
1047         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1048         cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
1049         if ((data & 0x01) == 0) {
1050                 *tslock = 0;
1051         } else {
1052                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1053                 *tslock = ((data & 0x20) ? 1 : 0);
1054         }
1055         return 0;
1056 }
1057
1058 static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
1059                 u8 *sync, u8 *tslock, u8 *unlock)
1060 {
1061         u8 data = 0;
1062
1063         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1064         if (priv->state != STATE_ACTIVE_TC)
1065                 return -EINVAL;
1066         /* Set SLV-T Bank : 0x60 */
1067         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1068         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1069         dev_dbg(&priv->i2c->dev,
1070                         "%s(): lock=0x%x\n", __func__, data);
1071         *sync = ((data & 0x02) ? 1 : 0);
1072         *tslock = ((data & 0x01) ? 1 : 0);
1073         *unlock = ((data & 0x10) ? 1 : 0);
1074         return 0;
1075 }
1076
1077 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1078                                     enum fe_status *status)
1079 {
1080         int ret = 0;
1081         u8 sync = 0;
1082         u8 tslock = 0;
1083         u8 unlock = 0;
1084         struct cxd2841er_priv *priv = fe->demodulator_priv;
1085
1086         *status = 0;
1087         if (priv->state == STATE_ACTIVE_TC) {
1088                 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1089                         ret = cxd2841er_read_status_t_t2(
1090                                 priv, &sync, &tslock, &unlock);
1091                         if (ret)
1092                                 goto done;
1093                         if (unlock)
1094                                 goto done;
1095                         if (sync)
1096                                 *status = FE_HAS_SIGNAL |
1097                                         FE_HAS_CARRIER |
1098                                         FE_HAS_VITERBI |
1099                                         FE_HAS_SYNC;
1100                         if (tslock)
1101                                 *status |= FE_HAS_LOCK;
1102                 } else if (priv->system == SYS_ISDBT) {
1103                         ret = cxd2841er_read_status_i(
1104                                         priv, &sync, &tslock, &unlock);
1105                         if (ret)
1106                                 goto done;
1107                         if (unlock)
1108                                 goto done;
1109                         if (sync)
1110                                 *status = FE_HAS_SIGNAL |
1111                                         FE_HAS_CARRIER |
1112                                         FE_HAS_VITERBI |
1113                                         FE_HAS_SYNC;
1114                         if (tslock)
1115                                 *status |= FE_HAS_LOCK;
1116                 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1117                         ret = cxd2841er_read_status_c(priv, &tslock);
1118                         if (ret)
1119                                 goto done;
1120                         if (tslock)
1121                                 *status = FE_HAS_SIGNAL |
1122                                         FE_HAS_CARRIER |
1123                                         FE_HAS_VITERBI |
1124                                         FE_HAS_SYNC |
1125                                         FE_HAS_LOCK;
1126                 }
1127         }
1128 done:
1129         dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1130         return ret;
1131 }
1132
1133 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1134                                              int *offset)
1135 {
1136         u8 data[3];
1137         u8 is_hs_mode;
1138         s32 cfrl_ctrlval;
1139         s32 temp_div, temp_q, temp_r;
1140
1141         if (priv->state != STATE_ACTIVE_S) {
1142                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1143                         __func__, priv->state);
1144                 return -EINVAL;
1145         }
1146         /*
1147          * Get High Sampling Rate mode
1148          *  slave     Bank      Addr      Bit      Signal name
1149          * <SLV-T>    A0h       10h       [0]      ITRL_LOCK
1150          */
1151         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1152         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1153         if (data[0] & 0x01) {
1154                 /*
1155                  *  slave     Bank      Addr      Bit      Signal name
1156                  * <SLV-T>    A0h       50h       [4]      IHSMODE
1157                  */
1158                 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1159                 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1160         } else {
1161                 dev_dbg(&priv->i2c->dev,
1162                         "%s(): unable to detect sampling rate mode\n",
1163                         __func__);
1164                 return -EINVAL;
1165         }
1166         /*
1167          *  slave     Bank      Addr      Bit      Signal name
1168          * <SLV-T>    A0h       45h       [4:0]    ICFRL_CTRLVAL[20:16]
1169          * <SLV-T>    A0h       46h       [7:0]    ICFRL_CTRLVAL[15:8]
1170          * <SLV-T>    A0h       47h       [7:0]    ICFRL_CTRLVAL[7:0]
1171          */
1172         cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1173         cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1174                                 (((u32)data[1] & 0xFF) <<  8) |
1175                                 ((u32)data[2] & 0xFF), 20);
1176         temp_div = (is_hs_mode ? 1048576 : 1572864);
1177         if (cfrl_ctrlval > 0) {
1178                 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1179                         temp_div, &temp_r);
1180         } else {
1181                 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1182                         temp_div, &temp_r);
1183         }
1184         if (temp_r >= temp_div / 2)
1185                 temp_q++;
1186         if (cfrl_ctrlval > 0)
1187                 temp_q *= -1;
1188         *offset = temp_q;
1189         return 0;
1190 }
1191
1192 static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1193                                            u32 bandwidth, int *offset)
1194 {
1195         u8 data[4];
1196
1197         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1198         if (priv->state != STATE_ACTIVE_TC) {
1199                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1200                         __func__, priv->state);
1201                 return -EINVAL;
1202         }
1203         if (priv->system != SYS_ISDBT) {
1204                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1205                         __func__, priv->system);
1206                 return -EINVAL;
1207         }
1208         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1209         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1210         *offset = -1 * sign_extend32(
1211                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1212                 ((u32)data[2] << 8) | (u32)data[3], 29);
1213
1214         switch (bandwidth) {
1215         case 6000000:
1216                 *offset = -1 * ((*offset) * 8/264);
1217                 break;
1218         case 7000000:
1219                 *offset = -1 * ((*offset) * 8/231);
1220                 break;
1221         case 8000000:
1222                 *offset = -1 * ((*offset) * 8/198);
1223                 break;
1224         default:
1225                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1226                                 __func__, bandwidth);
1227                 return -EINVAL;
1228         }
1229
1230         dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1231                         __func__, bandwidth, *offset);
1232
1233         return 0;
1234 }
1235
1236 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1237                                            u32 bandwidth, int *offset)
1238 {
1239         u8 data[4];
1240
1241         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1242         if (priv->state != STATE_ACTIVE_TC) {
1243                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1244                         __func__, priv->state);
1245                 return -EINVAL;
1246         }
1247         if (priv->system != SYS_DVBT) {
1248                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1249                         __func__, priv->system);
1250                 return -EINVAL;
1251         }
1252         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1253         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1254         *offset = -1 * sign_extend32(
1255                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1256                 ((u32)data[2] << 8) | (u32)data[3], 29);
1257         *offset *= (bandwidth / 1000000);
1258         *offset /= 235;
1259         return 0;
1260 }
1261
1262 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1263                                            u32 bandwidth, int *offset)
1264 {
1265         u8 data[4];
1266
1267         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1268         if (priv->state != STATE_ACTIVE_TC) {
1269                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1270                         __func__, priv->state);
1271                 return -EINVAL;
1272         }
1273         if (priv->system != SYS_DVBT2) {
1274                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1275                         __func__, priv->system);
1276                 return -EINVAL;
1277         }
1278         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1279         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1280         *offset = -1 * sign_extend32(
1281                 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1282                 ((u32)data[2] << 8) | (u32)data[3], 27);
1283         switch (bandwidth) {
1284         case 1712000:
1285                 *offset /= 582;
1286                 break;
1287         case 5000000:
1288         case 6000000:
1289         case 7000000:
1290         case 8000000:
1291                 *offset *= (bandwidth / 1000000);
1292                 *offset /= 940;
1293                 break;
1294         default:
1295                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1296                         __func__, bandwidth);
1297                 return -EINVAL;
1298         }
1299         return 0;
1300 }
1301
1302 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1303                                           int *offset)
1304 {
1305         u8 data[2];
1306
1307         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1308         if (priv->state != STATE_ACTIVE_TC) {
1309                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1310                         __func__, priv->state);
1311                 return -EINVAL;
1312         }
1313         if (priv->system != SYS_DVBC_ANNEX_A) {
1314                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1315                         __func__, priv->system);
1316                 return -EINVAL;
1317         }
1318         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1319         cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1320         *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1321                                                 | (u32)data[1], 13), 16384);
1322         return 0;
1323 }
1324
1325 static int cxd2841er_read_packet_errors_c(
1326                 struct cxd2841er_priv *priv, u32 *penum)
1327 {
1328         u8 data[3];
1329
1330         *penum = 0;
1331         if (priv->state != STATE_ACTIVE_TC) {
1332                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1333                                 __func__, priv->state);
1334                 return -EINVAL;
1335         }
1336         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1337         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1338         if (data[2] & 0x01)
1339                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1340         return 0;
1341 }
1342
1343 static int cxd2841er_read_packet_errors_t(
1344                 struct cxd2841er_priv *priv, u32 *penum)
1345 {
1346         u8 data[3];
1347
1348         *penum = 0;
1349         if (priv->state != STATE_ACTIVE_TC) {
1350                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1351                         __func__, priv->state);
1352                 return -EINVAL;
1353         }
1354         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1355         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1356         if (data[2] & 0x01)
1357                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1358         return 0;
1359 }
1360
1361 static int cxd2841er_read_packet_errors_t2(
1362                 struct cxd2841er_priv *priv, u32 *penum)
1363 {
1364         u8 data[3];
1365
1366         *penum = 0;
1367         if (priv->state != STATE_ACTIVE_TC) {
1368                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1369                         __func__, priv->state);
1370                 return -EINVAL;
1371         }
1372         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1373         cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1374         if (data[0] & 0x01)
1375                 *penum = ((u32)data[1] << 8) | (u32)data[2];
1376         return 0;
1377 }
1378
1379 static int cxd2841er_read_packet_errors_i(
1380                 struct cxd2841er_priv *priv, u32 *penum)
1381 {
1382         u8 data[2];
1383
1384         *penum = 0;
1385         if (priv->state != STATE_ACTIVE_TC) {
1386                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1387                                 __func__, priv->state);
1388                 return -EINVAL;
1389         }
1390         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1391         cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1392
1393         if (!(data[0] & 0x01))
1394                 return 0;
1395
1396         /* Layer A */
1397         cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1398         *penum = ((u32)data[0] << 8) | (u32)data[1];
1399
1400         /* Layer B */
1401         cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1402         *penum += ((u32)data[0] << 8) | (u32)data[1];
1403
1404         /* Layer C */
1405         cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1406         *penum += ((u32)data[0] << 8) | (u32)data[1];
1407
1408         return 0;
1409 }
1410
1411 static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
1412                 u32 *bit_error, u32 *bit_count)
1413 {
1414         u8 data[3];
1415         u32 bit_err, period_exp;
1416
1417         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1418         if (priv->state != STATE_ACTIVE_TC) {
1419                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1420                                 __func__, priv->state);
1421                 return -EINVAL;
1422         }
1423         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1424         cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
1425         if (!(data[0] & 0x80)) {
1426                 dev_dbg(&priv->i2c->dev,
1427                                 "%s(): no valid BER data\n", __func__);
1428                 return -EINVAL;
1429         }
1430         bit_err = ((u32)(data[0] & 0x3f) << 16) |
1431                 ((u32)data[1] << 8) |
1432                 (u32)data[2];
1433         cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
1434         period_exp = data[0] & 0x1f;
1435
1436         if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
1437                 dev_dbg(&priv->i2c->dev,
1438                                 "%s(): period_exp(%u) or bit_err(%u)  not in range. no valid BER data\n",
1439                                 __func__, period_exp, bit_err);
1440                 return -EINVAL;
1441         }
1442
1443         dev_dbg(&priv->i2c->dev,
1444                         "%s(): period_exp(%u) or bit_err(%u) count=%d\n",
1445                         __func__, period_exp, bit_err,
1446                         ((1 << period_exp) * 204 * 8));
1447
1448         *bit_error = bit_err;
1449         *bit_count = ((1 << period_exp) * 204 * 8);
1450
1451         return 0;
1452 }
1453
1454 static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv,
1455                 u32 *bit_error, u32 *bit_count)
1456 {
1457         u8 data[3];
1458         u8 pktnum[2];
1459
1460         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1461         if (priv->state != STATE_ACTIVE_TC) {
1462                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1463                                 __func__, priv->state);
1464                 return -EINVAL;
1465         }
1466
1467         cxd2841er_freeze_regs(priv);
1468         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1469         cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum));
1470         cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data));
1471         cxd2841er_unfreeze_regs(priv);
1472
1473         if (!pktnum[0] && !pktnum[1]) {
1474                 dev_dbg(&priv->i2c->dev,
1475                                 "%s(): no valid BER data\n", __func__);
1476                 return -EINVAL;
1477         }
1478
1479         *bit_error = ((u32)(data[0] & 0x7F) << 16) |
1480                 ((u32)data[1] << 8) | data[2];
1481         *bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8);
1482         dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n",
1483                         __func__, *bit_error, *bit_count);
1484
1485         return 0;
1486 }
1487
1488 static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
1489                                     u32 *bit_error, u32 *bit_count)
1490 {
1491         u8 data[11];
1492
1493         /* Set SLV-T Bank : 0xA0 */
1494         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1495         /*
1496          *  slave     Bank      Addr      Bit      Signal name
1497          * <SLV-T>    A0h       35h       [0]      IFVBER_VALID
1498          * <SLV-T>    A0h       36h       [5:0]    IFVBER_BITERR[21:16]
1499          * <SLV-T>    A0h       37h       [7:0]    IFVBER_BITERR[15:8]
1500          * <SLV-T>    A0h       38h       [7:0]    IFVBER_BITERR[7:0]
1501          * <SLV-T>    A0h       3Dh       [5:0]    IFVBER_BITNUM[21:16]
1502          * <SLV-T>    A0h       3Eh       [7:0]    IFVBER_BITNUM[15:8]
1503          * <SLV-T>    A0h       3Fh       [7:0]    IFVBER_BITNUM[7:0]
1504          */
1505         cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1506         if (data[0] & 0x01) {
1507                 *bit_error = ((u32)(data[1]  & 0x3F) << 16) |
1508                              ((u32)(data[2]  & 0xFF) <<  8) |
1509                              (u32)(data[3]  & 0xFF);
1510                 *bit_count = ((u32)(data[8]  & 0x3F) << 16) |
1511                              ((u32)(data[9]  & 0xFF) <<  8) |
1512                              (u32)(data[10] & 0xFF);
1513                 if ((*bit_count == 0) || (*bit_error > *bit_count)) {
1514                         dev_dbg(&priv->i2c->dev,
1515                                 "%s(): invalid bit_error %d, bit_count %d\n",
1516                                 __func__, *bit_error, *bit_count);
1517                         return -EINVAL;
1518                 }
1519                 return 0;
1520         }
1521         dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1522         return -EINVAL;
1523 }
1524
1525
1526 static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
1527                                      u32 *bit_error, u32 *bit_count)
1528 {
1529         u8 data[5];
1530         u32 period;
1531
1532         /* Set SLV-T Bank : 0xB2 */
1533         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1534         /*
1535          *  slave     Bank      Addr      Bit      Signal name
1536          * <SLV-T>    B2h       30h       [0]      IFLBER_VALID
1537          * <SLV-T>    B2h       31h       [3:0]    IFLBER_BITERR[27:24]
1538          * <SLV-T>    B2h       32h       [7:0]    IFLBER_BITERR[23:16]
1539          * <SLV-T>    B2h       33h       [7:0]    IFLBER_BITERR[15:8]
1540          * <SLV-T>    B2h       34h       [7:0]    IFLBER_BITERR[7:0]
1541          */
1542         cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1543         if (data[0] & 0x01) {
1544                 /* Bit error count */
1545                 *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1546                              ((u32)(data[2] & 0xFF) << 16) |
1547                              ((u32)(data[3] & 0xFF) <<  8) |
1548                              (u32)(data[4] & 0xFF);
1549
1550                 /* Set SLV-T Bank : 0xA0 */
1551                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1552                 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1553                 /* Measurement period */
1554                 period = (u32)(1 << (data[0] & 0x0F));
1555                 if (period == 0) {
1556                         dev_dbg(&priv->i2c->dev,
1557                                 "%s(): period is 0\n", __func__);
1558                         return -EINVAL;
1559                 }
1560                 if (*bit_error > (period * 64800)) {
1561                         dev_dbg(&priv->i2c->dev,
1562                                 "%s(): invalid bit_err 0x%x period 0x%x\n",
1563                                 __func__, *bit_error, period);
1564                         return -EINVAL;
1565                 }
1566                 *bit_count = period * 64800;
1567
1568                 return 0;
1569         } else {
1570                 dev_dbg(&priv->i2c->dev,
1571                         "%s(): no data available\n", __func__);
1572         }
1573         return -EINVAL;
1574 }
1575
1576 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
1577                                  u32 *bit_error, u32 *bit_count)
1578 {
1579         u8 data[4];
1580         u32 period_exp, n_ldpc;
1581
1582         if (priv->state != STATE_ACTIVE_TC) {
1583                 dev_dbg(&priv->i2c->dev,
1584                         "%s(): invalid state %d\n", __func__, priv->state);
1585                 return -EINVAL;
1586         }
1587         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1588         cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1589         if (!(data[0] & 0x10)) {
1590                 dev_dbg(&priv->i2c->dev,
1591                         "%s(): no valid BER data\n", __func__);
1592                 return -EINVAL;
1593         }
1594         *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1595                      ((u32)data[1] << 16) |
1596                      ((u32)data[2] << 8) |
1597                      (u32)data[3];
1598         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1599         period_exp = data[0] & 0x0f;
1600         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1601         cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1602         n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1603         if (*bit_error > ((1U << period_exp) * n_ldpc)) {
1604                 dev_dbg(&priv->i2c->dev,
1605                         "%s(): invalid BER value\n", __func__);
1606                 return -EINVAL;
1607         }
1608
1609         /*
1610          * FIXME: the right thing would be to return bit_error untouched,
1611          * but, as we don't know the scale returned by the counters, let's
1612          * at least preserver BER = bit_error/bit_count.
1613          */
1614         if (period_exp >= 4) {
1615                 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
1616                 *bit_error *= 3125ULL;
1617         } else {
1618                 *bit_count = (1U << period_exp) * (n_ldpc / 200);
1619                 *bit_error *= 50000ULL;
1620         }
1621         return 0;
1622 }
1623
1624 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
1625                                 u32 *bit_error, u32 *bit_count)
1626 {
1627         u8 data[2];
1628         u32 period;
1629
1630         if (priv->state != STATE_ACTIVE_TC) {
1631                 dev_dbg(&priv->i2c->dev,
1632                         "%s(): invalid state %d\n", __func__, priv->state);
1633                 return -EINVAL;
1634         }
1635         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1636         cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1637         if (!(data[0] & 0x01)) {
1638                 dev_dbg(&priv->i2c->dev,
1639                         "%s(): no valid BER data\n", __func__);
1640                 return 0;
1641         }
1642         cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1643         *bit_error = ((u32)data[0] << 8) | (u32)data[1];
1644         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1645         period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1646
1647         /*
1648          * FIXME: the right thing would be to return bit_error untouched,
1649          * but, as we don't know the scale returned by the counters, let's
1650          * at least preserver BER = bit_error/bit_count.
1651          */
1652         *bit_count = period / 128;
1653         *bit_error *= 78125ULL;
1654         return 0;
1655 }
1656
1657 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv)
1658 {
1659         /*
1660          * Freeze registers: ensure multiple separate register reads
1661          * are from the same snapshot
1662          */
1663         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1664         return 0;
1665 }
1666
1667 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv)
1668 {
1669         /*
1670          * un-freeze registers
1671          */
1672         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00);
1673         return 0;
1674 }
1675
1676 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
1677                 u8 delsys, u32 *snr)
1678 {
1679         u8 data[3];
1680         u32 res = 0, value;
1681         int min_index, max_index, index;
1682         static const struct cxd2841er_cnr_data *cn_data;
1683
1684         cxd2841er_freeze_regs(priv);
1685         /* Set SLV-T Bank : 0xA1 */
1686         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1687         /*
1688          *  slave     Bank      Addr      Bit     Signal name
1689          * <SLV-T>    A1h       10h       [0]     ICPM_QUICKRDY
1690          * <SLV-T>    A1h       11h       [4:0]   ICPM_QUICKCNDT[12:8]
1691          * <SLV-T>    A1h       12h       [7:0]   ICPM_QUICKCNDT[7:0]
1692          */
1693         cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1694         cxd2841er_unfreeze_regs(priv);
1695
1696         if (data[0] & 0x01) {
1697                 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1698                 min_index = 0;
1699                 if (delsys == SYS_DVBS) {
1700                         cn_data = s_cn_data;
1701                         max_index = sizeof(s_cn_data) /
1702                                 sizeof(s_cn_data[0]) - 1;
1703                 } else {
1704                         cn_data = s2_cn_data;
1705                         max_index = sizeof(s2_cn_data) /
1706                                 sizeof(s2_cn_data[0]) - 1;
1707                 }
1708                 if (value >= cn_data[min_index].value) {
1709                         res = cn_data[min_index].cnr_x1000;
1710                         goto done;
1711                 }
1712                 if (value <= cn_data[max_index].value) {
1713                         res = cn_data[max_index].cnr_x1000;
1714                         goto done;
1715                 }
1716                 while ((max_index - min_index) > 1) {
1717                         index = (max_index + min_index) / 2;
1718                         if (value == cn_data[index].value) {
1719                                 res = cn_data[index].cnr_x1000;
1720                                 goto done;
1721                         } else if (value > cn_data[index].value)
1722                                 max_index = index;
1723                         else
1724                                 min_index = index;
1725                         if ((max_index - min_index) <= 1) {
1726                                 if (value == cn_data[max_index].value) {
1727                                         res = cn_data[max_index].cnr_x1000;
1728                                         goto done;
1729                                 } else {
1730                                         res = cn_data[min_index].cnr_x1000;
1731                                         goto done;
1732                                 }
1733                         }
1734                 }
1735         } else {
1736                 dev_dbg(&priv->i2c->dev,
1737                         "%s(): no data available\n", __func__);
1738                 return -EINVAL;
1739         }
1740 done:
1741         *snr = res;
1742         return 0;
1743 }
1744
1745 static uint32_t sony_log(uint32_t x)
1746 {
1747         return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
1748 }
1749
1750 static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
1751 {
1752         u32 reg;
1753         u8 data[2];
1754         enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
1755
1756         *snr = 0;
1757         if (priv->state != STATE_ACTIVE_TC) {
1758                 dev_dbg(&priv->i2c->dev,
1759                                 "%s(): invalid state %d\n",
1760                                 __func__, priv->state);
1761                 return -EINVAL;
1762         }
1763
1764         cxd2841er_freeze_regs(priv);
1765         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1766         cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
1767         qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
1768         cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
1769         cxd2841er_unfreeze_regs(priv);
1770
1771         reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
1772         if (reg == 0) {
1773                 dev_dbg(&priv->i2c->dev,
1774                                 "%s(): reg value out of range\n", __func__);
1775                 return 0;
1776         }
1777
1778         switch (qam) {
1779         case SONY_DVBC_CONSTELLATION_16QAM:
1780         case SONY_DVBC_CONSTELLATION_64QAM:
1781         case SONY_DVBC_CONSTELLATION_256QAM:
1782                 /* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */
1783                 if (reg < 126)
1784                         reg = 126;
1785                 *snr = -95 * (int32_t)sony_log(reg) + 95941;
1786                 break;
1787         case SONY_DVBC_CONSTELLATION_32QAM:
1788         case SONY_DVBC_CONSTELLATION_128QAM:
1789                 /* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */
1790                 if (reg < 69)
1791                         reg = 69;
1792                 *snr = -88 * (int32_t)sony_log(reg) + 86999;
1793                 break;
1794         default:
1795                 return -EINVAL;
1796         }
1797
1798         return 0;
1799 }
1800
1801 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1802 {
1803         u32 reg;
1804         u8 data[2];
1805
1806         *snr = 0;
1807         if (priv->state != STATE_ACTIVE_TC) {
1808                 dev_dbg(&priv->i2c->dev,
1809                         "%s(): invalid state %d\n", __func__, priv->state);
1810                 return -EINVAL;
1811         }
1812
1813         cxd2841er_freeze_regs(priv);
1814         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1815         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1816         cxd2841er_unfreeze_regs(priv);
1817
1818         reg = ((u32)data[0] << 8) | (u32)data[1];
1819         if (reg == 0) {
1820                 dev_dbg(&priv->i2c->dev,
1821                         "%s(): reg value out of range\n", __func__);
1822                 return 0;
1823         }
1824         if (reg > 4996)
1825                 reg = 4996;
1826         *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(5350 - reg)) + 285);
1827         return 0;
1828 }
1829
1830 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1831 {
1832         u32 reg;
1833         u8 data[2];
1834
1835         *snr = 0;
1836         if (priv->state != STATE_ACTIVE_TC) {
1837                 dev_dbg(&priv->i2c->dev,
1838                         "%s(): invalid state %d\n", __func__, priv->state);
1839                 return -EINVAL;
1840         }
1841
1842         cxd2841er_freeze_regs(priv);
1843         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1844         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1845         cxd2841er_unfreeze_regs(priv);
1846
1847         reg = ((u32)data[0] << 8) | (u32)data[1];
1848         if (reg == 0) {
1849                 dev_dbg(&priv->i2c->dev,
1850                         "%s(): reg value out of range\n", __func__);
1851                 return 0;
1852         }
1853         if (reg > 10876)
1854                 reg = 10876;
1855         *snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(12600 - reg)) + 320);
1856         return 0;
1857 }
1858
1859 static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1860 {
1861         u32 reg;
1862         u8 data[2];
1863
1864         *snr = 0;
1865         if (priv->state != STATE_ACTIVE_TC) {
1866                 dev_dbg(&priv->i2c->dev,
1867                                 "%s(): invalid state %d\n", __func__,
1868                                 priv->state);
1869                 return -EINVAL;
1870         }
1871
1872         cxd2841er_freeze_regs(priv);
1873         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1874         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1875         cxd2841er_unfreeze_regs(priv);
1876
1877         reg = ((u32)data[0] << 8) | (u32)data[1];
1878         if (reg == 0) {
1879                 dev_dbg(&priv->i2c->dev,
1880                                 "%s(): reg value out of range\n", __func__);
1881                 return 0;
1882         }
1883         *snr = 10000 * (intlog10(reg) >> 24) - 9031;
1884         return 0;
1885 }
1886
1887 static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1888                                         u8 delsys)
1889 {
1890         u8 data[2];
1891
1892         cxd2841er_write_reg(
1893                 priv, I2C_SLVT, 0x00, 0x40);
1894         cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1895         dev_dbg(&priv->i2c->dev,
1896                         "%s(): AGC value=%u\n",
1897                         __func__, (((u16)data[0] & 0x0F) << 8) |
1898                         (u16)(data[1] & 0xFF));
1899         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1900 }
1901
1902 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1903                                         u8 delsys)
1904 {
1905         u8 data[2];
1906
1907         cxd2841er_write_reg(
1908                 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1909         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1910         dev_dbg(&priv->i2c->dev,
1911                         "%s(): AGC value=%u\n",
1912                         __func__, (((u16)data[0] & 0x0F) << 8) |
1913                         (u16)(data[1] & 0xFF));
1914         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1915 }
1916
1917 static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1918                 u8 delsys)
1919 {
1920         u8 data[2];
1921
1922         cxd2841er_write_reg(
1923                         priv, I2C_SLVT, 0x00, 0x60);
1924         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1925
1926         dev_dbg(&priv->i2c->dev,
1927                         "%s(): AGC value=%u\n",
1928                         __func__, (((u16)data[0] & 0x0F) << 8) |
1929                         (u16)(data[1] & 0xFF));
1930         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1931 }
1932
1933 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1934 {
1935         u8 data[2];
1936
1937         /* Set SLV-T Bank : 0xA0 */
1938         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1939         /*
1940          *  slave     Bank      Addr      Bit       Signal name
1941          * <SLV-T>    A0h       1Fh       [4:0]     IRFAGC_GAIN[12:8]
1942          * <SLV-T>    A0h       20h       [7:0]     IRFAGC_GAIN[7:0]
1943          */
1944         cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1945         return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1946 }
1947
1948 static void cxd2841er_read_ber(struct dvb_frontend *fe)
1949 {
1950         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1951         struct cxd2841er_priv *priv = fe->demodulator_priv;
1952         u32 ret, bit_error = 0, bit_count = 0;
1953
1954         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1955         switch (p->delivery_system) {
1956         case SYS_DVBC_ANNEX_A:
1957         case SYS_DVBC_ANNEX_B:
1958         case SYS_DVBC_ANNEX_C:
1959                 ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
1960                 break;
1961         case SYS_ISDBT:
1962                 ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count);
1963                 break;
1964         case SYS_DVBS:
1965                 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
1966                 break;
1967         case SYS_DVBS2:
1968                 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
1969                 break;
1970         case SYS_DVBT:
1971                 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
1972                 break;
1973         case SYS_DVBT2:
1974                 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
1975                 break;
1976         default:
1977                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1978                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1979                 return;
1980         }
1981
1982         if (!ret) {
1983                 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1984                 p->post_bit_error.stat[0].uvalue += bit_error;
1985                 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1986                 p->post_bit_count.stat[0].uvalue += bit_count;
1987         } else {
1988                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1989                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1990         }
1991 }
1992
1993 static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
1994 {
1995         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1996         struct cxd2841er_priv *priv = fe->demodulator_priv;
1997         s32 strength;
1998
1999         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2000         switch (p->delivery_system) {
2001         case SYS_DVBT:
2002         case SYS_DVBT2:
2003                 strength = cxd2841er_read_agc_gain_t_t2(priv,
2004                                                         p->delivery_system);
2005                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2006                 /* Formula was empirically determinated @ 410 MHz */
2007                 p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
2008                 break;  /* Code moved out of the function */
2009         case SYS_DVBC_ANNEX_A:
2010         case SYS_DVBC_ANNEX_B:
2011         case SYS_DVBC_ANNEX_C:
2012                 strength = cxd2841er_read_agc_gain_c(priv,
2013                                                         p->delivery_system);
2014                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2015                 /*
2016                  * Formula was empirically determinated via linear regression,
2017                  * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
2018                  * stream modulated with QAM64
2019                  */
2020                 p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
2021                 break;
2022         case SYS_ISDBT:
2023                 strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
2024                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
2025                 /*
2026                  * Formula was empirically determinated via linear regression,
2027                  * using frequencies: 175 MHz, 410 MHz and 800 MHz.
2028                  */
2029                 p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
2030                 break;
2031         case SYS_DVBS:
2032         case SYS_DVBS2:
2033                 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
2034                 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2035                 p->strength.stat[0].uvalue = strength;
2036                 break;
2037         default:
2038                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2039                 break;
2040         }
2041 }
2042
2043 static void cxd2841er_read_snr(struct dvb_frontend *fe)
2044 {
2045         u32 tmp = 0;
2046         int ret = 0;
2047         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2048         struct cxd2841er_priv *priv = fe->demodulator_priv;
2049
2050         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2051         switch (p->delivery_system) {
2052         case SYS_DVBC_ANNEX_A:
2053         case SYS_DVBC_ANNEX_B:
2054         case SYS_DVBC_ANNEX_C:
2055                 ret = cxd2841er_read_snr_c(priv, &tmp);
2056                 break;
2057         case SYS_DVBT:
2058                 ret = cxd2841er_read_snr_t(priv, &tmp);
2059                 break;
2060         case SYS_DVBT2:
2061                 ret = cxd2841er_read_snr_t2(priv, &tmp);
2062                 break;
2063         case SYS_ISDBT:
2064                 ret = cxd2841er_read_snr_i(priv, &tmp);
2065                 break;
2066         case SYS_DVBS:
2067         case SYS_DVBS2:
2068                 ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
2069                 break;
2070         default:
2071                 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
2072                         __func__, p->delivery_system);
2073                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2074                 return;
2075         }
2076
2077         dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n",
2078                         __func__, (int32_t)tmp);
2079
2080         if (!ret) {
2081                 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2082                 p->cnr.stat[0].svalue = tmp;
2083         } else {
2084                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2085         }
2086 }
2087
2088 static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
2089 {
2090         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2091         struct cxd2841er_priv *priv = fe->demodulator_priv;
2092         u32 ucblocks = 0;
2093
2094         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2095         switch (p->delivery_system) {
2096         case SYS_DVBC_ANNEX_A:
2097         case SYS_DVBC_ANNEX_B:
2098         case SYS_DVBC_ANNEX_C:
2099                 cxd2841er_read_packet_errors_c(priv, &ucblocks);
2100                 break;
2101         case SYS_DVBT:
2102                 cxd2841er_read_packet_errors_t(priv, &ucblocks);
2103                 break;
2104         case SYS_DVBT2:
2105                 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
2106                 break;
2107         case SYS_ISDBT:
2108                 cxd2841er_read_packet_errors_i(priv, &ucblocks);
2109                 break;
2110         default:
2111                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2112                 return;
2113         }
2114         dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks);
2115
2116         p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2117         p->block_error.stat[0].uvalue = ucblocks;
2118 }
2119
2120 static int cxd2841er_dvbt2_set_profile(
2121         struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
2122 {
2123         u8 tune_mode;
2124         u8 seq_not2d_time;
2125
2126         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2127         switch (profile) {
2128         case DVBT2_PROFILE_BASE:
2129                 tune_mode = 0x01;
2130                 /* Set early unlock time */
2131                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
2132                 break;
2133         case DVBT2_PROFILE_LITE:
2134                 tune_mode = 0x05;
2135                 /* Set early unlock time */
2136                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2137                 break;
2138         case DVBT2_PROFILE_ANY:
2139                 tune_mode = 0x00;
2140                 /* Set early unlock time */
2141                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2142                 break;
2143         default:
2144                 return -EINVAL;
2145         }
2146         /* Set SLV-T Bank : 0x2E */
2147         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
2148         /* Set profile and tune mode */
2149         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
2150         /* Set SLV-T Bank : 0x2B */
2151         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2152         /* Set early unlock detection time */
2153         cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
2154         return 0;
2155 }
2156
2157 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
2158                                           u8 is_auto, u8 plp_id)
2159 {
2160         if (is_auto) {
2161                 dev_dbg(&priv->i2c->dev,
2162                         "%s() using auto PLP selection\n", __func__);
2163         } else {
2164                 dev_dbg(&priv->i2c->dev,
2165                         "%s() using manual PLP selection, ID %d\n",
2166                         __func__, plp_id);
2167         }
2168         /* Set SLV-T Bank : 0x23 */
2169         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2170         if (!is_auto) {
2171                 /* Manual PLP selection mode. Set the data PLP Id. */
2172                 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
2173         }
2174         /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
2175         cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
2176         return 0;
2177 }
2178
2179 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
2180                                                 u32 bandwidth)
2181 {
2182         u32 iffreq, ifhz;
2183         u8 data[MAX_WRITE_REGSIZE];
2184
2185         static const uint8_t nominalRate8bw[3][5] = {
2186                 /* TRCG Nominal Rate [37:0] */
2187                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2188                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2189                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2190         };
2191
2192         static const uint8_t nominalRate7bw[3][5] = {
2193                 /* TRCG Nominal Rate [37:0] */
2194                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2195                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2196                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2197         };
2198
2199         static const uint8_t nominalRate6bw[3][5] = {
2200                 /* TRCG Nominal Rate [37:0] */
2201                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2202                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2203                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2204         };
2205
2206         static const uint8_t nominalRate5bw[3][5] = {
2207                 /* TRCG Nominal Rate [37:0] */
2208                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2209                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2210                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2211         };
2212
2213         static const uint8_t nominalRate17bw[3][5] = {
2214                 /* TRCG Nominal Rate [37:0] */
2215                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
2216                 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
2217                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}  /* 41MHz XTal */
2218         };
2219
2220         static const uint8_t itbCoef8bw[3][14] = {
2221                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2222                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2223                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
2224                         0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2225                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2226                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2227         };
2228
2229         static const uint8_t itbCoef7bw[3][14] = {
2230                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2231                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2232                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
2233                         0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2234                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2235                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2236         };
2237
2238         static const uint8_t itbCoef6bw[3][14] = {
2239                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2240                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2241                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2242                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2243                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2244                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2245         };
2246
2247         static const uint8_t itbCoef5bw[3][14] = {
2248                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2249                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2250                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2251                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2252                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2253                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2254         };
2255
2256         static const uint8_t itbCoef17bw[3][14] = {
2257                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2258                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
2259                 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
2260                         0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal   */
2261                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2262                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}  /* 41MHz XTal   */
2263         };
2264
2265         /* Set SLV-T Bank : 0x20 */
2266         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2267
2268         switch (bandwidth) {
2269         case 8000000:
2270                 /* <Timing Recovery setting> */
2271                 cxd2841er_write_regs(priv, I2C_SLVT,
2272                                 0x9F, nominalRate8bw[priv->xtal], 5);
2273
2274                 /* Set SLV-T Bank : 0x27 */
2275                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2276                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2277                                 0x7a, 0x00, 0x0f);
2278
2279                 /* Set SLV-T Bank : 0x10 */
2280                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2281
2282                 /* Group delay equaliser settings for
2283                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2284                  */
2285                 if (priv->flags & CXD2841ER_ASCOT)
2286                         cxd2841er_write_regs(priv, I2C_SLVT,
2287                                 0xA6, itbCoef8bw[priv->xtal], 14);
2288                 /* <IF freq setting> */
2289                 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2290                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2291                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2292                 data[1] = (u8)((iffreq >> 8) & 0xff);
2293                 data[2] = (u8)(iffreq & 0xff);
2294                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2295                 /* System bandwidth setting */
2296                 cxd2841er_set_reg_bits(
2297                                 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2298                 break;
2299         case 7000000:
2300                 /* <Timing Recovery setting> */
2301                 cxd2841er_write_regs(priv, I2C_SLVT,
2302                                 0x9F, nominalRate7bw[priv->xtal], 5);
2303
2304                 /* Set SLV-T Bank : 0x27 */
2305                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2306                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2307                                 0x7a, 0x00, 0x0f);
2308
2309                 /* Set SLV-T Bank : 0x10 */
2310                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2311
2312                 /* Group delay equaliser settings for
2313                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2314                  */
2315                 if (priv->flags & CXD2841ER_ASCOT)
2316                         cxd2841er_write_regs(priv, I2C_SLVT,
2317                                 0xA6, itbCoef7bw[priv->xtal], 14);
2318                 /* <IF freq setting> */
2319                 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2320                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2321                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2322                 data[1] = (u8)((iffreq >> 8) & 0xff);
2323                 data[2] = (u8)(iffreq & 0xff);
2324                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2325                 /* System bandwidth setting */
2326                 cxd2841er_set_reg_bits(
2327                                 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2328                 break;
2329         case 6000000:
2330                 /* <Timing Recovery setting> */
2331                 cxd2841er_write_regs(priv, I2C_SLVT,
2332                                 0x9F, nominalRate6bw[priv->xtal], 5);
2333
2334                 /* Set SLV-T Bank : 0x27 */
2335                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2336                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2337                                 0x7a, 0x00, 0x0f);
2338
2339                 /* Set SLV-T Bank : 0x10 */
2340                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2341
2342                 /* Group delay equaliser settings for
2343                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2344                  */
2345                 if (priv->flags & CXD2841ER_ASCOT)
2346                         cxd2841er_write_regs(priv, I2C_SLVT,
2347                                 0xA6, itbCoef6bw[priv->xtal], 14);
2348                 /* <IF freq setting> */
2349                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2350                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2351                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2352                 data[1] = (u8)((iffreq >> 8) & 0xff);
2353                 data[2] = (u8)(iffreq & 0xff);
2354                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2355                 /* System bandwidth setting */
2356                 cxd2841er_set_reg_bits(
2357                                 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2358                 break;
2359         case 5000000:
2360                 /* <Timing Recovery setting> */
2361                 cxd2841er_write_regs(priv, I2C_SLVT,
2362                                 0x9F, nominalRate5bw[priv->xtal], 5);
2363
2364                 /* Set SLV-T Bank : 0x27 */
2365                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2366                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2367                                 0x7a, 0x00, 0x0f);
2368
2369                 /* Set SLV-T Bank : 0x10 */
2370                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2371
2372                 /* Group delay equaliser settings for
2373                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2374                  */
2375                 if (priv->flags & CXD2841ER_ASCOT)
2376                         cxd2841er_write_regs(priv, I2C_SLVT,
2377                                 0xA6, itbCoef5bw[priv->xtal], 14);
2378                 /* <IF freq setting> */
2379                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2380                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2381                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2382                 data[1] = (u8)((iffreq >> 8) & 0xff);
2383                 data[2] = (u8)(iffreq & 0xff);
2384                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2385                 /* System bandwidth setting */
2386                 cxd2841er_set_reg_bits(
2387                                 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2388                 break;
2389         case 1712000:
2390                 /* <Timing Recovery setting> */
2391                 cxd2841er_write_regs(priv, I2C_SLVT,
2392                                 0x9F, nominalRate17bw[priv->xtal], 5);
2393
2394                 /* Set SLV-T Bank : 0x27 */
2395                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2396                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2397                                 0x7a, 0x03, 0x0f);
2398
2399                 /* Set SLV-T Bank : 0x10 */
2400                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2401
2402                 /* Group delay equaliser settings for
2403                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2404                  */
2405                 if (priv->flags & CXD2841ER_ASCOT)
2406                         cxd2841er_write_regs(priv, I2C_SLVT,
2407                                 0xA6, itbCoef17bw[priv->xtal], 14);
2408                 /* <IF freq setting> */
2409                 ifhz = cxd2841er_get_if_hz(priv, 3500000);
2410                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2411                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2412                 data[1] = (u8)((iffreq >> 8) & 0xff);
2413                 data[2] = (u8)(iffreq & 0xff);
2414                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2415                 /* System bandwidth setting */
2416                 cxd2841er_set_reg_bits(
2417                                 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
2418                 break;
2419         default:
2420                 return -EINVAL;
2421         }
2422         return 0;
2423 }
2424
2425 static int cxd2841er_sleep_tc_to_active_t_band(
2426                 struct cxd2841er_priv *priv, u32 bandwidth)
2427 {
2428         u8 data[MAX_WRITE_REGSIZE];
2429         u32 iffreq, ifhz;
2430         static const u8 nominalRate8bw[3][5] = {
2431                 /* TRCG Nominal Rate [37:0] */
2432                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2433                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2434                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2435         };
2436         static const u8 nominalRate7bw[3][5] = {
2437                 /* TRCG Nominal Rate [37:0] */
2438                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2439                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2440                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2441         };
2442         static const u8 nominalRate6bw[3][5] = {
2443                 /* TRCG Nominal Rate [37:0] */
2444                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2445                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2446                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2447         };
2448         static const u8 nominalRate5bw[3][5] = {
2449                 /* TRCG Nominal Rate [37:0] */
2450                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2451                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2452                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2453         };
2454
2455         static const u8 itbCoef8bw[3][14] = {
2456                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2457                         0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2458                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2459                         0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2460                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2461                         0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2462         };
2463         static const u8 itbCoef7bw[3][14] = {
2464                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2465                         0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2466                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2467                         0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2468                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2469                         0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2470         };
2471         static const u8 itbCoef6bw[3][14] = {
2472                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2473                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2474                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2475                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2476                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2477                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2478         };
2479         static const u8 itbCoef5bw[3][14] = {
2480                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2481                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2482                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2483                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2484                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2485                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2486         };
2487
2488         /* Set SLV-T Bank : 0x13 */
2489         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2490         /* Echo performance optimization setting */
2491         data[0] = 0x01;
2492         data[1] = 0x14;
2493         cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2494
2495         /* Set SLV-T Bank : 0x10 */
2496         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2497
2498         switch (bandwidth) {
2499         case 8000000:
2500                 /* <Timing Recovery setting> */
2501                 cxd2841er_write_regs(priv, I2C_SLVT,
2502                                 0x9F, nominalRate8bw[priv->xtal], 5);
2503                 /* Group delay equaliser settings for
2504                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2505                 */
2506                 if (priv->flags & CXD2841ER_ASCOT)
2507                         cxd2841er_write_regs(priv, I2C_SLVT,
2508                                 0xA6, itbCoef8bw[priv->xtal], 14);
2509                 /* <IF freq setting> */
2510                 ifhz = cxd2841er_get_if_hz(priv, 4800000);
2511                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2512                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2513                 data[1] = (u8)((iffreq >> 8) & 0xff);
2514                 data[2] = (u8)(iffreq & 0xff);
2515                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2516                 /* System bandwidth setting */
2517                 cxd2841er_set_reg_bits(
2518                         priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2519
2520                 /* Demod core latency setting */
2521                 if (priv->xtal == SONY_XTAL_24000) {
2522                         data[0] = 0x15;
2523                         data[1] = 0x28;
2524                 } else {
2525                         data[0] = 0x01;
2526                         data[1] = 0xE0;
2527                 }
2528                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2529
2530                 /* Notch filter setting */
2531                 data[0] = 0x01;
2532                 data[1] = 0x02;
2533                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2534                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2535                 break;
2536         case 7000000:
2537                 /* <Timing Recovery setting> */
2538                 cxd2841er_write_regs(priv, I2C_SLVT,
2539                                 0x9F, nominalRate7bw[priv->xtal], 5);
2540                 /* Group delay equaliser settings for
2541                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2542                 */
2543                 if (priv->flags & CXD2841ER_ASCOT)
2544                         cxd2841er_write_regs(priv, I2C_SLVT,
2545                                 0xA6, itbCoef7bw[priv->xtal], 14);
2546                 /* <IF freq setting> */
2547                 ifhz = cxd2841er_get_if_hz(priv, 4200000);
2548                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2549                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2550                 data[1] = (u8)((iffreq >> 8) & 0xff);
2551                 data[2] = (u8)(iffreq & 0xff);
2552                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2553                 /* System bandwidth setting */
2554                 cxd2841er_set_reg_bits(
2555                         priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2556
2557                 /* Demod core latency setting */
2558                 if (priv->xtal == SONY_XTAL_24000) {
2559                         data[0] = 0x1F;
2560                         data[1] = 0xF8;
2561                 } else {
2562                         data[0] = 0x12;
2563                         data[1] = 0xF8;
2564                 }
2565                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2566
2567                 /* Notch filter setting */
2568                 data[0] = 0x00;
2569                 data[1] = 0x03;
2570                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2571                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2572                 break;
2573         case 6000000:
2574                 /* <Timing Recovery setting> */
2575                 cxd2841er_write_regs(priv, I2C_SLVT,
2576                                 0x9F, nominalRate6bw[priv->xtal], 5);
2577                 /* Group delay equaliser settings for
2578                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2579                 */
2580                 if (priv->flags & CXD2841ER_ASCOT)
2581                         cxd2841er_write_regs(priv, I2C_SLVT,
2582                                 0xA6, itbCoef6bw[priv->xtal], 14);
2583                 /* <IF freq setting> */
2584                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2585                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2586                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2587                 data[1] = (u8)((iffreq >> 8) & 0xff);
2588                 data[2] = (u8)(iffreq & 0xff);
2589                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2590                 /* System bandwidth setting */
2591                 cxd2841er_set_reg_bits(
2592                         priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2593
2594                 /* Demod core latency setting */
2595                 if (priv->xtal == SONY_XTAL_24000) {
2596                         data[0] = 0x25;
2597                         data[1] = 0x4C;
2598                 } else {
2599                         data[0] = 0x1F;
2600                         data[1] = 0xDC;
2601                 }
2602                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2603
2604                 /* Notch filter setting */
2605                 data[0] = 0x00;
2606                 data[1] = 0x03;
2607                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2608                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2609                 break;
2610         case 5000000:
2611                 /* <Timing Recovery setting> */
2612                 cxd2841er_write_regs(priv, I2C_SLVT,
2613                                 0x9F, nominalRate5bw[priv->xtal], 5);
2614                 /* Group delay equaliser settings for
2615                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2616                 */
2617                 if (priv->flags & CXD2841ER_ASCOT)
2618                         cxd2841er_write_regs(priv, I2C_SLVT,
2619                                 0xA6, itbCoef5bw[priv->xtal], 14);
2620                 /* <IF freq setting> */
2621                 ifhz = cxd2841er_get_if_hz(priv, 3600000);
2622                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2623                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2624                 data[1] = (u8)((iffreq >> 8) & 0xff);
2625                 data[2] = (u8)(iffreq & 0xff);
2626                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2627                 /* System bandwidth setting */
2628                 cxd2841er_set_reg_bits(
2629                         priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2630
2631                 /* Demod core latency setting */
2632                 if (priv->xtal == SONY_XTAL_24000) {
2633                         data[0] = 0x2C;
2634                         data[1] = 0xC2;
2635                 } else {
2636                         data[0] = 0x26;
2637                         data[1] = 0x3C;
2638                 }
2639                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2640
2641                 /* Notch filter setting */
2642                 data[0] = 0x00;
2643                 data[1] = 0x03;
2644                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2645                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2646                 break;
2647         }
2648
2649         return 0;
2650 }
2651
2652 static int cxd2841er_sleep_tc_to_active_i_band(
2653                 struct cxd2841er_priv *priv, u32 bandwidth)
2654 {
2655         u32 iffreq, ifhz;
2656         u8 data[3];
2657
2658         /* TRCG Nominal Rate */
2659         static const u8 nominalRate8bw[3][5] = {
2660                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2661                 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2662                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2663         };
2664
2665         static const u8 nominalRate7bw[3][5] = {
2666                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2667                 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2668                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2669         };
2670
2671         static const u8 nominalRate6bw[3][5] = {
2672                 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2673                 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2674                 {0x14, 0x2E, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2675         };
2676
2677         static const u8 itbCoef8bw[3][14] = {
2678                 {0x00}, /* 20.5MHz XTal */
2679                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2680                         0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2681                 {0x0}, /* 41MHz XTal   */
2682         };
2683
2684         static const u8 itbCoef7bw[3][14] = {
2685                 {0x00}, /* 20.5MHz XTal */
2686                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2687                         0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2688                 {0x00}, /* 41MHz XTal   */
2689         };
2690
2691         static const u8 itbCoef6bw[3][14] = {
2692                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2693                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2694                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2695                         0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal   */
2696                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2697                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal   */
2698         };
2699
2700         dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2701         /* Set SLV-T Bank : 0x10 */
2702         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2703
2704         /*  20.5/41MHz Xtal support is not available
2705          *  on ISDB-T 7MHzBW and 8MHzBW
2706         */
2707         if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2708                 dev_err(&priv->i2c->dev,
2709                         "%s(): bandwidth %d supported only for 24MHz xtal\n",
2710                         __func__, bandwidth);
2711                 return -EINVAL;
2712         }
2713
2714         switch (bandwidth) {
2715         case 8000000:
2716                 /* TRCG Nominal Rate */
2717                 cxd2841er_write_regs(priv, I2C_SLVT,
2718                                 0x9F, nominalRate8bw[priv->xtal], 5);
2719                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2720                 if (priv->flags & CXD2841ER_ASCOT)
2721                         cxd2841er_write_regs(priv, I2C_SLVT,
2722                                 0xA6, itbCoef8bw[priv->xtal], 14);
2723
2724                 /* IF freq setting */
2725                 ifhz = cxd2841er_get_if_hz(priv, 4750000);
2726                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2727                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2728                 data[1] = (u8)((iffreq >> 8) & 0xff);
2729                 data[2] = (u8)(iffreq & 0xff);
2730                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2731
2732                 /* System bandwidth setting */
2733                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2734
2735                 /* Demod core latency setting */
2736                 data[0] = 0x13;
2737                 data[1] = 0xFC;
2738                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2739
2740                 /* Acquisition optimization setting */
2741                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2742                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2743                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2744                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2745                 break;
2746         case 7000000:
2747                 /* TRCG Nominal Rate */
2748                 cxd2841er_write_regs(priv, I2C_SLVT,
2749                                 0x9F, nominalRate7bw[priv->xtal], 5);
2750                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2751                 if (priv->flags & CXD2841ER_ASCOT)
2752                         cxd2841er_write_regs(priv, I2C_SLVT,
2753                                 0xA6, itbCoef7bw[priv->xtal], 14);
2754
2755                 /* IF freq setting */
2756                 ifhz = cxd2841er_get_if_hz(priv, 4150000);
2757                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2758                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2759                 data[1] = (u8)((iffreq >> 8) & 0xff);
2760                 data[2] = (u8)(iffreq & 0xff);
2761                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2762
2763                 /* System bandwidth setting */
2764                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2765
2766                 /* Demod core latency setting */
2767                 data[0] = 0x1A;
2768                 data[1] = 0xFA;
2769                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2770
2771                 /* Acquisition optimization setting */
2772                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2773                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2774                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2775                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2776                 break;
2777         case 6000000:
2778                 /* TRCG Nominal Rate */
2779                 cxd2841er_write_regs(priv, I2C_SLVT,
2780                                 0x9F, nominalRate6bw[priv->xtal], 5);
2781                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2782                 if (priv->flags & CXD2841ER_ASCOT)
2783                         cxd2841er_write_regs(priv, I2C_SLVT,
2784                                 0xA6, itbCoef6bw[priv->xtal], 14);
2785
2786                 /* IF freq setting */
2787                 ifhz = cxd2841er_get_if_hz(priv, 3550000);
2788                 iffreq = cxd2841er_calc_iffreq_xtal(priv->xtal, ifhz);
2789                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2790                 data[1] = (u8)((iffreq >> 8) & 0xff);
2791                 data[2] = (u8)(iffreq & 0xff);
2792                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2793
2794                 /* System bandwidth setting */
2795                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2796
2797                 /* Demod core latency setting */
2798                 if (priv->xtal == SONY_XTAL_24000) {
2799                         data[0] = 0x1F;
2800                         data[1] = 0x79;
2801                 } else {
2802                         data[0] = 0x1A;
2803                         data[1] = 0xE2;
2804                 }
2805                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2806
2807                 /* Acquisition optimization setting */
2808                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2809                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2810                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2811                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2812                 break;
2813         default:
2814                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2815                                 __func__, bandwidth);
2816                 return -EINVAL;
2817         }
2818         return 0;
2819 }
2820
2821 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2822                                                u32 bandwidth)
2823 {
2824         u8 bw7_8mhz_b10_a6[] = {
2825                 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2826                 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2827         u8 bw6mhz_b10_a6[] = {
2828                 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2829                 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2830         u8 b10_b6[3];
2831         u32 iffreq, ifhz;
2832
2833         if (bandwidth != 6000000 &&
2834                         bandwidth != 7000000 &&
2835                         bandwidth != 8000000) {
2836                 dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n",
2837                                 __func__, bandwidth);
2838                 bandwidth = 8000000;
2839         }
2840
2841         dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
2842         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2843         switch (bandwidth) {
2844         case 8000000:
2845         case 7000000:
2846                 if (priv->flags & CXD2841ER_ASCOT)
2847                         cxd2841er_write_regs(
2848                                 priv, I2C_SLVT, 0xa6,
2849                                 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2850                 ifhz = cxd2841er_get_if_hz(priv, 4900000);
2851                 iffreq = cxd2841er_calc_iffreq(ifhz);
2852                 break;
2853         case 6000000:
2854                 if (priv->flags & CXD2841ER_ASCOT)
2855                         cxd2841er_write_regs(
2856                                 priv, I2C_SLVT, 0xa6,
2857                                 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2858                 ifhz = cxd2841er_get_if_hz(priv, 3700000);
2859                 iffreq = cxd2841er_calc_iffreq(ifhz);
2860                 break;
2861         default:
2862                 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2863                         __func__, bandwidth);
2864                 return -EINVAL;
2865         }
2866         /* <IF freq setting> */
2867         b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2868         b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2869         b10_b6[2] = (u8)(iffreq & 0xff);
2870         cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2871         /* Set SLV-T Bank : 0x11 */
2872         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2873         switch (bandwidth) {
2874         case 8000000:
2875         case 7000000:
2876                 cxd2841er_set_reg_bits(
2877                         priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2878                 break;
2879         case 6000000:
2880                 cxd2841er_set_reg_bits(
2881                         priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2882                 break;
2883         }
2884         /* Set SLV-T Bank : 0x40 */
2885         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2886         switch (bandwidth) {
2887         case 8000000:
2888                 cxd2841er_set_reg_bits(
2889                         priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2890                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x3e);
2891                 break;
2892         case 7000000:
2893                 cxd2841er_set_reg_bits(
2894                         priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2895                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0xd6);
2896                 break;
2897         case 6000000:
2898                 cxd2841er_set_reg_bits(
2899                         priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2900                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x6e);
2901                 break;
2902         }
2903         return 0;
2904 }
2905
2906 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2907                                           u32 bandwidth)
2908 {
2909         u8 data[2] = { 0x09, 0x54 };
2910         u8 data24m[3] = {0xDC, 0x6C, 0x00};
2911
2912         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2913         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2914         /* Set SLV-X Bank : 0x00 */
2915         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2916         /* Set demod mode */
2917         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2918         /* Set SLV-T Bank : 0x00 */
2919         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2920         /* Enable demod clock */
2921         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2922         /* Disable RF level monitor */
2923         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2924         /* Enable ADC clock */
2925         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2926         /* Enable ADC 1 */
2927         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2928         /* Enable ADC 2 & 3 */
2929         if (priv->xtal == SONY_XTAL_41000) {
2930                 data[0] = 0x0A;
2931                 data[1] = 0xD4;
2932         }
2933         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2934         /* Enable ADC 4 */
2935         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2936         /* Set SLV-T Bank : 0x10 */
2937         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2938         /* IFAGC gain settings */
2939         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2940         /* Set SLV-T Bank : 0x11 */
2941         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2942         /* BBAGC TARGET level setting */
2943         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2944         /* Set SLV-T Bank : 0x10 */
2945         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2946         /* ASCOT setting */
2947         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
2948                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
2949         /* Set SLV-T Bank : 0x18 */
2950         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2951         /* Pre-RS BER moniter setting */
2952         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2953         /* FEC Auto Recovery setting */
2954         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2955         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2956         /* Set SLV-T Bank : 0x00 */
2957         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2958         /* TSIF setting */
2959         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2960         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2961
2962         if (priv->xtal == SONY_XTAL_24000) {
2963                 /* Set SLV-T Bank : 0x10 */
2964                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2965                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2966                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2967                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2968         }
2969
2970         cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2971         /* Set SLV-T Bank : 0x00 */
2972         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2973         /* Disable HiZ Setting 1 */
2974         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2975         /* Disable HiZ Setting 2 */
2976         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2977         priv->state = STATE_ACTIVE_TC;
2978         return 0;
2979 }
2980
2981 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2982                                            u32 bandwidth)
2983 {
2984         u8 data[MAX_WRITE_REGSIZE];
2985
2986         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2987         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2988         /* Set SLV-X Bank : 0x00 */
2989         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2990         /* Set demod mode */
2991         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2992         /* Set SLV-T Bank : 0x00 */
2993         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2994         /* Enable demod clock */
2995         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2996         /* Disable RF level monitor */
2997         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
2998         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2999         /* Enable ADC clock */
3000         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3001         /* Enable ADC 1 */
3002         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3003
3004         if (priv->xtal == SONY_XTAL_41000) {
3005                 data[0] = 0x0A;
3006                 data[1] = 0xD4;
3007         } else {
3008                 data[0] = 0x09;
3009                 data[1] = 0x54;
3010         }
3011
3012         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3013         /* Enable ADC 4 */
3014         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3015         /* Set SLV-T Bank : 0x10 */
3016         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3017         /* IFAGC gain settings */
3018         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
3019         /* Set SLV-T Bank : 0x11 */
3020         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3021         /* BBAGC TARGET level setting */
3022         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
3023         /* Set SLV-T Bank : 0x10 */
3024         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3025         /* ASCOT setting */
3026         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3027                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3028         /* Set SLV-T Bank : 0x20 */
3029         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3030         /* Acquisition optimization setting */
3031         cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
3032         /* Set SLV-T Bank : 0x2b */
3033         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3034         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
3035         /* Set SLV-T Bank : 0x23 */
3036         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
3037         /* L1 Control setting */
3038         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
3039         /* Set SLV-T Bank : 0x00 */
3040         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3041         /* TSIF setting */
3042         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3043         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3044         /* DVB-T2 initial setting */
3045         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
3046         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
3047         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
3048         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
3049         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
3050         /* Set SLV-T Bank : 0x2a */
3051         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
3052         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
3053         /* Set SLV-T Bank : 0x2b */
3054         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
3055         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
3056
3057         /* 24MHz Xtal setting */
3058         if (priv->xtal == SONY_XTAL_24000) {
3059                 /* Set SLV-T Bank : 0x11 */
3060                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3061                 data[0] = 0xEB;
3062                 data[1] = 0x03;
3063                 data[2] = 0x3B;
3064                 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
3065
3066                 /* Set SLV-T Bank : 0x20 */
3067                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3068                 data[0] = 0x5E;
3069                 data[1] = 0x5E;
3070                 data[2] = 0x47;
3071                 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
3072
3073                 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
3074
3075                 data[0] = 0x3F;
3076                 data[1] = 0xFF;
3077                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
3078
3079                 /* Set SLV-T Bank : 0x24 */
3080                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
3081                 data[0] = 0x0B;
3082                 data[1] = 0x72;
3083                 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
3084
3085                 data[0] = 0x93;
3086                 data[1] = 0xF3;
3087                 data[2] = 0x00;
3088                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
3089
3090                 data[0] = 0x05;
3091                 data[1] = 0xB8;
3092                 data[2] = 0xD8;
3093                 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
3094
3095                 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
3096
3097                 /* Set SLV-T Bank : 0x25 */
3098                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
3099                 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
3100
3101                 /* Set SLV-T Bank : 0x27 */
3102                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
3103                 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
3104
3105                 /* Set SLV-T Bank : 0x2B */
3106                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
3107                 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
3108                 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
3109
3110                 /* Set SLV-T Bank : 0x2D */
3111                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
3112                 data[0] = 0x89;
3113                 data[1] = 0x89;
3114                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
3115
3116                 /* Set SLV-T Bank : 0x5E */
3117                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
3118                 data[0] = 0x24;
3119                 data[1] = 0x95;
3120                 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
3121         }
3122
3123         cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
3124
3125         /* Set SLV-T Bank : 0x00 */
3126         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3127         /* Disable HiZ Setting 1 */
3128         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3129         /* Disable HiZ Setting 2 */
3130         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3131         priv->state = STATE_ACTIVE_TC;
3132         return 0;
3133 }
3134
3135 /* ISDB-Tb part */
3136 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
3137                 u32 bandwidth)
3138 {
3139         u8 data[2] = { 0x09, 0x54 };
3140         u8 data24m[2] = {0x60, 0x00};
3141         u8 data24m2[3] = {0xB7, 0x1B, 0x00};
3142
3143         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3144         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
3145         /* Set SLV-X Bank : 0x00 */
3146         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3147         /* Set demod mode */
3148         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
3149         /* Set SLV-T Bank : 0x00 */
3150         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3151         /* Enable demod clock */
3152         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3153         /* Enable RF level monitor */
3154         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
3155         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
3156         /* Enable ADC clock */
3157         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3158         /* Enable ADC 1 */
3159         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3160         /* xtal freq 20.5MHz or 24M */
3161         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3162         /* Enable ADC 4 */
3163         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3164         /* ASCOT setting */
3165         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3166                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3167         /* FEC Auto Recovery setting */
3168         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
3169         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
3170         /* ISDB-T initial setting */
3171         /* Set SLV-T Bank : 0x00 */
3172         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3173         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
3174         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
3175         /* Set SLV-T Bank : 0x10 */
3176         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3177         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
3178         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
3179         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
3180         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
3181         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
3182         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
3183         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
3184         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
3185         /* Set SLV-T Bank : 0x15 */
3186         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
3187         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
3188         /* Set SLV-T Bank : 0x1E */
3189         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
3190         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
3191         /* Set SLV-T Bank : 0x63 */
3192         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
3193         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
3194
3195         /* for xtal 24MHz */
3196         /* Set SLV-T Bank : 0x10 */
3197         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3198         cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
3199         /* Set SLV-T Bank : 0x60 */
3200         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
3201         cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
3202
3203         cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
3204         /* Set SLV-T Bank : 0x00 */
3205         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3206         /* Disable HiZ Setting 1 */
3207         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3208         /* Disable HiZ Setting 2 */
3209         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3210         priv->state = STATE_ACTIVE_TC;
3211         return 0;
3212 }
3213
3214 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
3215                                           u32 bandwidth)
3216 {
3217         u8 data[2] = { 0x09, 0x54 };
3218
3219         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3220         cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
3221         /* Set SLV-X Bank : 0x00 */
3222         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3223         /* Set demod mode */
3224         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
3225         /* Set SLV-T Bank : 0x00 */
3226         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3227         /* Enable demod clock */
3228         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3229         /* Disable RF level monitor */
3230         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
3231         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
3232         /* Enable ADC clock */
3233         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3234         /* Enable ADC 1 */
3235         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3236         /* xtal freq 20.5MHz */
3237         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3238         /* Enable ADC 4 */
3239         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3240         /* Set SLV-T Bank : 0x10 */
3241         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3242         /* IFAGC gain settings */
3243         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
3244         /* Set SLV-T Bank : 0x11 */
3245         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3246         /* BBAGC TARGET level setting */
3247         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
3248         /* Set SLV-T Bank : 0x10 */
3249         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3250         /* ASCOT setting */
3251         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5,
3252                 ((priv->flags & CXD2841ER_ASCOT) ? 0x01 : 0x00), 0x01);
3253         /* Set SLV-T Bank : 0x40 */
3254         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
3255         /* Demod setting */
3256         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
3257         /* Set SLV-T Bank : 0x00 */
3258         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3259         /* TSIF setting */
3260         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3261         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3262
3263         cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
3264         /* Set SLV-T Bank : 0x00 */
3265         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3266         /* Disable HiZ Setting 1 */
3267         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3268         /* Disable HiZ Setting 2 */
3269         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3270         priv->state = STATE_ACTIVE_TC;
3271         return 0;
3272 }
3273
3274 static int cxd2841er_get_frontend(struct dvb_frontend *fe,
3275                                   struct dtv_frontend_properties *p)
3276 {
3277         enum fe_status status = 0;
3278         struct cxd2841er_priv *priv = fe->demodulator_priv;
3279
3280         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3281         if (priv->state == STATE_ACTIVE_S)
3282                 cxd2841er_read_status_s(fe, &status);
3283         else if (priv->state == STATE_ACTIVE_TC)
3284                 cxd2841er_read_status_tc(fe, &status);
3285
3286         if (priv->state == STATE_ACTIVE_TC || priv->state == STATE_ACTIVE_S)
3287                 cxd2841er_read_signal_strength(fe);
3288         else
3289                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3290
3291         if (status & FE_HAS_LOCK) {
3292                 cxd2841er_read_snr(fe);
3293                 cxd2841er_read_ucblocks(fe);
3294
3295                 cxd2841er_read_ber(fe);
3296         } else {
3297                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3298                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3299                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3300                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3301         }
3302         return 0;
3303 }
3304
3305 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
3306 {
3307         int ret = 0, i, timeout, carr_offset;
3308         enum fe_status status;
3309         struct cxd2841er_priv *priv = fe->demodulator_priv;
3310         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3311         u32 symbol_rate = p->symbol_rate/1000;
3312
3313         dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
3314                 __func__,
3315                 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
3316                  p->frequency, symbol_rate, priv->xtal);
3317
3318         if (priv->flags & CXD2841ER_EARLY_TUNE)
3319                 cxd2841er_tuner_set(fe);
3320
3321         switch (priv->state) {
3322         case STATE_SLEEP_S:
3323                 ret = cxd2841er_sleep_s_to_active_s(
3324                         priv, p->delivery_system, symbol_rate);
3325                 break;
3326         case STATE_ACTIVE_S:
3327                 ret = cxd2841er_retune_active(priv, p);
3328                 break;
3329         default:
3330                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3331                         __func__, priv->state);
3332                 ret = -EINVAL;
3333                 goto done;
3334         }
3335         if (ret) {
3336                 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3337                 goto done;
3338         }
3339
3340         if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3341                 cxd2841er_tuner_set(fe);
3342
3343         cxd2841er_tune_done(priv);
3344         timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3345         for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
3346                 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3347                         (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3348                 cxd2841er_read_status_s(fe, &status);
3349                 if (status & FE_HAS_LOCK)
3350                         break;
3351         }
3352         if (status & FE_HAS_LOCK) {
3353                 if (cxd2841er_get_carrier_offset_s_s2(
3354                                 priv, &carr_offset)) {
3355                         ret = -EINVAL;
3356                         goto done;
3357                 }
3358                 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3359                         __func__, carr_offset);
3360         }
3361 done:
3362         /* Reset stats */
3363         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3364         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3365         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3366         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3367         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3368
3369         return ret;
3370 }
3371
3372 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3373 {
3374         int ret = 0, timeout;
3375         enum fe_status status;
3376         struct cxd2841er_priv *priv = fe->demodulator_priv;
3377         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3378
3379         dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3380                  __func__, p->delivery_system, p->bandwidth_hz);
3381
3382         if (priv->flags & CXD2841ER_EARLY_TUNE)
3383                 cxd2841er_tuner_set(fe);
3384
3385         /* deconfigure/put demod to sleep on delsys switch if active */
3386         if (priv->state == STATE_ACTIVE_TC &&
3387             priv->system != p->delivery_system) {
3388                 dev_dbg(&priv->i2c->dev, "%s(): old_delsys=%d, new_delsys=%d -> sleep\n",
3389                          __func__, priv->system, p->delivery_system);
3390                 cxd2841er_sleep_tc(fe);
3391         }
3392
3393         if (p->delivery_system == SYS_DVBT) {
3394                 priv->system = SYS_DVBT;
3395                 switch (priv->state) {
3396                 case STATE_SLEEP_TC:
3397                         ret = cxd2841er_sleep_tc_to_active_t(
3398                                 priv, p->bandwidth_hz);
3399                         break;
3400                 case STATE_ACTIVE_TC:
3401                         ret = cxd2841er_retune_active(priv, p);
3402                         break;
3403                 default:
3404                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3405                                 __func__, priv->state);
3406                         ret = -EINVAL;
3407                 }
3408         } else if (p->delivery_system == SYS_DVBT2) {
3409                 priv->system = SYS_DVBT2;
3410                 cxd2841er_dvbt2_set_plp_config(priv,
3411                         (int)(p->stream_id > 255), p->stream_id);
3412                 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3413                 switch (priv->state) {
3414                 case STATE_SLEEP_TC:
3415                         ret = cxd2841er_sleep_tc_to_active_t2(priv,
3416                                 p->bandwidth_hz);
3417                         break;
3418                 case STATE_ACTIVE_TC:
3419                         ret = cxd2841er_retune_active(priv, p);
3420                         break;
3421                 default:
3422                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3423                                 __func__, priv->state);
3424                         ret = -EINVAL;
3425                 }
3426         } else if (p->delivery_system == SYS_ISDBT) {
3427                 priv->system = SYS_ISDBT;
3428                 switch (priv->state) {
3429                 case STATE_SLEEP_TC:
3430                         ret = cxd2841er_sleep_tc_to_active_i(
3431                                         priv, p->bandwidth_hz);
3432                         break;
3433                 case STATE_ACTIVE_TC:
3434                         ret = cxd2841er_retune_active(priv, p);
3435                         break;
3436                 default:
3437                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3438                                         __func__, priv->state);
3439                         ret = -EINVAL;
3440                 }
3441         } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3442                         p->delivery_system == SYS_DVBC_ANNEX_C) {
3443                 priv->system = SYS_DVBC_ANNEX_A;
3444                 /* correct bandwidth */
3445                 if (p->bandwidth_hz != 6000000 &&
3446                                 p->bandwidth_hz != 7000000 &&
3447                                 p->bandwidth_hz != 8000000) {
3448                         p->bandwidth_hz = 8000000;
3449                         dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3450                                         __func__, p->bandwidth_hz);
3451                 }
3452
3453                 switch (priv->state) {
3454                 case STATE_SLEEP_TC:
3455                         ret = cxd2841er_sleep_tc_to_active_c(
3456                                 priv, p->bandwidth_hz);
3457                         break;
3458                 case STATE_ACTIVE_TC:
3459                         ret = cxd2841er_retune_active(priv, p);
3460                         break;
3461                 default:
3462                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3463                                 __func__, priv->state);
3464                         ret = -EINVAL;
3465                 }
3466         } else {
3467                 dev_dbg(&priv->i2c->dev,
3468                         "%s(): invalid delivery system %d\n",
3469                         __func__, p->delivery_system);
3470                 ret = -EINVAL;
3471         }
3472         if (ret)
3473                 goto done;
3474
3475         if (!(priv->flags & CXD2841ER_EARLY_TUNE))
3476                 cxd2841er_tuner_set(fe);
3477
3478         cxd2841er_tune_done(priv);
3479
3480         if (priv->flags & CXD2841ER_NO_WAIT_LOCK)
3481                 goto done;
3482
3483         timeout = 2500;
3484         while (timeout > 0) {
3485                 ret = cxd2841er_read_status_tc(fe, &status);
3486                 if (ret)
3487                         goto done;
3488                 if (status & FE_HAS_LOCK)
3489                         break;
3490                 msleep(20);
3491                 timeout -= 20;
3492         }
3493         if (timeout < 0)
3494                 dev_dbg(&priv->i2c->dev,
3495                         "%s(): LOCK wait timeout\n", __func__);
3496 done:
3497         return ret;
3498 }
3499
3500 static int cxd2841er_tune_s(struct dvb_frontend *fe,
3501                             bool re_tune,
3502                             unsigned int mode_flags,
3503                             unsigned int *delay,
3504                             enum fe_status *status)
3505 {
3506         int ret, carrier_offset;
3507         struct cxd2841er_priv *priv = fe->demodulator_priv;
3508         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3509
3510         dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3511         if (re_tune) {
3512                 ret = cxd2841er_set_frontend_s(fe);
3513                 if (ret)
3514                         return ret;
3515                 cxd2841er_read_status_s(fe, status);
3516                 if (*status & FE_HAS_LOCK) {
3517                         if (cxd2841er_get_carrier_offset_s_s2(
3518                                         priv, &carrier_offset))
3519                                 return -EINVAL;
3520                         p->frequency += carrier_offset;
3521                         ret = cxd2841er_set_frontend_s(fe);
3522                         if (ret)
3523                                 return ret;
3524                 }
3525         }
3526         *delay = HZ / 5;
3527         return cxd2841er_read_status_s(fe, status);
3528 }
3529
3530 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3531                              bool re_tune,
3532                              unsigned int mode_flags,
3533                              unsigned int *delay,
3534                              enum fe_status *status)
3535 {
3536         int ret, carrier_offset;
3537         struct cxd2841er_priv *priv = fe->demodulator_priv;
3538         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3539
3540         dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3541                         re_tune, p->bandwidth_hz);
3542         if (re_tune) {
3543                 ret = cxd2841er_set_frontend_tc(fe);
3544                 if (ret)
3545                         return ret;
3546                 cxd2841er_read_status_tc(fe, status);
3547                 if (*status & FE_HAS_LOCK) {
3548                         switch (priv->system) {
3549                         case SYS_ISDBT:
3550                                 ret = cxd2841er_get_carrier_offset_i(
3551                                                 priv, p->bandwidth_hz,
3552                                                 &carrier_offset);
3553                                 if (ret)
3554                                         return ret;
3555                                 break;
3556                         case SYS_DVBT:
3557                                 ret = cxd2841er_get_carrier_offset_t(
3558                                         priv, p->bandwidth_hz,
3559                                         &carrier_offset);
3560                                 if (ret)
3561                                         return ret;
3562                                 break;
3563                         case SYS_DVBT2:
3564                                 ret = cxd2841er_get_carrier_offset_t2(
3565                                         priv, p->bandwidth_hz,
3566                                         &carrier_offset);
3567                                 if (ret)
3568                                         return ret;
3569                                 break;
3570                         case SYS_DVBC_ANNEX_A:
3571                                 ret = cxd2841er_get_carrier_offset_c(
3572                                         priv, &carrier_offset);
3573                                 if (ret)
3574                                         return ret;
3575                                 break;
3576                         default:
3577                                 dev_dbg(&priv->i2c->dev,
3578                                         "%s(): invalid delivery system %d\n",
3579                                         __func__, priv->system);
3580                                 return -EINVAL;
3581                         }
3582                         dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3583                                 __func__, carrier_offset);
3584                         p->frequency += carrier_offset;
3585                         ret = cxd2841er_set_frontend_tc(fe);
3586                         if (ret)
3587                                 return ret;
3588                 }
3589         }
3590         *delay = HZ / 5;
3591         return cxd2841er_read_status_tc(fe, status);
3592 }
3593
3594 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3595 {
3596         struct cxd2841er_priv *priv = fe->demodulator_priv;
3597
3598         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3599         cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3600         cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3601         return 0;
3602 }
3603
3604 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3605 {
3606         struct cxd2841er_priv *priv = fe->demodulator_priv;
3607
3608         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3609
3610         if (priv->state == STATE_ACTIVE_TC) {
3611                 switch (priv->system) {
3612                 case SYS_DVBT:
3613                         cxd2841er_active_t_to_sleep_tc(priv);
3614                         break;
3615                 case SYS_DVBT2:
3616                         cxd2841er_active_t2_to_sleep_tc(priv);
3617                         break;
3618                 case SYS_ISDBT:
3619                         cxd2841er_active_i_to_sleep_tc(priv);
3620                         break;
3621                 case SYS_DVBC_ANNEX_A:
3622                         cxd2841er_active_c_to_sleep_tc(priv);
3623                         break;
3624                 default:
3625                         dev_warn(&priv->i2c->dev,
3626                                 "%s(): unknown delivery system %d\n",
3627                                 __func__, priv->system);
3628                 }
3629         }
3630         if (priv->state != STATE_SLEEP_TC) {
3631                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3632                         __func__, priv->state);
3633                 return -EINVAL;
3634         }
3635         return 0;
3636 }
3637
3638 static int cxd2841er_shutdown_tc(struct dvb_frontend *fe)
3639 {
3640         struct cxd2841er_priv *priv = fe->demodulator_priv;
3641
3642         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3643
3644         if (!cxd2841er_sleep_tc(fe))
3645                 cxd2841er_sleep_tc_to_shutdown(priv);
3646         return 0;
3647 }
3648
3649 static int cxd2841er_send_burst(struct dvb_frontend *fe,
3650                                 enum fe_sec_mini_cmd burst)
3651 {
3652         u8 data;
3653         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3654
3655         dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3656                 (burst == SEC_MINI_A ? "A" : "B"));
3657         if (priv->state != STATE_SLEEP_S &&
3658                         priv->state != STATE_ACTIVE_S) {
3659                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3660                         __func__, priv->state);
3661                 return -EINVAL;
3662         }
3663         data = (burst == SEC_MINI_A ? 0 : 1);
3664         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3665         cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3666         cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3667         return 0;
3668 }
3669
3670 static int cxd2841er_set_tone(struct dvb_frontend *fe,
3671                               enum fe_sec_tone_mode tone)
3672 {
3673         u8 data;
3674         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3675
3676         dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3677                 (tone == SEC_TONE_ON ? "On" : "Off"));
3678         if (priv->state != STATE_SLEEP_S &&
3679                         priv->state != STATE_ACTIVE_S) {
3680                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3681                         __func__, priv->state);
3682                 return -EINVAL;
3683         }
3684         data = (tone == SEC_TONE_ON ? 1 : 0);
3685         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3686         cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3687         return 0;
3688 }
3689
3690 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3691                                      struct dvb_diseqc_master_cmd *cmd)
3692 {
3693         int i;
3694         u8 data[12];
3695         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3696
3697         if (priv->state != STATE_SLEEP_S &&
3698                         priv->state != STATE_ACTIVE_S) {
3699                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3700                         __func__, priv->state);
3701                 return -EINVAL;
3702         }
3703         dev_dbg(&priv->i2c->dev,
3704                 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3705         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3706         /* DiDEqC enable */
3707         cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3708         /* cmd1 length & data */
3709         cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3710         memset(data, 0, sizeof(data));
3711         for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3712                 data[i] = cmd->msg[i];
3713         cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3714         /* repeat count for cmd1 */
3715         cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3716         /* repeat count for cmd2: always 0 */
3717         cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3718         /* start transmit */
3719         cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3720         /* wait for 1 sec timeout */
3721         for (i = 0; i < 50; i++) {
3722                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3723                 if (!data[0]) {
3724                         dev_dbg(&priv->i2c->dev,
3725                                 "%s(): DiSEqC cmd has been sent\n", __func__);
3726                         return 0;
3727                 }
3728                 msleep(20);
3729         }
3730         dev_dbg(&priv->i2c->dev,
3731                 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3732         return -ETIMEDOUT;
3733 }
3734
3735 static void cxd2841er_release(struct dvb_frontend *fe)
3736 {
3737         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3738
3739         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3740         kfree(priv);
3741 }
3742
3743 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3744 {
3745         struct cxd2841er_priv *priv = fe->demodulator_priv;
3746
3747         dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3748         cxd2841er_set_reg_bits(
3749                 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3750         return 0;
3751 }
3752
3753 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3754 {
3755         struct cxd2841er_priv *priv = fe->demodulator_priv;
3756
3757         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3758         return DVBFE_ALGO_HW;
3759 }
3760
3761 static void cxd2841er_init_stats(struct dvb_frontend *fe)
3762 {
3763         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3764
3765         p->strength.len = 1;
3766         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3767         p->cnr.len = 1;
3768         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3769         p->block_error.len = 1;
3770         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3771         p->post_bit_error.len = 1;
3772         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3773         p->post_bit_count.len = 1;
3774         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3775 }
3776
3777
3778 static int cxd2841er_init_s(struct dvb_frontend *fe)
3779 {
3780         struct cxd2841er_priv *priv = fe->demodulator_priv;
3781
3782         /* sanity. force demod to SHUTDOWN state */
3783         if (priv->state == STATE_SLEEP_S) {
3784                 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3785                                 __func__);
3786                 cxd2841er_sleep_s_to_shutdown(priv);
3787         } else if (priv->state == STATE_ACTIVE_S) {
3788                 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3789                                 __func__);
3790                 cxd2841er_active_s_to_sleep_s(priv);
3791                 cxd2841er_sleep_s_to_shutdown(priv);
3792         }
3793
3794         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3795         cxd2841er_shutdown_to_sleep_s(priv);
3796         /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3797         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3798         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3799
3800         cxd2841er_init_stats(fe);
3801
3802         return 0;
3803 }
3804
3805 static int cxd2841er_init_tc(struct dvb_frontend *fe)
3806 {
3807         struct cxd2841er_priv *priv = fe->demodulator_priv;
3808         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3809
3810         dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3811                         __func__, p->bandwidth_hz);
3812         cxd2841er_shutdown_to_sleep_tc(priv);
3813         /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 (0 for NO_AGCNEG */
3814         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3815         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb,
3816                 ((priv->flags & CXD2841ER_NO_AGCNEG) ? 0x00 : 0x40), 0x40);
3817         /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3818         cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3819         /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3820         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3821         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4,
3822                 ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80);
3823
3824         /* clear TSCFG bits 3+4 */
3825         if (priv->flags & CXD2841ER_TSBITS)
3826                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18);
3827
3828         cxd2841er_init_stats(fe);
3829
3830         return 0;
3831 }
3832
3833 static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3834 static struct dvb_frontend_ops cxd2841er_t_c_ops;
3835
3836 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3837                                              struct i2c_adapter *i2c,
3838                                              u8 system)
3839 {
3840         u8 chip_id = 0;
3841         const char *type;
3842         const char *name;
3843         struct cxd2841er_priv *priv = NULL;
3844
3845         /* allocate memory for the internal state */
3846         priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3847         if (!priv)
3848                 return NULL;
3849         priv->i2c = i2c;
3850         priv->config = cfg;
3851         priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3852         priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
3853         priv->xtal = cfg->xtal;
3854         priv->flags = cfg->flags;
3855         priv->frontend.demodulator_priv = priv;
3856         dev_info(&priv->i2c->dev,
3857                 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3858                 __func__, priv->i2c,
3859                 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3860         chip_id = cxd2841er_chip_id(priv);
3861         switch (chip_id) {
3862         case CXD2837ER_CHIP_ID:
3863                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3864                                 "Sony CXD2837ER DVB-T/T2/C demodulator");
3865                 name = "CXD2837ER";
3866                 type = "C/T/T2";
3867                 break;
3868         case CXD2838ER_CHIP_ID:
3869                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3870                                 "Sony CXD2838ER ISDB-T demodulator");
3871                 cxd2841er_t_c_ops.delsys[0] = SYS_ISDBT;
3872                 cxd2841er_t_c_ops.delsys[1] = SYS_UNDEFINED;
3873                 cxd2841er_t_c_ops.delsys[2] = SYS_UNDEFINED;
3874                 name = "CXD2838ER";
3875                 type = "ISDB-T";
3876                 break;
3877         case CXD2841ER_CHIP_ID:
3878                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3879                                 "Sony CXD2841ER DVB-T/T2/C demodulator");
3880                 name = "CXD2841ER";
3881                 type = "T/T2/C/ISDB-T";
3882                 break;
3883         case CXD2843ER_CHIP_ID:
3884                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3885                                 "Sony CXD2843ER DVB-T/T2/C/C2 demodulator");
3886                 name = "CXD2843ER";
3887                 type = "C/C2/T/T2";
3888                 break;
3889         case CXD2854ER_CHIP_ID:
3890                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3891                                 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3892                 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3893                 name = "CXD2854ER";
3894                 type = "C/C2/T/T2/ISDB-T";
3895                 break;
3896         default:
3897                 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3898                                 __func__, chip_id);
3899                 priv->frontend.demodulator_priv = NULL;
3900                 kfree(priv);
3901                 return NULL;
3902         }
3903
3904         /* create dvb_frontend */
3905         if (system == SYS_DVBS) {
3906                 memcpy(&priv->frontend.ops,
3907                         &cxd2841er_dvbs_s2_ops,
3908                         sizeof(struct dvb_frontend_ops));
3909                 type = "S/S2";
3910         } else {
3911                 memcpy(&priv->frontend.ops,
3912                         &cxd2841er_t_c_ops,
3913                         sizeof(struct dvb_frontend_ops));
3914         }
3915
3916         dev_info(&priv->i2c->dev,
3917                 "%s(): attaching %s DVB-%s frontend\n",
3918                 __func__, name, type);
3919         dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3920                 __func__, chip_id);
3921         return &priv->frontend;
3922 }
3923
3924 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3925                                         struct i2c_adapter *i2c)
3926 {
3927         return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3928 }
3929 EXPORT_SYMBOL(cxd2841er_attach_s);
3930
3931 struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
3932                                         struct i2c_adapter *i2c)
3933 {
3934         return cxd2841er_attach(cfg, i2c, 0);
3935 }
3936 EXPORT_SYMBOL(cxd2841er_attach_t_c);
3937
3938 static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3939         .delsys = { SYS_DVBS, SYS_DVBS2 },
3940         .info = {
3941                 .name           = "Sony CXD2841ER DVB-S/S2 demodulator",
3942                 .frequency_min  = 500000,
3943                 .frequency_max  = 2500000,
3944                 .frequency_stepsize     = 0,
3945                 .symbol_rate_min = 1000000,
3946                 .symbol_rate_max = 45000000,
3947                 .symbol_rate_tolerance = 500,
3948                 .caps = FE_CAN_INVERSION_AUTO |
3949                         FE_CAN_FEC_AUTO |
3950                         FE_CAN_QPSK,
3951         },
3952         .init = cxd2841er_init_s,
3953         .sleep = cxd2841er_sleep_s,
3954         .release = cxd2841er_release,
3955         .set_frontend = cxd2841er_set_frontend_s,
3956         .get_frontend = cxd2841er_get_frontend,
3957         .read_status = cxd2841er_read_status_s,
3958         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3959         .get_frontend_algo = cxd2841er_get_algo,
3960         .set_tone = cxd2841er_set_tone,
3961         .diseqc_send_burst = cxd2841er_send_burst,
3962         .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3963         .tune = cxd2841er_tune_s
3964 };
3965
3966 static struct dvb_frontend_ops cxd2841er_t_c_ops = {
3967         .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
3968         .info = {
3969                 .name   = "", /* will set in attach function */
3970                 .caps = FE_CAN_FEC_1_2 |
3971                         FE_CAN_FEC_2_3 |
3972                         FE_CAN_FEC_3_4 |
3973                         FE_CAN_FEC_5_6 |
3974                         FE_CAN_FEC_7_8 |
3975                         FE_CAN_FEC_AUTO |
3976                         FE_CAN_QPSK |
3977                         FE_CAN_QAM_16 |
3978                         FE_CAN_QAM_32 |
3979                         FE_CAN_QAM_64 |
3980                         FE_CAN_QAM_128 |
3981                         FE_CAN_QAM_256 |
3982                         FE_CAN_QAM_AUTO |
3983                         FE_CAN_TRANSMISSION_MODE_AUTO |
3984                         FE_CAN_GUARD_INTERVAL_AUTO |
3985                         FE_CAN_HIERARCHY_AUTO |
3986                         FE_CAN_MUTE_TS |
3987                         FE_CAN_2G_MODULATION,
3988                 .frequency_min = 42000000,
3989                 .frequency_max = 1002000000,
3990                 .symbol_rate_min = 870000,
3991                 .symbol_rate_max = 11700000
3992         },
3993         .init = cxd2841er_init_tc,
3994         .sleep = cxd2841er_shutdown_tc,
3995         .release = cxd2841er_release,
3996         .set_frontend = cxd2841er_set_frontend_tc,
3997         .get_frontend = cxd2841er_get_frontend,
3998         .read_status = cxd2841er_read_status_tc,
3999         .tune = cxd2841er_tune_tc,
4000         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
4001         .get_frontend_algo = cxd2841er_get_algo
4002 };
4003
4004 MODULE_DESCRIPTION("Sony CXD2837/38/41/43/54ER DVB-C/C2/T/T2/S/S2 demodulator driver");
4005 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
4006 MODULE_LICENSE("GPL");