4 * Sony digital demodulator driver for
5 * CXD2841ER - DVB-S/S2/T/T2/C/C2
6 * CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
8 * Copyright 2012 Sony Corporation
9 * Copyright (C) 2014 NetUP Inc.
10 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
11 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/string.h>
27 #include <linux/slab.h>
28 #include <linux/bitops.h>
29 #include <linux/math64.h>
30 #include <linux/log2.h>
31 #include <linux/dynamic_debug.h>
34 #include "dvb_frontend.h"
35 #include "cxd2841er.h"
36 #include "cxd2841er_priv.h"
38 #define MAX_WRITE_REGSIZE 16
39 #define LOG2_E_100X 144
41 /* DVB-C constellation */
42 enum sony_dvbc_constellation_t {
43 SONY_DVBC_CONSTELLATION_16QAM,
44 SONY_DVBC_CONSTELLATION_32QAM,
45 SONY_DVBC_CONSTELLATION_64QAM,
46 SONY_DVBC_CONSTELLATION_128QAM,
47 SONY_DVBC_CONSTELLATION_256QAM
50 enum cxd2841er_state {
58 struct cxd2841er_priv {
59 struct dvb_frontend frontend;
60 struct i2c_adapter *i2c;
63 const struct cxd2841er_config *config;
64 enum cxd2841er_state state;
66 enum cxd2841er_xtal xtal;
70 static const struct cxd2841er_cnr_data s_cn_data[] = {
71 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
72 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
73 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
74 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
75 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
76 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
77 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
78 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
79 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
80 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
81 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
82 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
83 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
84 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
85 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
86 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
87 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
88 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
89 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
90 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
91 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
92 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
93 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
94 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
95 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
96 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
97 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
98 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
99 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
100 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
101 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
102 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
103 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
104 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
105 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
106 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
107 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
108 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
109 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
110 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
111 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
112 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
113 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
114 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
115 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
116 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
117 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
118 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
119 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
120 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
121 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
122 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
123 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
124 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
125 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
126 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
127 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
128 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
129 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
130 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
131 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
132 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
133 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
134 { 0x0015, 19900 }, { 0x0014, 20000 },
137 static const struct cxd2841er_cnr_data s2_cn_data[] = {
138 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
139 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
140 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
141 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
142 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
143 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
144 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
145 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
146 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
147 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
148 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
149 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
150 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
151 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
152 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
153 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
154 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
155 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
156 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
157 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
158 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
159 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
160 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
161 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
162 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
163 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
164 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
165 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
166 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
167 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
168 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
169 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
170 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
171 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
172 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
173 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
174 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
175 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
176 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
177 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
178 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
179 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
180 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
181 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
182 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
183 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
184 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
185 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
186 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
187 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
188 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
189 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
190 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
191 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
192 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
193 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
194 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
195 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
196 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
197 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
198 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
199 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
200 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
201 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
204 #define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
205 #define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
206 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
207 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
209 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv);
210 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv);
212 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
213 u8 addr, u8 reg, u8 write,
214 const u8 *data, u32 len)
216 dev_dbg(&priv->i2c->dev,
217 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
218 (write == 0 ? "read" : "write"), addr, reg, len);
219 print_hex_dump_bytes("cxd2841er: I2C data: ",
220 DUMP_PREFIX_OFFSET, data, len);
223 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
224 u8 addr, u8 reg, const u8 *data, u32 len)
227 u8 buf[MAX_WRITE_REGSIZE + 1];
228 u8 i2c_addr = (addr == I2C_SLVX ?
229 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
230 struct i2c_msg msg[1] = {
239 if (len + 1 >= sizeof(buf)) {
240 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
245 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
247 memcpy(&buf[1], data, len);
249 ret = i2c_transfer(priv->i2c, msg, 1);
250 if (ret >= 0 && ret != 1)
253 dev_warn(&priv->i2c->dev,
254 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
255 KBUILD_MODNAME, ret, i2c_addr, reg, len);
261 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
262 u8 addr, u8 reg, u8 val)
264 u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
266 return cxd2841er_write_regs(priv, addr, reg, &tmp, 1);
269 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
270 u8 addr, u8 reg, u8 *val, u32 len)
273 u8 i2c_addr = (addr == I2C_SLVX ?
274 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
275 struct i2c_msg msg[2] = {
289 ret = i2c_transfer(priv->i2c, &msg[0], 1);
290 if (ret >= 0 && ret != 1)
293 dev_warn(&priv->i2c->dev,
294 "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
295 KBUILD_MODNAME, ret, i2c_addr, reg);
298 ret = i2c_transfer(priv->i2c, &msg[1], 1);
299 if (ret >= 0 && ret != 1)
302 dev_warn(&priv->i2c->dev,
303 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
304 KBUILD_MODNAME, ret, i2c_addr, reg);
307 cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
311 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
312 u8 addr, u8 reg, u8 *val)
314 return cxd2841er_read_regs(priv, addr, reg, val, 1);
317 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
318 u8 addr, u8 reg, u8 data, u8 mask)
324 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
327 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
329 return cxd2841er_write_reg(priv, addr, reg, data);
332 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
336 u8 data[3] = {0, 0, 0};
338 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
340 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
341 * = ((symbolRateKSps * 2^14) + 500) / 1000
342 * = ((symbolRateKSps * 16384) + 500) / 1000
344 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
345 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
346 dev_err(&priv->i2c->dev,
347 "%s(): reg_value is out of range\n", __func__);
350 data[0] = (u8)((reg_value >> 16) & 0x0F);
351 data[1] = (u8)((reg_value >> 8) & 0xFF);
352 data[2] = (u8)(reg_value & 0xFF);
353 /* Set SLV-T Bank : 0xAE */
354 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
355 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
359 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
362 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
363 u8 system, u32 symbol_rate)
366 u8 data[4] = { 0, 0, 0, 0 };
368 if (priv->state != STATE_SLEEP_S) {
369 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
370 __func__, (int)priv->state);
373 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
374 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
376 if (system == SYS_DVBS) {
378 } else if (system == SYS_DVBS2) {
381 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
385 /* Set SLV-X Bank : 0x00 */
386 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
387 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
390 /* Set SLV-T Bank : 0x00 */
391 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
392 /* Enable S/S2 auto detection 1 */
393 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
394 /* Set SLV-T Bank : 0xAE */
395 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
396 /* Enable S/S2 auto detection 2 */
397 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
398 /* Set SLV-T Bank : 0x00 */
399 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
400 /* Enable demod clock */
401 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
402 /* Enable ADC clock */
403 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
405 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
407 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
408 /* Set SLV-X Bank : 0x00 */
409 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
411 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
412 /* Set SLV-T Bank : 0xA3 */
413 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
414 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
419 /* Set SLV-T Bank : 0xAB */
420 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
421 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
426 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
429 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
430 /* Set demod parameter */
431 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
434 /* Set SLV-T Bank : 0x00 */
435 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
436 /* disable Hi-Z setting 1 */
437 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
438 /* disable Hi-Z setting 2 */
439 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
440 priv->state = STATE_ACTIVE_S;
444 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
447 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
450 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
453 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
456 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
458 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
460 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
462 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
463 struct dtv_frontend_properties *p)
465 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
466 if (priv->state != STATE_ACTIVE_S &&
467 priv->state != STATE_ACTIVE_TC) {
468 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
469 __func__, priv->state);
472 /* Set SLV-T Bank : 0x00 */
473 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
474 /* disable TS output */
475 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
476 if (priv->state == STATE_ACTIVE_S)
477 return cxd2841er_dvbs2_set_symbol_rate(
478 priv, p->symbol_rate / 1000);
479 else if (priv->state == STATE_ACTIVE_TC) {
480 switch (priv->system) {
482 return cxd2841er_sleep_tc_to_active_t_band(
483 priv, p->bandwidth_hz);
485 return cxd2841er_sleep_tc_to_active_t2_band(
486 priv, p->bandwidth_hz);
487 case SYS_DVBC_ANNEX_A:
488 return cxd2841er_sleep_tc_to_active_c_band(
489 priv, p->bandwidth_hz);
491 cxd2841er_active_i_to_sleep_tc(priv);
492 cxd2841er_sleep_tc_to_shutdown(priv);
493 cxd2841er_shutdown_to_sleep_tc(priv);
494 return cxd2841er_sleep_tc_to_active_i(
495 priv, p->bandwidth_hz);
498 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
499 __func__, priv->system);
503 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
505 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
506 if (priv->state != STATE_ACTIVE_S) {
507 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
508 __func__, priv->state);
511 /* Set SLV-T Bank : 0x00 */
512 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
513 /* disable TS output */
514 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
515 /* enable Hi-Z setting 1 */
516 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
517 /* enable Hi-Z setting 2 */
518 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
519 /* Set SLV-X Bank : 0x00 */
520 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
522 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
523 /* Set SLV-T Bank : 0x00 */
524 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
525 /* disable ADC clock */
526 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
528 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
530 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
532 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
533 /* disable demod clock */
534 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
535 /* Set SLV-T Bank : 0xAE */
536 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
537 /* disable S/S2 auto detection1 */
538 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
539 /* Set SLV-T Bank : 0x00 */
540 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
541 /* disable S/S2 auto detection2 */
542 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
543 priv->state = STATE_SLEEP_S;
547 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
549 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
550 if (priv->state != STATE_SLEEP_S) {
551 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
552 __func__, priv->state);
555 /* Set SLV-T Bank : 0x00 */
556 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
558 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
560 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
561 /* Set SLV-X Bank : 0x00 */
562 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
563 /* Disable oscillator */
564 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
566 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
567 priv->state = STATE_SHUTDOWN;
571 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
573 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
574 if (priv->state != STATE_SLEEP_TC) {
575 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
576 __func__, priv->state);
579 /* Set SLV-X Bank : 0x00 */
580 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
581 /* Disable oscillator */
582 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
584 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
585 priv->state = STATE_SHUTDOWN;
589 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
591 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
592 if (priv->state != STATE_ACTIVE_TC) {
593 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
594 __func__, priv->state);
597 /* Set SLV-T Bank : 0x00 */
598 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
599 /* disable TS output */
600 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
601 /* enable Hi-Z setting 1 */
602 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
603 /* enable Hi-Z setting 2 */
604 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
605 /* Set SLV-X Bank : 0x00 */
606 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
608 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
609 /* Set SLV-T Bank : 0x00 */
610 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
612 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
614 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
615 /* Disable ADC clock */
616 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
617 /* Disable RF level monitor */
618 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
619 /* Disable demod clock */
620 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
621 priv->state = STATE_SLEEP_TC;
625 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
627 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
628 if (priv->state != STATE_ACTIVE_TC) {
629 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
630 __func__, priv->state);
633 /* Set SLV-T Bank : 0x00 */
634 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
635 /* disable TS output */
636 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
637 /* enable Hi-Z setting 1 */
638 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
639 /* enable Hi-Z setting 2 */
640 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
641 /* Cancel DVB-T2 setting */
642 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
643 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
644 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
645 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
646 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
647 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
648 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
649 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
650 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
651 /* Set SLV-X Bank : 0x00 */
652 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
654 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
655 /* Set SLV-T Bank : 0x00 */
656 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
658 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
660 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
661 /* Disable ADC clock */
662 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
663 /* Disable RF level monitor */
664 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
665 /* Disable demod clock */
666 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
667 priv->state = STATE_SLEEP_TC;
671 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
673 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
674 if (priv->state != STATE_ACTIVE_TC) {
675 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
676 __func__, priv->state);
679 /* Set SLV-T Bank : 0x00 */
680 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
681 /* disable TS output */
682 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
683 /* enable Hi-Z setting 1 */
684 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
685 /* enable Hi-Z setting 2 */
686 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
687 /* Cancel DVB-C setting */
688 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
689 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
690 /* Set SLV-X Bank : 0x00 */
691 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
693 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
694 /* Set SLV-T Bank : 0x00 */
695 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
697 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
699 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
700 /* Disable ADC clock */
701 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
702 /* Disable RF level monitor */
703 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
704 /* Disable demod clock */
705 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
706 priv->state = STATE_SLEEP_TC;
710 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
712 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
713 if (priv->state != STATE_ACTIVE_TC) {
714 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
715 __func__, priv->state);
718 /* Set SLV-T Bank : 0x00 */
719 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
720 /* disable TS output */
721 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
722 /* enable Hi-Z setting 1 */
723 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
724 /* enable Hi-Z setting 2 */
725 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
727 /* TODO: Cancel demod parameter */
729 /* Set SLV-X Bank : 0x00 */
730 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
732 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
733 /* Set SLV-T Bank : 0x00 */
734 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
736 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
738 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
739 /* Disable ADC clock */
740 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
741 /* Disable RF level monitor */
742 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
743 /* Disable demod clock */
744 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
745 priv->state = STATE_SLEEP_TC;
749 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
751 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
752 if (priv->state != STATE_SHUTDOWN) {
753 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
754 __func__, priv->state);
757 /* Set SLV-X Bank : 0x00 */
758 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
759 /* Clear all demodulator registers */
760 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
761 usleep_range(3000, 5000);
762 /* Set SLV-X Bank : 0x00 */
763 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
764 /* Set demod SW reset */
765 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
767 switch (priv->xtal) {
768 case SONY_XTAL_20500:
769 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
771 case SONY_XTAL_24000:
772 /* Select demod frequency */
773 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
774 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
776 case SONY_XTAL_41000:
777 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
780 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
781 __func__, priv->xtal);
786 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
787 /* Clear demod SW reset */
788 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
789 usleep_range(1000, 2000);
790 /* Set SLV-T Bank : 0x00 */
791 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
793 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
795 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
797 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
798 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
800 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
801 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
802 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
803 priv->state = STATE_SLEEP_S;
807 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
811 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
812 if (priv->state != STATE_SHUTDOWN) {
813 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
814 __func__, priv->state);
817 /* Set SLV-X Bank : 0x00 */
818 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
819 /* Clear all demodulator registers */
820 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
821 usleep_range(3000, 5000);
822 /* Set SLV-X Bank : 0x00 */
823 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
824 /* Set demod SW reset */
825 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
826 /* Select ADC clock mode */
827 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
829 switch (priv->xtal) {
830 case SONY_XTAL_20500:
833 case SONY_XTAL_24000:
834 /* Select demod frequency */
835 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
838 case SONY_XTAL_41000:
839 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
843 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
844 /* Clear demod SW reset */
845 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
846 usleep_range(1000, 2000);
847 /* Set SLV-T Bank : 0x00 */
848 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
850 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
851 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
853 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
854 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
855 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
856 priv->state = STATE_SLEEP_TC;
860 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
862 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
863 /* Set SLV-T Bank : 0x00 */
864 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
866 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
867 /* Enable TS output */
868 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
872 /* Set TS parallel mode */
873 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
876 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
878 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
879 /* Set SLV-T Bank : 0x00 */
880 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
881 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
882 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
883 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
884 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
885 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
888 * slave Bank Addr Bit default Name
889 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
891 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
893 * Disable TS IF Clock
894 * slave Bank Addr Bit default Name
895 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
897 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
899 * slave Bank Addr Bit default Name
900 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
902 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
905 * slave Bank Addr Bit default Name
906 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
908 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
910 if (system == SYS_DVBT) {
911 /* Enable parity period for DVB-T */
912 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
913 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
914 } else if (system == SYS_DVBC_ANNEX_A) {
915 /* Enable parity period for DVB-C */
916 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
917 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
921 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
925 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
926 if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
927 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
928 else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
929 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
934 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
935 enum fe_status *status)
938 struct cxd2841er_priv *priv = fe->demodulator_priv;
940 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
942 if (priv->state != STATE_ACTIVE_S) {
943 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
944 __func__, priv->state);
947 /* Set SLV-T Bank : 0xA0 */
948 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
950 * slave Bank Addr Bit Signal name
951 * <SLV-T> A0h 11h [2] ITSLOCK
953 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, ®);
955 *status = FE_HAS_SIGNAL
961 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
965 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
966 u8 *sync, u8 *tslock, u8 *unlock)
970 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
971 if (priv->state != STATE_ACTIVE_TC)
973 if (priv->system == SYS_DVBT) {
974 /* Set SLV-T Bank : 0x10 */
975 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
977 /* Set SLV-T Bank : 0x20 */
978 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
980 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
981 if ((data & 0x07) == 0x07) {
982 dev_dbg(&priv->i2c->dev,
983 "%s(): invalid hardware state detected\n", __func__);
988 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
989 *tslock = ((data & 0x20) ? 1 : 0);
990 *unlock = ((data & 0x10) ? 1 : 0);
995 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
999 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1000 if (priv->state != STATE_ACTIVE_TC)
1002 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1003 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
1004 if ((data & 0x01) == 0) {
1007 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1008 *tslock = ((data & 0x20) ? 1 : 0);
1013 static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
1014 u8 *sync, u8 *tslock, u8 *unlock)
1018 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1019 if (priv->state != STATE_ACTIVE_TC)
1021 /* Set SLV-T Bank : 0x60 */
1022 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1023 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1024 dev_dbg(&priv->i2c->dev,
1025 "%s(): lock=0x%x\n", __func__, data);
1026 *sync = ((data & 0x02) ? 1 : 0);
1027 *tslock = ((data & 0x01) ? 1 : 0);
1028 *unlock = ((data & 0x10) ? 1 : 0);
1032 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1033 enum fe_status *status)
1039 struct cxd2841er_priv *priv = fe->demodulator_priv;
1042 if (priv->state == STATE_ACTIVE_TC) {
1043 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1044 ret = cxd2841er_read_status_t_t2(
1045 priv, &sync, &tslock, &unlock);
1051 *status = FE_HAS_SIGNAL |
1056 *status |= FE_HAS_LOCK;
1057 } else if (priv->system == SYS_ISDBT) {
1058 ret = cxd2841er_read_status_i(
1059 priv, &sync, &tslock, &unlock);
1065 *status = FE_HAS_SIGNAL |
1070 *status |= FE_HAS_LOCK;
1071 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1072 ret = cxd2841er_read_status_c(priv, &tslock);
1076 *status = FE_HAS_SIGNAL |
1084 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1088 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1094 s32 temp_div, temp_q, temp_r;
1096 if (priv->state != STATE_ACTIVE_S) {
1097 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1098 __func__, priv->state);
1102 * Get High Sampling Rate mode
1103 * slave Bank Addr Bit Signal name
1104 * <SLV-T> A0h 10h [0] ITRL_LOCK
1106 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1107 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1108 if (data[0] & 0x01) {
1110 * slave Bank Addr Bit Signal name
1111 * <SLV-T> A0h 50h [4] IHSMODE
1113 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1114 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1116 dev_dbg(&priv->i2c->dev,
1117 "%s(): unable to detect sampling rate mode\n",
1122 * slave Bank Addr Bit Signal name
1123 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
1124 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
1125 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
1127 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1128 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1129 (((u32)data[1] & 0xFF) << 8) |
1130 ((u32)data[2] & 0xFF), 20);
1131 temp_div = (is_hs_mode ? 1048576 : 1572864);
1132 if (cfrl_ctrlval > 0) {
1133 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1136 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1139 if (temp_r >= temp_div / 2)
1141 if (cfrl_ctrlval > 0)
1147 static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1148 u32 bandwidth, int *offset)
1152 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1153 if (priv->state != STATE_ACTIVE_TC) {
1154 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1155 __func__, priv->state);
1158 if (priv->system != SYS_ISDBT) {
1159 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1160 __func__, priv->system);
1163 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1164 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1165 *offset = -1 * sign_extend32(
1166 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1167 ((u32)data[2] << 8) | (u32)data[3], 29);
1169 switch (bandwidth) {
1171 *offset = -1 * ((*offset) * 8/264);
1174 *offset = -1 * ((*offset) * 8/231);
1177 *offset = -1 * ((*offset) * 8/198);
1180 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1181 __func__, bandwidth);
1185 dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1186 __func__, bandwidth, *offset);
1191 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1192 u32 bandwidth, int *offset)
1196 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1197 if (priv->state != STATE_ACTIVE_TC) {
1198 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1199 __func__, priv->state);
1202 if (priv->system != SYS_DVBT) {
1203 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1204 __func__, priv->system);
1207 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1208 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1209 *offset = -1 * sign_extend32(
1210 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1211 ((u32)data[2] << 8) | (u32)data[3], 29);
1212 *offset *= (bandwidth / 1000000);
1217 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1218 u32 bandwidth, int *offset)
1222 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1223 if (priv->state != STATE_ACTIVE_TC) {
1224 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1225 __func__, priv->state);
1228 if (priv->system != SYS_DVBT2) {
1229 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1230 __func__, priv->system);
1233 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1234 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1235 *offset = -1 * sign_extend32(
1236 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1237 ((u32)data[2] << 8) | (u32)data[3], 27);
1238 switch (bandwidth) {
1246 *offset *= (bandwidth / 1000000);
1250 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1251 __func__, bandwidth);
1257 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1262 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1263 if (priv->state != STATE_ACTIVE_TC) {
1264 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1265 __func__, priv->state);
1268 if (priv->system != SYS_DVBC_ANNEX_A) {
1269 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1270 __func__, priv->system);
1273 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1274 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1275 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1276 | (u32)data[1], 13), 16384);
1280 static int cxd2841er_read_packet_errors_c(
1281 struct cxd2841er_priv *priv, u32 *penum)
1286 if (priv->state != STATE_ACTIVE_TC) {
1287 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1288 __func__, priv->state);
1291 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1292 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1294 *penum = ((u32)data[0] << 8) | (u32)data[1];
1298 static int cxd2841er_read_packet_errors_t(
1299 struct cxd2841er_priv *priv, u32 *penum)
1304 if (priv->state != STATE_ACTIVE_TC) {
1305 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1306 __func__, priv->state);
1309 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1310 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1312 *penum = ((u32)data[0] << 8) | (u32)data[1];
1316 static int cxd2841er_read_packet_errors_t2(
1317 struct cxd2841er_priv *priv, u32 *penum)
1322 if (priv->state != STATE_ACTIVE_TC) {
1323 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1324 __func__, priv->state);
1327 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1328 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1330 *penum = ((u32)data[1] << 8) | (u32)data[2];
1334 static int cxd2841er_read_packet_errors_i(
1335 struct cxd2841er_priv *priv, u32 *penum)
1340 if (priv->state != STATE_ACTIVE_TC) {
1341 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1342 __func__, priv->state);
1345 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1346 cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1348 if (!(data[0] & 0x01))
1352 cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1353 *penum = ((u32)data[0] << 8) | (u32)data[1];
1356 cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1357 *penum += ((u32)data[0] << 8) | (u32)data[1];
1360 cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1361 *penum += ((u32)data[0] << 8) | (u32)data[1];
1366 static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
1367 u32 *bit_error, u32 *bit_count)
1370 u32 bit_err, period_exp;
1372 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1373 if (priv->state != STATE_ACTIVE_TC) {
1374 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1375 __func__, priv->state);
1378 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1379 cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
1380 if (!(data[0] & 0x80)) {
1381 dev_dbg(&priv->i2c->dev,
1382 "%s(): no valid BER data\n", __func__);
1385 bit_err = ((u32)(data[0] & 0x3f) << 16) |
1386 ((u32)data[1] << 8) |
1388 cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
1389 period_exp = data[0] & 0x1f;
1391 if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
1392 dev_dbg(&priv->i2c->dev,
1393 "%s(): period_exp(%u) or bit_err(%u) not in range. no valid BER data\n",
1394 __func__, period_exp, bit_err);
1398 dev_dbg(&priv->i2c->dev,
1399 "%s(): period_exp(%u) or bit_err(%u) count=%d\n",
1400 __func__, period_exp, bit_err,
1401 ((1 << period_exp) * 204 * 8));
1403 *bit_error = bit_err;
1404 *bit_count = ((1 << period_exp) * 204 * 8);
1409 static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv,
1410 u32 *bit_error, u32 *bit_count)
1415 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1416 if (priv->state != STATE_ACTIVE_TC) {
1417 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1418 __func__, priv->state);
1422 cxd2841er_freeze_regs(priv);
1423 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1424 cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum));
1425 cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data));
1427 if (!pktnum[0] && !pktnum[1]) {
1428 dev_dbg(&priv->i2c->dev,
1429 "%s(): no valid BER data\n", __func__);
1430 cxd2841er_unfreeze_regs(priv);
1434 *bit_error = ((u32)(data[0] & 0x7F) << 16) |
1435 ((u32)data[1] << 8) | data[2];
1436 *bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8);
1437 dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n",
1438 __func__, *bit_error, *bit_count);
1440 cxd2841er_unfreeze_regs(priv);
1444 static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
1445 u32 *bit_error, u32 *bit_count)
1449 /* Set SLV-T Bank : 0xA0 */
1450 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1452 * slave Bank Addr Bit Signal name
1453 * <SLV-T> A0h 35h [0] IFVBER_VALID
1454 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1455 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1456 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1457 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1458 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1459 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1461 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1462 if (data[0] & 0x01) {
1463 *bit_error = ((u32)(data[1] & 0x3F) << 16) |
1464 ((u32)(data[2] & 0xFF) << 8) |
1465 (u32)(data[3] & 0xFF);
1466 *bit_count = ((u32)(data[8] & 0x3F) << 16) |
1467 ((u32)(data[9] & 0xFF) << 8) |
1468 (u32)(data[10] & 0xFF);
1469 if ((*bit_count == 0) || (*bit_error > *bit_count)) {
1470 dev_dbg(&priv->i2c->dev,
1471 "%s(): invalid bit_error %d, bit_count %d\n",
1472 __func__, *bit_error, *bit_count);
1477 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1482 static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
1483 u32 *bit_error, u32 *bit_count)
1488 /* Set SLV-T Bank : 0xB2 */
1489 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1491 * slave Bank Addr Bit Signal name
1492 * <SLV-T> B2h 30h [0] IFLBER_VALID
1493 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1494 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1495 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1496 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1498 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1499 if (data[0] & 0x01) {
1500 /* Bit error count */
1501 *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1502 ((u32)(data[2] & 0xFF) << 16) |
1503 ((u32)(data[3] & 0xFF) << 8) |
1504 (u32)(data[4] & 0xFF);
1506 /* Set SLV-T Bank : 0xA0 */
1507 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1508 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1509 /* Measurement period */
1510 period = (u32)(1 << (data[0] & 0x0F));
1512 dev_dbg(&priv->i2c->dev,
1513 "%s(): period is 0\n", __func__);
1516 if (*bit_error > (period * 64800)) {
1517 dev_dbg(&priv->i2c->dev,
1518 "%s(): invalid bit_err 0x%x period 0x%x\n",
1519 __func__, *bit_error, period);
1522 *bit_count = period * 64800;
1526 dev_dbg(&priv->i2c->dev,
1527 "%s(): no data available\n", __func__);
1532 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
1533 u32 *bit_error, u32 *bit_count)
1536 u32 period_exp, n_ldpc;
1538 if (priv->state != STATE_ACTIVE_TC) {
1539 dev_dbg(&priv->i2c->dev,
1540 "%s(): invalid state %d\n", __func__, priv->state);
1543 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1544 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1545 if (!(data[0] & 0x10)) {
1546 dev_dbg(&priv->i2c->dev,
1547 "%s(): no valid BER data\n", __func__);
1550 *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1551 ((u32)data[1] << 16) |
1552 ((u32)data[2] << 8) |
1554 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1555 period_exp = data[0] & 0x0f;
1556 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1557 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1558 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1559 if (*bit_error > ((1U << period_exp) * n_ldpc)) {
1560 dev_dbg(&priv->i2c->dev,
1561 "%s(): invalid BER value\n", __func__);
1566 * FIXME: the right thing would be to return bit_error untouched,
1567 * but, as we don't know the scale returned by the counters, let's
1568 * at least preserver BER = bit_error/bit_count.
1570 if (period_exp >= 4) {
1571 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
1572 *bit_error *= 3125ULL;
1574 *bit_count = (1U << period_exp) * (n_ldpc / 200);
1575 *bit_error *= 50000ULL;
1580 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
1581 u32 *bit_error, u32 *bit_count)
1586 if (priv->state != STATE_ACTIVE_TC) {
1587 dev_dbg(&priv->i2c->dev,
1588 "%s(): invalid state %d\n", __func__, priv->state);
1591 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1592 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1593 if (!(data[0] & 0x01)) {
1594 dev_dbg(&priv->i2c->dev,
1595 "%s(): no valid BER data\n", __func__);
1598 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1599 *bit_error = ((u32)data[0] << 8) | (u32)data[1];
1600 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1601 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1604 * FIXME: the right thing would be to return bit_error untouched,
1605 * but, as we don't know the scale returned by the counters, let's
1606 * at least preserver BER = bit_error/bit_count.
1608 *bit_count = period / 128;
1609 *bit_error *= 78125ULL;
1613 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv)
1616 * Freeze registers: ensure multiple separate register reads
1617 * are from the same snapshot
1619 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1623 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv)
1626 * un-freeze registers
1628 cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00);
1632 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
1633 u8 delsys, u32 *snr)
1637 int min_index, max_index, index;
1638 static const struct cxd2841er_cnr_data *cn_data;
1640 cxd2841er_freeze_regs(priv);
1641 /* Set SLV-T Bank : 0xA1 */
1642 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1644 * slave Bank Addr Bit Signal name
1645 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1646 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1647 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1649 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1650 if (data[0] & 0x01) {
1651 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1653 if (delsys == SYS_DVBS) {
1654 cn_data = s_cn_data;
1655 max_index = sizeof(s_cn_data) /
1656 sizeof(s_cn_data[0]) - 1;
1658 cn_data = s2_cn_data;
1659 max_index = sizeof(s2_cn_data) /
1660 sizeof(s2_cn_data[0]) - 1;
1662 if (value >= cn_data[min_index].value) {
1663 res = cn_data[min_index].cnr_x1000;
1666 if (value <= cn_data[max_index].value) {
1667 res = cn_data[max_index].cnr_x1000;
1670 while ((max_index - min_index) > 1) {
1671 index = (max_index + min_index) / 2;
1672 if (value == cn_data[index].value) {
1673 res = cn_data[index].cnr_x1000;
1675 } else if (value > cn_data[index].value)
1679 if ((max_index - min_index) <= 1) {
1680 if (value == cn_data[max_index].value) {
1681 res = cn_data[max_index].cnr_x1000;
1684 res = cn_data[min_index].cnr_x1000;
1690 dev_dbg(&priv->i2c->dev,
1691 "%s(): no data available\n", __func__);
1692 cxd2841er_unfreeze_regs(priv);
1696 cxd2841er_unfreeze_regs(priv);
1701 static uint32_t sony_log(uint32_t x)
1703 return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
1706 static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
1710 enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
1713 if (priv->state != STATE_ACTIVE_TC) {
1714 dev_dbg(&priv->i2c->dev,
1715 "%s(): invalid state %d\n",
1716 __func__, priv->state);
1720 cxd2841er_freeze_regs(priv);
1721 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1722 cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
1723 qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
1724 cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
1726 reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
1728 dev_dbg(&priv->i2c->dev,
1729 "%s(): reg value out of range\n", __func__);
1730 cxd2841er_unfreeze_regs(priv);
1735 case SONY_DVBC_CONSTELLATION_16QAM:
1736 case SONY_DVBC_CONSTELLATION_64QAM:
1737 case SONY_DVBC_CONSTELLATION_256QAM:
1738 /* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */
1741 *snr = -95 * (int32_t)sony_log(reg) + 95941;
1743 case SONY_DVBC_CONSTELLATION_32QAM:
1744 case SONY_DVBC_CONSTELLATION_128QAM:
1745 /* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */
1748 *snr = -88 * (int32_t)sony_log(reg) + 86999;
1751 cxd2841er_unfreeze_regs(priv);
1755 cxd2841er_unfreeze_regs(priv);
1759 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1765 if (priv->state != STATE_ACTIVE_TC) {
1766 dev_dbg(&priv->i2c->dev,
1767 "%s(): invalid state %d\n", __func__, priv->state);
1771 cxd2841er_freeze_regs(priv);
1772 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1773 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1774 reg = ((u32)data[0] << 8) | (u32)data[1];
1776 dev_dbg(&priv->i2c->dev,
1777 "%s(): reg value out of range\n", __func__);
1778 cxd2841er_unfreeze_regs(priv);
1783 *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1784 cxd2841er_unfreeze_regs(priv);
1788 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1794 if (priv->state != STATE_ACTIVE_TC) {
1795 dev_dbg(&priv->i2c->dev,
1796 "%s(): invalid state %d\n", __func__, priv->state);
1800 cxd2841er_freeze_regs(priv);
1801 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1802 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1803 reg = ((u32)data[0] << 8) | (u32)data[1];
1805 dev_dbg(&priv->i2c->dev,
1806 "%s(): reg value out of range\n", __func__);
1807 cxd2841er_unfreeze_regs(priv);
1812 *snr = 10000 * ((intlog10(reg) -
1813 intlog10(12600 - reg)) >> 24) + 32000;
1814 cxd2841er_unfreeze_regs(priv);
1818 static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1824 if (priv->state != STATE_ACTIVE_TC) {
1825 dev_dbg(&priv->i2c->dev,
1826 "%s(): invalid state %d\n", __func__,
1831 cxd2841er_freeze_regs(priv);
1832 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1833 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1834 reg = ((u32)data[0] << 8) | (u32)data[1];
1836 dev_dbg(&priv->i2c->dev,
1837 "%s(): reg value out of range\n", __func__);
1838 cxd2841er_unfreeze_regs(priv);
1841 *snr = 10000 * (intlog10(reg) >> 24) - 9031;
1842 cxd2841er_unfreeze_regs(priv);
1846 static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1851 cxd2841er_write_reg(
1852 priv, I2C_SLVT, 0x00, 0x40);
1853 cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1854 dev_dbg(&priv->i2c->dev,
1855 "%s(): AGC value=%u\n",
1856 __func__, (((u16)data[0] & 0x0F) << 8) |
1857 (u16)(data[1] & 0xFF));
1858 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1861 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1866 cxd2841er_write_reg(
1867 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1868 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1869 dev_dbg(&priv->i2c->dev,
1870 "%s(): AGC value=%u\n",
1871 __func__, (((u16)data[0] & 0x0F) << 8) |
1872 (u16)(data[1] & 0xFF));
1873 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1876 static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1881 cxd2841er_write_reg(
1882 priv, I2C_SLVT, 0x00, 0x60);
1883 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1885 dev_dbg(&priv->i2c->dev,
1886 "%s(): AGC value=%u\n",
1887 __func__, (((u16)data[0] & 0x0F) << 8) |
1888 (u16)(data[1] & 0xFF));
1889 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1892 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1896 /* Set SLV-T Bank : 0xA0 */
1897 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1899 * slave Bank Addr Bit Signal name
1900 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1901 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1903 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1904 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1907 static void cxd2841er_read_ber(struct dvb_frontend *fe)
1909 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1910 struct cxd2841er_priv *priv = fe->demodulator_priv;
1911 u32 ret, bit_error = 0, bit_count = 0;
1913 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1914 switch (p->delivery_system) {
1915 case SYS_DVBC_ANNEX_A:
1916 case SYS_DVBC_ANNEX_B:
1917 case SYS_DVBC_ANNEX_C:
1918 ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
1921 ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count);
1924 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
1927 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
1930 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
1933 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
1936 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1937 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1942 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1943 p->post_bit_error.stat[0].uvalue += bit_error;
1944 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1945 p->post_bit_count.stat[0].uvalue += bit_count;
1947 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1948 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1952 static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
1954 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1955 struct cxd2841er_priv *priv = fe->demodulator_priv;
1958 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1959 switch (p->delivery_system) {
1962 strength = cxd2841er_read_agc_gain_t_t2(priv,
1963 p->delivery_system);
1964 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1965 /* Formula was empirically determinated @ 410 MHz */
1966 p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
1967 break; /* Code moved out of the function */
1968 case SYS_DVBC_ANNEX_A:
1969 case SYS_DVBC_ANNEX_B:
1970 case SYS_DVBC_ANNEX_C:
1971 strength = cxd2841er_read_agc_gain_c(priv,
1972 p->delivery_system);
1973 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1975 * Formula was empirically determinated via linear regression,
1976 * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
1977 * stream modulated with QAM64
1979 p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
1982 strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
1983 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1985 * Formula was empirically determinated via linear regression,
1986 * using frequencies: 175 MHz, 410 MHz and 800 MHz.
1988 p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
1992 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1993 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1994 p->strength.stat[0].uvalue = strength;
1997 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2002 static void cxd2841er_read_snr(struct dvb_frontend *fe)
2006 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2007 struct cxd2841er_priv *priv = fe->demodulator_priv;
2009 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2010 switch (p->delivery_system) {
2011 case SYS_DVBC_ANNEX_A:
2012 case SYS_DVBC_ANNEX_B:
2013 case SYS_DVBC_ANNEX_C:
2014 ret = cxd2841er_read_snr_c(priv, &tmp);
2017 ret = cxd2841er_read_snr_t(priv, &tmp);
2020 ret = cxd2841er_read_snr_t2(priv, &tmp);
2023 ret = cxd2841er_read_snr_i(priv, &tmp);
2027 ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
2030 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
2031 __func__, p->delivery_system);
2032 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2036 dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n",
2037 __func__, (int32_t)tmp);
2040 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2041 p->cnr.stat[0].svalue = tmp;
2043 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2047 static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
2049 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2050 struct cxd2841er_priv *priv = fe->demodulator_priv;
2053 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2054 switch (p->delivery_system) {
2055 case SYS_DVBC_ANNEX_A:
2056 case SYS_DVBC_ANNEX_B:
2057 case SYS_DVBC_ANNEX_C:
2058 cxd2841er_read_packet_errors_c(priv, &ucblocks);
2061 cxd2841er_read_packet_errors_t(priv, &ucblocks);
2064 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
2067 cxd2841er_read_packet_errors_i(priv, &ucblocks);
2070 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2073 dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks);
2075 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2076 p->block_error.stat[0].uvalue = ucblocks;
2079 static int cxd2841er_dvbt2_set_profile(
2080 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
2085 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2087 case DVBT2_PROFILE_BASE:
2089 /* Set early unlock time */
2090 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
2092 case DVBT2_PROFILE_LITE:
2094 /* Set early unlock time */
2095 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2097 case DVBT2_PROFILE_ANY:
2099 /* Set early unlock time */
2100 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2105 /* Set SLV-T Bank : 0x2E */
2106 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
2107 /* Set profile and tune mode */
2108 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
2109 /* Set SLV-T Bank : 0x2B */
2110 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2111 /* Set early unlock detection time */
2112 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
2116 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
2117 u8 is_auto, u8 plp_id)
2120 dev_dbg(&priv->i2c->dev,
2121 "%s() using auto PLP selection\n", __func__);
2123 dev_dbg(&priv->i2c->dev,
2124 "%s() using manual PLP selection, ID %d\n",
2127 /* Set SLV-T Bank : 0x23 */
2128 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2130 /* Manual PLP selection mode. Set the data PLP Id. */
2131 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
2133 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
2134 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
2138 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
2142 u8 data[MAX_WRITE_REGSIZE];
2144 const uint8_t nominalRate8bw[3][5] = {
2145 /* TRCG Nominal Rate [37:0] */
2146 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2147 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2148 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
2151 const uint8_t nominalRate7bw[3][5] = {
2152 /* TRCG Nominal Rate [37:0] */
2153 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2154 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2155 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
2158 const uint8_t nominalRate6bw[3][5] = {
2159 /* TRCG Nominal Rate [37:0] */
2160 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2161 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2162 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
2165 const uint8_t nominalRate5bw[3][5] = {
2166 /* TRCG Nominal Rate [37:0] */
2167 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2168 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2169 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
2172 const uint8_t nominalRate17bw[3][5] = {
2173 /* TRCG Nominal Rate [37:0] */
2174 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
2175 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
2176 {0x58, 0xE2, 0xAF, 0xE0, 0xBC} /* 41MHz XTal */
2179 const uint8_t itbCoef8bw[3][14] = {
2180 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2181 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2182 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
2183 0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
2184 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2185 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
2188 const uint8_t itbCoef7bw[3][14] = {
2189 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2190 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2191 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
2192 0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
2193 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2194 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
2197 const uint8_t itbCoef6bw[3][14] = {
2198 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2199 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2200 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2201 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2202 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2203 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2206 const uint8_t itbCoef5bw[3][14] = {
2207 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2208 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2209 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2210 0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2211 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2212 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2215 const uint8_t itbCoef17bw[3][14] = {
2216 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2217 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
2218 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
2219 0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal */
2220 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2221 0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99} /* 41MHz XTal */
2224 /* Set SLV-T Bank : 0x20 */
2225 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2227 switch (bandwidth) {
2229 /* <Timing Recovery setting> */
2230 cxd2841er_write_regs(priv, I2C_SLVT,
2231 0x9F, nominalRate8bw[priv->xtal], 5);
2233 /* Set SLV-T Bank : 0x27 */
2234 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2235 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2238 /* Set SLV-T Bank : 0x10 */
2239 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2241 /* Group delay equaliser settings for
2242 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2244 cxd2841er_write_regs(priv, I2C_SLVT,
2245 0xA6, itbCoef8bw[priv->xtal], 14);
2246 /* <IF freq setting> */
2247 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2248 data[0] = (u8) ((iffreq >> 16) & 0xff);
2249 data[1] = (u8)((iffreq >> 8) & 0xff);
2250 data[2] = (u8)(iffreq & 0xff);
2251 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2252 /* System bandwidth setting */
2253 cxd2841er_set_reg_bits(
2254 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2257 /* <Timing Recovery setting> */
2258 cxd2841er_write_regs(priv, I2C_SLVT,
2259 0x9F, nominalRate7bw[priv->xtal], 5);
2261 /* Set SLV-T Bank : 0x27 */
2262 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2263 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2266 /* Set SLV-T Bank : 0x10 */
2267 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2269 /* Group delay equaliser settings for
2270 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2272 cxd2841er_write_regs(priv, I2C_SLVT,
2273 0xA6, itbCoef7bw[priv->xtal], 14);
2274 /* <IF freq setting> */
2275 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2276 data[0] = (u8) ((iffreq >> 16) & 0xff);
2277 data[1] = (u8)((iffreq >> 8) & 0xff);
2278 data[2] = (u8)(iffreq & 0xff);
2279 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2280 /* System bandwidth setting */
2281 cxd2841er_set_reg_bits(
2282 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2285 /* <Timing Recovery setting> */
2286 cxd2841er_write_regs(priv, I2C_SLVT,
2287 0x9F, nominalRate6bw[priv->xtal], 5);
2289 /* Set SLV-T Bank : 0x27 */
2290 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2291 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2294 /* Set SLV-T Bank : 0x10 */
2295 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2297 /* Group delay equaliser settings for
2298 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2300 cxd2841er_write_regs(priv, I2C_SLVT,
2301 0xA6, itbCoef6bw[priv->xtal], 14);
2302 /* <IF freq setting> */
2303 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2304 data[0] = (u8) ((iffreq >> 16) & 0xff);
2305 data[1] = (u8)((iffreq >> 8) & 0xff);
2306 data[2] = (u8)(iffreq & 0xff);
2307 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2308 /* System bandwidth setting */
2309 cxd2841er_set_reg_bits(
2310 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2313 /* <Timing Recovery setting> */
2314 cxd2841er_write_regs(priv, I2C_SLVT,
2315 0x9F, nominalRate5bw[priv->xtal], 5);
2317 /* Set SLV-T Bank : 0x27 */
2318 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2319 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2322 /* Set SLV-T Bank : 0x10 */
2323 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2325 /* Group delay equaliser settings for
2326 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2328 cxd2841er_write_regs(priv, I2C_SLVT,
2329 0xA6, itbCoef5bw[priv->xtal], 14);
2330 /* <IF freq setting> */
2331 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2332 data[0] = (u8) ((iffreq >> 16) & 0xff);
2333 data[1] = (u8)((iffreq >> 8) & 0xff);
2334 data[2] = (u8)(iffreq & 0xff);
2335 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2336 /* System bandwidth setting */
2337 cxd2841er_set_reg_bits(
2338 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2341 /* <Timing Recovery setting> */
2342 cxd2841er_write_regs(priv, I2C_SLVT,
2343 0x9F, nominalRate17bw[priv->xtal], 5);
2345 /* Set SLV-T Bank : 0x27 */
2346 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2347 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2350 /* Set SLV-T Bank : 0x10 */
2351 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2353 /* Group delay equaliser settings for
2354 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2356 cxd2841er_write_regs(priv, I2C_SLVT,
2357 0xA6, itbCoef17bw[priv->xtal], 14);
2358 /* <IF freq setting> */
2359 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.50);
2360 data[0] = (u8) ((iffreq >> 16) & 0xff);
2361 data[1] = (u8)((iffreq >> 8) & 0xff);
2362 data[2] = (u8)(iffreq & 0xff);
2363 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2364 /* System bandwidth setting */
2365 cxd2841er_set_reg_bits(
2366 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
2374 static int cxd2841er_sleep_tc_to_active_t_band(
2375 struct cxd2841er_priv *priv, u32 bandwidth)
2377 u8 data[MAX_WRITE_REGSIZE];
2379 u8 nominalRate8bw[3][5] = {
2380 /* TRCG Nominal Rate [37:0] */
2381 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2382 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2383 {0x11, 0xF0, 0x00, 0x00, 0x00} /* 41MHz XTal */
2385 u8 nominalRate7bw[3][5] = {
2386 /* TRCG Nominal Rate [37:0] */
2387 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2388 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2389 {0x14, 0x80, 0x00, 0x00, 0x00} /* 41MHz XTal */
2391 u8 nominalRate6bw[3][5] = {
2392 /* TRCG Nominal Rate [37:0] */
2393 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2394 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2395 {0x17, 0xEA, 0xAA, 0xAA, 0xAA} /* 41MHz XTal */
2397 u8 nominalRate5bw[3][5] = {
2398 /* TRCG Nominal Rate [37:0] */
2399 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2400 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2401 {0x1C, 0xB3, 0x33, 0x33, 0x33} /* 41MHz XTal */
2404 u8 itbCoef8bw[3][14] = {
2405 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2406 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2407 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2408 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal */
2409 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2410 0x1F, 0xA8, 0x2C, 0xC8} /* 41MHz XTal */
2412 u8 itbCoef7bw[3][14] = {
2413 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2414 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2415 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2416 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal */
2417 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2418 0x26, 0xA9, 0x21, 0xA5} /* 41MHz XTal */
2420 u8 itbCoef6bw[3][14] = {
2421 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2422 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2423 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2424 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2425 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2426 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2428 u8 itbCoef5bw[3][14] = {
2429 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2430 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2431 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2432 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal */
2433 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2434 0x00, 0xE6, 0x23, 0xA4} /* 41MHz XTal */
2437 /* Set SLV-T Bank : 0x13 */
2438 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2439 /* Echo performance optimization setting */
2442 cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2444 /* Set SLV-T Bank : 0x10 */
2445 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2447 switch (bandwidth) {
2449 /* <Timing Recovery setting> */
2450 cxd2841er_write_regs(priv, I2C_SLVT,
2451 0x9F, nominalRate8bw[priv->xtal], 5);
2452 /* Group delay equaliser settings for
2453 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2455 cxd2841er_write_regs(priv, I2C_SLVT,
2456 0xA6, itbCoef8bw[priv->xtal], 14);
2457 /* <IF freq setting> */
2458 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2459 data[0] = (u8) ((iffreq >> 16) & 0xff);
2460 data[1] = (u8)((iffreq >> 8) & 0xff);
2461 data[2] = (u8)(iffreq & 0xff);
2462 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2463 /* System bandwidth setting */
2464 cxd2841er_set_reg_bits(
2465 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2467 /* Demod core latency setting */
2468 if (priv->xtal == SONY_XTAL_24000) {
2475 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2477 /* Notch filter setting */
2480 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2481 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2484 /* <Timing Recovery setting> */
2485 cxd2841er_write_regs(priv, I2C_SLVT,
2486 0x9F, nominalRate7bw[priv->xtal], 5);
2487 /* Group delay equaliser settings for
2488 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2490 cxd2841er_write_regs(priv, I2C_SLVT,
2491 0xA6, itbCoef7bw[priv->xtal], 14);
2492 /* <IF freq setting> */
2493 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2494 data[0] = (u8) ((iffreq >> 16) & 0xff);
2495 data[1] = (u8)((iffreq >> 8) & 0xff);
2496 data[2] = (u8)(iffreq & 0xff);
2497 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2498 /* System bandwidth setting */
2499 cxd2841er_set_reg_bits(
2500 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2502 /* Demod core latency setting */
2503 if (priv->xtal == SONY_XTAL_24000) {
2510 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2512 /* Notch filter setting */
2515 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2516 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2519 /* <Timing Recovery setting> */
2520 cxd2841er_write_regs(priv, I2C_SLVT,
2521 0x9F, nominalRate6bw[priv->xtal], 5);
2522 /* Group delay equaliser settings for
2523 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2525 cxd2841er_write_regs(priv, I2C_SLVT,
2526 0xA6, itbCoef6bw[priv->xtal], 14);
2527 /* <IF freq setting> */
2528 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2529 data[0] = (u8) ((iffreq >> 16) & 0xff);
2530 data[1] = (u8)((iffreq >> 8) & 0xff);
2531 data[2] = (u8)(iffreq & 0xff);
2532 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2533 /* System bandwidth setting */
2534 cxd2841er_set_reg_bits(
2535 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2537 /* Demod core latency setting */
2538 if (priv->xtal == SONY_XTAL_24000) {
2545 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2547 /* Notch filter setting */
2550 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2551 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2554 /* <Timing Recovery setting> */
2555 cxd2841er_write_regs(priv, I2C_SLVT,
2556 0x9F, nominalRate5bw[priv->xtal], 5);
2557 /* Group delay equaliser settings for
2558 * ASCOT2D, ASCOT2E and ASCOT3 tuners
2560 cxd2841er_write_regs(priv, I2C_SLVT,
2561 0xA6, itbCoef5bw[priv->xtal], 14);
2562 /* <IF freq setting> */
2563 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2564 data[0] = (u8) ((iffreq >> 16) & 0xff);
2565 data[1] = (u8)((iffreq >> 8) & 0xff);
2566 data[2] = (u8)(iffreq & 0xff);
2567 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2568 /* System bandwidth setting */
2569 cxd2841er_set_reg_bits(
2570 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2572 /* Demod core latency setting */
2573 if (priv->xtal == SONY_XTAL_24000) {
2580 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2582 /* Notch filter setting */
2585 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2586 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2593 static int cxd2841er_sleep_tc_to_active_i_band(
2594 struct cxd2841er_priv *priv, u32 bandwidth)
2599 /* TRCG Nominal Rate */
2600 u8 nominalRate8bw[3][5] = {
2601 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2602 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2603 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2606 u8 nominalRate7bw[3][5] = {
2607 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2608 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2609 {0x00, 0x00, 0x00, 0x00, 0x00} /* 41MHz XTal */
2612 u8 nominalRate6bw[3][5] = {
2613 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2614 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2615 {0x14, 0x2E, 0x00, 0x00, 0x00} /* 41MHz XTal */
2618 u8 itbCoef8bw[3][14] = {
2619 {0x00}, /* 20.5MHz XTal */
2620 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2621 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2622 {0x0}, /* 41MHz XTal */
2625 u8 itbCoef7bw[3][14] = {
2626 {0x00}, /* 20.5MHz XTal */
2627 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2628 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2629 {0x00}, /* 41MHz XTal */
2632 u8 itbCoef6bw[3][14] = {
2633 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2634 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2635 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2636 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal */
2637 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2638 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal */
2641 dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2642 /* Set SLV-T Bank : 0x10 */
2643 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2645 /* 20.5/41MHz Xtal support is not available
2646 * on ISDB-T 7MHzBW and 8MHzBW
2648 if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2649 dev_err(&priv->i2c->dev,
2650 "%s(): bandwidth %d supported only for 24MHz xtal\n",
2651 __func__, bandwidth);
2655 switch (bandwidth) {
2657 /* TRCG Nominal Rate */
2658 cxd2841er_write_regs(priv, I2C_SLVT,
2659 0x9F, nominalRate8bw[priv->xtal], 5);
2660 /* Group delay equaliser settings for ASCOT tuners optimized */
2661 cxd2841er_write_regs(priv, I2C_SLVT,
2662 0xA6, itbCoef8bw[priv->xtal], 14);
2664 /* IF freq setting */
2665 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75);
2666 data[0] = (u8) ((iffreq >> 16) & 0xff);
2667 data[1] = (u8)((iffreq >> 8) & 0xff);
2668 data[2] = (u8)(iffreq & 0xff);
2669 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2671 /* System bandwidth setting */
2672 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2674 /* Demod core latency setting */
2677 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2679 /* Acquisition optimization setting */
2680 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2681 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2682 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2683 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2686 /* TRCG Nominal Rate */
2687 cxd2841er_write_regs(priv, I2C_SLVT,
2688 0x9F, nominalRate7bw[priv->xtal], 5);
2689 /* Group delay equaliser settings for ASCOT tuners optimized */
2690 cxd2841er_write_regs(priv, I2C_SLVT,
2691 0xA6, itbCoef7bw[priv->xtal], 14);
2693 /* IF freq setting */
2694 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15);
2695 data[0] = (u8) ((iffreq >> 16) & 0xff);
2696 data[1] = (u8)((iffreq >> 8) & 0xff);
2697 data[2] = (u8)(iffreq & 0xff);
2698 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2700 /* System bandwidth setting */
2701 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2703 /* Demod core latency setting */
2706 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2708 /* Acquisition optimization setting */
2709 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2710 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2711 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2712 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2715 /* TRCG Nominal Rate */
2716 cxd2841er_write_regs(priv, I2C_SLVT,
2717 0x9F, nominalRate6bw[priv->xtal], 5);
2718 /* Group delay equaliser settings for ASCOT tuners optimized */
2719 cxd2841er_write_regs(priv, I2C_SLVT,
2720 0xA6, itbCoef6bw[priv->xtal], 14);
2722 /* IF freq setting */
2723 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55);
2724 data[0] = (u8) ((iffreq >> 16) & 0xff);
2725 data[1] = (u8)((iffreq >> 8) & 0xff);
2726 data[2] = (u8)(iffreq & 0xff);
2727 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2729 /* System bandwidth setting */
2730 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2732 /* Demod core latency setting */
2733 if (priv->xtal == SONY_XTAL_24000) {
2740 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2742 /* Acquisition optimization setting */
2743 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2744 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2745 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2746 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2749 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2750 __func__, bandwidth);
2756 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2759 u8 bw7_8mhz_b10_a6[] = {
2760 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2761 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2762 u8 bw6mhz_b10_a6[] = {
2763 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2764 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2768 if (bandwidth != 6000000 &&
2769 bandwidth != 7000000 &&
2770 bandwidth != 8000000) {
2771 dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n",
2772 __func__, bandwidth);
2773 bandwidth = 8000000;
2776 dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
2777 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2778 switch (bandwidth) {
2781 cxd2841er_write_regs(
2782 priv, I2C_SLVT, 0xa6,
2783 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2784 iffreq = MAKE_IFFREQ_CONFIG(4.9);
2787 cxd2841er_write_regs(
2788 priv, I2C_SLVT, 0xa6,
2789 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2790 iffreq = MAKE_IFFREQ_CONFIG(3.7);
2793 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2794 __func__, bandwidth);
2797 /* <IF freq setting> */
2798 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2799 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2800 b10_b6[2] = (u8)(iffreq & 0xff);
2801 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2802 /* Set SLV-T Bank : 0x11 */
2803 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2804 switch (bandwidth) {
2807 cxd2841er_set_reg_bits(
2808 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2811 cxd2841er_set_reg_bits(
2812 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2815 /* Set SLV-T Bank : 0x40 */
2816 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2817 switch (bandwidth) {
2819 cxd2841er_set_reg_bits(
2820 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2821 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
2824 cxd2841er_set_reg_bits(
2825 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2826 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
2829 cxd2841er_set_reg_bits(
2830 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2831 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
2837 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2840 u8 data[2] = { 0x09, 0x54 };
2841 u8 data24m[3] = {0xDC, 0x6C, 0x00};
2843 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2844 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2845 /* Set SLV-X Bank : 0x00 */
2846 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2847 /* Set demod mode */
2848 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2849 /* Set SLV-T Bank : 0x00 */
2850 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2851 /* Enable demod clock */
2852 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2853 /* Disable RF level monitor */
2854 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2855 /* Enable ADC clock */
2856 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2858 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2859 /* Enable ADC 2 & 3 */
2860 if (priv->xtal == SONY_XTAL_41000) {
2864 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2866 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2867 /* Set SLV-T Bank : 0x10 */
2868 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2869 /* IFAGC gain settings */
2870 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2871 /* Set SLV-T Bank : 0x11 */
2872 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2873 /* BBAGC TARGET level setting */
2874 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2875 /* Set SLV-T Bank : 0x10 */
2876 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2877 /* ASCOT setting ON */
2878 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2879 /* Set SLV-T Bank : 0x18 */
2880 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2881 /* Pre-RS BER moniter setting */
2882 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2883 /* FEC Auto Recovery setting */
2884 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2885 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2886 /* Set SLV-T Bank : 0x00 */
2887 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2889 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2890 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2892 if (priv->xtal == SONY_XTAL_24000) {
2893 /* Set SLV-T Bank : 0x10 */
2894 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2895 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2896 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2897 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2900 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2901 /* Set SLV-T Bank : 0x00 */
2902 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2903 /* Disable HiZ Setting 1 */
2904 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2905 /* Disable HiZ Setting 2 */
2906 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2907 priv->state = STATE_ACTIVE_TC;
2911 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2914 u8 data[MAX_WRITE_REGSIZE];
2916 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2917 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2918 /* Set SLV-X Bank : 0x00 */
2919 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2920 /* Set demod mode */
2921 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2922 /* Set SLV-T Bank : 0x00 */
2923 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2924 /* Enable demod clock */
2925 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2926 /* Disable RF level monitor */
2927 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
2928 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2929 /* Enable ADC clock */
2930 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2932 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2934 if (priv->xtal == SONY_XTAL_41000) {
2942 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2944 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2945 /* Set SLV-T Bank : 0x10 */
2946 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2947 /* IFAGC gain settings */
2948 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2949 /* Set SLV-T Bank : 0x11 */
2950 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2951 /* BBAGC TARGET level setting */
2952 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2953 /* Set SLV-T Bank : 0x10 */
2954 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2955 /* ASCOT setting ON */
2956 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2957 /* Set SLV-T Bank : 0x20 */
2958 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2959 /* Acquisition optimization setting */
2960 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2961 /* Set SLV-T Bank : 0x2b */
2962 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2963 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
2964 /* Set SLV-T Bank : 0x23 */
2965 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2966 /* L1 Control setting */
2967 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
2968 /* Set SLV-T Bank : 0x00 */
2969 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2971 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2972 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2973 /* DVB-T2 initial setting */
2974 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2975 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2976 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2977 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2978 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2979 /* Set SLV-T Bank : 0x2a */
2980 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2981 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2982 /* Set SLV-T Bank : 0x2b */
2983 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2984 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2986 /* 24MHz Xtal setting */
2987 if (priv->xtal == SONY_XTAL_24000) {
2988 /* Set SLV-T Bank : 0x11 */
2989 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2993 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
2995 /* Set SLV-T Bank : 0x20 */
2996 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
3000 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
3002 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
3006 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
3008 /* Set SLV-T Bank : 0x24 */
3009 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
3012 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
3017 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
3022 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
3024 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
3026 /* Set SLV-T Bank : 0x25 */
3027 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
3028 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
3030 /* Set SLV-T Bank : 0x27 */
3031 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
3032 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
3034 /* Set SLV-T Bank : 0x2B */
3035 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
3036 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
3037 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
3039 /* Set SLV-T Bank : 0x2D */
3040 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
3043 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
3045 /* Set SLV-T Bank : 0x5E */
3046 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
3049 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
3052 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
3054 /* Set SLV-T Bank : 0x00 */
3055 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3056 /* Disable HiZ Setting 1 */
3057 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3058 /* Disable HiZ Setting 2 */
3059 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3060 priv->state = STATE_ACTIVE_TC;
3065 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
3068 u8 data[2] = { 0x09, 0x54 };
3069 u8 data24m[2] = {0x60, 0x00};
3070 u8 data24m2[3] = {0xB7, 0x1B, 0x00};
3072 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3073 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
3074 /* Set SLV-X Bank : 0x00 */
3075 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3076 /* Set demod mode */
3077 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
3078 /* Set SLV-T Bank : 0x00 */
3079 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3080 /* Enable demod clock */
3081 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3082 /* Enable RF level monitor */
3083 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
3084 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
3085 /* Enable ADC clock */
3086 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3088 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3089 /* xtal freq 20.5MHz or 24M */
3090 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3092 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3093 /* ASCOT setting ON */
3094 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
3095 /* FEC Auto Recovery setting */
3096 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
3097 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
3098 /* ISDB-T initial setting */
3099 /* Set SLV-T Bank : 0x00 */
3100 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3101 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
3102 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
3103 /* Set SLV-T Bank : 0x10 */
3104 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3105 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
3106 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
3107 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
3108 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
3109 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
3110 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
3111 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
3112 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
3113 /* Set SLV-T Bank : 0x15 */
3114 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
3115 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
3116 /* Set SLV-T Bank : 0x1E */
3117 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
3118 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
3119 /* Set SLV-T Bank : 0x63 */
3120 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
3121 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
3123 /* for xtal 24MHz */
3124 /* Set SLV-T Bank : 0x10 */
3125 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3126 cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
3127 /* Set SLV-T Bank : 0x60 */
3128 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
3129 cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
3131 cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
3132 /* Set SLV-T Bank : 0x00 */
3133 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3134 /* Disable HiZ Setting 1 */
3135 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3136 /* Disable HiZ Setting 2 */
3137 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3138 priv->state = STATE_ACTIVE_TC;
3142 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
3145 u8 data[2] = { 0x09, 0x54 };
3147 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3148 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
3149 /* Set SLV-X Bank : 0x00 */
3150 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3151 /* Set demod mode */
3152 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
3153 /* Set SLV-T Bank : 0x00 */
3154 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3155 /* Enable demod clock */
3156 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3157 /* Disable RF level monitor */
3158 cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
3159 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
3160 /* Enable ADC clock */
3161 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3163 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3164 /* xtal freq 20.5MHz */
3165 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3167 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3168 /* Set SLV-T Bank : 0x10 */
3169 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3170 /* IFAGC gain settings */
3171 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
3172 /* Set SLV-T Bank : 0x11 */
3173 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3174 /* BBAGC TARGET level setting */
3175 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
3176 /* Set SLV-T Bank : 0x10 */
3177 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3178 /* ASCOT setting ON */
3179 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
3180 /* Set SLV-T Bank : 0x40 */
3181 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
3183 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
3184 /* Set SLV-T Bank : 0x00 */
3185 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3187 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3188 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3190 cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
3191 /* Set SLV-T Bank : 0x00 */
3192 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3193 /* Disable HiZ Setting 1 */
3194 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3195 /* Disable HiZ Setting 2 */
3196 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3197 priv->state = STATE_ACTIVE_TC;
3201 static int cxd2841er_get_frontend(struct dvb_frontend *fe,
3202 struct dtv_frontend_properties *p)
3204 enum fe_status status = 0;
3205 struct cxd2841er_priv *priv = fe->demodulator_priv;
3207 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3208 if (priv->state == STATE_ACTIVE_S)
3209 cxd2841er_read_status_s(fe, &status);
3210 else if (priv->state == STATE_ACTIVE_TC)
3211 cxd2841er_read_status_tc(fe, &status);
3213 cxd2841er_read_signal_strength(fe);
3215 if (status & FE_HAS_LOCK) {
3216 cxd2841er_read_snr(fe);
3217 cxd2841er_read_ucblocks(fe);
3219 cxd2841er_read_ber(fe);
3221 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3222 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3223 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3224 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3229 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
3231 int ret = 0, i, timeout, carr_offset;
3232 enum fe_status status;
3233 struct cxd2841er_priv *priv = fe->demodulator_priv;
3234 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3235 u32 symbol_rate = p->symbol_rate/1000;
3237 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
3239 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
3240 p->frequency, symbol_rate, priv->xtal);
3241 switch (priv->state) {
3243 ret = cxd2841er_sleep_s_to_active_s(
3244 priv, p->delivery_system, symbol_rate);
3246 case STATE_ACTIVE_S:
3247 ret = cxd2841er_retune_active(priv, p);
3250 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3251 __func__, priv->state);
3256 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3259 if (fe->ops.i2c_gate_ctrl)
3260 fe->ops.i2c_gate_ctrl(fe, 1);
3261 if (fe->ops.tuner_ops.set_params)
3262 fe->ops.tuner_ops.set_params(fe);
3263 if (fe->ops.i2c_gate_ctrl)
3264 fe->ops.i2c_gate_ctrl(fe, 0);
3265 cxd2841er_tune_done(priv);
3266 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3267 for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
3268 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3269 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3270 cxd2841er_read_status_s(fe, &status);
3271 if (status & FE_HAS_LOCK)
3274 if (status & FE_HAS_LOCK) {
3275 if (cxd2841er_get_carrier_offset_s_s2(
3276 priv, &carr_offset)) {
3280 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3281 __func__, carr_offset);
3285 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3286 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3287 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3288 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3289 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3294 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3296 int ret = 0, timeout;
3297 enum fe_status status;
3298 struct cxd2841er_priv *priv = fe->demodulator_priv;
3299 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3301 dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3302 __func__, p->delivery_system, p->bandwidth_hz);
3303 if (p->delivery_system == SYS_DVBT) {
3304 priv->system = SYS_DVBT;
3305 switch (priv->state) {
3306 case STATE_SLEEP_TC:
3307 ret = cxd2841er_sleep_tc_to_active_t(
3308 priv, p->bandwidth_hz);
3310 case STATE_ACTIVE_TC:
3311 ret = cxd2841er_retune_active(priv, p);
3314 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3315 __func__, priv->state);
3318 } else if (p->delivery_system == SYS_DVBT2) {
3319 priv->system = SYS_DVBT2;
3320 cxd2841er_dvbt2_set_plp_config(priv,
3321 (int)(p->stream_id > 255), p->stream_id);
3322 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3323 switch (priv->state) {
3324 case STATE_SLEEP_TC:
3325 ret = cxd2841er_sleep_tc_to_active_t2(priv,
3328 case STATE_ACTIVE_TC:
3329 ret = cxd2841er_retune_active(priv, p);
3332 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3333 __func__, priv->state);
3336 } else if (p->delivery_system == SYS_ISDBT) {
3337 priv->system = SYS_ISDBT;
3338 switch (priv->state) {
3339 case STATE_SLEEP_TC:
3340 ret = cxd2841er_sleep_tc_to_active_i(
3341 priv, p->bandwidth_hz);
3343 case STATE_ACTIVE_TC:
3344 ret = cxd2841er_retune_active(priv, p);
3347 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3348 __func__, priv->state);
3351 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3352 p->delivery_system == SYS_DVBC_ANNEX_C) {
3353 priv->system = SYS_DVBC_ANNEX_A;
3354 /* correct bandwidth */
3355 if (p->bandwidth_hz != 6000000 &&
3356 p->bandwidth_hz != 7000000 &&
3357 p->bandwidth_hz != 8000000) {
3358 p->bandwidth_hz = 8000000;
3359 dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3360 __func__, p->bandwidth_hz);
3363 switch (priv->state) {
3364 case STATE_SLEEP_TC:
3365 ret = cxd2841er_sleep_tc_to_active_c(
3366 priv, p->bandwidth_hz);
3368 case STATE_ACTIVE_TC:
3369 ret = cxd2841er_retune_active(priv, p);
3372 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3373 __func__, priv->state);
3377 dev_dbg(&priv->i2c->dev,
3378 "%s(): invalid delivery system %d\n",
3379 __func__, p->delivery_system);
3384 if (fe->ops.i2c_gate_ctrl)
3385 fe->ops.i2c_gate_ctrl(fe, 1);
3386 if (fe->ops.tuner_ops.set_params)
3387 fe->ops.tuner_ops.set_params(fe);
3388 if (fe->ops.i2c_gate_ctrl)
3389 fe->ops.i2c_gate_ctrl(fe, 0);
3390 cxd2841er_tune_done(priv);
3392 while (timeout > 0) {
3393 ret = cxd2841er_read_status_tc(fe, &status);
3396 if (status & FE_HAS_LOCK)
3402 dev_dbg(&priv->i2c->dev,
3403 "%s(): LOCK wait timeout\n", __func__);
3408 static int cxd2841er_tune_s(struct dvb_frontend *fe,
3410 unsigned int mode_flags,
3411 unsigned int *delay,
3412 enum fe_status *status)
3414 int ret, carrier_offset;
3415 struct cxd2841er_priv *priv = fe->demodulator_priv;
3416 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3418 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3420 ret = cxd2841er_set_frontend_s(fe);
3423 cxd2841er_read_status_s(fe, status);
3424 if (*status & FE_HAS_LOCK) {
3425 if (cxd2841er_get_carrier_offset_s_s2(
3426 priv, &carrier_offset))
3428 p->frequency += carrier_offset;
3429 ret = cxd2841er_set_frontend_s(fe);
3435 return cxd2841er_read_status_s(fe, status);
3438 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3440 unsigned int mode_flags,
3441 unsigned int *delay,
3442 enum fe_status *status)
3444 int ret, carrier_offset;
3445 struct cxd2841er_priv *priv = fe->demodulator_priv;
3446 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3448 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3449 re_tune, p->bandwidth_hz);
3451 ret = cxd2841er_set_frontend_tc(fe);
3454 cxd2841er_read_status_tc(fe, status);
3455 if (*status & FE_HAS_LOCK) {
3456 switch (priv->system) {
3458 ret = cxd2841er_get_carrier_offset_i(
3459 priv, p->bandwidth_hz,
3465 ret = cxd2841er_get_carrier_offset_t(
3466 priv, p->bandwidth_hz,
3472 ret = cxd2841er_get_carrier_offset_t2(
3473 priv, p->bandwidth_hz,
3478 case SYS_DVBC_ANNEX_A:
3479 ret = cxd2841er_get_carrier_offset_c(
3480 priv, &carrier_offset);
3485 dev_dbg(&priv->i2c->dev,
3486 "%s(): invalid delivery system %d\n",
3487 __func__, priv->system);
3490 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3491 __func__, carrier_offset);
3492 p->frequency += carrier_offset;
3493 ret = cxd2841er_set_frontend_tc(fe);
3499 return cxd2841er_read_status_tc(fe, status);
3502 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3504 struct cxd2841er_priv *priv = fe->demodulator_priv;
3506 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3507 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3508 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3512 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3514 struct cxd2841er_priv *priv = fe->demodulator_priv;
3516 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3517 if (priv->state == STATE_ACTIVE_TC) {
3518 switch (priv->system) {
3520 cxd2841er_active_t_to_sleep_tc(priv);
3523 cxd2841er_active_t2_to_sleep_tc(priv);
3526 cxd2841er_active_i_to_sleep_tc(priv);
3528 case SYS_DVBC_ANNEX_A:
3529 cxd2841er_active_c_to_sleep_tc(priv);
3532 dev_warn(&priv->i2c->dev,
3533 "%s(): unknown delivery system %d\n",
3534 __func__, priv->system);
3537 if (priv->state != STATE_SLEEP_TC) {
3538 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3539 __func__, priv->state);
3542 cxd2841er_sleep_tc_to_shutdown(priv);
3546 static int cxd2841er_send_burst(struct dvb_frontend *fe,
3547 enum fe_sec_mini_cmd burst)
3550 struct cxd2841er_priv *priv = fe->demodulator_priv;
3552 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3553 (burst == SEC_MINI_A ? "A" : "B"));
3554 if (priv->state != STATE_SLEEP_S &&
3555 priv->state != STATE_ACTIVE_S) {
3556 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3557 __func__, priv->state);
3560 data = (burst == SEC_MINI_A ? 0 : 1);
3561 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3562 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3563 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3567 static int cxd2841er_set_tone(struct dvb_frontend *fe,
3568 enum fe_sec_tone_mode tone)
3571 struct cxd2841er_priv *priv = fe->demodulator_priv;
3573 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3574 (tone == SEC_TONE_ON ? "On" : "Off"));
3575 if (priv->state != STATE_SLEEP_S &&
3576 priv->state != STATE_ACTIVE_S) {
3577 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3578 __func__, priv->state);
3581 data = (tone == SEC_TONE_ON ? 1 : 0);
3582 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3583 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3587 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3588 struct dvb_diseqc_master_cmd *cmd)
3592 struct cxd2841er_priv *priv = fe->demodulator_priv;
3594 if (priv->state != STATE_SLEEP_S &&
3595 priv->state != STATE_ACTIVE_S) {
3596 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3597 __func__, priv->state);
3600 dev_dbg(&priv->i2c->dev,
3601 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3602 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3604 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3605 /* cmd1 length & data */
3606 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3607 memset(data, 0, sizeof(data));
3608 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3609 data[i] = cmd->msg[i];
3610 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3611 /* repeat count for cmd1 */
3612 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3613 /* repeat count for cmd2: always 0 */
3614 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3615 /* start transmit */
3616 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3617 /* wait for 1 sec timeout */
3618 for (i = 0; i < 50; i++) {
3619 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3621 dev_dbg(&priv->i2c->dev,
3622 "%s(): DiSEqC cmd has been sent\n", __func__);
3627 dev_dbg(&priv->i2c->dev,
3628 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3632 static void cxd2841er_release(struct dvb_frontend *fe)
3634 struct cxd2841er_priv *priv = fe->demodulator_priv;
3636 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3640 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3642 struct cxd2841er_priv *priv = fe->demodulator_priv;
3644 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3645 cxd2841er_set_reg_bits(
3646 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3650 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3652 struct cxd2841er_priv *priv = fe->demodulator_priv;
3654 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3655 return DVBFE_ALGO_HW;
3658 static void cxd2841er_init_stats(struct dvb_frontend *fe)
3660 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3662 p->strength.len = 1;
3663 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3665 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3666 p->block_error.len = 1;
3667 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3668 p->post_bit_error.len = 1;
3669 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3670 p->post_bit_count.len = 1;
3671 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3675 static int cxd2841er_init_s(struct dvb_frontend *fe)
3677 struct cxd2841er_priv *priv = fe->demodulator_priv;
3679 /* sanity. force demod to SHUTDOWN state */
3680 if (priv->state == STATE_SLEEP_S) {
3681 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3683 cxd2841er_sleep_s_to_shutdown(priv);
3684 } else if (priv->state == STATE_ACTIVE_S) {
3685 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3687 cxd2841er_active_s_to_sleep_s(priv);
3688 cxd2841er_sleep_s_to_shutdown(priv);
3691 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3692 cxd2841er_shutdown_to_sleep_s(priv);
3693 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3694 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3695 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3697 cxd2841er_init_stats(fe);
3702 static int cxd2841er_init_tc(struct dvb_frontend *fe)
3704 struct cxd2841er_priv *priv = fe->demodulator_priv;
3705 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3707 dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3708 __func__, p->bandwidth_hz);
3709 cxd2841er_shutdown_to_sleep_tc(priv);
3710 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3711 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3712 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3713 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3714 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3715 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3716 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3717 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
3719 cxd2841er_init_stats(fe);
3724 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3725 static struct dvb_frontend_ops cxd2841er_t_c_ops;
3727 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3728 struct i2c_adapter *i2c,
3734 struct cxd2841er_priv *priv = NULL;
3736 /* allocate memory for the internal state */
3737 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3742 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3743 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
3744 priv->xtal = cfg->xtal;
3745 priv->frontend.demodulator_priv = priv;
3746 dev_info(&priv->i2c->dev,
3747 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3748 __func__, priv->i2c,
3749 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3750 chip_id = cxd2841er_chip_id(priv);
3752 case CXD2841ER_CHIP_ID:
3753 snprintf(cxd2841er_t_c_ops.info.name, 128,
3754 "Sony CXD2841ER DVB-T/T2/C demodulator");
3757 case CXD2854ER_CHIP_ID:
3758 snprintf(cxd2841er_t_c_ops.info.name, 128,
3759 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3760 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3764 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3766 priv->frontend.demodulator_priv = NULL;
3771 /* create dvb_frontend */
3772 if (system == SYS_DVBS) {
3773 memcpy(&priv->frontend.ops,
3774 &cxd2841er_dvbs_s2_ops,
3775 sizeof(struct dvb_frontend_ops));
3778 memcpy(&priv->frontend.ops,
3780 sizeof(struct dvb_frontend_ops));
3781 type = "T/T2/C/ISDB-T";
3784 dev_info(&priv->i2c->dev,
3785 "%s(): attaching %s DVB-%s frontend\n",
3786 __func__, name, type);
3787 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3789 return &priv->frontend;
3792 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3793 struct i2c_adapter *i2c)
3795 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3797 EXPORT_SYMBOL(cxd2841er_attach_s);
3799 struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
3800 struct i2c_adapter *i2c)
3802 return cxd2841er_attach(cfg, i2c, 0);
3804 EXPORT_SYMBOL(cxd2841er_attach_t_c);
3806 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3807 .delsys = { SYS_DVBS, SYS_DVBS2 },
3809 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
3810 .frequency_min = 500000,
3811 .frequency_max = 2500000,
3812 .frequency_stepsize = 0,
3813 .symbol_rate_min = 1000000,
3814 .symbol_rate_max = 45000000,
3815 .symbol_rate_tolerance = 500,
3816 .caps = FE_CAN_INVERSION_AUTO |
3820 .init = cxd2841er_init_s,
3821 .sleep = cxd2841er_sleep_s,
3822 .release = cxd2841er_release,
3823 .set_frontend = cxd2841er_set_frontend_s,
3824 .get_frontend = cxd2841er_get_frontend,
3825 .read_status = cxd2841er_read_status_s,
3826 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3827 .get_frontend_algo = cxd2841er_get_algo,
3828 .set_tone = cxd2841er_set_tone,
3829 .diseqc_send_burst = cxd2841er_send_burst,
3830 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3831 .tune = cxd2841er_tune_s
3834 static struct dvb_frontend_ops cxd2841er_t_c_ops = {
3835 .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
3837 .name = "", /* will set in attach function */
3838 .caps = FE_CAN_FEC_1_2 |
3851 FE_CAN_TRANSMISSION_MODE_AUTO |
3852 FE_CAN_GUARD_INTERVAL_AUTO |
3853 FE_CAN_HIERARCHY_AUTO |
3855 FE_CAN_2G_MODULATION,
3856 .frequency_min = 42000000,
3857 .frequency_max = 1002000000,
3858 .symbol_rate_min = 870000,
3859 .symbol_rate_max = 11700000
3861 .init = cxd2841er_init_tc,
3862 .sleep = cxd2841er_sleep_tc,
3863 .release = cxd2841er_release,
3864 .set_frontend = cxd2841er_set_frontend_tc,
3865 .get_frontend = cxd2841er_get_frontend,
3866 .read_status = cxd2841er_read_status_tc,
3867 .tune = cxd2841er_tune_tc,
3868 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3869 .get_frontend_algo = cxd2841er_get_algo
3872 MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3873 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
3874 MODULE_LICENSE("GPL");