2 * Sony CXD2820R demodulator driver
4 * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 #include "cxd2820r_priv.h"
24 int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
26 struct cxd2820r_priv *priv = fe->demodulator_priv;
27 struct i2c_client *client = priv->client[0];
28 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
33 u8 bw_params1[][5] = {
34 { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
35 { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
36 { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
38 u8 bw_params2[][2] = {
39 { 0x1f, 0xdc }, /* 6 MHz */
40 { 0x12, 0xf8 }, /* 7 MHz */
41 { 0x01, 0xe0 }, /* 8 MHz */
43 struct reg_val_mask tab[] = {
44 { 0x00080, 0x00, 0xff },
45 { 0x00081, 0x03, 0xff },
46 { 0x00085, 0x07, 0xff },
47 { 0x00088, 0x01, 0xff },
49 { 0x00070, priv->ts_mode, 0xff },
50 { 0x00071, !priv->ts_clk_inv << 4, 0x10 },
51 { 0x000cb, priv->if_agc_polarity << 6, 0x40 },
52 { 0x000a5, 0x00, 0x01 },
53 { 0x00082, 0x20, 0x60 },
54 { 0x000c2, 0xc3, 0xff },
55 { 0x0016a, 0x50, 0xff },
56 { 0x00427, 0x41, 0xff },
60 "delivery_system=%d modulation=%d frequency=%u bandwidth_hz=%u inversion=%d\n",
61 c->delivery_system, c->modulation, c->frequency,
62 c->bandwidth_hz, c->inversion);
64 switch (c->bandwidth_hz) {
82 if (fe->ops.tuner_ops.set_params)
83 fe->ops.tuner_ops.set_params(fe);
85 if (priv->delivery_system != SYS_DVBT) {
86 ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
91 priv->delivery_system = SYS_DVBT;
92 priv->ber_running = false; /* tune stops BER counter */
94 /* program IF frequency */
95 if (fe->ops.tuner_ops.get_if_frequency) {
96 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
99 dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
105 utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, CXD2820R_CLK);
106 buf[0] = (utmp >> 16) & 0xff;
107 buf[1] = (utmp >> 8) & 0xff;
108 buf[2] = (utmp >> 0) & 0xff;
109 ret = regmap_bulk_write(priv->regmap[0], 0x00b6, buf, 3);
113 ret = regmap_bulk_write(priv->regmap[0], 0x009f, bw_params1[bw_i], 5);
117 ret = regmap_update_bits(priv->regmap[0], 0x00d7, 0xc0, bw_param << 6);
121 ret = regmap_bulk_write(priv->regmap[0], 0x00d9, bw_params2[bw_i], 2);
125 ret = regmap_write(priv->regmap[0], 0x00ff, 0x08);
129 ret = regmap_write(priv->regmap[0], 0x00fe, 0x01);
135 dev_dbg(&client->dev, "failed=%d\n", ret);
139 int cxd2820r_get_frontend_t(struct dvb_frontend *fe,
140 struct dtv_frontend_properties *c)
142 struct cxd2820r_priv *priv = fe->demodulator_priv;
143 struct i2c_client *client = priv->client[0];
148 dev_dbg(&client->dev, "\n");
150 ret = regmap_bulk_read(priv->regmap[0], 0x002f, buf, sizeof(buf));
154 switch ((buf[0] >> 6) & 0x03) {
156 c->modulation = QPSK;
159 c->modulation = QAM_16;
162 c->modulation = QAM_64;
166 switch ((buf[1] >> 1) & 0x03) {
168 c->transmission_mode = TRANSMISSION_MODE_2K;
171 c->transmission_mode = TRANSMISSION_MODE_8K;
175 switch ((buf[1] >> 3) & 0x03) {
177 c->guard_interval = GUARD_INTERVAL_1_32;
180 c->guard_interval = GUARD_INTERVAL_1_16;
183 c->guard_interval = GUARD_INTERVAL_1_8;
186 c->guard_interval = GUARD_INTERVAL_1_4;
190 switch ((buf[0] >> 3) & 0x07) {
192 c->hierarchy = HIERARCHY_NONE;
195 c->hierarchy = HIERARCHY_1;
198 c->hierarchy = HIERARCHY_2;
201 c->hierarchy = HIERARCHY_4;
205 switch ((buf[0] >> 0) & 0x07) {
207 c->code_rate_HP = FEC_1_2;
210 c->code_rate_HP = FEC_2_3;
213 c->code_rate_HP = FEC_3_4;
216 c->code_rate_HP = FEC_5_6;
219 c->code_rate_HP = FEC_7_8;
223 switch ((buf[1] >> 5) & 0x07) {
225 c->code_rate_LP = FEC_1_2;
228 c->code_rate_LP = FEC_2_3;
231 c->code_rate_LP = FEC_3_4;
234 c->code_rate_LP = FEC_5_6;
237 c->code_rate_LP = FEC_7_8;
241 ret = regmap_read(priv->regmap[0], 0x07c6, &utmp);
245 switch ((utmp >> 0) & 0x01) {
247 c->inversion = INVERSION_OFF;
250 c->inversion = INVERSION_ON;
256 dev_dbg(&client->dev, "failed=%d\n", ret);
260 int cxd2820r_read_status_t(struct dvb_frontend *fe, enum fe_status *status)
262 struct cxd2820r_priv *priv = fe->demodulator_priv;
263 struct i2c_client *client = priv->client[0];
264 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
266 unsigned int utmp, utmp1, utmp2;
270 ret = regmap_bulk_read(priv->regmap[0], 0x0010, &buf[0], 1);
273 ret = regmap_bulk_read(priv->regmap[0], 0x0073, &buf[1], 1);
277 utmp1 = (buf[0] >> 0) & 0x07;
278 utmp2 = (buf[1] >> 3) & 0x01;
280 if (utmp1 == 6 && utmp2 == 1) {
281 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
282 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
283 } else if (utmp1 == 6 || utmp2 == 1) {
284 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
285 FE_HAS_VITERBI | FE_HAS_SYNC;
290 dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
291 *status, 2, buf, utmp1, utmp2);
293 /* Signal strength */
294 if (*status & FE_HAS_SIGNAL) {
295 unsigned int strength;
297 ret = regmap_bulk_read(priv->regmap[0], 0x0026, buf, 2);
301 utmp = buf[0] << 8 | buf[1] << 0;
302 utmp = ~utmp & 0x0fff;
303 /* Scale value to 0x0000-0xffff */
304 strength = utmp << 4 | utmp >> 8;
307 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
308 c->strength.stat[0].uvalue = strength;
311 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
315 if (*status & FE_HAS_VITERBI) {
318 ret = regmap_bulk_read(priv->regmap[0], 0x002c, buf, 2);
322 utmp = buf[0] << 8 | buf[1] << 0;
324 cnr = div_u64((u64)(intlog10(utmp)
325 - intlog10(32000 - utmp) + 55532585)
331 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
332 c->cnr.stat[0].svalue = cnr;
335 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
339 if (*status & FE_HAS_SYNC) {
340 unsigned int post_bit_error;
343 if (priv->ber_running) {
344 ret = regmap_bulk_read(priv->regmap[0], 0x0076, buf, 3);
348 if ((buf[2] >> 7) & 0x01) {
349 post_bit_error = buf[2] << 16 | buf[1] << 8 |
351 post_bit_error &= 0x0fffff;
363 ret = regmap_write(priv->regmap[0], 0x0079, 0x01);
366 priv->ber_running = true;
369 priv->post_bit_error += post_bit_error;
371 c->post_bit_error.len = 1;
372 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
373 c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
375 c->post_bit_error.len = 1;
376 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
381 dev_dbg(&client->dev, "failed=%d\n", ret);
385 int cxd2820r_init_t(struct dvb_frontend *fe)
387 struct cxd2820r_priv *priv = fe->demodulator_priv;
388 struct i2c_client *client = priv->client[0];
391 dev_dbg(&client->dev, "\n");
393 ret = regmap_write(priv->regmap[0], 0x0085, 0x07);
399 dev_dbg(&client->dev, "failed=%d\n", ret);
403 int cxd2820r_sleep_t(struct dvb_frontend *fe)
405 struct cxd2820r_priv *priv = fe->demodulator_priv;
406 struct i2c_client *client = priv->client[0];
408 struct reg_val_mask tab[] = {
409 { 0x000ff, 0x1f, 0xff },
410 { 0x00085, 0x00, 0xff },
411 { 0x00088, 0x01, 0xff },
412 { 0x00081, 0x00, 0xff },
413 { 0x00080, 0x00, 0xff },
416 dev_dbg(&client->dev, "\n");
418 priv->delivery_system = SYS_UNDEFINED;
420 ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
426 dev_dbg(&client->dev, "failed=%d\n", ret);
430 int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
431 struct dvb_frontend_tune_settings *s)
433 s->min_delay_ms = 500;
434 s->step_size = fe->ops.info.frequency_stepsize * 2;
435 s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;