1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Sony CXD2820R demodulator driver
5 * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
9 #include "cxd2820r_priv.h"
11 int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
13 struct cxd2820r_priv *priv = fe->demodulator_priv;
14 struct i2c_client *client = priv->client[0];
15 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
20 u8 bw_params1[][5] = {
21 { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
22 { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
23 { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
25 u8 bw_params2[][2] = {
26 { 0x1f, 0xdc }, /* 6 MHz */
27 { 0x12, 0xf8 }, /* 7 MHz */
28 { 0x01, 0xe0 }, /* 8 MHz */
30 struct reg_val_mask tab[] = {
31 { 0x00080, 0x00, 0xff },
32 { 0x00081, 0x03, 0xff },
33 { 0x00085, 0x07, 0xff },
34 { 0x00088, 0x01, 0xff },
36 { 0x00070, priv->ts_mode, 0xff },
37 { 0x00071, !priv->ts_clk_inv << 4, 0x10 },
38 { 0x000cb, priv->if_agc_polarity << 6, 0x40 },
39 { 0x000a5, 0x00, 0x01 },
40 { 0x00082, 0x20, 0x60 },
41 { 0x000c2, 0xc3, 0xff },
42 { 0x0016a, 0x50, 0xff },
43 { 0x00427, 0x41, 0xff },
47 "delivery_system=%d modulation=%d frequency=%u bandwidth_hz=%u inversion=%d\n",
48 c->delivery_system, c->modulation, c->frequency,
49 c->bandwidth_hz, c->inversion);
51 switch (c->bandwidth_hz) {
69 if (fe->ops.tuner_ops.set_params)
70 fe->ops.tuner_ops.set_params(fe);
72 if (priv->delivery_system != SYS_DVBT) {
73 ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
78 priv->delivery_system = SYS_DVBT;
79 priv->ber_running = false; /* tune stops BER counter */
81 /* program IF frequency */
82 if (fe->ops.tuner_ops.get_if_frequency) {
83 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
86 dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
92 utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, CXD2820R_CLK);
93 buf[0] = (utmp >> 16) & 0xff;
94 buf[1] = (utmp >> 8) & 0xff;
95 buf[2] = (utmp >> 0) & 0xff;
96 ret = regmap_bulk_write(priv->regmap[0], 0x00b6, buf, 3);
100 ret = regmap_bulk_write(priv->regmap[0], 0x009f, bw_params1[bw_i], 5);
104 ret = regmap_update_bits(priv->regmap[0], 0x00d7, 0xc0, bw_param << 6);
108 ret = regmap_bulk_write(priv->regmap[0], 0x00d9, bw_params2[bw_i], 2);
112 ret = regmap_write(priv->regmap[0], 0x00ff, 0x08);
116 ret = regmap_write(priv->regmap[0], 0x00fe, 0x01);
122 dev_dbg(&client->dev, "failed=%d\n", ret);
126 int cxd2820r_get_frontend_t(struct dvb_frontend *fe,
127 struct dtv_frontend_properties *c)
129 struct cxd2820r_priv *priv = fe->demodulator_priv;
130 struct i2c_client *client = priv->client[0];
135 dev_dbg(&client->dev, "\n");
137 ret = regmap_bulk_read(priv->regmap[0], 0x002f, buf, sizeof(buf));
141 switch ((buf[0] >> 6) & 0x03) {
143 c->modulation = QPSK;
146 c->modulation = QAM_16;
149 c->modulation = QAM_64;
153 switch ((buf[1] >> 1) & 0x03) {
155 c->transmission_mode = TRANSMISSION_MODE_2K;
158 c->transmission_mode = TRANSMISSION_MODE_8K;
162 switch ((buf[1] >> 3) & 0x03) {
164 c->guard_interval = GUARD_INTERVAL_1_32;
167 c->guard_interval = GUARD_INTERVAL_1_16;
170 c->guard_interval = GUARD_INTERVAL_1_8;
173 c->guard_interval = GUARD_INTERVAL_1_4;
177 switch ((buf[0] >> 3) & 0x07) {
179 c->hierarchy = HIERARCHY_NONE;
182 c->hierarchy = HIERARCHY_1;
185 c->hierarchy = HIERARCHY_2;
188 c->hierarchy = HIERARCHY_4;
192 switch ((buf[0] >> 0) & 0x07) {
194 c->code_rate_HP = FEC_1_2;
197 c->code_rate_HP = FEC_2_3;
200 c->code_rate_HP = FEC_3_4;
203 c->code_rate_HP = FEC_5_6;
206 c->code_rate_HP = FEC_7_8;
210 switch ((buf[1] >> 5) & 0x07) {
212 c->code_rate_LP = FEC_1_2;
215 c->code_rate_LP = FEC_2_3;
218 c->code_rate_LP = FEC_3_4;
221 c->code_rate_LP = FEC_5_6;
224 c->code_rate_LP = FEC_7_8;
228 ret = regmap_read(priv->regmap[0], 0x07c6, &utmp);
232 switch ((utmp >> 0) & 0x01) {
234 c->inversion = INVERSION_OFF;
237 c->inversion = INVERSION_ON;
243 dev_dbg(&client->dev, "failed=%d\n", ret);
247 int cxd2820r_read_status_t(struct dvb_frontend *fe, enum fe_status *status)
249 struct cxd2820r_priv *priv = fe->demodulator_priv;
250 struct i2c_client *client = priv->client[0];
251 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
253 unsigned int utmp, utmp1, utmp2;
257 ret = regmap_bulk_read(priv->regmap[0], 0x0010, &buf[0], 1);
260 ret = regmap_bulk_read(priv->regmap[0], 0x0073, &buf[1], 1);
264 utmp1 = (buf[0] >> 0) & 0x07;
265 utmp2 = (buf[1] >> 3) & 0x01;
267 if (utmp1 == 6 && utmp2 == 1) {
268 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
269 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
270 } else if (utmp1 == 6 || utmp2 == 1) {
271 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
272 FE_HAS_VITERBI | FE_HAS_SYNC;
277 dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
278 *status, 2, buf, utmp1, utmp2);
280 /* Signal strength */
281 if (*status & FE_HAS_SIGNAL) {
282 unsigned int strength;
284 ret = regmap_bulk_read(priv->regmap[0], 0x0026, buf, 2);
288 utmp = buf[0] << 8 | buf[1] << 0;
289 utmp = ~utmp & 0x0fff;
290 /* Scale value to 0x0000-0xffff */
291 strength = utmp << 4 | utmp >> 8;
294 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
295 c->strength.stat[0].uvalue = strength;
298 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
302 if (*status & FE_HAS_VITERBI) {
305 ret = regmap_bulk_read(priv->regmap[0], 0x002c, buf, 2);
309 utmp = buf[0] << 8 | buf[1] << 0;
311 cnr = div_u64((u64)(intlog10(utmp)
312 - intlog10(32000 - utmp) + 55532585)
318 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
319 c->cnr.stat[0].svalue = cnr;
322 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
326 if (*status & FE_HAS_SYNC) {
327 unsigned int post_bit_error;
330 if (priv->ber_running) {
331 ret = regmap_bulk_read(priv->regmap[0], 0x0076, buf, 3);
335 if ((buf[2] >> 7) & 0x01) {
336 post_bit_error = buf[2] << 16 | buf[1] << 8 |
338 post_bit_error &= 0x0fffff;
350 ret = regmap_write(priv->regmap[0], 0x0079, 0x01);
353 priv->ber_running = true;
356 priv->post_bit_error += post_bit_error;
358 c->post_bit_error.len = 1;
359 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
360 c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
362 c->post_bit_error.len = 1;
363 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
368 dev_dbg(&client->dev, "failed=%d\n", ret);
372 int cxd2820r_init_t(struct dvb_frontend *fe)
374 struct cxd2820r_priv *priv = fe->demodulator_priv;
375 struct i2c_client *client = priv->client[0];
378 dev_dbg(&client->dev, "\n");
380 ret = regmap_write(priv->regmap[0], 0x0085, 0x07);
386 dev_dbg(&client->dev, "failed=%d\n", ret);
390 int cxd2820r_sleep_t(struct dvb_frontend *fe)
392 struct cxd2820r_priv *priv = fe->demodulator_priv;
393 struct i2c_client *client = priv->client[0];
395 static struct reg_val_mask tab[] = {
396 { 0x000ff, 0x1f, 0xff },
397 { 0x00085, 0x00, 0xff },
398 { 0x00088, 0x01, 0xff },
399 { 0x00081, 0x00, 0xff },
400 { 0x00080, 0x00, 0xff },
403 dev_dbg(&client->dev, "\n");
405 priv->delivery_system = SYS_UNDEFINED;
407 ret = cxd2820r_wr_reg_val_mask_tab(priv, tab, ARRAY_SIZE(tab));
413 dev_dbg(&client->dev, "failed=%d\n", ret);
417 int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
418 struct dvb_frontend_tune_settings *s)
420 s->min_delay_ms = 500;
421 s->step_size = fe->ops.info.frequency_stepsize_hz * 2;
422 s->max_drift = (fe->ops.info.frequency_stepsize_hz * 2) + 1;