1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Conexant cx24120/cx24118 - DVBS/S2 Satellite demod/tuner driver
5 Copyright (C) 2008 Patrick Boettcher <pb@linuxtv.org>
6 Copyright (C) 2009 Sergey Tyurin <forum.free-x.de>
7 Updated 2012 by Jannis Achstetter <jannis_achstetter@web.de>
8 Copyright (C) 2015 Jemma Denson <jdenson@gmail.com>
10 Refactored & simplified driver
11 Updated to work with delivery system supplied by DVBv5
12 Add frequency, fec & pilot to get_frontend
14 Cards supported: Technisat Skystar S2
18 #include <linux/slab.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/init.h>
23 #include <linux/firmware.h>
24 #include <media/dvb_frontend.h>
27 #define CX24120_SEARCH_RANGE_KHZ 5000
28 #define CX24120_FIRMWARE "/*(DEBLOBBED)*/"
30 /* cx24120 i2c registers */
31 #define CX24120_REG_CMD_START 0x00 /* write cmd_id */
32 #define CX24120_REG_CMD_ARGS 0x01 /* write command arguments */
33 #define CX24120_REG_CMD_END 0x1f /* write 0x01 for end */
35 #define CX24120_REG_MAILBOX 0x33
36 #define CX24120_REG_FREQ3 0x34 /* frequency */
37 #define CX24120_REG_FREQ2 0x35
38 #define CX24120_REG_FREQ1 0x36
40 #define CX24120_REG_FECMODE 0x39 /* FEC status */
41 #define CX24120_REG_STATUS 0x3a /* Tuner status */
42 #define CX24120_REG_SIGSTR_H 0x3a /* Signal strength high */
43 #define CX24120_REG_SIGSTR_L 0x3b /* Signal strength low byte */
44 #define CX24120_REG_QUALITY_H 0x40 /* SNR high byte */
45 #define CX24120_REG_QUALITY_L 0x41 /* SNR low byte */
47 #define CX24120_REG_BER_HH 0x47 /* BER high byte of high word */
48 #define CX24120_REG_BER_HL 0x48 /* BER low byte of high word */
49 #define CX24120_REG_BER_LH 0x49 /* BER high byte of low word */
50 #define CX24120_REG_BER_LL 0x4a /* BER low byte of low word */
52 #define CX24120_REG_UCB_H 0x50 /* UCB high byte */
53 #define CX24120_REG_UCB_L 0x51 /* UCB low byte */
55 #define CX24120_REG_CLKDIV 0xe6
56 #define CX24120_REG_RATEDIV 0xf0
58 #define CX24120_REG_REVISION 0xff /* Chip revision (ro) */
60 /* Command messages */
61 enum command_message_id {
62 CMD_VCO_SET = 0x10, /* cmd.len = 12; */
63 CMD_TUNEREQUEST = 0x11, /* cmd.len = 15; */
65 CMD_MPEG_ONOFF = 0x13, /* cmd.len = 4; */
66 CMD_MPEG_INIT = 0x14, /* cmd.len = 7; */
67 CMD_BANDWIDTH = 0x15, /* cmd.len = 12; */
68 CMD_CLOCK_READ = 0x16, /* read clock */
69 CMD_CLOCK_SET = 0x17, /* cmd.len = 10; */
71 CMD_DISEQC_MSG1 = 0x20, /* cmd.len = 11; */
72 CMD_DISEQC_MSG2 = 0x21, /* cmd.len = d->msg_len + 6; */
73 CMD_SETVOLTAGE = 0x22, /* cmd.len = 2; */
74 CMD_SETTONE = 0x23, /* cmd.len = 4; */
75 CMD_DISEQC_BURST = 0x24, /* cmd.len not used !!! */
77 CMD_READ_SNR = 0x1a, /* Read signal strength */
78 CMD_START_TUNER = 0x1b, /* ??? */
82 CMD_BER_CTRL = 0x3c, /* cmd.len = 0x03; */
85 #define CX24120_MAX_CMD_LEN 30
88 #define CX24120_PILOT_OFF 0x00
89 #define CX24120_PILOT_ON 0x40
90 #define CX24120_PILOT_AUTO 0x80
93 #define CX24120_HAS_SIGNAL 0x01
94 #define CX24120_HAS_CARRIER 0x02
95 #define CX24120_HAS_VITERBI 0x04
96 #define CX24120_HAS_LOCK 0x08
97 #define CX24120_HAS_UNK1 0x10
98 #define CX24120_HAS_UNK2 0x20
99 #define CX24120_STATUS_MASK 0x0f
100 #define CX24120_SIGNAL_MASK 0xc0
103 #define CX24120_BER_WINDOW 16
104 #define CX24120_BER_WSIZE ((1 << CX24120_BER_WINDOW) * 208 * 8)
106 #define info(args...) pr_info("cx24120: " args)
107 #define err(args...) pr_err("cx24120: ### ERROR: " args)
109 /* The Demod/Tuner can't easily provide these, we cache them */
110 struct cx24120_tuning {
113 enum fe_spectral_inversion inversion;
114 enum fe_code_rate fec;
116 enum fe_delivery_system delsys;
117 enum fe_modulation modulation;
130 struct cx24120_state {
131 struct i2c_adapter *i2c;
132 const struct cx24120_config *config;
133 struct dvb_frontend frontend;
139 /* current and next tuning parameters */
140 struct cx24120_tuning dcur;
141 struct cx24120_tuning dnxt;
143 enum fe_status fe_status;
145 /* dvbv5 stats calculations */
150 unsigned long ber_jiffies_stats;
151 unsigned long per_jiffies_stats;
154 /* Command message to firmware */
158 u8 arg[CX24120_MAX_CMD_LEN];
161 /* Read single register */
162 static int cx24120_readreg(struct cx24120_state *state, u8 reg)
166 struct i2c_msg msg[] = {
168 .addr = state->config->i2c_addr,
173 .addr = state->config->i2c_addr,
180 ret = i2c_transfer(state->i2c, msg, 2);
182 err("Read error: reg=0x%02x, ret=%i)\n", reg, ret);
186 dev_dbg(&state->i2c->dev, "reg=0x%02x; data=0x%02x\n", reg, buf);
191 /* Write single register */
192 static int cx24120_writereg(struct cx24120_state *state, u8 reg, u8 data)
194 u8 buf[] = { reg, data };
195 struct i2c_msg msg = {
196 .addr = state->config->i2c_addr,
203 ret = i2c_transfer(state->i2c, &msg, 1);
205 err("Write error: i2c_write error(err == %i, 0x%02x: 0x%02x)\n",
210 dev_dbg(&state->i2c->dev, "reg=0x%02x; data=0x%02x\n", reg, data);
215 /* Write multiple registers in chunks of i2c_wr_max-sized buffers */
216 static int cx24120_writeregs(struct cx24120_state *state,
217 u8 reg, const u8 *values, u16 len, u8 incr)
220 u16 max = state->config->i2c_wr_max > 0 ?
221 state->config->i2c_wr_max :
224 struct i2c_msg msg = {
225 .addr = state->config->i2c_addr,
229 msg.buf = kmalloc(max + 1, GFP_KERNEL);
235 msg.len = len > max ? max : len;
236 memcpy(&msg.buf[1], values, msg.len);
238 len -= msg.len; /* data length revers counter */
239 values += msg.len; /* incr data pointer */
243 msg.len++; /* don't forget the addr byte */
245 ret = i2c_transfer(state->i2c, &msg, 1);
247 err("i2c_write error(err == %i, 0x%02x)\n", ret, reg);
251 dev_dbg(&state->i2c->dev, "reg=0x%02x; data=%*ph\n",
252 reg, msg.len - 1, msg.buf + 1);
262 static const struct dvb_frontend_ops cx24120_ops;
264 struct dvb_frontend *cx24120_attach(const struct cx24120_config *config,
265 struct i2c_adapter *i2c)
267 struct cx24120_state *state;
270 info("Conexant cx24120/cx24118 - DVBS/S2 Satellite demod/tuner\n");
271 state = kzalloc(sizeof(*state), GFP_KERNEL);
273 err("Unable to allocate memory for cx24120_state\n");
277 /* setup the state */
278 state->config = config;
281 /* check if the demod is present and has proper type */
282 demod_rev = cx24120_readreg(state, CX24120_REG_REVISION);
285 info("Demod cx24120 rev. 0x07 detected.\n");
288 info("Demod cx24120 rev. 0x05 detected.\n");
291 err("Unsupported demod revision: 0x%x detected.\n", demod_rev);
295 /* create dvb_frontend */
296 state->cold_init = 0;
297 memcpy(&state->frontend.ops, &cx24120_ops,
298 sizeof(struct dvb_frontend_ops));
299 state->frontend.demodulator_priv = state;
301 info("Conexant cx24120/cx24118 attached.\n");
302 return &state->frontend;
308 EXPORT_SYMBOL_GPL(cx24120_attach);
310 static int cx24120_test_rom(struct cx24120_state *state)
314 err = cx24120_readreg(state, 0xfd);
316 ret = cx24120_readreg(state, 0xdf) & 0xfe;
317 err = cx24120_writereg(state, 0xdf, ret);
322 static int cx24120_read_snr(struct dvb_frontend *fe, u16 *snr)
324 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
326 if (c->cnr.stat[0].scale != FE_SCALE_DECIBEL)
329 *snr = div_s64(c->cnr.stat[0].svalue, 100);
334 static int cx24120_read_ber(struct dvb_frontend *fe, u32 *ber)
336 struct cx24120_state *state = fe->demodulator_priv;
337 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
339 if (c->post_bit_error.stat[0].scale != FE_SCALE_COUNTER) {
344 *ber = c->post_bit_error.stat[0].uvalue - state->ber_prev;
345 state->ber_prev = c->post_bit_error.stat[0].uvalue;
350 static int cx24120_msg_mpeg_output_global_config(struct cx24120_state *state,
353 /* Check if we're running a command that needs to disable mpeg out */
354 static void cx24120_check_cmd(struct cx24120_state *state, u8 id)
357 case CMD_TUNEREQUEST:
359 case CMD_DISEQC_MSG1:
360 case CMD_DISEQC_MSG2:
363 case CMD_DISEQC_BURST:
364 cx24120_msg_mpeg_output_global_config(state, 0);
365 /* Old driver would do a msleep(100) here */
371 /* Send a message to the firmware */
372 static int cx24120_message_send(struct cx24120_state *state,
373 struct cx24120_cmd *cmd)
377 if (state->mpeg_enabled) {
378 /* Disable mpeg out on certain commands */
379 cx24120_check_cmd(state, cmd->id);
382 cx24120_writereg(state, CX24120_REG_CMD_START, cmd->id);
383 cx24120_writeregs(state, CX24120_REG_CMD_ARGS, &cmd->arg[0],
385 cx24120_writereg(state, CX24120_REG_CMD_END, 0x01);
388 while (cx24120_readreg(state, CX24120_REG_CMD_END)) {
392 err("Error sending message to firmware\n");
396 dev_dbg(&state->i2c->dev, "sent message 0x%02x\n", cmd->id);
401 /* Send a message and fill arg[] with the results */
402 static int cx24120_message_sendrcv(struct cx24120_state *state,
403 struct cx24120_cmd *cmd, u8 numreg)
407 if (numreg > CX24120_MAX_CMD_LEN) {
408 err("Too many registers to read. cmd->reg = %d", numreg);
412 ret = cx24120_message_send(state, cmd);
419 /* Read numreg registers starting from register cmd->len */
420 for (i = 0; i < numreg; i++)
421 cmd->arg[i] = cx24120_readreg(state, (cmd->len + i + 1));
426 static int cx24120_read_signal_strength(struct dvb_frontend *fe,
427 u16 *signal_strength)
429 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
431 if (c->strength.stat[0].scale != FE_SCALE_RELATIVE)
432 *signal_strength = 0;
434 *signal_strength = c->strength.stat[0].uvalue;
439 static int cx24120_msg_mpeg_output_global_config(struct cx24120_state *state,
442 struct cx24120_cmd cmd;
445 cmd.id = CMD_MPEG_ONOFF;
449 cmd.arg[2] = enable ? 0 : (u8)(-1);
452 ret = cx24120_message_send(state, &cmd);
454 dev_dbg(&state->i2c->dev, "failed to %s MPEG output\n",
455 enable ? "enable" : "disable");
459 state->mpeg_enabled = enable;
460 dev_dbg(&state->i2c->dev, "MPEG output %s\n",
461 enable ? "enabled" : "disabled");
466 static int cx24120_msg_mpeg_output_config(struct cx24120_state *state, u8 seq)
468 struct cx24120_cmd cmd;
469 struct cx24120_initial_mpeg_config i =
470 state->config->initial_mpeg_config;
472 cmd.id = CMD_MPEG_INIT;
474 cmd.arg[0] = seq; /* sequental number - can be 0,1,2 */
475 cmd.arg[1] = ((i.x1 & 0x01) << 1) | ((i.x1 >> 1) & 0x01);
478 cmd.arg[4] = ((i.x2 >> 1) & 0x01);
479 cmd.arg[5] = (i.x2 & 0xf0) | (i.x3 & 0x0f);
482 return cx24120_message_send(state, &cmd);
485 static int cx24120_diseqc_send_burst(struct dvb_frontend *fe,
486 enum fe_sec_mini_cmd burst)
488 struct cx24120_state *state = fe->demodulator_priv;
489 struct cx24120_cmd cmd;
491 dev_dbg(&state->i2c->dev, "\n");
494 * Yes, cmd.len is set to zero. The old driver
495 * didn't specify any len, but also had a
496 * memset 0 before every use of the cmd struct
497 * which would have set it to zero.
498 * This quite probably needs looking into.
500 cmd.id = CMD_DISEQC_BURST;
503 cmd.arg[1] = (burst == SEC_MINI_B) ? 0x01 : 0x00;
505 return cx24120_message_send(state, &cmd);
508 static int cx24120_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)
510 struct cx24120_state *state = fe->demodulator_priv;
511 struct cx24120_cmd cmd;
513 dev_dbg(&state->i2c->dev, "(%d)\n", tone);
515 if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) {
516 err("Invalid tone=%d\n", tone);
520 cmd.id = CMD_SETTONE;
525 cmd.arg[3] = (tone == SEC_TONE_ON) ? 0x01 : 0x00;
527 return cx24120_message_send(state, &cmd);
530 static int cx24120_set_voltage(struct dvb_frontend *fe,
531 enum fe_sec_voltage voltage)
533 struct cx24120_state *state = fe->demodulator_priv;
534 struct cx24120_cmd cmd;
536 dev_dbg(&state->i2c->dev, "(%d)\n", voltage);
538 cmd.id = CMD_SETVOLTAGE;
541 cmd.arg[1] = (voltage == SEC_VOLTAGE_18) ? 0x01 : 0x00;
543 return cx24120_message_send(state, &cmd);
546 static int cx24120_send_diseqc_msg(struct dvb_frontend *fe,
547 struct dvb_diseqc_master_cmd *d)
549 struct cx24120_state *state = fe->demodulator_priv;
550 struct cx24120_cmd cmd;
553 dev_dbg(&state->i2c->dev, "\n");
555 cmd.id = CMD_DISEQC_MSG1;
569 if (cx24120_message_send(state, &cmd)) {
570 err("send 1st message(0x%x) failed\n", cmd.id);
574 cmd.id = CMD_DISEQC_MSG2;
575 cmd.len = d->msg_len + 6;
581 cmd.arg[5] = d->msg_len;
583 memcpy(&cmd.arg[6], &d->msg, d->msg_len);
585 if (cx24120_message_send(state, &cmd)) {
586 err("send 2nd message(0x%x) failed\n", cmd.id);
592 if (!(cx24120_readreg(state, 0x93) & 0x01)) {
593 dev_dbg(&state->i2c->dev, "diseqc sequence sent\n");
598 } while (back_count);
600 err("Too long waiting for diseqc.\n");
604 static void cx24120_get_stats(struct cx24120_state *state)
606 struct dvb_frontend *fe = &state->frontend;
607 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
608 struct cx24120_cmd cmd;
613 dev_dbg(&state->i2c->dev, "\n");
615 /* signal strength */
616 if (state->fe_status & FE_HAS_SIGNAL) {
617 cmd.id = CMD_READ_SNR;
621 ret = cx24120_message_send(state, &cmd);
623 err("error reading signal strength\n");
628 sig = cx24120_readreg(state, CX24120_REG_SIGSTR_H) >> 6;
630 sig |= cx24120_readreg(state, CX24120_REG_SIGSTR_L);
631 dev_dbg(&state->i2c->dev,
632 "signal strength from firmware = 0x%x\n", sig);
635 sig = -100 * sig + 94324;
637 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
638 c->strength.stat[0].uvalue = sig;
640 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
644 if (state->fe_status & FE_HAS_VITERBI) {
645 cnr = cx24120_readreg(state, CX24120_REG_QUALITY_H) << 8;
646 cnr |= cx24120_readreg(state, CX24120_REG_QUALITY_L);
647 dev_dbg(&state->i2c->dev, "read SNR index = %d\n", cnr);
649 /* guessed - seems about right */
652 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
653 c->cnr.stat[0].svalue = cnr;
655 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
658 /* BER & UCB require lock */
659 if (!(state->fe_status & FE_HAS_LOCK)) {
660 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
661 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
662 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
663 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
668 if (time_after(jiffies, state->ber_jiffies_stats)) {
669 msecs = (state->berw_usecs + 500) / 1000;
670 state->ber_jiffies_stats = jiffies + msecs_to_jiffies(msecs);
672 ber = cx24120_readreg(state, CX24120_REG_BER_HH) << 24;
673 ber |= cx24120_readreg(state, CX24120_REG_BER_HL) << 16;
674 ber |= cx24120_readreg(state, CX24120_REG_BER_LH) << 8;
675 ber |= cx24120_readreg(state, CX24120_REG_BER_LL);
676 dev_dbg(&state->i2c->dev, "read BER index = %d\n", ber);
678 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
679 c->post_bit_error.stat[0].uvalue += ber;
681 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
682 c->post_bit_count.stat[0].uvalue += CX24120_BER_WSIZE;
686 if (time_after(jiffies, state->per_jiffies_stats)) {
687 state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
689 ucb = cx24120_readreg(state, CX24120_REG_UCB_H) << 8;
690 ucb |= cx24120_readreg(state, CX24120_REG_UCB_L);
691 dev_dbg(&state->i2c->dev, "ucblocks = %d\n", ucb);
694 if (ucb < state->ucb_offset)
695 state->ucb_offset = c->block_error.stat[0].uvalue;
697 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
698 c->block_error.stat[0].uvalue = ucb + state->ucb_offset;
700 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
701 c->block_count.stat[0].uvalue += state->bitrate / 8 / 208;
705 static void cx24120_set_clock_ratios(struct dvb_frontend *fe);
707 /* Read current tuning status */
708 static int cx24120_read_status(struct dvb_frontend *fe, enum fe_status *status)
710 struct cx24120_state *state = fe->demodulator_priv;
713 lock = cx24120_readreg(state, CX24120_REG_STATUS);
715 dev_dbg(&state->i2c->dev, "status = 0x%02x\n", lock);
719 if (lock & CX24120_HAS_SIGNAL)
720 *status = FE_HAS_SIGNAL;
721 if (lock & CX24120_HAS_CARRIER)
722 *status |= FE_HAS_CARRIER;
723 if (lock & CX24120_HAS_VITERBI)
724 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
725 if (lock & CX24120_HAS_LOCK)
726 *status |= FE_HAS_LOCK;
729 * TODO: is FE_HAS_SYNC in the right place?
730 * Other cx241xx drivers have this slightly
734 state->fe_status = *status;
735 cx24120_get_stats(state);
737 /* Set the clock once tuned in */
738 if (state->need_clock_set && *status & FE_HAS_LOCK) {
739 /* Set clock ratios */
740 cx24120_set_clock_ratios(fe);
742 /* Old driver would do a msleep(200) here */
744 /* Renable mpeg output */
745 if (!state->mpeg_enabled)
746 cx24120_msg_mpeg_output_global_config(state, 1);
748 state->need_clock_set = 0;
755 * FEC & modulation lookup table
756 * Used for decoding the REG_FECMODE register
759 struct cx24120_modfec {
760 enum fe_delivery_system delsys;
761 enum fe_modulation mod;
762 enum fe_code_rate fec;
766 static const struct cx24120_modfec modfec_lookup_table[] = {
767 /*delsys mod fec val */
768 { SYS_DVBS, QPSK, FEC_1_2, 0x01 },
769 { SYS_DVBS, QPSK, FEC_2_3, 0x02 },
770 { SYS_DVBS, QPSK, FEC_3_4, 0x03 },
771 { SYS_DVBS, QPSK, FEC_4_5, 0x04 },
772 { SYS_DVBS, QPSK, FEC_5_6, 0x05 },
773 { SYS_DVBS, QPSK, FEC_6_7, 0x06 },
774 { SYS_DVBS, QPSK, FEC_7_8, 0x07 },
776 { SYS_DVBS2, QPSK, FEC_1_2, 0x04 },
777 { SYS_DVBS2, QPSK, FEC_3_5, 0x05 },
778 { SYS_DVBS2, QPSK, FEC_2_3, 0x06 },
779 { SYS_DVBS2, QPSK, FEC_3_4, 0x07 },
780 { SYS_DVBS2, QPSK, FEC_4_5, 0x08 },
781 { SYS_DVBS2, QPSK, FEC_5_6, 0x09 },
782 { SYS_DVBS2, QPSK, FEC_8_9, 0x0a },
783 { SYS_DVBS2, QPSK, FEC_9_10, 0x0b },
785 { SYS_DVBS2, PSK_8, FEC_3_5, 0x0c },
786 { SYS_DVBS2, PSK_8, FEC_2_3, 0x0d },
787 { SYS_DVBS2, PSK_8, FEC_3_4, 0x0e },
788 { SYS_DVBS2, PSK_8, FEC_5_6, 0x0f },
789 { SYS_DVBS2, PSK_8, FEC_8_9, 0x10 },
790 { SYS_DVBS2, PSK_8, FEC_9_10, 0x11 },
793 /* Retrieve current fec, modulation & pilot values */
794 static int cx24120_get_fec(struct dvb_frontend *fe)
796 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
797 struct cx24120_state *state = fe->demodulator_priv;
802 ret = cx24120_readreg(state, CX24120_REG_FECMODE);
803 fec = ret & 0x3f; /* Lower 6 bits */
805 dev_dbg(&state->i2c->dev, "raw fec = %d\n", fec);
807 for (idx = 0; idx < ARRAY_SIZE(modfec_lookup_table); idx++) {
808 if (modfec_lookup_table[idx].delsys != state->dcur.delsys)
810 if (modfec_lookup_table[idx].val != fec)
816 if (idx >= ARRAY_SIZE(modfec_lookup_table)) {
817 dev_dbg(&state->i2c->dev, "couldn't find fec!\n");
821 /* save values back to cache */
822 c->modulation = modfec_lookup_table[idx].mod;
823 c->fec_inner = modfec_lookup_table[idx].fec;
824 c->pilot = (ret & 0x80) ? PILOT_ON : PILOT_OFF;
826 dev_dbg(&state->i2c->dev, "mod(%d), fec(%d), pilot(%d)\n",
827 c->modulation, c->fec_inner, c->pilot);
832 /* Calculate ber window time */
833 static void cx24120_calculate_ber_window(struct cx24120_state *state, u32 rate)
835 struct dvb_frontend *fe = &state->frontend;
836 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
840 * Calculate bitrate from rate in the clock ratios table.
841 * This isn't *exactly* right but close enough.
843 tmp = (u64)c->symbol_rate * rate;
845 state->bitrate = tmp;
847 /* usecs per ber window */
848 tmp = 1000000ULL * CX24120_BER_WSIZE;
849 do_div(tmp, state->bitrate);
850 state->berw_usecs = tmp;
852 dev_dbg(&state->i2c->dev, "bitrate: %u, berw_usecs: %u\n",
853 state->bitrate, state->berw_usecs);
857 * Clock ratios lookup table
859 * Values obtained from much larger table in old driver
860 * which had numerous entries which would never match.
862 * There's probably some way of calculating these but I
863 * can't determine the pattern
865 struct cx24120_clock_ratios_table {
866 enum fe_delivery_system delsys;
868 enum fe_modulation mod;
869 enum fe_code_rate fec;
875 static const struct cx24120_clock_ratios_table clock_ratios_table[] = {
876 /*delsys pilot mod fec m_rat n_rat rate */
877 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_1_2, 273088, 254505, 274 },
878 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_3_5, 17272, 13395, 330 },
879 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_2_3, 24344, 16967, 367 },
880 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_3_4, 410788, 254505, 413 },
881 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_4_5, 438328, 254505, 440 },
882 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_5_6, 30464, 16967, 459 },
883 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_8_9, 487832, 254505, 490 },
884 { SYS_DVBS2, PILOT_OFF, QPSK, FEC_9_10, 493952, 254505, 496 },
885 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_3_5, 328168, 169905, 494 },
886 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_2_3, 24344, 11327, 550 },
887 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_3_4, 410788, 169905, 618 },
888 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_5_6, 30464, 11327, 688 },
889 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_8_9, 487832, 169905, 735 },
890 { SYS_DVBS2, PILOT_OFF, PSK_8, FEC_9_10, 493952, 169905, 744 },
891 { SYS_DVBS2, PILOT_ON, QPSK, FEC_1_2, 273088, 260709, 268 },
892 { SYS_DVBS2, PILOT_ON, QPSK, FEC_3_5, 328168, 260709, 322 },
893 { SYS_DVBS2, PILOT_ON, QPSK, FEC_2_3, 121720, 86903, 358 },
894 { SYS_DVBS2, PILOT_ON, QPSK, FEC_3_4, 410788, 260709, 403 },
895 { SYS_DVBS2, PILOT_ON, QPSK, FEC_4_5, 438328, 260709, 430 },
896 { SYS_DVBS2, PILOT_ON, QPSK, FEC_5_6, 152320, 86903, 448 },
897 { SYS_DVBS2, PILOT_ON, QPSK, FEC_8_9, 487832, 260709, 479 },
898 { SYS_DVBS2, PILOT_ON, QPSK, FEC_9_10, 493952, 260709, 485 },
899 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_3_5, 328168, 173853, 483 },
900 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_2_3, 121720, 57951, 537 },
901 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_3_4, 410788, 173853, 604 },
902 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_5_6, 152320, 57951, 672 },
903 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_8_9, 487832, 173853, 718 },
904 { SYS_DVBS2, PILOT_ON, PSK_8, FEC_9_10, 493952, 173853, 727 },
905 { SYS_DVBS, PILOT_OFF, QPSK, FEC_1_2, 152592, 152592, 256 },
906 { SYS_DVBS, PILOT_OFF, QPSK, FEC_2_3, 305184, 228888, 341 },
907 { SYS_DVBS, PILOT_OFF, QPSK, FEC_3_4, 457776, 305184, 384 },
908 { SYS_DVBS, PILOT_OFF, QPSK, FEC_5_6, 762960, 457776, 427 },
909 { SYS_DVBS, PILOT_OFF, QPSK, FEC_7_8, 1068144, 610368, 448 },
912 /* Set clock ratio from lookup table */
913 static void cx24120_set_clock_ratios(struct dvb_frontend *fe)
915 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
916 struct cx24120_state *state = fe->demodulator_priv;
917 struct cx24120_cmd cmd;
920 /* Find fec, modulation, pilot */
921 ret = cx24120_get_fec(fe);
925 /* Find the clock ratios in the lookup table */
926 for (idx = 0; idx < ARRAY_SIZE(clock_ratios_table); idx++) {
927 if (clock_ratios_table[idx].delsys != state->dcur.delsys)
929 if (clock_ratios_table[idx].mod != c->modulation)
931 if (clock_ratios_table[idx].fec != c->fec_inner)
933 if (clock_ratios_table[idx].pilot != c->pilot)
939 if (idx >= ARRAY_SIZE(clock_ratios_table)) {
940 info("Clock ratio not found - data reception in danger\n");
944 /* Read current values? */
945 cmd.id = CMD_CLOCK_READ;
948 ret = cx24120_message_sendrcv(state, &cmd, 6);
951 /* in cmd[0]-[5] - result */
953 dev_dbg(&state->i2c->dev, "m=%d, n=%d; idx: %d m=%d, n=%d, rate=%d\n",
954 cmd.arg[2] | (cmd.arg[1] << 8) | (cmd.arg[0] << 16),
955 cmd.arg[5] | (cmd.arg[4] << 8) | (cmd.arg[3] << 16),
957 clock_ratios_table[idx].m_rat,
958 clock_ratios_table[idx].n_rat,
959 clock_ratios_table[idx].rate);
962 cmd.id = CMD_CLOCK_SET;
966 cmd.arg[2] = (clock_ratios_table[idx].m_rat >> 16) & 0xff;
967 cmd.arg[3] = (clock_ratios_table[idx].m_rat >> 8) & 0xff;
968 cmd.arg[4] = (clock_ratios_table[idx].m_rat >> 0) & 0xff;
969 cmd.arg[5] = (clock_ratios_table[idx].n_rat >> 16) & 0xff;
970 cmd.arg[6] = (clock_ratios_table[idx].n_rat >> 8) & 0xff;
971 cmd.arg[7] = (clock_ratios_table[idx].n_rat >> 0) & 0xff;
972 cmd.arg[8] = (clock_ratios_table[idx].rate >> 8) & 0xff;
973 cmd.arg[9] = (clock_ratios_table[idx].rate >> 0) & 0xff;
975 ret = cx24120_message_send(state, &cmd);
979 /* Calculate ber window rates for stat work */
980 cx24120_calculate_ber_window(state, clock_ratios_table[idx].rate);
983 /* Set inversion value */
984 static int cx24120_set_inversion(struct cx24120_state *state,
985 enum fe_spectral_inversion inversion)
987 dev_dbg(&state->i2c->dev, "(%d)\n", inversion);
991 state->dnxt.inversion_val = 0x00;
994 state->dnxt.inversion_val = 0x04;
997 state->dnxt.inversion_val = 0x0c;
1003 state->dnxt.inversion = inversion;
1008 /* FEC lookup table for tuning */
1009 struct cx24120_modfec_table {
1010 enum fe_delivery_system delsys;
1011 enum fe_modulation mod;
1012 enum fe_code_rate fec;
1016 static const struct cx24120_modfec_table modfec_table[] = {
1017 /*delsys mod fec val */
1018 { SYS_DVBS, QPSK, FEC_1_2, 0x2e },
1019 { SYS_DVBS, QPSK, FEC_2_3, 0x2f },
1020 { SYS_DVBS, QPSK, FEC_3_4, 0x30 },
1021 { SYS_DVBS, QPSK, FEC_5_6, 0x31 },
1022 { SYS_DVBS, QPSK, FEC_6_7, 0x32 },
1023 { SYS_DVBS, QPSK, FEC_7_8, 0x33 },
1025 { SYS_DVBS2, QPSK, FEC_1_2, 0x04 },
1026 { SYS_DVBS2, QPSK, FEC_3_5, 0x05 },
1027 { SYS_DVBS2, QPSK, FEC_2_3, 0x06 },
1028 { SYS_DVBS2, QPSK, FEC_3_4, 0x07 },
1029 { SYS_DVBS2, QPSK, FEC_4_5, 0x08 },
1030 { SYS_DVBS2, QPSK, FEC_5_6, 0x09 },
1031 { SYS_DVBS2, QPSK, FEC_8_9, 0x0a },
1032 { SYS_DVBS2, QPSK, FEC_9_10, 0x0b },
1034 { SYS_DVBS2, PSK_8, FEC_3_5, 0x0c },
1035 { SYS_DVBS2, PSK_8, FEC_2_3, 0x0d },
1036 { SYS_DVBS2, PSK_8, FEC_3_4, 0x0e },
1037 { SYS_DVBS2, PSK_8, FEC_5_6, 0x0f },
1038 { SYS_DVBS2, PSK_8, FEC_8_9, 0x10 },
1039 { SYS_DVBS2, PSK_8, FEC_9_10, 0x11 },
1042 /* Set fec_val & fec_mask values from delsys, modulation & fec */
1043 static int cx24120_set_fec(struct cx24120_state *state, enum fe_modulation mod,
1044 enum fe_code_rate fec)
1048 dev_dbg(&state->i2c->dev, "(0x%02x,0x%02x)\n", mod, fec);
1050 state->dnxt.fec = fec;
1052 /* Lookup fec_val from modfec table */
1053 for (idx = 0; idx < ARRAY_SIZE(modfec_table); idx++) {
1054 if (modfec_table[idx].delsys != state->dnxt.delsys)
1056 if (modfec_table[idx].mod != mod)
1058 if (modfec_table[idx].fec != fec)
1062 state->dnxt.fec_mask = 0x00;
1063 state->dnxt.fec_val = modfec_table[idx].val;
1067 if (state->dnxt.delsys == SYS_DVBS2) {
1068 /* DVBS2 auto is 0x00/0x00 */
1069 state->dnxt.fec_mask = 0x00;
1070 state->dnxt.fec_val = 0x00;
1072 /* Set DVB-S to auto */
1073 state->dnxt.fec_val = 0x2e;
1074 state->dnxt.fec_mask = 0xac;
1081 static int cx24120_set_pilot(struct cx24120_state *state, enum fe_pilot pilot)
1083 dev_dbg(&state->i2c->dev, "(%d)\n", pilot);
1085 /* Pilot only valid in DVBS2 */
1086 if (state->dnxt.delsys != SYS_DVBS2) {
1087 state->dnxt.pilot_val = CX24120_PILOT_OFF;
1093 state->dnxt.pilot_val = CX24120_PILOT_OFF;
1096 state->dnxt.pilot_val = CX24120_PILOT_ON;
1100 state->dnxt.pilot_val = CX24120_PILOT_AUTO;
1106 /* Set symbol rate */
1107 static int cx24120_set_symbolrate(struct cx24120_state *state, u32 rate)
1109 dev_dbg(&state->i2c->dev, "(%d)\n", rate);
1111 state->dnxt.symbol_rate = rate;
1113 /* Check symbol rate */
1114 if (rate > 31000000) {
1115 state->dnxt.clkdiv = (-(rate < 31000001) & 3) + 2;
1116 state->dnxt.ratediv = (-(rate < 31000001) & 6) + 4;
1118 state->dnxt.clkdiv = 3;
1119 state->dnxt.ratediv = 6;
1125 /* Overwrite the current tuning params, we are about to tune */
1126 static void cx24120_clone_params(struct dvb_frontend *fe)
1128 struct cx24120_state *state = fe->demodulator_priv;
1130 state->dcur = state->dnxt;
1133 static int cx24120_set_frontend(struct dvb_frontend *fe)
1135 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1136 struct cx24120_state *state = fe->demodulator_priv;
1137 struct cx24120_cmd cmd;
1140 switch (c->delivery_system) {
1142 dev_dbg(&state->i2c->dev, "DVB-S2\n");
1145 dev_dbg(&state->i2c->dev, "DVB-S\n");
1148 dev_dbg(&state->i2c->dev,
1149 "delivery system(%d) not supported\n",
1150 c->delivery_system);
1154 state->dnxt.delsys = c->delivery_system;
1155 state->dnxt.modulation = c->modulation;
1156 state->dnxt.frequency = c->frequency;
1157 state->dnxt.pilot = c->pilot;
1159 ret = cx24120_set_inversion(state, c->inversion);
1163 ret = cx24120_set_fec(state, c->modulation, c->fec_inner);
1167 ret = cx24120_set_pilot(state, c->pilot);
1171 ret = cx24120_set_symbolrate(state, c->symbol_rate);
1175 /* discard the 'current' tuning parameters and prepare to tune */
1176 cx24120_clone_params(fe);
1178 dev_dbg(&state->i2c->dev,
1179 "delsys = %d\n", state->dcur.delsys);
1180 dev_dbg(&state->i2c->dev,
1181 "modulation = %d\n", state->dcur.modulation);
1182 dev_dbg(&state->i2c->dev,
1183 "frequency = %d\n", state->dcur.frequency);
1184 dev_dbg(&state->i2c->dev,
1185 "pilot = %d (val = 0x%02x)\n",
1186 state->dcur.pilot, state->dcur.pilot_val);
1187 dev_dbg(&state->i2c->dev,
1188 "symbol_rate = %d (clkdiv/ratediv = 0x%02x/0x%02x)\n",
1189 state->dcur.symbol_rate,
1190 state->dcur.clkdiv, state->dcur.ratediv);
1191 dev_dbg(&state->i2c->dev,
1192 "FEC = %d (mask/val = 0x%02x/0x%02x)\n",
1193 state->dcur.fec, state->dcur.fec_mask, state->dcur.fec_val);
1194 dev_dbg(&state->i2c->dev,
1195 "Inversion = %d (val = 0x%02x)\n",
1196 state->dcur.inversion, state->dcur.inversion_val);
1198 /* Flag that clock needs to be set after tune */
1199 state->need_clock_set = 1;
1202 cmd.id = CMD_TUNEREQUEST;
1205 cmd.arg[1] = (state->dcur.frequency & 0xff0000) >> 16;
1206 cmd.arg[2] = (state->dcur.frequency & 0x00ff00) >> 8;
1207 cmd.arg[3] = (state->dcur.frequency & 0x0000ff);
1208 cmd.arg[4] = ((state->dcur.symbol_rate / 1000) & 0xff00) >> 8;
1209 cmd.arg[5] = ((state->dcur.symbol_rate / 1000) & 0x00ff);
1210 cmd.arg[6] = state->dcur.inversion;
1211 cmd.arg[7] = state->dcur.fec_val | state->dcur.pilot_val;
1212 cmd.arg[8] = CX24120_SEARCH_RANGE_KHZ >> 8;
1213 cmd.arg[9] = CX24120_SEARCH_RANGE_KHZ & 0xff;
1214 cmd.arg[10] = 0; /* maybe rolloff? */
1215 cmd.arg[11] = state->dcur.fec_mask;
1216 cmd.arg[12] = state->dcur.ratediv;
1217 cmd.arg[13] = state->dcur.clkdiv;
1220 /* Send tune command */
1221 ret = cx24120_message_send(state, &cmd);
1225 /* Write symbol rate values */
1226 ret = cx24120_writereg(state, CX24120_REG_CLKDIV, state->dcur.clkdiv);
1227 ret = cx24120_readreg(state, CX24120_REG_RATEDIV);
1229 ret |= state->dcur.ratediv;
1230 ret = cx24120_writereg(state, CX24120_REG_RATEDIV, ret);
1235 /* Set vco from config */
1236 static int cx24120_set_vco(struct cx24120_state *state)
1238 struct cx24120_cmd cmd;
1241 u32 xtal_khz = state->config->xtal_khz;
1243 nxtal_khz = xtal_khz * 4;
1244 vco = nxtal_khz * 10;
1245 inv_vco = DIV_ROUND_CLOSEST_ULL(0x400000000ULL, vco);
1247 dev_dbg(&state->i2c->dev, "xtal=%d, vco=%d, inv_vco=%lld\n",
1248 xtal_khz, vco, inv_vco);
1250 cmd.id = CMD_VCO_SET;
1252 cmd.arg[0] = (vco >> 16) & 0xff;
1253 cmd.arg[1] = (vco >> 8) & 0xff;
1254 cmd.arg[2] = vco & 0xff;
1255 cmd.arg[3] = (inv_vco >> 8) & 0xff;
1256 cmd.arg[4] = (inv_vco) & 0xff;
1258 cmd.arg[6] = (nxtal_khz >> 8) & 0xff;
1259 cmd.arg[7] = nxtal_khz & 0xff;
1262 cmd.arg[10] = (xtal_khz >> 16) & 0xff;
1263 cmd.arg[11] = xtal_khz & 0xff;
1265 return cx24120_message_send(state, &cmd);
1268 static int cx24120_init(struct dvb_frontend *fe)
1270 const struct firmware *fw;
1271 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1272 struct cx24120_state *state = fe->demodulator_priv;
1273 struct cx24120_cmd cmd;
1276 unsigned char vers[4];
1278 if (state->cold_init)
1282 cx24120_writereg(state, 0xea, 0x00);
1283 cx24120_test_rom(state);
1284 reg = cx24120_readreg(state, 0xfb) & 0xfe;
1285 cx24120_writereg(state, 0xfb, reg);
1286 reg = cx24120_readreg(state, 0xfc) & 0xfe;
1287 cx24120_writereg(state, 0xfc, reg);
1288 cx24120_writereg(state, 0xc3, 0x04);
1289 cx24120_writereg(state, 0xc4, 0x04);
1290 cx24120_writereg(state, 0xce, 0x00);
1291 cx24120_writereg(state, 0xcf, 0x00);
1292 reg = cx24120_readreg(state, 0xea) & 0xfe;
1293 cx24120_writereg(state, 0xea, reg);
1294 cx24120_writereg(state, 0xeb, 0x0c);
1295 cx24120_writereg(state, 0xec, 0x06);
1296 cx24120_writereg(state, 0xed, 0x05);
1297 cx24120_writereg(state, 0xee, 0x03);
1298 cx24120_writereg(state, 0xef, 0x05);
1299 cx24120_writereg(state, 0xf3, 0x03);
1300 cx24120_writereg(state, 0xf4, 0x44);
1302 for (i = 0; i < 3; i++) {
1303 cx24120_writereg(state, 0xf0 + i, 0x04);
1304 cx24120_writereg(state, 0xe6 + i, 0x02);
1307 cx24120_writereg(state, 0xea, (reg | 0x01));
1308 for (i = 0; i < 6; i += 2) {
1309 cx24120_writereg(state, 0xc5 + i, 0x00);
1310 cx24120_writereg(state, 0xc6 + i, 0x00);
1313 cx24120_writereg(state, 0xe4, 0x03);
1314 cx24120_writereg(state, 0xeb, 0x0a);
1316 dev_dbg(&state->i2c->dev, "requesting firmware (%s) to download...\n",
1319 ret = state->config->request_firmware(fe, &fw, CX24120_FIRMWARE);
1321 err("Could not load firmware (%s): %d\n", CX24120_FIRMWARE,
1326 dev_dbg(&state->i2c->dev,
1327 "Firmware found, size %d bytes (%02x %02x .. %02x %02x)\n",
1328 (int)fw->size, /* firmware_size in bytes */
1329 fw->data[0], /* fw 1st byte */
1330 fw->data[1], /* fw 2d byte */
1331 fw->data[fw->size - 2], /* fw before last byte */
1332 fw->data[fw->size - 1]); /* fw last byte */
1334 cx24120_test_rom(state);
1335 reg = cx24120_readreg(state, 0xfb) & 0xfe;
1336 cx24120_writereg(state, 0xfb, reg);
1337 cx24120_writereg(state, 0xe0, 0x76);
1338 cx24120_writereg(state, 0xf7, 0x81);
1339 cx24120_writereg(state, 0xf8, 0x00);
1340 cx24120_writereg(state, 0xf9, 0x00);
1341 cx24120_writeregs(state, 0xfa, fw->data, (fw->size - 1), 0x00);
1342 cx24120_writereg(state, 0xf7, 0xc0);
1343 cx24120_writereg(state, 0xe0, 0x00);
1344 reg = (fw->size - 2) & 0x00ff;
1345 cx24120_writereg(state, 0xf8, reg);
1346 reg = ((fw->size - 2) >> 8) & 0x00ff;
1347 cx24120_writereg(state, 0xf9, reg);
1348 cx24120_writereg(state, 0xf7, 0x00);
1349 cx24120_writereg(state, 0xdc, 0x00);
1350 cx24120_writereg(state, 0xdc, 0x07);
1353 /* Check final byte matches final byte of firmware */
1354 reg = cx24120_readreg(state, 0xe1);
1355 if (reg == fw->data[fw->size - 1]) {
1356 dev_dbg(&state->i2c->dev, "Firmware uploaded successfully\n");
1359 err("Firmware upload failed. Last byte returned=0x%x\n", ret);
1362 cx24120_writereg(state, 0xdc, 0x00);
1363 release_firmware(fw);
1368 cmd.id = CMD_START_TUNER;
1374 if (cx24120_message_send(state, &cmd) != 0) {
1375 err("Error tuner start! :(\n");
1380 ret = cx24120_set_vco(state);
1382 err("Error set VCO! :(\n");
1387 cmd.id = CMD_BANDWIDTH;
1402 if (cx24120_message_send(state, &cmd)) {
1403 err("Error set bandwidth!\n");
1407 reg = cx24120_readreg(state, 0xba);
1409 dev_dbg(&state->i2c->dev, "Reset-readreg 0xba: %x\n", ret);
1410 err("Error initialising tuner!\n");
1414 dev_dbg(&state->i2c->dev, "Tuner initialised correctly.\n");
1416 /* Initialise mpeg outputs */
1417 cx24120_writereg(state, 0xeb, 0x0a);
1418 if (cx24120_msg_mpeg_output_global_config(state, 0) ||
1419 cx24120_msg_mpeg_output_config(state, 0) ||
1420 cx24120_msg_mpeg_output_config(state, 1) ||
1421 cx24120_msg_mpeg_output_config(state, 2)) {
1422 err("Error initialising mpeg output. :(\n");
1426 /* Set size of BER window */
1427 cmd.id = CMD_BER_CTRL;
1430 cmd.arg[1] = CX24120_BER_WINDOW;
1431 cmd.arg[2] = CX24120_BER_WINDOW;
1432 if (cx24120_message_send(state, &cmd)) {
1433 err("Error setting ber window\n");
1437 /* Firmware CMD 35: Get firmware version */
1438 cmd.id = CMD_FWVERSION;
1440 for (i = 0; i < 4; i++) {
1442 ret = cx24120_message_send(state, &cmd);
1445 vers[i] = cx24120_readreg(state, CX24120_REG_MAILBOX);
1447 info("FW version %i.%i.%i.%i\n", vers[0], vers[1], vers[2], vers[3]);
1449 /* init stats here in order signal app which stats are supported */
1450 c->strength.len = 1;
1451 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1453 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1454 c->post_bit_error.len = 1;
1455 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1456 c->post_bit_count.len = 1;
1457 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1458 c->block_error.len = 1;
1459 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1460 c->block_count.len = 1;
1461 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1463 state->cold_init = 1;
1468 static int cx24120_tune(struct dvb_frontend *fe, bool re_tune,
1469 unsigned int mode_flags, unsigned int *delay,
1470 enum fe_status *status)
1472 struct cx24120_state *state = fe->demodulator_priv;
1475 dev_dbg(&state->i2c->dev, "(%d)\n", re_tune);
1477 /* TODO: Do we need to set delay? */
1480 ret = cx24120_set_frontend(fe);
1485 return cx24120_read_status(fe, status);
1488 static enum dvbfe_algo cx24120_get_algo(struct dvb_frontend *fe)
1490 return DVBFE_ALGO_HW;
1493 static int cx24120_sleep(struct dvb_frontend *fe)
1498 static int cx24120_get_frontend(struct dvb_frontend *fe,
1499 struct dtv_frontend_properties *c)
1501 struct cx24120_state *state = fe->demodulator_priv;
1502 u8 freq1, freq2, freq3;
1505 dev_dbg(&state->i2c->dev, "\n");
1507 /* don't return empty data if we're not tuned in */
1508 status = cx24120_readreg(state, CX24120_REG_STATUS);
1509 if (!(status & CX24120_HAS_LOCK))
1513 freq1 = cx24120_readreg(state, CX24120_REG_FREQ1);
1514 freq2 = cx24120_readreg(state, CX24120_REG_FREQ2);
1515 freq3 = cx24120_readreg(state, CX24120_REG_FREQ3);
1516 c->frequency = (freq3 << 16) | (freq2 << 8) | freq1;
1517 dev_dbg(&state->i2c->dev, "frequency = %d\n", c->frequency);
1519 /* Get modulation, fec, pilot */
1520 cx24120_get_fec(fe);
1525 static void cx24120_release(struct dvb_frontend *fe)
1527 struct cx24120_state *state = fe->demodulator_priv;
1529 dev_dbg(&state->i2c->dev, "Clear state structure\n");
1533 static int cx24120_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1535 struct cx24120_state *state = fe->demodulator_priv;
1536 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1538 if (c->block_error.stat[0].scale != FE_SCALE_COUNTER) {
1543 *ucblocks = c->block_error.stat[0].uvalue - state->ucb_offset;
1548 static const struct dvb_frontend_ops cx24120_ops = {
1549 .delsys = { SYS_DVBS, SYS_DVBS2 },
1551 .name = "Conexant CX24120/CX24118",
1552 .frequency_min_hz = 950 * MHz,
1553 .frequency_max_hz = 2150 * MHz,
1554 .frequency_stepsize_hz = 1011 * kHz,
1555 .frequency_tolerance_hz = 5 * MHz,
1556 .symbol_rate_min = 1000000,
1557 .symbol_rate_max = 45000000,
1558 .caps = FE_CAN_INVERSION_AUTO |
1559 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1560 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1561 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1562 FE_CAN_2G_MODULATION |
1563 FE_CAN_QPSK | FE_CAN_RECOVER
1565 .release = cx24120_release,
1567 .init = cx24120_init,
1568 .sleep = cx24120_sleep,
1570 .tune = cx24120_tune,
1571 .get_frontend_algo = cx24120_get_algo,
1572 .set_frontend = cx24120_set_frontend,
1574 .get_frontend = cx24120_get_frontend,
1575 .read_status = cx24120_read_status,
1576 .read_ber = cx24120_read_ber,
1577 .read_signal_strength = cx24120_read_signal_strength,
1578 .read_snr = cx24120_read_snr,
1579 .read_ucblocks = cx24120_read_ucblocks,
1581 .diseqc_send_master_cmd = cx24120_send_diseqc_msg,
1583 .diseqc_send_burst = cx24120_diseqc_send_burst,
1584 .set_tone = cx24120_set_tone,
1585 .set_voltage = cx24120_set_voltage,
1588 MODULE_DESCRIPTION("DVB Frontend module for Conexant CX24120/CX24118 hardware");
1589 MODULE_AUTHOR("Jemma Denson");
1590 MODULE_LICENSE("GPL");